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nvc0: identify VERTEX_QUARANTINE
[mesa.git] / src / gallium / drivers / nvc0 / nvc0_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27 #include "translate/translate.h"
28
29 #include "nvc0_context.h"
30 #include "nvc0_resource.h"
31
32 #include "nvc0_3d.xml.h"
33
34 void
35 nvc0_vertex_state_delete(struct pipe_context *pipe,
36 void *hwcso)
37 {
38 struct nvc0_vertex_stateobj *so = hwcso;
39
40 if (so->translate)
41 so->translate->release(so->translate);
42 FREE(hwcso);
43 }
44
45 void *
46 nvc0_vertex_state_create(struct pipe_context *pipe,
47 unsigned num_elements,
48 const struct pipe_vertex_element *elements)
49 {
50 struct nvc0_vertex_stateobj *so;
51 struct translate_key transkey;
52 unsigned i;
53
54 assert(num_elements);
55
56 so = MALLOC(sizeof(*so) +
57 num_elements * sizeof(struct nvc0_vertex_element));
58 if (!so)
59 return NULL;
60 so->num_elements = num_elements;
61 so->instance_elts = 0;
62 so->instance_bufs = 0;
63 so->need_conversion = FALSE;
64
65 transkey.nr_elements = 0;
66 transkey.output_stride = 0;
67
68 for (i = 0; i < num_elements; ++i) {
69 const struct pipe_vertex_element *ve = &elements[i];
70 const unsigned vbi = ve->vertex_buffer_index;
71 enum pipe_format fmt = ve->src_format;
72
73 so->element[i].pipe = elements[i];
74 so->element[i].state = nvc0_format_table[fmt].vtx;
75
76 if (!so->element[i].state) {
77 switch (util_format_get_nr_components(fmt)) {
78 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
79 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
80 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
81 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
82 default:
83 assert(0);
84 return NULL;
85 }
86 so->element[i].state = nvc0_format_table[fmt].vtx;
87 so->need_conversion = TRUE;
88 }
89 so->element[i].state |= i;
90
91 if (1) {
92 unsigned j = transkey.nr_elements++;
93
94 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
95 transkey.element[j].input_format = ve->src_format;
96 transkey.element[j].input_buffer = vbi;
97 transkey.element[j].input_offset = ve->src_offset;
98 transkey.element[j].instance_divisor = ve->instance_divisor;
99
100 transkey.element[j].output_format = fmt;
101 transkey.element[j].output_offset = transkey.output_stride;
102 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
103
104 if (unlikely(ve->instance_divisor)) {
105 so->instance_elts |= 1 << i;
106 so->instance_bufs |= 1 << vbi;
107 }
108 }
109 }
110
111 so->translate = translate_create(&transkey);
112 so->vtx_size = transkey.output_stride / 4;
113 so->vtx_per_packet_max = NV04_PFIFO_MAX_PACKET_LEN / MAX2(so->vtx_size, 1);
114
115 return so;
116 }
117
118 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE \
119 NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT | \
120 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
121
122 #define VTX_ATTR(a, c, t, s) \
123 ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) | \
124 (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) | \
125 ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) | \
126 ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
127
128 static void
129 nvc0_emit_vtxattr(struct nvc0_context *nvc0, struct pipe_vertex_buffer *vb,
130 struct pipe_vertex_element *ve, unsigned attr)
131 {
132 const void *data;
133 struct nouveau_channel *chan = nvc0->screen->base.channel;
134 struct nv04_resource *res = nv04_resource(vb->buffer);
135 float v[4];
136 int i;
137 const unsigned nc = util_format_get_nr_components(ve->src_format);
138
139 data = nouveau_resource_map_offset(&nvc0->base, res, vb->buffer_offset +
140 ve->src_offset, NOUVEAU_BO_RD);
141
142 util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
143
144 BEGIN_RING(chan, RING_3D(VTX_ATTR_DEFINE), nc + 1);
145 OUT_RING (chan, VTX_ATTR(attr, nc, FLOAT, 32));
146 for (i = 0; i < nc; ++i)
147 OUT_RINGf(chan, v[i]);
148 }
149
150 static INLINE void
151 nvc0_vbuf_range(struct nvc0_context *nvc0, int vbi,
152 uint32_t *base, uint32_t *size)
153 {
154 if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
155 /* TODO: use min and max instance divisor to get a proper range */
156 *base = 0;
157 *size = nvc0->vtxbuf[vbi].buffer->width0;
158 } else {
159 assert(nvc0->vbo_max_index != ~0);
160 *base = nvc0->vbo_min_index * nvc0->vtxbuf[vbi].stride;
161 *size = (nvc0->vbo_max_index -
162 nvc0->vbo_min_index + 1) * nvc0->vtxbuf[vbi].stride;
163 }
164 }
165
166 static void
167 nvc0_prevalidate_vbufs(struct nvc0_context *nvc0)
168 {
169 struct pipe_vertex_buffer *vb;
170 struct nv04_resource *buf;
171 int i;
172 uint32_t base, size;
173
174 nvc0->vbo_fifo = nvc0->vbo_user = 0;
175
176 nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_VERTEX);
177
178 for (i = 0; i < nvc0->num_vtxbufs; ++i) {
179 vb = &nvc0->vtxbuf[i];
180 if (!vb->stride)
181 continue;
182 buf = nv04_resource(vb->buffer);
183
184 /* NOTE: user buffers with temporary storage count as mapped by GPU */
185 if (!nouveau_resource_mapped_by_gpu(vb->buffer)) {
186 if (nvc0->vbo_push_hint) {
187 nvc0->vbo_fifo = ~0;
188 continue;
189 } else {
190 if (buf->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY) {
191 nvc0->vbo_user |= 1 << i;
192 assert(vb->stride > vb->buffer_offset);
193 nvc0_vbuf_range(nvc0, i, &base, &size);
194 nouveau_user_buffer_upload(buf, base, size);
195 } else {
196 nouveau_buffer_migrate(&nvc0->base, buf, NOUVEAU_BO_GART);
197 }
198 nvc0->base.vbo_dirty = TRUE;
199 }
200 }
201 nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_VERTEX, buf, NOUVEAU_BO_RD);
202 nouveau_buffer_adjust_score(&nvc0->base, buf, 1);
203 }
204 }
205
206 static void
207 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
208 {
209 struct nouveau_channel *chan = nvc0->screen->base.channel;
210 uint32_t base, offset, size;
211 int i;
212 uint32_t written = 0;
213
214 for (i = 0; i < nvc0->vertex->num_elements; ++i) {
215 struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
216 const int b = ve->vertex_buffer_index;
217 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
218 struct nv04_resource *buf = nv04_resource(vb->buffer);
219
220 if (!(nvc0->vbo_user & (1 << b)))
221 continue;
222
223 if (!vb->stride) {
224 nvc0_emit_vtxattr(nvc0, vb, ve, i);
225 continue;
226 }
227 nvc0_vbuf_range(nvc0, b, &base, &size);
228
229 if (!(written & (1 << b))) {
230 written |= 1 << b;
231 nouveau_user_buffer_upload(buf, base, size);
232 }
233 offset = vb->buffer_offset + ve->src_offset;
234
235 MARK_RING (chan, 6, 4);
236 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
237 OUT_RING (chan, i);
238 OUT_RESRCh(chan, buf, base + size - 1, NOUVEAU_BO_RD);
239 OUT_RESRCl(chan, buf, base + size - 1, NOUVEAU_BO_RD);
240 OUT_RESRCh(chan, buf, offset, NOUVEAU_BO_RD);
241 OUT_RESRCl(chan, buf, offset, NOUVEAU_BO_RD);
242 }
243 nvc0->base.vbo_dirty = TRUE;
244 }
245
246 static INLINE void
247 nvc0_release_user_vbufs(struct nvc0_context *nvc0)
248 {
249 uint32_t vbo_user = nvc0->vbo_user;
250
251 while (vbo_user) {
252 int i = ffs(vbo_user) - 1;
253 vbo_user &= ~(1 << i);
254
255 nouveau_buffer_release_gpu_storage(nv04_resource(nvc0->vtxbuf[i].buffer));
256 }
257 }
258
259 void
260 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
261 {
262 struct nouveau_channel *chan = nvc0->screen->base.channel;
263 struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
264 struct pipe_vertex_buffer *vb;
265 struct nvc0_vertex_element *ve;
266 unsigned i;
267
268 if (unlikely(vertex->need_conversion)) {
269 nvc0->vbo_fifo = ~0;
270 nvc0->vbo_user = 0;
271 } else {
272 nvc0_prevalidate_vbufs(nvc0);
273 }
274
275 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(0)), vertex->num_elements);
276 for (i = 0; i < vertex->num_elements; ++i) {
277 ve = &vertex->element[i];
278 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
279
280 if (likely(vb->stride) || nvc0->vbo_fifo) {
281 OUT_RING(chan, ve->state);
282 } else {
283 OUT_RING(chan, ve->state | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
284 nvc0->vbo_fifo &= ~(1 << i);
285 }
286 }
287
288 for (i = 0; i < vertex->num_elements; ++i) {
289 struct nv04_resource *res;
290 unsigned size, offset;
291
292 ve = &vertex->element[i];
293 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
294
295 if (unlikely(ve->pipe.instance_divisor)) {
296 if (!(nvc0->state.instance_elts & (1 << i))) {
297 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
298 }
299 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
300 OUT_RING (chan, ve->pipe.instance_divisor);
301 } else
302 if (unlikely(nvc0->state.instance_elts & (1 << i))) {
303 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0);
304 }
305
306 res = nv04_resource(vb->buffer);
307
308 if (nvc0->vbo_fifo || unlikely(vb->stride == 0)) {
309 if (!nvc0->vbo_fifo)
310 nvc0_emit_vtxattr(nvc0, vb, &ve->pipe, i);
311 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
312 OUT_RING (chan, 0);
313 continue;
314 }
315
316 size = vb->buffer->width0;
317 offset = ve->pipe.src_offset + vb->buffer_offset;
318
319 MARK_RING (chan, 8, 4);
320 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
321 OUT_RING (chan, (1 << 12) | vb->stride);
322 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
323 OUT_RING (chan, i);
324 OUT_RESRCh(chan, res, size - 1, NOUVEAU_BO_RD);
325 OUT_RESRCl(chan, res, size - 1, NOUVEAU_BO_RD);
326 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
327 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
328 }
329 for (; i < nvc0->state.num_vtxelts; ++i) {
330 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(i)), 1);
331 OUT_RING (chan, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
332 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
333 OUT_RING (chan, 0);
334 }
335
336 nvc0->state.num_vtxelts = vertex->num_elements;
337 nvc0->state.instance_elts = vertex->instance_elts;
338 }
339
340 #define NVC0_PRIM_GL_CASE(n) \
341 case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
342
343 static INLINE unsigned
344 nvc0_prim_gl(unsigned prim)
345 {
346 switch (prim) {
347 NVC0_PRIM_GL_CASE(POINTS);
348 NVC0_PRIM_GL_CASE(LINES);
349 NVC0_PRIM_GL_CASE(LINE_LOOP);
350 NVC0_PRIM_GL_CASE(LINE_STRIP);
351 NVC0_PRIM_GL_CASE(TRIANGLES);
352 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
353 NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
354 NVC0_PRIM_GL_CASE(QUADS);
355 NVC0_PRIM_GL_CASE(QUAD_STRIP);
356 NVC0_PRIM_GL_CASE(POLYGON);
357 NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
358 NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
359 NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
360 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
361 /*
362 NVC0_PRIM_GL_CASE(PATCHES); */
363 default:
364 return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
365 break;
366 }
367 }
368
369 static void
370 nvc0_draw_vbo_flush_notify(struct nouveau_channel *chan)
371 {
372 struct nvc0_context *nvc0 = chan->user_private;
373
374 nouveau_fence_update(&nvc0->screen->base, TRUE);
375
376 nvc0_bufctx_emit_relocs(nvc0);
377 }
378
379 static void
380 nvc0_draw_arrays(struct nvc0_context *nvc0,
381 unsigned mode, unsigned start, unsigned count,
382 unsigned instance_count)
383 {
384 struct nouveau_channel *chan = nvc0->screen->base.channel;
385 unsigned prim;
386
387 chan->flush_notify = nvc0_draw_vbo_flush_notify;
388 chan->user_private = nvc0;
389
390 prim = nvc0_prim_gl(mode);
391
392 while (instance_count--) {
393 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
394 OUT_RING (chan, prim);
395 BEGIN_RING(chan, RING_3D(VERTEX_BUFFER_FIRST), 2);
396 OUT_RING (chan, start);
397 OUT_RING (chan, count);
398 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
399
400 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
401 }
402
403 chan->flush_notify = nvc0_default_flush_notify;
404 }
405
406 static void
407 nvc0_draw_elements_inline_u08(struct nouveau_channel *chan, uint8_t *map,
408 unsigned start, unsigned count)
409 {
410 map += start;
411
412 if (count & 3) {
413 unsigned i;
414 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), count & 3);
415 for (i = 0; i < (count & 3); ++i)
416 OUT_RING(chan, *map++);
417 count &= ~3;
418 }
419 while (count) {
420 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
421
422 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U8), nr);
423 for (i = 0; i < nr; ++i) {
424 OUT_RING(chan,
425 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
426 map += 4;
427 }
428 count -= nr * 4;
429 }
430 }
431
432 static void
433 nvc0_draw_elements_inline_u16(struct nouveau_channel *chan, uint16_t *map,
434 unsigned start, unsigned count)
435 {
436 map += start;
437
438 if (count & 1) {
439 count &= ~1;
440 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
441 OUT_RING (chan, *map++);
442 }
443 while (count) {
444 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
445
446 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
447 for (i = 0; i < nr; ++i) {
448 OUT_RING(chan, (map[1] << 16) | map[0]);
449 map += 2;
450 }
451 count -= nr * 2;
452 }
453 }
454
455 static void
456 nvc0_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map,
457 unsigned start, unsigned count)
458 {
459 map += start;
460
461 while (count) {
462 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
463
464 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), nr);
465 OUT_RINGp (chan, map, nr);
466
467 map += nr;
468 count -= nr;
469 }
470 }
471
472 static void
473 nvc0_draw_elements_inline_u32_short(struct nouveau_channel *chan, uint32_t *map,
474 unsigned start, unsigned count)
475 {
476 map += start;
477
478 if (count & 1) {
479 count--;
480 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
481 OUT_RING (chan, *map++);
482 }
483 while (count) {
484 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
485
486 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
487 for (i = 0; i < nr; ++i) {
488 OUT_RING(chan, (map[1] << 16) | map[0]);
489 map += 2;
490 }
491 count -= nr * 2;
492 }
493 }
494
495 static void
496 nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten,
497 unsigned mode, unsigned start, unsigned count,
498 unsigned instance_count, int32_t index_bias)
499 {
500 struct nouveau_channel *chan = nvc0->screen->base.channel;
501 void *data;
502 unsigned prim;
503 const unsigned index_size = nvc0->idxbuf.index_size;
504
505 chan->flush_notify = nvc0_draw_vbo_flush_notify;
506 chan->user_private = nvc0;
507
508 prim = nvc0_prim_gl(mode);
509
510 if (index_bias != nvc0->state.index_bias) {
511 BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
512 OUT_RING (chan, index_bias);
513 nvc0->state.index_bias = index_bias;
514 }
515
516 if (nouveau_resource_mapped_by_gpu(nvc0->idxbuf.buffer)) {
517 struct nv04_resource *res = nv04_resource(nvc0->idxbuf.buffer);
518 unsigned offset = nvc0->idxbuf.offset;
519 unsigned limit = nvc0->idxbuf.buffer->width0 - 1;
520
521 nouveau_buffer_adjust_score(&nvc0->base, res, 1);
522
523 while (instance_count--) {
524 MARK_RING (chan, 11, 4);
525 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
526 OUT_RING (chan, mode);
527 BEGIN_RING(chan, RING_3D(INDEX_ARRAY_START_HIGH), 7);
528 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
529 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
530 OUT_RESRCh(chan, res, limit, NOUVEAU_BO_RD);
531 OUT_RESRCl(chan, res, limit, NOUVEAU_BO_RD);
532 OUT_RING (chan, index_size >> 1);
533 OUT_RING (chan, start);
534 OUT_RING (chan, count);
535 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
536
537 nvc0_resource_fence(res, NOUVEAU_BO_RD);
538
539 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
540 }
541 } else {
542 data = nouveau_resource_map_offset(&nvc0->base,
543 nv04_resource(nvc0->idxbuf.buffer),
544 nvc0->idxbuf.offset, NOUVEAU_BO_RD);
545 if (!data)
546 return;
547
548 while (instance_count--) {
549 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
550 OUT_RING (chan, prim);
551 switch (index_size) {
552 case 1:
553 nvc0_draw_elements_inline_u08(chan, data, start, count);
554 break;
555 case 2:
556 nvc0_draw_elements_inline_u16(chan, data, start, count);
557 break;
558 case 4:
559 if (shorten)
560 nvc0_draw_elements_inline_u32_short(chan, data, start, count);
561 else
562 nvc0_draw_elements_inline_u32(chan, data, start, count);
563 break;
564 default:
565 assert(0);
566 return;
567 }
568 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
569
570 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
571 }
572 }
573
574 chan->flush_notify = nvc0_default_flush_notify;
575 }
576
577 void
578 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
579 {
580 struct nvc0_context *nvc0 = nvc0_context(pipe);
581 struct nouveau_channel *chan = nvc0->screen->base.channel;
582
583 /* For picking only a few vertices from a large user buffer, push is better,
584 * if index count is larger and we expect repeated vertices, suggest upload.
585 */
586 nvc0->vbo_push_hint = /* the 64 is heuristic */
587 !(info->indexed &&
588 ((info->max_index - info->min_index + 64) < info->count));
589
590 nvc0->vbo_min_index = info->min_index;
591 nvc0->vbo_max_index = info->max_index;
592
593 if (nvc0->vbo_push_hint != !!nvc0->vbo_fifo)
594 nvc0->dirty |= NVC0_NEW_ARRAYS;
595
596 if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS)))
597 nvc0_update_user_vbufs(nvc0);
598
599 nvc0_state_validate(nvc0);
600
601 if (nvc0->vbo_fifo) {
602 nvc0_push_vbo(nvc0, info);
603 return;
604 }
605
606 if (nvc0->state.instance_base != info->start_instance) {
607 nvc0->state.instance_base = info->start_instance;
608 /* NOTE: this does not affect the shader input, should it ? */
609 BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1);
610 OUT_RING (chan, info->start_instance);
611 }
612
613 if (nvc0->base.vbo_dirty) {
614 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1);
615 OUT_RING (chan, 0);
616 nvc0->base.vbo_dirty = FALSE;
617 }
618
619 if (!info->indexed) {
620 nvc0_draw_arrays(nvc0,
621 info->mode, info->start, info->count,
622 info->instance_count);
623 } else {
624 boolean shorten = info->max_index <= 65535;
625
626 assert(nvc0->idxbuf.buffer);
627
628 if (info->primitive_restart != nvc0->state.prim_restart) {
629 if (info->primitive_restart) {
630 BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 2);
631 OUT_RING (chan, 1);
632 OUT_RING (chan, info->restart_index);
633
634 if (info->restart_index > 65535)
635 shorten = FALSE;
636 } else {
637 IMMED_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 0);
638 }
639 nvc0->state.prim_restart = info->primitive_restart;
640 } else
641 if (info->primitive_restart) {
642 BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1);
643 OUT_RING (chan, info->restart_index);
644
645 if (info->restart_index > 65535)
646 shorten = FALSE;
647 }
648
649 nvc0_draw_elements(nvc0, shorten,
650 info->mode, info->start, info->count,
651 info->instance_count, info->index_bias);
652 }
653
654 nvc0_release_user_vbufs(nvc0);
655 }