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[mesa.git] / src / gallium / drivers / nvc0 / nvc0_vbo.c
1 /*
2 * Copyright 2010 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23 #include "pipe/p_context.h"
24 #include "pipe/p_state.h"
25 #include "util/u_inlines.h"
26 #include "util/u_format.h"
27 #include "translate/translate.h"
28
29 #include "nvc0_context.h"
30 #include "nvc0_resource.h"
31
32 #include "nvc0_3d.xml.h"
33
34 void
35 nvc0_vertex_state_delete(struct pipe_context *pipe,
36 void *hwcso)
37 {
38 struct nvc0_vertex_stateobj *so = hwcso;
39
40 if (so->translate)
41 so->translate->release(so->translate);
42 FREE(hwcso);
43 }
44
45 void *
46 nvc0_vertex_state_create(struct pipe_context *pipe,
47 unsigned num_elements,
48 const struct pipe_vertex_element *elements)
49 {
50 struct nvc0_vertex_stateobj *so;
51 struct translate_key transkey;
52 unsigned i;
53
54 assert(num_elements);
55
56 so = MALLOC(sizeof(*so) +
57 num_elements * sizeof(struct nvc0_vertex_element));
58 if (!so)
59 return NULL;
60 so->num_elements = num_elements;
61 so->instance_elts = 0;
62 so->instance_bufs = 0;
63
64 transkey.nr_elements = 0;
65 transkey.output_stride = 0;
66
67 for (i = 0; i < num_elements; ++i) {
68 const struct pipe_vertex_element *ve = &elements[i];
69 const unsigned vbi = ve->vertex_buffer_index;
70 enum pipe_format fmt = ve->src_format;
71
72 so->element[i].pipe = elements[i];
73 so->element[i].state = nvc0_format_table[fmt].vtx;
74
75 if (!so->element[i].state) {
76 switch (util_format_get_nr_components(fmt)) {
77 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
78 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
79 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
80 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
81 default:
82 assert(0);
83 return NULL;
84 }
85 so->element[i].state = nvc0_format_table[fmt].vtx;
86 }
87 so->element[i].state |= i;
88
89 if (1) {
90 unsigned j = transkey.nr_elements++;
91
92 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
93 transkey.element[j].input_format = ve->src_format;
94 transkey.element[j].input_buffer = vbi;
95 transkey.element[j].input_offset = ve->src_offset;
96 transkey.element[j].instance_divisor = ve->instance_divisor;
97
98 transkey.element[j].output_format = fmt;
99 transkey.element[j].output_offset = transkey.output_stride;
100 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
101
102 if (unlikely(ve->instance_divisor)) {
103 so->instance_elts |= 1 << i;
104 so->instance_bufs |= 1 << vbi;
105 }
106 }
107 }
108
109 so->translate = translate_create(&transkey);
110 so->vtx_size = transkey.output_stride / 4;
111 so->vtx_per_packet_max = NV04_PFIFO_MAX_PACKET_LEN / MAX2(so->vtx_size, 1);
112
113 return so;
114 }
115
116 #define NVC0_3D_VERTEX_ATTRIB_INACTIVE \
117 NVC0_3D_VERTEX_ATTRIB_FORMAT_TYPE_FLOAT | \
118 NVC0_3D_VERTEX_ATTRIB_FORMAT_SIZE_32 | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST
119
120 #define VTX_ATTR(a, c, t, s) \
121 ((NVC0_3D_VTX_ATTR_DEFINE_TYPE_##t) | \
122 (NVC0_3D_VTX_ATTR_DEFINE_SIZE_##s) | \
123 ((a) << NVC0_3D_VTX_ATTR_DEFINE_ATTR__SHIFT) | \
124 ((c) << NVC0_3D_VTX_ATTR_DEFINE_COMP__SHIFT))
125
126 static void
127 nvc0_emit_vtxattr(struct nvc0_context *nvc0, struct pipe_vertex_buffer *vb,
128 struct pipe_vertex_element *ve, unsigned attr)
129 {
130 const void *data;
131 struct nouveau_channel *chan = nvc0->screen->base.channel;
132 struct nvc0_resource *res = nvc0_resource(vb->buffer);
133 float v[4];
134 int i;
135 const unsigned nc = util_format_get_nr_components(ve->src_format);
136
137 data = nvc0_resource_map_offset(nvc0, res, vb->buffer_offset +
138 ve->src_offset, NOUVEAU_BO_RD);
139
140 util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
141
142 BEGIN_RING(chan, RING_3D(VTX_ATTR_DEFINE), nc + 1);
143 OUT_RING (chan, VTX_ATTR(attr, nc, FLOAT, 32));
144 for (i = 0; i < nc; ++i)
145 OUT_RINGf(chan, v[i]);
146 }
147
148 static INLINE void
149 nvc0_vbuf_range(struct nvc0_context *nvc0, int vbi,
150 uint32_t *base, uint32_t *size)
151 {
152 if (unlikely(nvc0->vertex->instance_bufs & (1 << vbi))) {
153 /* TODO: use min and max instance divisor to get a proper range */
154 *base = 0;
155 *size = nvc0->vtxbuf[vbi].buffer->width0;
156 } else {
157 assert(nvc0->vbo_max_index != ~0);
158 *base = nvc0->vbo_min_index * nvc0->vtxbuf[vbi].stride;
159 *size = (nvc0->vbo_max_index -
160 nvc0->vbo_min_index + 1) * nvc0->vtxbuf[vbi].stride;
161 }
162 }
163
164 static void
165 nvc0_prevalidate_vbufs(struct nvc0_context *nvc0)
166 {
167 struct pipe_vertex_buffer *vb;
168 struct nvc0_resource *buf;
169 int i;
170 uint32_t base, size;
171
172 nvc0->vbo_fifo = nvc0->vbo_user = 0;
173
174 nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_VERTEX);
175
176 for (i = 0; i < nvc0->num_vtxbufs; ++i) {
177 vb = &nvc0->vtxbuf[i];
178 if (!vb->stride)
179 continue;
180 buf = nvc0_resource(vb->buffer);
181
182 /* NOTE: user buffers with temporary storage count as mapped by GPU */
183 if (!nvc0_resource_mapped_by_gpu(vb->buffer)) {
184 if (nvc0->vbo_push_hint) {
185 nvc0->vbo_fifo = ~0;
186 continue;
187 } else {
188 if (buf->status & NVC0_BUFFER_STATUS_USER_MEMORY) {
189 nvc0->vbo_user |= 1 << i;
190 assert(vb->stride > vb->buffer_offset);
191 nvc0_vbuf_range(nvc0, i, &base, &size);
192 nvc0_user_buffer_upload(buf, base, size);
193 } else {
194 nvc0_buffer_migrate(nvc0, buf, NOUVEAU_BO_GART);
195 }
196 nvc0->vbo_dirty = TRUE;
197 }
198 }
199 nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_VERTEX, buf, NOUVEAU_BO_RD);
200 nvc0_buffer_adjust_score(nvc0, buf, 1);
201 }
202 }
203
204 static void
205 nvc0_update_user_vbufs(struct nvc0_context *nvc0)
206 {
207 struct nouveau_channel *chan = nvc0->screen->base.channel;
208 uint32_t base, offset, size;
209 int i;
210 uint32_t written = 0;
211
212 for (i = 0; i < nvc0->vertex->num_elements; ++i) {
213 struct pipe_vertex_element *ve = &nvc0->vertex->element[i].pipe;
214 const int b = ve->vertex_buffer_index;
215 struct pipe_vertex_buffer *vb = &nvc0->vtxbuf[b];
216 struct nvc0_resource *buf = nvc0_resource(vb->buffer);
217
218 if (!(nvc0->vbo_user & (1 << b)))
219 continue;
220
221 if (!vb->stride) {
222 nvc0_emit_vtxattr(nvc0, vb, ve, i);
223 continue;
224 }
225 nvc0_vbuf_range(nvc0, b, &base, &size);
226
227 if (!(written & (1 << b))) {
228 written |= 1 << b;
229 nvc0_user_buffer_upload(buf, base, size);
230 }
231 offset = vb->buffer_offset + ve->src_offset;
232
233 MARK_RING (chan, 6, 4);
234 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
235 OUT_RING (chan, i);
236 OUT_RESRCh(chan, buf, base + size - 1, NOUVEAU_BO_RD);
237 OUT_RESRCl(chan, buf, base + size - 1, NOUVEAU_BO_RD);
238 OUT_RESRCh(chan, buf, offset, NOUVEAU_BO_RD);
239 OUT_RESRCl(chan, buf, offset, NOUVEAU_BO_RD);
240 }
241 nvc0->vbo_dirty = TRUE;
242 }
243
244 static INLINE void
245 nvc0_release_user_vbufs(struct nvc0_context *nvc0)
246 {
247 uint32_t vbo_user = nvc0->vbo_user;
248
249 while (vbo_user) {
250 int i = ffs(vbo_user) - 1;
251 vbo_user &= ~(1 << i);
252
253 nvc0_buffer_release_gpu_storage(nvc0_resource(nvc0->vtxbuf[i].buffer));
254 }
255 }
256
257 void
258 nvc0_vertex_arrays_validate(struct nvc0_context *nvc0)
259 {
260 struct nouveau_channel *chan = nvc0->screen->base.channel;
261 struct nvc0_vertex_stateobj *vertex = nvc0->vertex;
262 struct pipe_vertex_buffer *vb;
263 struct nvc0_vertex_element *ve;
264 unsigned i;
265
266 nvc0_prevalidate_vbufs(nvc0);
267
268 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(0)), vertex->num_elements);
269 for (i = 0; i < vertex->num_elements; ++i) {
270 ve = &vertex->element[i];
271 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
272
273 if (likely(vb->stride) || nvc0->vbo_fifo) {
274 OUT_RING(chan, ve->state);
275 } else {
276 OUT_RING(chan, ve->state | NVC0_3D_VERTEX_ATTRIB_FORMAT_CONST);
277 nvc0->vbo_fifo &= ~(1 << i);
278 }
279 }
280
281 for (i = 0; i < vertex->num_elements; ++i) {
282 struct nvc0_resource *res;
283 unsigned size, offset;
284
285 ve = &vertex->element[i];
286 vb = &nvc0->vtxbuf[ve->pipe.vertex_buffer_index];
287
288 if (unlikely(ve->pipe.instance_divisor)) {
289 if (!(nvc0->state.instance_elts & (1 << i))) {
290 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1);
291 }
292 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_DIVISOR(i)), 1);
293 OUT_RING (chan, ve->pipe.instance_divisor);
294 } else
295 if (unlikely(nvc0->state.instance_elts & (1 << i))) {
296 IMMED_RING(chan, RING_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 0);
297 }
298
299 res = nvc0_resource(vb->buffer);
300
301 if (nvc0->vbo_fifo || unlikely(vb->stride == 0)) {
302 if (!nvc0->vbo_fifo)
303 nvc0_emit_vtxattr(nvc0, vb, &ve->pipe, i);
304 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
305 OUT_RING (chan, 0);
306 continue;
307 }
308
309 size = vb->buffer->width0;
310 offset = ve->pipe.src_offset + vb->buffer_offset;
311
312 MARK_RING (chan, 8, 4);
313 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
314 OUT_RING (chan, (1 << 12) | vb->stride);
315 BEGIN_RING_1I(chan, RING_3D(VERTEX_ARRAY_SELECT), 5);
316 OUT_RING (chan, i);
317 OUT_RESRCh(chan, res, size - 1, NOUVEAU_BO_RD);
318 OUT_RESRCl(chan, res, size - 1, NOUVEAU_BO_RD);
319 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
320 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
321 }
322 for (; i < nvc0->state.num_vtxelts; ++i) {
323 BEGIN_RING(chan, RING_3D(VERTEX_ATTRIB_FORMAT(i)), 1);
324 OUT_RING (chan, NVC0_3D_VERTEX_ATTRIB_INACTIVE);
325 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FETCH(i)), 1);
326 OUT_RING (chan, 0);
327 }
328
329 nvc0->state.num_vtxelts = vertex->num_elements;
330 nvc0->state.instance_elts = vertex->instance_elts;
331 }
332
333 #define NVC0_PRIM_GL_CASE(n) \
334 case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n
335
336 static INLINE unsigned
337 nvc0_prim_gl(unsigned prim)
338 {
339 switch (prim) {
340 NVC0_PRIM_GL_CASE(POINTS);
341 NVC0_PRIM_GL_CASE(LINES);
342 NVC0_PRIM_GL_CASE(LINE_LOOP);
343 NVC0_PRIM_GL_CASE(LINE_STRIP);
344 NVC0_PRIM_GL_CASE(TRIANGLES);
345 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP);
346 NVC0_PRIM_GL_CASE(TRIANGLE_FAN);
347 NVC0_PRIM_GL_CASE(QUADS);
348 NVC0_PRIM_GL_CASE(QUAD_STRIP);
349 NVC0_PRIM_GL_CASE(POLYGON);
350 NVC0_PRIM_GL_CASE(LINES_ADJACENCY);
351 NVC0_PRIM_GL_CASE(LINE_STRIP_ADJACENCY);
352 NVC0_PRIM_GL_CASE(TRIANGLES_ADJACENCY);
353 NVC0_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY);
354 /*
355 NVC0_PRIM_GL_CASE(PATCHES); */
356 default:
357 return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS;
358 break;
359 }
360 }
361
362 static void
363 nvc0_draw_vbo_flush_notify(struct nouveau_channel *chan)
364 {
365 struct nvc0_context *nvc0 = chan->user_private;
366
367 nvc0_bufctx_emit_relocs(nvc0);
368 }
369
370 static void
371 nvc0_draw_arrays(struct nvc0_context *nvc0,
372 unsigned mode, unsigned start, unsigned count,
373 unsigned instance_count)
374 {
375 struct nouveau_channel *chan = nvc0->screen->base.channel;
376 unsigned prim;
377
378 chan->flush_notify = nvc0_draw_vbo_flush_notify;
379 chan->user_private = nvc0;
380
381 prim = nvc0_prim_gl(mode);
382
383 while (instance_count--) {
384 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
385 OUT_RING (chan, prim);
386 BEGIN_RING(chan, RING_3D(VERTEX_BUFFER_FIRST), 2);
387 OUT_RING (chan, start);
388 OUT_RING (chan, count);
389 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
390
391 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
392 }
393
394 chan->flush_notify = NULL;
395 }
396
397 static void
398 nvc0_draw_elements_inline_u08(struct nouveau_channel *chan, uint8_t *map,
399 unsigned start, unsigned count)
400 {
401 map += start;
402
403 if (count & 3) {
404 unsigned i;
405 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), count & 3);
406 for (i = 0; i < (count & 3); ++i)
407 OUT_RING(chan, *map++);
408 count &= ~3;
409 }
410 while (count) {
411 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4;
412
413 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U8), nr);
414 for (i = 0; i < nr; ++i) {
415 OUT_RING(chan,
416 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]);
417 map += 4;
418 }
419 count -= nr * 4;
420 }
421 }
422
423 static void
424 nvc0_draw_elements_inline_u16(struct nouveau_channel *chan, uint16_t *map,
425 unsigned start, unsigned count)
426 {
427 map += start;
428
429 if (count & 1) {
430 count &= ~1;
431 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
432 OUT_RING (chan, *map++);
433 }
434 while (count) {
435 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
436
437 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
438 for (i = 0; i < nr; ++i) {
439 OUT_RING(chan, (map[1] << 16) | map[0]);
440 map += 2;
441 }
442 count -= nr * 2;
443 }
444 }
445
446 static void
447 nvc0_draw_elements_inline_u32(struct nouveau_channel *chan, uint32_t *map,
448 unsigned start, unsigned count)
449 {
450 map += start;
451
452 while (count) {
453 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
454
455 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U32), nr);
456 OUT_RINGp (chan, map, nr);
457
458 map += nr;
459 count -= nr;
460 }
461 }
462
463 static void
464 nvc0_draw_elements_inline_u32_short(struct nouveau_channel *chan, uint32_t *map,
465 unsigned start, unsigned count)
466 {
467 map += start;
468
469 if (count & 1) {
470 count--;
471 BEGIN_RING(chan, RING_3D(VB_ELEMENT_U32), 1);
472 OUT_RING (chan, *map++);
473 }
474 while (count) {
475 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2;
476
477 BEGIN_RING_NI(chan, RING_3D(VB_ELEMENT_U16), nr);
478 for (i = 0; i < nr; ++i) {
479 OUT_RING(chan, (map[1] << 16) | map[0]);
480 map += 2;
481 }
482 count -= nr * 2;
483 }
484 }
485
486 static void
487 nvc0_draw_elements(struct nvc0_context *nvc0, boolean shorten,
488 unsigned mode, unsigned start, unsigned count,
489 unsigned instance_count, int32_t index_bias)
490 {
491 struct nouveau_channel *chan = nvc0->screen->base.channel;
492 void *data;
493 unsigned prim;
494 const unsigned index_size = nvc0->idxbuf.index_size;
495
496 chan->flush_notify = nvc0_draw_vbo_flush_notify;
497 chan->user_private = nvc0;
498
499 prim = nvc0_prim_gl(mode);
500
501 if (index_bias != nvc0->state.index_bias) {
502 BEGIN_RING(chan, RING_3D(VB_ELEMENT_BASE), 1);
503 OUT_RING (chan, index_bias);
504 nvc0->state.index_bias = index_bias;
505 }
506
507 if (nvc0_resource_mapped_by_gpu(nvc0->idxbuf.buffer)) {
508 struct nvc0_resource *res = nvc0_resource(nvc0->idxbuf.buffer);
509 unsigned offset = nvc0->idxbuf.offset;
510 unsigned limit = nvc0->idxbuf.buffer->width0 - 1;
511
512 nvc0_buffer_adjust_score(nvc0, res, 1);
513
514 while (instance_count--) {
515 MARK_RING (chan, 11, 4);
516 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
517 OUT_RING (chan, mode);
518 BEGIN_RING(chan, RING_3D(INDEX_ARRAY_START_HIGH), 7);
519 OUT_RESRCh(chan, res, offset, NOUVEAU_BO_RD);
520 OUT_RESRCl(chan, res, offset, NOUVEAU_BO_RD);
521 OUT_RESRCh(chan, res, limit, NOUVEAU_BO_RD);
522 OUT_RESRCl(chan, res, limit, NOUVEAU_BO_RD);
523 OUT_RING (chan, index_size >> 1);
524 OUT_RING (chan, start);
525 OUT_RING (chan, count);
526 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
527
528 nvc0_resource_fence(res, NOUVEAU_BO_RD);
529
530 mode |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
531 }
532 } else {
533 data = nvc0_resource_map_offset(nvc0, nvc0_resource(nvc0->idxbuf.buffer),
534 nvc0->idxbuf.offset, NOUVEAU_BO_RD);
535 if (!data)
536 return;
537
538 while (instance_count--) {
539 BEGIN_RING(chan, RING_3D(VERTEX_BEGIN_GL), 1);
540 OUT_RING (chan, prim);
541 switch (index_size) {
542 case 1:
543 nvc0_draw_elements_inline_u08(chan, data, start, count);
544 break;
545 case 2:
546 nvc0_draw_elements_inline_u16(chan, data, start, count);
547 break;
548 case 4:
549 if (shorten)
550 nvc0_draw_elements_inline_u32_short(chan, data, start, count);
551 else
552 nvc0_draw_elements_inline_u32(chan, data, start, count);
553 break;
554 default:
555 assert(0);
556 return;
557 }
558 IMMED_RING(chan, RING_3D(VERTEX_END_GL), 0);
559
560 prim |= NVC0_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT;
561 }
562 }
563
564 chan->flush_notify = NULL;
565 }
566
567 void
568 nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
569 {
570 struct nvc0_context *nvc0 = nvc0_context(pipe);
571 struct nouveau_channel *chan = nvc0->screen->base.channel;
572
573 /* For picking only a few vertices from a large user buffer, push is better,
574 * if index count is larger and we expect repeated vertices, suggest upload.
575 */
576 nvc0->vbo_push_hint = /* the 64 is heuristic */
577 !(info->indexed &&
578 ((info->max_index - info->min_index + 64) < info->count));
579
580 nvc0->vbo_min_index = info->min_index;
581 nvc0->vbo_max_index = info->max_index;
582
583 if (nvc0->vbo_push_hint != !!nvc0->vbo_fifo)
584 nvc0->dirty |= NVC0_NEW_ARRAYS;
585
586 if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_VERTEX | NVC0_NEW_ARRAYS)))
587 nvc0_update_user_vbufs(nvc0);
588
589 nvc0_state_validate(nvc0);
590
591 if (nvc0->vbo_fifo) {
592 nvc0_push_vbo(nvc0, info);
593 return;
594 }
595
596 if (nvc0->state.instance_base != info->start_instance) {
597 nvc0->state.instance_base = info->start_instance;
598 /* NOTE: this does not affect the shader input, should it ? */
599 BEGIN_RING(chan, RING_3D(VB_INSTANCE_BASE), 1);
600 OUT_RING (chan, info->start_instance);
601 }
602
603 if (nvc0->vbo_dirty) {
604 BEGIN_RING(chan, RING_3D(VERTEX_ARRAY_FLUSH), 1);
605 OUT_RING (chan, 0);
606 nvc0->vbo_dirty = FALSE;
607 }
608
609 if (!info->indexed) {
610 nvc0_draw_arrays(nvc0,
611 info->mode, info->start, info->count,
612 info->instance_count);
613 } else {
614 boolean shorten = info->max_index <= 65535;
615
616 assert(nvc0->idxbuf.buffer);
617
618 if (info->primitive_restart != nvc0->state.prim_restart) {
619 if (info->primitive_restart) {
620 BEGIN_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 2);
621 OUT_RING (chan, 1);
622 OUT_RING (chan, info->restart_index);
623
624 if (info->restart_index > 65535)
625 shorten = FALSE;
626 } else {
627 IMMED_RING(chan, RING_3D(PRIM_RESTART_ENABLE), 0);
628 }
629 nvc0->state.prim_restart = info->primitive_restart;
630 } else
631 if (info->primitive_restart) {
632 BEGIN_RING(chan, RING_3D(PRIM_RESTART_INDEX), 1);
633 OUT_RING (chan, info->restart_index);
634
635 if (info->restart_index > 65535)
636 shorten = FALSE;
637 }
638
639 nvc0_draw_elements(nvc0, shorten,
640 info->mode, info->start, info->count,
641 info->instance_count, info->index_bias);
642 }
643
644 nvc0_release_user_vbufs(nvc0);
645 }