src/gallium/drivers/nvc0/nve4_compute.c

   1 /*
   2  * Copyright 2012 Nouveau Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Christoph Bumiller
  23  */
  24
  25 #include "nvc0_context.h"
  26 #include "nvc0_compute.h"
  27 #include "nve4_compute.h"
  28
  29 #include "nv50/codegen/nv50_ir_driver.h"
  30
  31 #ifdef DEBUG
  32 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
  33 #endif
  34
  35
  36 int
  37 nve4_screen_compute_setup(struct nvc0_screen *screen,
  38                           struct nouveau_pushbuf *push)
  39 {
  40    struct nouveau_device *dev = screen->base.device;
  41    struct nouveau_object *chan = screen->base.channel;
  42    unsigned i;
  43    int ret;
  44    uint32_t obj_class;
  45
  46    switch (dev->chipset & 0xf0) {
  47    case 0xf0:
  48       obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
  49       break;
  50    case 0xe0:
  51       obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
  52       break;
  53    default:
  54       NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
  55       return -1;
  56    }
  57
  58    ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
  59                             &screen->compute);
  60    if (ret) {
  61       NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
  62       return ret;
  63    }
  64
  65    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, NVE4_CP_PARAM_SIZE, NULL,
  66                         &screen->parm);
  67    if (ret)
  68       return ret;
  69
  70    BEGIN_NVC0(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1);
  71    PUSH_DATA (push, screen->compute->oclass);
  72
  73    BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_ADDRESS_HIGH), 2);
  74    PUSH_DATAh(push, screen->tls->offset);
  75    PUSH_DATA (push, screen->tls->offset);
  76    /* No idea why there are 2. Divide size by 2 to be safe.
  77     * Actually this might be per-MP TEMP size and looks like I'm only using
  78     * 2 MPs instead of all 8.
  79     */
  80    BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(0)), 3);
  81    PUSH_DATAh(push, screen->tls->size / screen->mp_count);
  82    PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
  83    PUSH_DATA (push, 0xff);
  84    BEGIN_NVC0(push, NVE4_COMPUTE(MP_TEMP_SIZE_HIGH(1)), 3);
  85    PUSH_DATAh(push, screen->tls->size / screen->mp_count);
  86    PUSH_DATA (push, (screen->tls->size / screen->mp_count) & ~0x7fff);
  87    PUSH_DATA (push, 0xff);
  88
  89    /* Unified address space ? Who needs that ? Certainly not OpenCL.
  90     *
  91     * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
  92     *  accessible. We cannot prevent that at the moment, so expect failure.
  93     */
  94    BEGIN_NVC0(push, NVE4_COMPUTE(LOCAL_BASE), 1);
  95    PUSH_DATA (push, 1 << 24);
  96    BEGIN_NVC0(push, NVE4_COMPUTE(SHARED_BASE), 1);
  97    PUSH_DATA (push, 2 << 24);
  98
  99    BEGIN_NVC0(push, NVE4_COMPUTE(CODE_ADDRESS_HIGH), 2);
 100    PUSH_DATAh(push, screen->text->offset);
 101    PUSH_DATA (push, screen->text->offset);
 102
 103    BEGIN_NVC0(push, SUBC_COMPUTE(0x0310), 1);
 104    PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
 105
 106    /* NOTE: these do not affect the state used by the 3D object */
 107    BEGIN_NVC0(push, NVE4_COMPUTE(TIC_ADDRESS_HIGH), 3);
 108    PUSH_DATAh(push, screen->txc->offset);
 109    PUSH_DATA (push, screen->txc->offset);
 110    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 111    BEGIN_NVC0(push, NVE4_COMPUTE(TSC_ADDRESS_HIGH), 3);
 112    PUSH_DATAh(push, screen->txc->offset + 65536);
 113    PUSH_DATA (push, screen->txc->offset + 65536);
 114    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 115
 116    if (obj_class >= NVF0_COMPUTE_CLASS) {
 117       BEGIN_NVC0(push, SUBC_COMPUTE(0x0248), 1);
 118       PUSH_DATA (push, 0x100);
 119       BEGIN_NIC0(push, SUBC_COMPUTE(0x0248), 63);
 120       for (i = 63; i >= 1; --i)
 121          PUSH_DATA(push, 0x38000 | i);
 122       IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0);
 123       IMMED_NVC0(push, SUBC_COMPUTE(0x518), 0);
 124    }
 125
 126    BEGIN_NVC0(push, NVE4_COMPUTE(TEX_CB_INDEX), 1);
 127    PUSH_DATA (push, 0); /* does not interefere with 3D */
 128
 129    if (obj_class >= NVF0_COMPUTE_CLASS)
 130       IMMED_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
 131
 132    /* MS sample coordinate offsets: these do not work with _ALT modes ! */
 133    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 134    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
 135    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
 136    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 137    PUSH_DATA (push, 64);
 138    PUSH_DATA (push, 1);
 139    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
 140    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 141    PUSH_DATA (push, 0); /* 0 */
 142    PUSH_DATA (push, 0);
 143    PUSH_DATA (push, 1); /* 1 */
 144    PUSH_DATA (push, 0);
 145    PUSH_DATA (push, 0); /* 2 */
 146    PUSH_DATA (push, 1);
 147    PUSH_DATA (push, 1); /* 3 */
 148    PUSH_DATA (push, 1);
 149    PUSH_DATA (push, 2); /* 4 */
 150    PUSH_DATA (push, 0);
 151    PUSH_DATA (push, 3); /* 5 */
 152    PUSH_DATA (push, 0);
 153    PUSH_DATA (push, 2); /* 6 */
 154    PUSH_DATA (push, 1);
 155    PUSH_DATA (push, 3); /* 7 */
 156    PUSH_DATA (push, 1);
 157
 158 #ifdef DEBUG
 159    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 160    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
 161    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
 162    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 163    PUSH_DATA (push, 28);
 164    PUSH_DATA (push, 1);
 165    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 8);
 166    PUSH_DATA (push, 1);
 167    PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
 168    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
 169    PUSH_DATA (push, screen->tls->offset);
 170    PUSH_DATAh(push, screen->tls->offset);
 171    PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */
 172    PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */
 173    PUSH_DATA (push, 0); /* warp cfstack size */
 174 #endif
 175
 176    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 177    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 178
 179    return 0;
 180 }
 181
 182
 183 static void
 184 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
 185 {
 186    struct nvc0_screen *screen = nvc0->screen;
 187    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 188    struct nv50_surface *sf;
 189    struct nv04_resource *res;
 190    uint32_t mask;
 191    unsigned i;
 192    const unsigned t = 1;
 193
 194    mask = nvc0->surfaces_dirty[t];
 195    while (mask) {
 196       i = ffs(mask) - 1;
 197       mask &= ~(1 << i);
 198
 199       /*
 200        * NVE4's surface load/store instructions receive all the information
 201        * directly instead of via binding points, so we have to supply them.
 202        */
 203       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 204       PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
 205       PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
 206       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 207       PUSH_DATA (push, 64);
 208       PUSH_DATA (push, 1);
 209       BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
 210       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 211
 212       nve4_set_surface_info(push, nvc0->surfaces[t][i], screen);
 213
 214       sf = nv50_surface(nvc0->surfaces[t][i]);
 215       if (sf) {
 216          res = nv04_resource(sf->base.texture);
 217
 218          if (sf->base.writable)
 219             BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
 220          else
 221             BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
 222       }
 223    }
 224    if (nvc0->surfaces_dirty[t]) {
 225       BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 226       PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 227    }
 228
 229    /* re-reference non-dirty surfaces */
 230    mask = nvc0->surfaces_valid[t] & ~nvc0->surfaces_dirty[t];
 231    while (mask) {
 232       i = ffs(mask) - 1;
 233       mask &= ~(1 << i);
 234
 235       sf = nv50_surface(nvc0->surfaces[t][i]);
 236       res = nv04_resource(sf->base.texture);
 237
 238       if (sf->base.writable)
 239          BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
 240       else
 241          BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
 242    }
 243
 244    nvc0->surfaces_dirty[t] = 0;
 245 }
 246
 247
 248 /* Thankfully, textures with samplers follow the normal rules. */
 249 static void
 250 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
 251 {
 252    boolean need_flush = nve4_validate_tsc(nvc0, 5);
 253    if (need_flush) {
 254       BEGIN_NVC0(nvc0->base.pushbuf, NVE4_COMPUTE(TSC_FLUSH), 1);
 255       PUSH_DATA (nvc0->base.pushbuf, 0);
 256    }
 257 }
 258 /* (Code duplicated at bottom for various non-convincing reasons.
 259  *  E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
 260  *  entries to avoid a subchannel switch.
 261  *  Same for texture cache flushes.
 262  *  Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
 263  */
 264 static void nve4_compute_validate_textures(struct nvc0_context *);
 265
 266 static void
 267 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
 268 {
 269    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 270    uint64_t address;
 271    const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
 272    unsigned i, n;
 273    uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
 274
 275    if (!dirty)
 276       return;
 277    i = ffs(dirty) - 1;
 278    n = util_logbase2(dirty) + 1 - i;
 279    assert(n);
 280
 281    address = nvc0->screen->parm->offset + NVE4_CP_INPUT_TEX(i);
 282
 283    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 284    PUSH_DATAh(push, address);
 285    PUSH_DATA (push, address);
 286    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 287    PUSH_DATA (push, n * 4);
 288    PUSH_DATA (push, 0x1);
 289    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + n);
 290    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 291    PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
 292
 293    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 294    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 295
 296    nvc0->textures_dirty[s] = 0;
 297    nvc0->samplers_dirty[s] = 0;
 298 }
 299
 300
 301 static boolean
 302 nve4_compute_state_validate(struct nvc0_context *nvc0)
 303 {
 304    if (!nvc0_compute_validate_program(nvc0))
 305       return FALSE;
 306    if (nvc0->dirty_cp & NVC0_NEW_CP_TEXTURES)
 307       nve4_compute_validate_textures(nvc0);
 308    if (nvc0->dirty_cp & NVC0_NEW_CP_SAMPLERS)
 309       nve4_compute_validate_samplers(nvc0);
 310    if (nvc0->dirty_cp & (NVC0_NEW_CP_TEXTURES | NVC0_NEW_CP_SAMPLERS))
 311        nve4_compute_set_tex_handles(nvc0);
 312    if (nvc0->dirty_cp & NVC0_NEW_CP_SURFACES)
 313       nve4_compute_validate_surfaces(nvc0);
 314    if (nvc0->dirty_cp & NVC0_NEW_CP_GLOBALS)
 315       nvc0_validate_global_residents(nvc0,
 316                                      nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
 317
 318    nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, FALSE);
 319
 320    nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_cp);
 321    if (unlikely(nouveau_pushbuf_validate(nvc0->base.pushbuf)))
 322       return FALSE;
 323    if (unlikely(nvc0->state.flushed))
 324       nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, TRUE);
 325
 326    return TRUE;
 327 }
 328
 329
 330 static void
 331 nve4_compute_upload_input(struct nvc0_context *nvc0, const void *input,
 332                           const uint *block_layout,
 333                           const uint *grid_layout)
 334 {
 335    struct nvc0_screen *screen = nvc0->screen;
 336    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 337    struct nvc0_program *cp = nvc0->compprog;
 338
 339    if (cp->parm_size) {
 340       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 341       PUSH_DATAh(push, screen->parm->offset);
 342       PUSH_DATA (push, screen->parm->offset);
 343       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 344       PUSH_DATA (push, cp->parm_size);
 345       PUSH_DATA (push, 0x1);
 346       BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
 347       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 348       PUSH_DATAp(push, input, cp->parm_size / 4);
 349    }
 350    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 351    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
 352    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
 353    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 354    PUSH_DATA (push, 7 * 4);
 355    PUSH_DATA (push, 0x1);
 356    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + 7);
 357    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 358    PUSH_DATAp(push, block_layout, 3);
 359    PUSH_DATAp(push, grid_layout, 3);
 360    PUSH_DATA (push, 0);
 361
 362    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 363    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 364 }
 365
 366 static INLINE uint8_t
 367 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
 368 {
 369    if (shared_size > (32 << 10))
 370       return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
 371    if (shared_size > (16 << 10))
 372       return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
 373    return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
 374 }
 375
 376 static void
 377 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
 378                                struct nve4_cp_launch_desc *desc,
 379                                uint32_t label,
 380                                const uint *block_layout,
 381                                const uint *grid_layout)
 382 {
 383    const struct nvc0_screen *screen = nvc0->screen;
 384    const struct nvc0_program *cp = nvc0->compprog;
 385    unsigned i;
 386
 387    nve4_cp_launch_desc_init_default(desc);
 388
 389    desc->entry = nvc0_program_symbol_offset(cp, label);
 390
 391    desc->griddim_x = grid_layout[0];
 392    desc->griddim_y = grid_layout[1];
 393    desc->griddim_z = grid_layout[2];
 394    desc->blockdim_x = block_layout[0];
 395    desc->blockdim_y = block_layout[1];
 396    desc->blockdim_z = block_layout[2];
 397
 398    desc->shared_size = align(cp->cp.smem_size, 0x100);
 399    desc->local_size_p = align(cp->cp.lmem_size, 0x10);
 400    desc->local_size_n = 0;
 401    desc->cstack_size = 0x800;
 402    desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
 403
 404    desc->gpr_alloc = cp->num_gprs;
 405    desc->bar_alloc = cp->num_barriers;
 406
 407    for (i = 0; i < 7; ++i) {
 408       const unsigned s = 5;
 409       if (nvc0->constbuf[s][i].u.buf)
 410          nve4_cp_launch_desc_set_ctx_cb(desc, i + 1, &nvc0->constbuf[s][i]);
 411    }
 412    nve4_cp_launch_desc_set_cb(desc, 0, screen->parm, 0, NVE4_CP_INPUT_SIZE);
 413 }
 414
 415 static INLINE struct nve4_cp_launch_desc *
 416 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
 417                                struct nouveau_bo **pbo, uint64_t *pgpuaddr)
 418 {
 419    uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
 420    if (!ptr)
 421       return NULL;
 422    if (*pgpuaddr & 255) {
 423       unsigned adj = 256 - (*pgpuaddr & 255);
 424       ptr += adj;
 425       *pgpuaddr += adj;
 426    }
 427    return (struct nve4_cp_launch_desc *)ptr;
 428 }
 429
 430 void
 431 nve4_launch_grid(struct pipe_context *pipe,
 432                  const uint *block_layout, const uint *grid_layout,
 433                  uint32_t label,
 434                  const void *input)
 435 {
 436    struct nvc0_context *nvc0 = nvc0_context(pipe);
 437    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 438    struct nve4_cp_launch_desc *desc;
 439    uint64_t desc_gpuaddr;
 440    struct nouveau_bo *desc_bo;
 441    int ret;
 442
 443    desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
 444    if (!desc) {
 445       ret = -1;
 446       goto out;
 447    }
 448    BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
 449                 desc_bo);
 450
 451    ret = !nve4_compute_state_validate(nvc0);
 452    if (ret)
 453       goto out;
 454
 455    nve4_compute_setup_launch_desc(nvc0, desc, label, block_layout, grid_layout);
 456 #ifdef DEBUG
 457    if (debug_get_num_option("NV50_PROG_DEBUG", 0))
 458       nve4_compute_dump_launch_desc(desc);
 459 #endif
 460
 461    nve4_compute_upload_input(nvc0, input, block_layout, grid_layout);
 462
 463    /* upload descriptor and flush */
 464 #if 0
 465    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 466    PUSH_DATAh(push, desc_gpuaddr);
 467    PUSH_DATA (push, desc_gpuaddr);
 468    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 469    PUSH_DATA (push, 256);
 470    PUSH_DATA (push, 1);
 471    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (256 / 4));
 472    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x08 << 1));
 473    PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
 474    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 475    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB | NVE4_COMPUTE_FLUSH_CODE);
 476 #endif
 477    BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH_DESC_ADDRESS), 1);
 478    PUSH_DATA (push, desc_gpuaddr >> 8);
 479    BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH), 1);
 480    PUSH_DATA (push, 0x3);
 481    BEGIN_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 1);
 482    PUSH_DATA (push, 0);
 483
 484 out:
 485    if (ret)
 486       NOUVEAU_ERR("Failed to launch grid !\n");
 487    nouveau_scratch_done(&nvc0->base);
 488    nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
 489 }
 490
 491
 492 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
 493
 494 static void
 495 nve4_compute_validate_textures(struct nvc0_context *nvc0)
 496 {
 497    struct nouveau_bo *txc = nvc0->screen->txc;
 498    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 499    const unsigned s = 5;
 500    unsigned i;
 501    uint32_t commands[2][NVE4_CP_INPUT_TEX_MAX];
 502    unsigned n[2] = { 0, 0 };
 503
 504    for (i = 0; i < nvc0->num_textures[s]; ++i) {
 505       struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
 506       struct nv04_resource *res;
 507       const boolean dirty = !!(nvc0->textures_dirty[s] & (1 << i));
 508
 509       if (!tic) {
 510          nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
 511          continue;
 512       }
 513       res = nv04_resource(tic->pipe.texture);
 514
 515       if (tic->id < 0) {
 516          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 517
 518          PUSH_SPACE(push, 16);
 519          BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_DST_ADDRESS_HIGH), 2);
 520          PUSH_DATAh(push, txc->offset + (tic->id * 32));
 521          PUSH_DATA (push, txc->offset + (tic->id * 32));
 522          BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_LINE_LENGTH_IN), 2);
 523          PUSH_DATA (push, 32);
 524          PUSH_DATA (push, 1);
 525          BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 9);
 526          PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
 527          PUSH_DATAp(push, &tic->tic[0], 8);
 528
 529          commands[0][n[0]++] = (tic->id << 4) | 1;
 530       } else
 531       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 532          commands[1][n[1]++] = (tic->id << 4) | 1;
 533       }
 534       nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
 535
 536       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 537       res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
 538
 539       nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
 540       nvc0->tex_handles[s][i] |= tic->id;
 541       if (dirty)
 542          BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
 543    }
 544    for (; i < nvc0->state.num_textures[s]; ++i)
 545       nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
 546
 547    if (n[0]) {
 548       BEGIN_NIC0(push, NVE4_COMPUTE(TIC_FLUSH), n[0]);
 549       PUSH_DATAp(push, commands[0], n[0]);
 550    }
 551    if (n[1]) {
 552       BEGIN_NIC0(push, NVE4_COMPUTE(TEX_CACHE_CTL), n[1]);
 553       PUSH_DATAp(push, commands[1], n[1]);
 554    }
 555
 556    nvc0->state.num_textures[s] = nvc0->num_textures[s];
 557 }
 558
 559
 560 #ifdef DEBUG
 561 static const char *nve4_cache_split_name(unsigned value)
 562 {
 563    switch (value) {
 564    case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
 565    case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
 566    case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
 567    default:
 568       return "(invalid)";
 569    }
 570 }
 571
 572 static void
 573 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
 574 {
 575    const uint32_t *data = (const uint32_t *)desc;
 576    unsigned i;
 577    boolean zero = FALSE;
 578
 579    debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
 580
 581    for (i = 0; i < sizeof(*desc); i += 4) {
 582       if (data[i / 4]) {
 583          debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
 584          zero = FALSE;
 585       } else
 586       if (!zero) {
 587          debug_printf("...\n");
 588          zero = TRUE;
 589       }
 590    }
 591
 592    debug_printf("entry = 0x%x\n", desc->entry);
 593    debug_printf("grid dimensions = %ux%ux%u\n",
 594                 desc->griddim_x, desc->griddim_y, desc->griddim_z);
 595    debug_printf("block dimensions = %ux%ux%u\n",
 596                 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
 597    debug_printf("s[] size: 0x%x\n", desc->shared_size);
 598    debug_printf("l[] size: -0x%x / +0x%x\n",
 599                 desc->local_size_n, desc->local_size_p);
 600    debug_printf("stack size: 0x%x\n", desc->cstack_size);
 601    debug_printf("barrier count: %u\n", desc->bar_alloc);
 602    debug_printf("$r count: %u\n", desc->gpr_alloc);
 603    debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
 604
 605    for (i = 0; i < 8; ++i) {
 606       uint64_t address;
 607       uint32_t size = desc->cb[i].size;
 608       boolean valid = !!(desc->cb_mask & (1 << i));
 609
 610       address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
 611
 612       if (!valid && !address && !size)
 613          continue;
 614       debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
 615                    i, address, size, valid ? "" : "  (invalid)");
 616    }
 617 }
 618 #endif
 619
 620 #ifdef NOUVEAU_NVE4_MP_TRAP_HANDLER
 621 static void
 622 nve4_compute_trap_info(struct nvc0_context *nvc0)
 623 {
 624    struct nvc0_screen *screen = nvc0->screen;
 625    struct nouveau_bo *bo = screen->parm;
 626    int ret, i;
 627    volatile struct nve4_mp_trap_info *info;
 628    uint8_t *map;
 629
 630    ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client);
 631    if (ret)
 632       return;
 633    map = (uint8_t *)bo->map;
 634    info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO);
 635
 636    if (info->lock) {
 637       debug_printf("trapstat = %08x\n", info->trapstat);
 638       debug_printf("warperr = %08x\n", info->warperr);
 639       debug_printf("PC = %x\n", info->pc);
 640       debug_printf("tid = %u %u %u\n",
 641                    info->tid[0], info->tid[1], info->tid[2]);
 642       debug_printf("ctaid = %u %u %u\n",
 643                    info->ctaid[0], info->ctaid[1], info->ctaid[2]);
 644       for (i = 0; i <= 63; ++i)
 645          debug_printf("$r%i = %08x\n", i, info->r[i]);
 646       for (i = 0; i <= 6; ++i)
 647          debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1);
 648       debug_printf("$c = %x\n", info->flags >> 12);
 649    }
 650    info->lock = 0;
 651 }
 652 #endif