src/gallium/drivers/nvc0/nve4_compute.c

   1 /*
   2  * Copyright 2012 Nouveau Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  * Authors: Christoph Bumiller
  23  */
  24
  25 #include "nvc0_context.h"
  26 #include "nve4_compute.h"
  27
  28 #include "nv50/codegen/nv50_ir_driver.h"
  29
  30 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
  31
  32
  33 int
  34 nve4_screen_compute_setup(struct nvc0_screen *screen,
  35                           struct nouveau_pushbuf *push)
  36 {
  37    struct nouveau_device *dev = screen->base.device;
  38    struct nouveau_object *chan = screen->base.channel;
  39    unsigned i;
  40    int ret;
  41    uint32_t obj_class;
  42
  43    switch (dev->chipset & 0xf0) {
  44    case 0xf0:
  45       obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
  46       break;
  47    case 0xe0:
  48       obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
  49       break;
  50    default:
  51       NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
  52       break;
  53    }
  54
  55    ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
  56                             &screen->compute);
  57    if (ret) {
  58       NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
  59       return ret;
  60    }
  61
  62    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, NVE4_CP_PARAM_SIZE, NULL,
  63                         &screen->parm);
  64    if (ret)
  65       return ret;
  66
  67    BEGIN_NVC0(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1);
  68    PUSH_DATA (push, screen->compute->oclass);
  69
  70    BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_ADDRESS_HIGH), 2);
  71    PUSH_DATAh(push, screen->tls->offset);
  72    PUSH_DATA (push, screen->tls->offset);
  73    /* No idea why there are 2. Divide size by 2 to be safe.
  74     * Actually this might be per-MP TEMP size and looks like I'm only using
  75     * 2 MPs instead of all 8.
  76     */
  77    BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_SIZE_HIGH(0)), 3);
  78    PUSH_DATAh(push, screen->tls_size / 2);
  79    PUSH_DATA (push, screen->tls_size / 2);
  80    PUSH_DATA (push, 0xff);
  81    BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_SIZE_HIGH(1)), 3);
  82    PUSH_DATAh(push, screen->tls_size / 2);
  83    PUSH_DATA (push, screen->tls_size / 2);
  84    PUSH_DATA (push, 0xff);
  85
  86    /* Unified address space ? Who needs that ? Certainly not OpenCL.
  87     *
  88     * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
  89     *  accessible. We cannot prevent that at the moment, so expect failure.
  90     */
  91    BEGIN_NVC0(push, NVE4_COMPUTE(LOCAL_BASE), 1);
  92    PUSH_DATA (push, 1 << 24);
  93    BEGIN_NVC0(push, NVE4_COMPUTE(SHARED_BASE), 1);
  94    PUSH_DATA (push, 2 << 24);
  95
  96    BEGIN_NVC0(push, NVE4_COMPUTE(CODE_ADDRESS_HIGH), 2);
  97    PUSH_DATAh(push, screen->text->offset);
  98    PUSH_DATA (push, screen->text->offset);
  99
 100    BEGIN_NVC0(push, SUBC_COMPUTE(0x0310), 1);
 101    PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
 102
 103    /* NOTE: these do not affect the state used by the 3D object */
 104    BEGIN_NVC0(push, NVE4_COMPUTE(TIC_ADDRESS_HIGH), 3);
 105    PUSH_DATAh(push, screen->txc->offset);
 106    PUSH_DATA (push, screen->txc->offset);
 107    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 108    BEGIN_NVC0(push, NVE4_COMPUTE(TSC_ADDRESS_HIGH), 3);
 109    PUSH_DATAh(push, screen->txc->offset + 65536);
 110    PUSH_DATA (push, screen->txc->offset + 65536);
 111    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 112
 113    if (obj_class >= NVF0_COMPUTE_CLASS) {
 114       BEGIN_NVC0(push, SUBC_COMPUTE(0x0248), 1);
 115       PUSH_DATA (push, 0x100);
 116       BEGIN_NIC0(push, SUBC_COMPUTE(0x0248), 63);
 117       for (i = 63; i >= 1; --i)
 118          PUSH_DATA(push, 0x38000 | i);
 119       IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0);
 120       IMMED_NVC0(push, SUBC_COMPUTE(0x518), 0);
 121    }
 122
 123    BEGIN_NVC0(push, NVE4_COMPUTE(TEX_CB_INDEX), 1);
 124    PUSH_DATA (push, 0); /* does not interefere with 3D */
 125
 126    if (obj_class >= NVF0_COMPUTE_CLASS)
 127       IMMED_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
 128
 129    /* MS sample coordinate offsets: these do not work with _ALT modes ! */
 130    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 131    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
 132    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
 133    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 134    PUSH_DATA (push, 64);
 135    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
 136    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
 137    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 138    PUSH_DATA (push, 0); /* 0 */
 139    PUSH_DATA (push, 0);
 140    PUSH_DATA (push, 1); /* 1 */
 141    PUSH_DATA (push, 0);
 142    PUSH_DATA (push, 0); /* 2 */
 143    PUSH_DATA (push, 1);
 144    PUSH_DATA (push, 1); /* 3 */
 145    PUSH_DATA (push, 1);
 146    PUSH_DATA (push, 2); /* 4 */
 147    PUSH_DATA (push, 0);
 148    PUSH_DATA (push, 3); /* 5 */
 149    PUSH_DATA (push, 0);
 150    PUSH_DATA (push, 2); /* 6 */
 151    PUSH_DATA (push, 1);
 152    PUSH_DATA (push, 3); /* 7 */
 153    PUSH_DATA (push, 1);
 154    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 155    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 156
 157    return 0;
 158 }
 159
 160
 161 static void
 162 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
 163 {
 164    struct nvc0_screen *screen = nvc0->screen;
 165    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 166    struct nv50_surface *sf;
 167    struct nv04_resource *res;
 168    uint32_t mask;
 169    unsigned i;
 170    const unsigned t = 1;
 171
 172    mask = nvc0->surfaces_dirty[t];
 173    while (mask) {
 174       i = ffs(mask) - 1;
 175       mask &= ~(1 << i);
 176
 177       /*
 178        * NVE4's surface load/store instructions receive all the information
 179        * directly instead of via binding points, so we have to supply them.
 180        */
 181       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 182       PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
 183       PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
 184       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 185       PUSH_DATA (push, 64);
 186       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
 187       BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
 188       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 189
 190       nve4_set_surface_info(push, nvc0->surfaces[t][i], screen);
 191
 192       sf = nv50_surface(nvc0->surfaces[t][i]);
 193       if (sf) {
 194          res = nv04_resource(sf->base.texture);
 195
 196          if (sf->base.writable)
 197             BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
 198          else
 199             BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
 200       }
 201    }
 202    if (nvc0->surfaces_dirty[t]) {
 203       BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 204       PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 205    }
 206
 207    /* re-reference non-dirty surfaces */
 208    mask = nvc0->surfaces_valid[t] & ~nvc0->surfaces_dirty[t];
 209    while (mask) {
 210       i = ffs(mask) - 1;
 211       mask &= ~(1 << i);
 212
 213       sf = nv50_surface(nvc0->surfaces[t][i]);
 214       res = nv04_resource(sf->base.texture);
 215
 216       if (sf->base.writable)
 217          BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
 218       else
 219          BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
 220    }
 221
 222    nvc0->surfaces_dirty[t] = 0;
 223 }
 224
 225
 226 /* Thankfully, textures with samplers follow the normal rules. */
 227 static void
 228 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
 229 {
 230    boolean need_flush = nve4_validate_tsc(nvc0, 5);
 231    if (need_flush) {
 232       BEGIN_NVC0(nvc0->base.pushbuf, NVE4_COMPUTE(TSC_FLUSH), 1);
 233       PUSH_DATA (nvc0->base.pushbuf, 0);
 234    }
 235 }
 236 /* (Code duplicated at bottom for various non-convincing reasons.
 237  *  E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
 238  *  entries to avoid a subchannel switch.
 239  *  Same for texture cache flushes.
 240  *  Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
 241  */
 242 static void nve4_compute_validate_textures(struct nvc0_context *);
 243
 244 static void
 245 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
 246 {
 247    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 248    uint64_t address;
 249    const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
 250    unsigned i, n;
 251    uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
 252
 253    if (!dirty)
 254       return;
 255    i = ffs(dirty) - 1;
 256    n = util_logbase2(dirty) + 1 - i;
 257    assert(n);
 258
 259    address = nvc0->screen->parm->offset + NVE4_CP_INPUT_TEX(i);
 260
 261    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 262    PUSH_DATAh(push, address);
 263    PUSH_DATA (push, address);
 264    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 265    PUSH_DATA (push, n * 4);
 266    PUSH_DATA (push, 0x1);
 267    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + n);
 268    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 269    PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
 270
 271    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 272    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 273
 274    nvc0->textures_dirty[s] = 0;
 275    nvc0->samplers_dirty[s] = 0;
 276 }
 277
 278
 279 static boolean
 280 nve4_compute_validate_program(struct nvc0_context *nvc0)
 281 {
 282    struct nvc0_program *prog = nvc0->compprog;
 283
 284    if (prog->mem)
 285       return TRUE;
 286
 287    if (!prog->translated) {
 288       prog->translated = nvc0_program_translate(
 289          prog, nvc0->screen->base.device->chipset);
 290       if (!prog->translated)
 291          return FALSE;
 292    }
 293    if (unlikely(!prog->code_size))
 294       return FALSE;
 295
 296    if (likely(prog->code_size)) {
 297       if (nvc0_program_upload_code(nvc0, prog)) {
 298          struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 299          BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 300          PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CODE);
 301          return TRUE;
 302       }
 303    }
 304    return FALSE;
 305 }
 306
 307
 308 static boolean
 309 nve4_compute_state_validate(struct nvc0_context *nvc0)
 310 {
 311    if (!nve4_compute_validate_program(nvc0))
 312       return FALSE;
 313    if (nvc0->dirty_cp & NVC0_NEW_CP_TEXTURES)
 314       nve4_compute_validate_textures(nvc0);
 315    if (nvc0->dirty_cp & NVC0_NEW_CP_SAMPLERS)
 316       nve4_compute_validate_samplers(nvc0);
 317    if (nvc0->dirty_cp & (NVC0_NEW_CP_TEXTURES | NVC0_NEW_CP_SAMPLERS))
 318        nve4_compute_set_tex_handles(nvc0);
 319    if (nvc0->dirty_cp & NVC0_NEW_CP_SURFACES)
 320       nve4_compute_validate_surfaces(nvc0);
 321    if (nvc0->dirty_cp & NVC0_NEW_CP_GLOBALS)
 322       nvc0_validate_global_residents(nvc0,
 323                                      nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
 324
 325    nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, FALSE);
 326
 327    nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_cp);
 328    if (unlikely(nouveau_pushbuf_validate(nvc0->base.pushbuf)))
 329       return FALSE;
 330    if (unlikely(nvc0->state.flushed))
 331       nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, TRUE);
 332
 333    return TRUE;
 334 }
 335
 336
 337 static void
 338 nve4_compute_upload_input(struct nvc0_context *nvc0, const void *input,
 339                           const uint *block_layout,
 340                           const uint *grid_layout)
 341 {
 342    struct nvc0_screen *screen = nvc0->screen;
 343    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 344    struct nvc0_program *cp = nvc0->compprog;
 345
 346    if (cp->parm_size) {
 347       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 348       PUSH_DATAh(push, screen->parm->offset);
 349       PUSH_DATA (push, screen->parm->offset);
 350       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 351       PUSH_DATA (push, cp->parm_size);
 352       PUSH_DATA (push, 0x1);
 353       BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
 354       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 355       PUSH_DATAp(push, input, cp->parm_size / 4);
 356    }
 357    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 358    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
 359    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
 360    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 361    PUSH_DATA (push, 7 * 4);
 362    PUSH_DATA (push, 0x1);
 363    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + 7);
 364    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 365    PUSH_DATAp(push, block_layout, 3);
 366    PUSH_DATAp(push, grid_layout, 3);
 367    PUSH_DATA (push, 0);
 368
 369    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 370    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 371 }
 372
 373 static INLINE uint8_t
 374 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
 375 {
 376    if (shared_size > (32 << 10))
 377       return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
 378    if (shared_size > (16 << 10))
 379       return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
 380    return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
 381 }
 382
 383 static void
 384 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
 385                                struct nve4_cp_launch_desc *desc,
 386                                uint32_t label,
 387                                const uint *block_layout,
 388                                const uint *grid_layout)
 389 {
 390    const struct nvc0_screen *screen = nvc0->screen;
 391    const struct nvc0_program *cp = nvc0->compprog;
 392    unsigned i;
 393
 394    nve4_cp_launch_desc_init_default(desc);
 395
 396    desc->entry = nvc0_program_symbol_offset(cp, label);
 397
 398    desc->griddim_x = grid_layout[0];
 399    desc->griddim_y = grid_layout[1];
 400    desc->griddim_z = grid_layout[2];
 401    desc->blockdim_x = block_layout[0];
 402    desc->blockdim_y = block_layout[1];
 403    desc->blockdim_z = block_layout[2];
 404
 405    desc->shared_size = align(cp->cp.smem_size, 0x100);
 406    desc->local_size_p = align(cp->cp.lmem_size, 0x10);
 407    desc->local_size_n = 0;
 408    desc->cstack_size = 0x800;
 409    desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
 410
 411    desc->gpr_alloc = cp->num_gprs;
 412    desc->bar_alloc = cp->num_barriers;
 413
 414    for (i = 0; i < 7; ++i) {
 415       const unsigned s = 5;
 416       if (nvc0->constbuf[s][i].u.buf)
 417          nve4_cp_launch_desc_set_ctx_cb(desc, i + 1, &nvc0->constbuf[s][i]);
 418    }
 419    nve4_cp_launch_desc_set_cb(desc, 0, screen->parm, 0, NVE4_CP_INPUT_SIZE);
 420 }
 421
 422 static INLINE struct nve4_cp_launch_desc *
 423 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
 424                                struct nouveau_bo **pbo, uint64_t *pgpuaddr)
 425 {
 426    uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
 427    if (!ptr)
 428       return NULL;
 429    if (*pgpuaddr & 255) {
 430       unsigned adj = 256 - (*pgpuaddr & 255);
 431       ptr += adj;
 432       *pgpuaddr += adj;
 433    }
 434    return (struct nve4_cp_launch_desc *)ptr;
 435 }
 436
 437 void
 438 nve4_launch_grid(struct pipe_context *pipe,
 439                  const uint *block_layout, const uint *grid_layout,
 440                  uint32_t label,
 441                  const void *input)
 442 {
 443    struct nvc0_context *nvc0 = nvc0_context(pipe);
 444    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 445    struct nve4_cp_launch_desc *desc;
 446    uint64_t desc_gpuaddr;
 447    struct nouveau_bo *desc_bo;
 448    int ret;
 449
 450    desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
 451    if (!desc)
 452       goto out;
 453    BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
 454                 desc_bo);
 455
 456    ret = !nve4_compute_state_validate(nvc0);
 457    if (ret)
 458       goto out;
 459
 460    nve4_compute_setup_launch_desc(nvc0, desc, label, block_layout, grid_layout);
 461    nve4_compute_dump_launch_desc(desc);
 462
 463    nve4_compute_upload_input(nvc0, input, block_layout, grid_layout);
 464
 465    /* upload descriptor and flush */
 466 #if 0
 467    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 468    PUSH_DATAh(push, desc_gpuaddr);
 469    PUSH_DATA (push, desc_gpuaddr);
 470    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 471    PUSH_DATA (push, 256);
 472    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
 473    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (256 / 4));
 474    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DESC);
 475    PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
 476    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 477    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB | NVE4_COMPUTE_FLUSH_CODE);
 478 #endif
 479    BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH_DESC_ADDRESS), 1);
 480    PUSH_DATA (push, desc_gpuaddr >> 8);
 481    BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH), 1);
 482    PUSH_DATA (push, 0x3);
 483    BEGIN_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 1);
 484    PUSH_DATA (push, 0);
 485
 486 out:
 487    if (ret)
 488       NOUVEAU_ERR("Failed to launch grid !\n");
 489    nouveau_scratch_done(&nvc0->base);
 490    nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
 491 }
 492
 493
 494 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
 495
 496 static void
 497 nve4_compute_validate_textures(struct nvc0_context *nvc0)
 498 {
 499    struct nouveau_bo *txc = nvc0->screen->txc;
 500    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 501    const unsigned s = 5;
 502    unsigned i;
 503    uint32_t commands[2][NVE4_CP_INPUT_TEX_MAX];
 504    unsigned n[2] = { 0, 0 };
 505
 506    for (i = 0; i < nvc0->num_textures[s]; ++i) {
 507       struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
 508       struct nv04_resource *res;
 509       const boolean dirty = !!(nvc0->textures_dirty[s] & (1 << i));
 510
 511       if (!tic) {
 512          nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
 513          continue;
 514       }
 515       res = nv04_resource(tic->pipe.texture);
 516
 517       if (tic->id < 0) {
 518          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 519
 520          PUSH_SPACE(push, 16);
 521          BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 522          PUSH_DATAh(push, txc->offset + (tic->id * 32));
 523          PUSH_DATA (push, txc->offset + (tic->id * 32));
 524          BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 525          PUSH_DATA (push, 32);
 526          PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
 527          BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 9);
 528          PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 529          PUSH_DATAp(push, &tic->tic[0], 8);
 530
 531          commands[0][n[0]++] = (tic->id << 4) | 1;
 532       } else
 533       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 534          commands[1][n[1]++] = (tic->id << 4) | 1;
 535       }
 536       nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
 537
 538       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 539       res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
 540
 541       nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
 542       nvc0->tex_handles[s][i] |= tic->id;
 543       if (dirty)
 544          BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
 545    }
 546    for (; i < nvc0->state.num_textures[s]; ++i)
 547       nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
 548
 549    if (n[0]) {
 550       BEGIN_NIC0(push, NVE4_COMPUTE(TIC_FLUSH), n[0]);
 551       PUSH_DATAp(push, commands[0], n[0]);
 552    }
 553    if (n[1]) {
 554       BEGIN_NIC0(push, NVE4_COMPUTE(TEX_CACHE_CTL), n[1]);
 555       PUSH_DATAp(push, commands[1], n[1]);
 556    }
 557
 558    nvc0->state.num_textures[s] = nvc0->num_textures[s];
 559 }
 560
 561
 562 static const char *nve4_cache_split_name(unsigned value)
 563 {
 564    switch (value) {
 565    case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
 566    case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
 567    case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
 568    default:
 569       return "(invalid)";
 570    }
 571 }
 572
 573 static void
 574 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
 575 {
 576    const uint32_t *data = (const uint32_t *)desc;
 577    unsigned i;
 578    boolean zero = FALSE;
 579
 580    debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
 581
 582    for (i = 0; i < sizeof(*desc); i += 4) {
 583       if (data[i / 4]) {
 584          debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
 585          zero = FALSE;
 586       } else
 587       if (!zero) {
 588          debug_printf("...\n");
 589          zero = TRUE;
 590       }
 591    }
 592
 593    debug_printf("entry = 0x%x\n", desc->entry);
 594    debug_printf("grid dimensions = %ux%ux%u\n",
 595                 desc->griddim_x, desc->griddim_y, desc->griddim_z);
 596    debug_printf("block dimensions = %ux%ux%u\n",
 597                 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
 598    debug_printf("s[] size: 0x%x\n", desc->shared_size);
 599    debug_printf("l[] size: -0x%x / +0x%x\n",
 600                 desc->local_size_n, desc->local_size_p);
 601    debug_printf("stack size: 0x%x\n", desc->cstack_size);
 602    debug_printf("barrier count: %u\n", desc->bar_alloc);
 603    debug_printf("$r count: %u\n", desc->gpr_alloc);
 604    debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
 605
 606    for (i = 0; i < 8; ++i) {
 607       uint64_t address;
 608       uint32_t size = desc->cb[i].size;
 609       boolean valid = !!(desc->cb_mask & (1 << i));
 610
 611       address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
 612
 613       if (!valid && !address && !size)
 614          continue;
 615       debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
 616                    i, address, size, valid ? "" : "  (invalid)");
 617    }
 618 }
 619