src/gallium/drivers/nvc0/nve4_compute.c

   1 /*
   2  * Copyright 2012 Nouveau Project
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  18  * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
  19  * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  20  * SOFTWARE.
  21  *
  22  * Authors: Christoph Bumiller
  23  */
  24
  25 #include "nvc0_context.h"
  26 #include "nve4_compute.h"
  27
  28 #include "nv50/codegen/nv50_ir_driver.h"
  29
  30 static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
  31
  32
  33 int
  34 nve4_screen_compute_setup(struct nvc0_screen *screen,
  35                           struct nouveau_pushbuf *push)
  36 {
  37    struct nouveau_device *dev = screen->base.device;
  38    struct nouveau_object *chan = screen->base.channel;
  39    unsigned i;
  40    int ret;
  41    uint32_t obj_class;
  42
  43    switch (dev->chipset & 0xf0) {
  44    case 0xf0:
  45       obj_class = NVF0_COMPUTE_CLASS; /* GK110 */
  46       break;
  47    case 0xe0:
  48       obj_class = NVE4_COMPUTE_CLASS; /* GK104 */
  49       break;
  50    default:
  51       NOUVEAU_ERR("unsupported chipset: NV%02x\n", dev->chipset);
  52       break;
  53    }
  54
  55    ret = nouveau_object_new(chan, 0xbeef00c0, obj_class, NULL, 0,
  56                             &screen->compute);
  57    if (ret) {
  58       NOUVEAU_ERR("Failed to allocate compute object: %d\n", ret);
  59       return ret;
  60    }
  61
  62    ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, NVE4_CP_PARAM_SIZE, NULL,
  63                         &screen->parm);
  64    if (ret)
  65       return ret;
  66
  67    BEGIN_NVC0(push, SUBC_COMPUTE(NV01_SUBCHAN_OBJECT), 1);
  68    PUSH_DATA (push, screen->compute->oclass);
  69
  70    BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_ADDRESS_HIGH), 2);
  71    PUSH_DATAh(push, screen->tls->offset);
  72    PUSH_DATA (push, screen->tls->offset);
  73    /* No idea why there are 2. Divide size by 2 to be safe.
  74     * Actually this might be per-MP TEMP size and looks like I'm only using
  75     * 2 MPs instead of all 8.
  76     */
  77    BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_SIZE_HIGH(0)), 3);
  78    PUSH_DATAh(push, screen->tls_size / 2);
  79    PUSH_DATA (push, screen->tls_size / 2);
  80    PUSH_DATA (push, 0xff);
  81    BEGIN_NVC0(push, NVE4_COMPUTE(TEMP_SIZE_HIGH(1)), 3);
  82    PUSH_DATAh(push, screen->tls_size / 2);
  83    PUSH_DATA (push, screen->tls_size / 2);
  84    PUSH_DATA (push, 0xff);
  85
  86    /* Unified address space ? Who needs that ? Certainly not OpenCL.
  87     *
  88     * FATAL: Buffers with addresses inside [0x1000000, 0x3000000] will NOT be
  89     *  accessible. We cannot prevent that at the moment, so expect failure.
  90     */
  91    BEGIN_NVC0(push, NVE4_COMPUTE(LOCAL_BASE), 1);
  92    PUSH_DATA (push, 1 << 24);
  93    BEGIN_NVC0(push, NVE4_COMPUTE(SHARED_BASE), 1);
  94    PUSH_DATA (push, 2 << 24);
  95
  96    BEGIN_NVC0(push, NVE4_COMPUTE(CODE_ADDRESS_HIGH), 2);
  97    PUSH_DATAh(push, screen->text->offset);
  98    PUSH_DATA (push, screen->text->offset);
  99
 100    BEGIN_NVC0(push, SUBC_COMPUTE(0x0310), 1);
 101    PUSH_DATA (push, (obj_class >= NVF0_COMPUTE_CLASS) ? 0x400 : 0x300);
 102
 103    /* NOTE: these do not affect the state used by the 3D object */
 104    BEGIN_NVC0(push, NVE4_COMPUTE(TIC_ADDRESS_HIGH), 3);
 105    PUSH_DATAh(push, screen->txc->offset);
 106    PUSH_DATA (push, screen->txc->offset);
 107    PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
 108    BEGIN_NVC0(push, NVE4_COMPUTE(TSC_ADDRESS_HIGH), 3);
 109    PUSH_DATAh(push, screen->txc->offset + 65536);
 110    PUSH_DATA (push, screen->txc->offset + 65536);
 111    PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 112
 113    if (obj_class >= NVF0_COMPUTE_CLASS) {
 114       BEGIN_NVC0(push, SUBC_COMPUTE(0x0248), 1);
 115       PUSH_DATA (push, 0x100);
 116       BEGIN_NIC0(push, SUBC_COMPUTE(0x0248), 63);
 117       for (i = 63; i >= 1; --i)
 118          PUSH_DATA(push, 0x38000 | i);
 119       IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0);
 120       IMMED_NVC0(push, SUBC_COMPUTE(0x518), 0);
 121    }
 122
 123    BEGIN_NVC0(push, NVE4_COMPUTE(TEX_CB_INDEX), 1);
 124    PUSH_DATA (push, 0); /* does not interefere with 3D */
 125
 126    if (obj_class >= NVF0_COMPUTE_CLASS)
 127       IMMED_NVC0(push, SUBC_COMPUTE(0x02c4), 1);
 128
 129    /* MS sample coordinate offsets: these do not work with _ALT modes ! */
 130    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 131    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
 132    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_MS_OFFSETS);
 133    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 134    PUSH_DATA (push, 64);
 135    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
 136    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
 137    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 138    PUSH_DATA (push, 0); /* 0 */
 139    PUSH_DATA (push, 0);
 140    PUSH_DATA (push, 1); /* 1 */
 141    PUSH_DATA (push, 0);
 142    PUSH_DATA (push, 0); /* 2 */
 143    PUSH_DATA (push, 1);
 144    PUSH_DATA (push, 1); /* 3 */
 145    PUSH_DATA (push, 1);
 146    PUSH_DATA (push, 2); /* 4 */
 147    PUSH_DATA (push, 0);
 148    PUSH_DATA (push, 3); /* 5 */
 149    PUSH_DATA (push, 0);
 150    PUSH_DATA (push, 2); /* 6 */
 151    PUSH_DATA (push, 1);
 152    PUSH_DATA (push, 3); /* 7 */
 153    PUSH_DATA (push, 1);
 154
 155 #ifdef DEBUG
 156    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 157    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
 158    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_TRAP_INFO_PTR);
 159    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 160    PUSH_DATA (push, 28);
 161    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
 162    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 8);
 163    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 164    PUSH_DATA (push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
 165    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_PARAM_TRAP_INFO);
 166    PUSH_DATA (push, screen->tls->offset);
 167    PUSH_DATAh(push, screen->tls->offset);
 168    PUSH_DATA (push, screen->tls->size / 2); /* MP TEMP block size */
 169    PUSH_DATA (push, screen->tls->size / 2 / 64); /* warp TEMP block size */
 170    PUSH_DATA (push, 0); /* warp cfstack size */
 171 #endif
 172
 173    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 174    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 175
 176    return 0;
 177 }
 178
 179
 180 static void
 181 nve4_compute_validate_surfaces(struct nvc0_context *nvc0)
 182 {
 183    struct nvc0_screen *screen = nvc0->screen;
 184    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 185    struct nv50_surface *sf;
 186    struct nv04_resource *res;
 187    uint32_t mask;
 188    unsigned i;
 189    const unsigned t = 1;
 190
 191    mask = nvc0->surfaces_dirty[t];
 192    while (mask) {
 193       i = ffs(mask) - 1;
 194       mask &= ~(1 << i);
 195
 196       /*
 197        * NVE4's surface load/store instructions receive all the information
 198        * directly instead of via binding points, so we have to supply them.
 199        */
 200       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 201       PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
 202       PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_SUF(i));
 203       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 204       PUSH_DATA (push, 64);
 205       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
 206       BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 17);
 207       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 208
 209       nve4_set_surface_info(push, nvc0->surfaces[t][i], screen);
 210
 211       sf = nv50_surface(nvc0->surfaces[t][i]);
 212       if (sf) {
 213          res = nv04_resource(sf->base.texture);
 214
 215          if (sf->base.writable)
 216             BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
 217          else
 218             BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
 219       }
 220    }
 221    if (nvc0->surfaces_dirty[t]) {
 222       BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 223       PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 224    }
 225
 226    /* re-reference non-dirty surfaces */
 227    mask = nvc0->surfaces_valid[t] & ~nvc0->surfaces_dirty[t];
 228    while (mask) {
 229       i = ffs(mask) - 1;
 230       mask &= ~(1 << i);
 231
 232       sf = nv50_surface(nvc0->surfaces[t][i]);
 233       res = nv04_resource(sf->base.texture);
 234
 235       if (sf->base.writable)
 236          BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RDWR);
 237       else
 238          BCTX_REFN(nvc0->bufctx_cp, CP_SUF, res, RD);
 239    }
 240
 241    nvc0->surfaces_dirty[t] = 0;
 242 }
 243
 244
 245 /* Thankfully, textures with samplers follow the normal rules. */
 246 static void
 247 nve4_compute_validate_samplers(struct nvc0_context *nvc0)
 248 {
 249    boolean need_flush = nve4_validate_tsc(nvc0, 5);
 250    if (need_flush) {
 251       BEGIN_NVC0(nvc0->base.pushbuf, NVE4_COMPUTE(TSC_FLUSH), 1);
 252       PUSH_DATA (nvc0->base.pushbuf, 0);
 253    }
 254 }
 255 /* (Code duplicated at bottom for various non-convincing reasons.
 256  *  E.g. we might want to use the COMPUTE subchannel to upload TIC/TSC
 257  *  entries to avoid a subchannel switch.
 258  *  Same for texture cache flushes.
 259  *  Also, the bufctx differs, and more IFs in the 3D version looks ugly.)
 260  */
 261 static void nve4_compute_validate_textures(struct nvc0_context *);
 262
 263 static void
 264 nve4_compute_set_tex_handles(struct nvc0_context *nvc0)
 265 {
 266    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 267    uint64_t address;
 268    const unsigned s = nvc0_shader_stage(PIPE_SHADER_COMPUTE);
 269    unsigned i, n;
 270    uint32_t dirty = nvc0->textures_dirty[s] | nvc0->samplers_dirty[s];
 271
 272    if (!dirty)
 273       return;
 274    i = ffs(dirty) - 1;
 275    n = util_logbase2(dirty) + 1 - i;
 276    assert(n);
 277
 278    address = nvc0->screen->parm->offset + NVE4_CP_INPUT_TEX(i);
 279
 280    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 281    PUSH_DATAh(push, address);
 282    PUSH_DATA (push, address);
 283    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 284    PUSH_DATA (push, n * 4);
 285    PUSH_DATA (push, 0x1);
 286    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + n);
 287    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 288    PUSH_DATAp(push, &nvc0->tex_handles[s][i], n);
 289
 290    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 291    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 292
 293    nvc0->textures_dirty[s] = 0;
 294    nvc0->samplers_dirty[s] = 0;
 295 }
 296
 297
 298 static boolean
 299 nve4_compute_validate_program(struct nvc0_context *nvc0)
 300 {
 301    struct nvc0_program *prog = nvc0->compprog;
 302
 303    if (prog->mem)
 304       return TRUE;
 305
 306    if (!prog->translated) {
 307       prog->translated = nvc0_program_translate(
 308          prog, nvc0->screen->base.device->chipset);
 309       if (!prog->translated)
 310          return FALSE;
 311    }
 312    if (unlikely(!prog->code_size))
 313       return FALSE;
 314
 315    if (likely(prog->code_size)) {
 316       if (nvc0_program_upload_code(nvc0, prog)) {
 317          struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 318          BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 319          PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CODE);
 320          return TRUE;
 321       }
 322    }
 323    return FALSE;
 324 }
 325
 326
 327 static boolean
 328 nve4_compute_state_validate(struct nvc0_context *nvc0)
 329 {
 330    if (!nve4_compute_validate_program(nvc0))
 331       return FALSE;
 332    if (nvc0->dirty_cp & NVC0_NEW_CP_TEXTURES)
 333       nve4_compute_validate_textures(nvc0);
 334    if (nvc0->dirty_cp & NVC0_NEW_CP_SAMPLERS)
 335       nve4_compute_validate_samplers(nvc0);
 336    if (nvc0->dirty_cp & (NVC0_NEW_CP_TEXTURES | NVC0_NEW_CP_SAMPLERS))
 337        nve4_compute_set_tex_handles(nvc0);
 338    if (nvc0->dirty_cp & NVC0_NEW_CP_SURFACES)
 339       nve4_compute_validate_surfaces(nvc0);
 340    if (nvc0->dirty_cp & NVC0_NEW_CP_GLOBALS)
 341       nvc0_validate_global_residents(nvc0,
 342                                      nvc0->bufctx_cp, NVC0_BIND_CP_GLOBAL);
 343
 344    nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, FALSE);
 345
 346    nouveau_pushbuf_bufctx(nvc0->base.pushbuf, nvc0->bufctx_cp);
 347    if (unlikely(nouveau_pushbuf_validate(nvc0->base.pushbuf)))
 348       return FALSE;
 349    if (unlikely(nvc0->state.flushed))
 350       nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, TRUE);
 351
 352    return TRUE;
 353 }
 354
 355
 356 static void
 357 nve4_compute_upload_input(struct nvc0_context *nvc0, const void *input,
 358                           const uint *block_layout,
 359                           const uint *grid_layout)
 360 {
 361    struct nvc0_screen *screen = nvc0->screen;
 362    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 363    struct nvc0_program *cp = nvc0->compprog;
 364
 365    if (cp->parm_size) {
 366       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 367       PUSH_DATAh(push, screen->parm->offset);
 368       PUSH_DATA (push, screen->parm->offset);
 369       BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 370       PUSH_DATA (push, cp->parm_size);
 371       PUSH_DATA (push, 0x1);
 372       BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (cp->parm_size / 4));
 373       PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 374       PUSH_DATAp(push, input, cp->parm_size / 4);
 375    }
 376    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 377    PUSH_DATAh(push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
 378    PUSH_DATA (push, screen->parm->offset + NVE4_CP_INPUT_GRID_INFO(0));
 379    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 380    PUSH_DATA (push, 7 * 4);
 381    PUSH_DATA (push, 0x1);
 382    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + 7);
 383    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 384    PUSH_DATAp(push, block_layout, 3);
 385    PUSH_DATAp(push, grid_layout, 3);
 386    PUSH_DATA (push, 0);
 387
 388    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 389    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
 390 }
 391
 392 static INLINE uint8_t
 393 nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
 394 {
 395    if (shared_size > (32 << 10))
 396       return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
 397    if (shared_size > (16 << 10))
 398       return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
 399    return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
 400 }
 401
 402 static void
 403 nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
 404                                struct nve4_cp_launch_desc *desc,
 405                                uint32_t label,
 406                                const uint *block_layout,
 407                                const uint *grid_layout)
 408 {
 409    const struct nvc0_screen *screen = nvc0->screen;
 410    const struct nvc0_program *cp = nvc0->compprog;
 411    unsigned i;
 412
 413    nve4_cp_launch_desc_init_default(desc);
 414
 415    desc->entry = nvc0_program_symbol_offset(cp, label);
 416
 417    desc->griddim_x = grid_layout[0];
 418    desc->griddim_y = grid_layout[1];
 419    desc->griddim_z = grid_layout[2];
 420    desc->blockdim_x = block_layout[0];
 421    desc->blockdim_y = block_layout[1];
 422    desc->blockdim_z = block_layout[2];
 423
 424    desc->shared_size = align(cp->cp.smem_size, 0x100);
 425    desc->local_size_p = align(cp->cp.lmem_size, 0x10);
 426    desc->local_size_n = 0;
 427    desc->cstack_size = 0x800;
 428    desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
 429
 430    desc->gpr_alloc = cp->num_gprs;
 431    desc->bar_alloc = cp->num_barriers;
 432
 433    for (i = 0; i < 7; ++i) {
 434       const unsigned s = 5;
 435       if (nvc0->constbuf[s][i].u.buf)
 436          nve4_cp_launch_desc_set_ctx_cb(desc, i + 1, &nvc0->constbuf[s][i]);
 437    }
 438    nve4_cp_launch_desc_set_cb(desc, 0, screen->parm, 0, NVE4_CP_INPUT_SIZE);
 439 }
 440
 441 static INLINE struct nve4_cp_launch_desc *
 442 nve4_compute_alloc_launch_desc(struct nouveau_context *nv,
 443                                struct nouveau_bo **pbo, uint64_t *pgpuaddr)
 444 {
 445    uint8_t *ptr = nouveau_scratch_get(nv, 512, pgpuaddr, pbo);
 446    if (!ptr)
 447       return NULL;
 448    if (*pgpuaddr & 255) {
 449       unsigned adj = 256 - (*pgpuaddr & 255);
 450       ptr += adj;
 451       *pgpuaddr += adj;
 452    }
 453    return (struct nve4_cp_launch_desc *)ptr;
 454 }
 455
 456 void
 457 nve4_launch_grid(struct pipe_context *pipe,
 458                  const uint *block_layout, const uint *grid_layout,
 459                  uint32_t label,
 460                  const void *input)
 461 {
 462    struct nvc0_context *nvc0 = nvc0_context(pipe);
 463    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 464    struct nve4_cp_launch_desc *desc;
 465    uint64_t desc_gpuaddr;
 466    struct nouveau_bo *desc_bo;
 467    int ret;
 468
 469    desc = nve4_compute_alloc_launch_desc(&nvc0->base, &desc_bo, &desc_gpuaddr);
 470    if (!desc)
 471       goto out;
 472    BCTX_REFN_bo(nvc0->bufctx_cp, CP_DESC, NOUVEAU_BO_GART | NOUVEAU_BO_RD,
 473                 desc_bo);
 474
 475    ret = !nve4_compute_state_validate(nvc0);
 476    if (ret)
 477       goto out;
 478
 479    nve4_compute_setup_launch_desc(nvc0, desc, label, block_layout, grid_layout);
 480    nve4_compute_dump_launch_desc(desc);
 481
 482    nve4_compute_upload_input(nvc0, input, block_layout, grid_layout);
 483
 484    /* upload descriptor and flush */
 485 #if 0
 486    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 487    PUSH_DATAh(push, desc_gpuaddr);
 488    PUSH_DATA (push, desc_gpuaddr);
 489    BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 490    PUSH_DATA (push, 256);
 491    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
 492    BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 1 + (256 / 4));
 493    PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DESC);
 494    PUSH_DATAp(push, (const uint32_t *)desc, 256 / 4);
 495    BEGIN_NVC0(push, NVE4_COMPUTE(FLUSH), 1);
 496    PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB | NVE4_COMPUTE_FLUSH_CODE);
 497 #endif
 498    BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH_DESC_ADDRESS), 1);
 499    PUSH_DATA (push, desc_gpuaddr >> 8);
 500    BEGIN_NVC0(push, NVE4_COMPUTE(LAUNCH), 1);
 501    PUSH_DATA (push, 0x3);
 502    BEGIN_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 1);
 503    PUSH_DATA (push, 0);
 504
 505 out:
 506    if (ret)
 507       NOUVEAU_ERR("Failed to launch grid !\n");
 508    nouveau_scratch_done(&nvc0->base);
 509    nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_DESC);
 510 }
 511
 512
 513 #define NVE4_TIC_ENTRY_INVALID 0x000fffff
 514
 515 static void
 516 nve4_compute_validate_textures(struct nvc0_context *nvc0)
 517 {
 518    struct nouveau_bo *txc = nvc0->screen->txc;
 519    struct nouveau_pushbuf *push = nvc0->base.pushbuf;
 520    const unsigned s = 5;
 521    unsigned i;
 522    uint32_t commands[2][NVE4_CP_INPUT_TEX_MAX];
 523    unsigned n[2] = { 0, 0 };
 524
 525    for (i = 0; i < nvc0->num_textures[s]; ++i) {
 526       struct nv50_tic_entry *tic = nv50_tic_entry(nvc0->textures[s][i]);
 527       struct nv04_resource *res;
 528       const boolean dirty = !!(nvc0->textures_dirty[s] & (1 << i));
 529
 530       if (!tic) {
 531          nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
 532          continue;
 533       }
 534       res = nv04_resource(tic->pipe.texture);
 535
 536       if (tic->id < 0) {
 537          tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
 538
 539          PUSH_SPACE(push, 16);
 540          BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_ADDRESS_HIGH), 2);
 541          PUSH_DATAh(push, txc->offset + (tic->id * 32));
 542          PUSH_DATA (push, txc->offset + (tic->id * 32));
 543          BEGIN_NVC0(push, NVE4_COMPUTE(UPLOAD_SIZE), 2);
 544          PUSH_DATA (push, 32);
 545          PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL);
 546          BEGIN_1IC0(push, NVE4_COMPUTE(UPLOAD_EXEC), 9);
 547          PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA);
 548          PUSH_DATAp(push, &tic->tic[0], 8);
 549
 550          commands[0][n[0]++] = (tic->id << 4) | 1;
 551       } else
 552       if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
 553          commands[1][n[1]++] = (tic->id << 4) | 1;
 554       }
 555       nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
 556
 557       res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
 558       res->status |=  NOUVEAU_BUFFER_STATUS_GPU_READING;
 559
 560       nvc0->tex_handles[s][i] &= ~NVE4_TIC_ENTRY_INVALID;
 561       nvc0->tex_handles[s][i] |= tic->id;
 562       if (dirty)
 563          BCTX_REFN(nvc0->bufctx_cp, CP_TEX(i), res, RD);
 564    }
 565    for (; i < nvc0->state.num_textures[s]; ++i)
 566       nvc0->tex_handles[s][i] |= NVE4_TIC_ENTRY_INVALID;
 567
 568    if (n[0]) {
 569       BEGIN_NIC0(push, NVE4_COMPUTE(TIC_FLUSH), n[0]);
 570       PUSH_DATAp(push, commands[0], n[0]);
 571    }
 572    if (n[1]) {
 573       BEGIN_NIC0(push, NVE4_COMPUTE(TEX_CACHE_CTL), n[1]);
 574       PUSH_DATAp(push, commands[1], n[1]);
 575    }
 576
 577    nvc0->state.num_textures[s] = nvc0->num_textures[s];
 578 }
 579
 580
 581 static const char *nve4_cache_split_name(unsigned value)
 582 {
 583    switch (value) {
 584    case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
 585    case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
 586    case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
 587    default:
 588       return "(invalid)";
 589    }
 590 }
 591
 592 static void
 593 nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
 594 {
 595    const uint32_t *data = (const uint32_t *)desc;
 596    unsigned i;
 597    boolean zero = FALSE;
 598
 599    debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
 600
 601    for (i = 0; i < sizeof(*desc); i += 4) {
 602       if (data[i / 4]) {
 603          debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
 604          zero = FALSE;
 605       } else
 606       if (!zero) {
 607          debug_printf("...\n");
 608          zero = TRUE;
 609       }
 610    }
 611
 612    debug_printf("entry = 0x%x\n", desc->entry);
 613    debug_printf("grid dimensions = %ux%ux%u\n",
 614                 desc->griddim_x, desc->griddim_y, desc->griddim_z);
 615    debug_printf("block dimensions = %ux%ux%u\n",
 616                 desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
 617    debug_printf("s[] size: 0x%x\n", desc->shared_size);
 618    debug_printf("l[] size: -0x%x / +0x%x\n",
 619                 desc->local_size_n, desc->local_size_p);
 620    debug_printf("stack size: 0x%x\n", desc->cstack_size);
 621    debug_printf("barrier count: %u\n", desc->bar_alloc);
 622    debug_printf("$r count: %u\n", desc->gpr_alloc);
 623    debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
 624
 625    for (i = 0; i < 8; ++i) {
 626       uint64_t address;
 627       uint32_t size = desc->cb[i].size;
 628       boolean valid = !!(desc->cb_mask & (1 << i));
 629
 630       address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
 631
 632       if (!valid && !address && !size)
 633          continue;
 634       debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
 635                    i, address, size, valid ? "" : "  (invalid)");
 636    }
 637 }
 638
 639 static void
 640 nve4_compute_trap_info(struct nvc0_context *nvc0)
 641 {
 642    struct nvc0_screen *screen = nvc0->screen;
 643    struct nouveau_bo *bo = screen->parm;
 644    int ret, i;
 645    volatile struct nve4_mp_trap_info *info;
 646    uint8_t *map;
 647
 648    ret = nouveau_bo_map(bo, NOUVEAU_BO_RDWR, nvc0->base.client);
 649    if (ret)
 650       return;
 651    map = (uint8_t *)bo->map;
 652    info = (volatile struct nve4_mp_trap_info *)(map + NVE4_CP_PARAM_TRAP_INFO);
 653
 654    if (info->lock) {
 655       debug_printf("trapstat = %08x\n", info->trapstat);
 656       debug_printf("warperr = %08x\n", info->warperr);
 657       debug_printf("PC = %x\n", info->pc);
 658       debug_printf("tid = %u %u %u\n",
 659                    info->tid[0], info->tid[1], info->tid[2]);
 660       debug_printf("ctaid = %u %u %u\n",
 661                    info->ctaid[0], info->ctaid[1], info->ctaid[2]);
 662       for (i = 0; i <= 63; ++i)
 663          debug_printf("$r%i = %08x\n", i, info->r[i]);
 664       for (i = 0; i <= 6; ++i)
 665          debug_printf("$p%i = %i\n", i, (info->flags >> i) & 1);
 666       debug_printf("$c = %x\n", info->flags >> 12);
 667    }
 668    info->lock = 0;
 669 }