src/gallium/drivers/nvc0/nve4_compute.h

   1
   2 #ifndef NVE4_COMPUTE_H
   3 #define NVE4_COMPUTE_H
   4
   5 #include "nv50/nv50_defs.xml.h"
   6 #include "nve4_compute.xml.h"
   7
   8 /* Input space is implemented as c0[], to which we bind the screen->parm bo.
   9  */
  10 #define NVE4_CP_INPUT_USER          0x0000
  11 #define NVE4_CP_INPUT_USER_LIMIT    0x1000
  12 #define NVE4_CP_INPUT_GRID_INFO(i) (0x1000 + (i) * 4)
  13 #define NVE4_CP_INPUT_NTID(i)      (0x1000 + (i) * 4)
  14 #define NVE4_CP_INPUT_NCTAID(i)    (0x100c + (i) * 4)
  15 #define NVE4_CP_INPUT_GRIDID        0x1018
  16 #define NVE4_CP_INPUT_TEX(i)       (0x1040 + (i) * 4)
  17 #define NVE4_CP_INPUT_TEX_STRIDE    4
  18 #define NVE4_CP_INPUT_TEX_MAX       32
  19 #define NVE4_CP_INPUT_MS_OFFSETS    0x10c0
  20 #define NVE4_CP_INPUT_SUF_STRIDE    64
  21 #define NVE4_CP_INPUT_SUF(i)       (0x1100 + (i) * NVE4_CP_INPUT_SUF_STRIDE)
  22 #define NVE4_CP_INPUT_SUF_MAX       32
  23 #define NVE4_CP_INPUT_SIZE          0x1900
  24 #define NVE4_CP_PARAM_SIZE          0x2000
  25
  26 struct nve4_cp_launch_desc
  27 {
  28    u32 unk0[8];
  29    u32 entry;
  30    u32 unk9[3];
  31    u32 griddim_x    : 31;
  32    u32 unk12        : 1;
  33    u16 griddim_y;
  34    u16 griddim_z;
  35    u32 unk14[3];
  36    u16 shared_size; /* must be aligned to 0x100 */
  37    u16 unk15;
  38    u16 unk16;
  39    u16 blockdim_x;
  40    u16 blockdim_y;
  41    u16 blockdim_z;
  42    u32 cb_mask      : 8;
  43    u32 unk20_8      : 21;
  44    u32 cache_split  : 2;
  45    u32 unk20_31     : 1;
  46    u32 unk21[8];
  47    struct {
  48       u32 address_l;
  49       u32 address_h : 8;
  50       u32 reserved  : 7;
  51       u32 size      : 17;
  52    } cb[8];
  53    u32 local_size_p : 20;
  54    u32 unk45_20     : 7;
  55    u32 bar_alloc    : 5;
  56    u32 local_size_n : 20;
  57    u32 unk46_20     : 4;
  58    u32 gpr_alloc    : 8;
  59    u32 cstack_size  : 20;
  60    u32 unk47_20     : 12;
  61    u32 unk48[16];
  62 };
  63
  64 #define NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DATA 0x41
  65 #define NVE4_COMPUTE_UPLOAD_EXEC_UNKVAL_DESC 0x11
  66 #define NVE4_COMPUTE_UPLOAD_UNK0184_UNKVAL   0x1
  67
  68 static INLINE void
  69 nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc)
  70 {
  71    memset(desc, 0, sizeof(*desc));
  72
  73    desc->unk0[7]  = 0xbc000000;
  74    desc->unk9[2]  = 0x44014000;
  75    desc->unk47_20 = 0x300;
  76 }
  77
  78 static INLINE void
  79 nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc,
  80                            unsigned index,
  81                            struct nouveau_bo *bo,
  82                            uint32_t base, uint16_t size)
  83 {
  84    uint64_t address = bo->offset + base;
  85
  86    assert(index < 8);
  87    assert(!(base & 0xff));
  88    assert(size <= 65536);
  89
  90    desc->cb[index].address_l = address;
  91    desc->cb[index].address_h = address >> 32;
  92    desc->cb[index].size = size;
  93
  94    desc->cb_mask |= 1 << index;
  95 }
  96
  97 static INLINE void
  98 nve4_cp_launch_desc_set_ctx_cb(struct nve4_cp_launch_desc *desc,
  99                                unsigned index,
 100                                const struct nvc0_constbuf *cb)
 101 {
 102    assert(index < 8);
 103
 104    if (!cb->u.buf) {
 105       desc->cb_mask &= ~(1 << index);
 106    } else {
 107       const struct nv04_resource *buf = nv04_resource(cb->u.buf);
 108       assert(!cb->user);
 109       nve4_cp_launch_desc_set_cb(desc, index,
 110                                  buf->bo, buf->offset + cb->offset, cb->size);
 111    }
 112 }
 113
 114 #endif /* NVE4_COMPUTE_H */