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22cfa0ecefa0e907d154f80b969a41cdf82ae88a
[mesa.git] / src / gallium / drivers / nvfx / nv04_surface_2d.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_format.h"
3 #include "util/u_format.h"
4 #include "util/u_math.h"
5 #include "util/u_memory.h"
6
7 #include "nouveau/nouveau_winsys.h"
8 #include "nouveau/nouveau_util.h"
9 #include "nouveau/nouveau_screen.h"
10 #include "nv04_surface_2d.h"
11
12 static INLINE int
13 nv04_surface_format(enum pipe_format format)
14 {
15 switch (format) {
16 case PIPE_FORMAT_A8_UNORM:
17 case PIPE_FORMAT_L8_UNORM:
18 case PIPE_FORMAT_I8_UNORM:
19 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y8;
20 case PIPE_FORMAT_R16_SNORM:
21 case PIPE_FORMAT_B5G6R5_UNORM:
22 case PIPE_FORMAT_Z16_UNORM:
23 case PIPE_FORMAT_L8A8_UNORM:
24 return NV04_CONTEXT_SURFACES_2D_FORMAT_R5G6B5;
25 case PIPE_FORMAT_B8G8R8X8_UNORM:
26 case PIPE_FORMAT_B8G8R8A8_UNORM:
27 return NV04_CONTEXT_SURFACES_2D_FORMAT_A8R8G8B8;
28 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
29 case PIPE_FORMAT_X8Z24_UNORM:
30 return NV04_CONTEXT_SURFACES_2D_FORMAT_Y32;
31 default:
32 return -1;
33 }
34 }
35
36 static INLINE int
37 nv04_rect_format(enum pipe_format format)
38 {
39 switch (format) {
40 case PIPE_FORMAT_A8_UNORM:
41 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
42 case PIPE_FORMAT_B5G6R5_UNORM:
43 case PIPE_FORMAT_L8A8_UNORM:
44 case PIPE_FORMAT_Z16_UNORM:
45 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A16R5G6B5;
46 case PIPE_FORMAT_B8G8R8X8_UNORM:
47 case PIPE_FORMAT_B8G8R8A8_UNORM:
48 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
49 case PIPE_FORMAT_X8Z24_UNORM:
50 return NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT_A8R8G8B8;
51 default:
52 return -1;
53 }
54 }
55
56 static INLINE int
57 nv04_scaled_image_format(enum pipe_format format)
58 {
59 switch (format) {
60 case PIPE_FORMAT_A8_UNORM:
61 case PIPE_FORMAT_L8_UNORM:
62 case PIPE_FORMAT_I8_UNORM:
63 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_Y8;
64 case PIPE_FORMAT_B5G5R5A1_UNORM:
65 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A1R5G5B5;
66 case PIPE_FORMAT_B8G8R8A8_UNORM:
67 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_A8R8G8B8;
68 case PIPE_FORMAT_B8G8R8X8_UNORM:
69 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_X8R8G8B8;
70 case PIPE_FORMAT_B5G6R5_UNORM:
71 case PIPE_FORMAT_R16_SNORM:
72 case PIPE_FORMAT_L8A8_UNORM:
73 return NV03_SCALED_IMAGE_FROM_MEMORY_COLOR_FORMAT_R5G6B5;
74 default:
75 return -1;
76 }
77 }
78
79 static INLINE unsigned
80 nv04_swizzle_bits_square(unsigned x, unsigned y)
81 {
82 unsigned u = (x & 0x001) << 0 |
83 (x & 0x002) << 1 |
84 (x & 0x004) << 2 |
85 (x & 0x008) << 3 |
86 (x & 0x010) << 4 |
87 (x & 0x020) << 5 |
88 (x & 0x040) << 6 |
89 (x & 0x080) << 7 |
90 (x & 0x100) << 8 |
91 (x & 0x200) << 9 |
92 (x & 0x400) << 10 |
93 (x & 0x800) << 11;
94
95 unsigned v = (y & 0x001) << 1 |
96 (y & 0x002) << 2 |
97 (y & 0x004) << 3 |
98 (y & 0x008) << 4 |
99 (y & 0x010) << 5 |
100 (y & 0x020) << 6 |
101 (y & 0x040) << 7 |
102 (y & 0x080) << 8 |
103 (y & 0x100) << 9 |
104 (y & 0x200) << 10 |
105 (y & 0x400) << 11 |
106 (y & 0x800) << 12;
107 return v | u;
108 }
109
110 /* rectangular swizzled textures are linear concatenations of swizzled square tiles */
111 static INLINE unsigned
112 nv04_swizzle_bits(unsigned x, unsigned y, unsigned w, unsigned h)
113 {
114 unsigned s = MIN2(w, h);
115 unsigned m = s - 1;
116 return (((x | y) & ~m) * s) | nv04_swizzle_bits_square(x & m, y & m);
117 }
118
119 static int
120 nv04_surface_copy_swizzle(struct nv04_surface_2d *ctx,
121 struct pipe_surface *dst, int dx, int dy,
122 struct pipe_surface *src, int sx, int sy,
123 int w, int h)
124 {
125 struct nouveau_channel *chan = ctx->swzsurf->channel;
126 struct nouveau_grobj *swzsurf = ctx->swzsurf;
127 struct nouveau_grobj *sifm = ctx->sifm;
128 struct nouveau_bo *src_bo = ctx->buf(src);
129 struct nouveau_bo *dst_bo = ctx->buf(dst);
130 const unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
131 /* Max width & height may not be the same on all HW, but must be POT */
132 const unsigned max_w = 1024;
133 const unsigned max_h = 1024;
134 unsigned sub_w = w > max_w ? max_w : w;
135 unsigned sub_h = h > max_h ? max_h : h;
136 unsigned x;
137 unsigned y;
138
139 /* Swizzled surfaces must be POT */
140 assert(util_is_pot(dst->width) && util_is_pot(dst->height));
141
142 /* If area is too large to copy in one shot we must copy it in POT chunks to meet alignment requirements */
143 assert(sub_w == w || util_is_pot(sub_w));
144 assert(sub_h == h || util_is_pot(sub_h));
145
146 MARK_RING (chan, 8 + ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*17, 2 +
147 ((w+sub_w)/sub_w)*((h+sub_h)/sub_h)*2);
148
149 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_DMA_IMAGE, 1);
150 OUT_RELOCo(chan, dst_bo,
151 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
152
153 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_FORMAT, 1);
154 OUT_RING (chan, nv04_surface_format(dst->format) |
155 log2i(dst->width) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_U_SHIFT |
156 log2i(dst->height) << NV04_SWIZZLED_SURFACE_FORMAT_BASE_SIZE_V_SHIFT);
157
158 BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_DMA_IMAGE, 1);
159 OUT_RELOCo(chan, src_bo,
160 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
161 BEGIN_RING(chan, sifm, NV04_SCALED_IMAGE_FROM_MEMORY_SURFACE, 1);
162 OUT_RING (chan, swzsurf->handle);
163
164 for (y = 0; y < h; y += sub_h) {
165 sub_h = MIN2(sub_h, h - y);
166
167 for (x = 0; x < w; x += sub_w) {
168 sub_w = MIN2(sub_w, w - x);
169
170 assert(!(dst->offset & 63));
171
172 BEGIN_RING(chan, swzsurf, NV04_SWIZZLED_SURFACE_OFFSET, 1);
173 OUT_RELOCl(chan, dst_bo, dst->offset,
174 NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
175
176 BEGIN_RING(chan, sifm, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION, 9);
177 OUT_RING (chan, NV05_SCALED_IMAGE_FROM_MEMORY_COLOR_CONVERSION_TRUNCATE);
178 OUT_RING (chan, nv04_scaled_image_format(src->format));
179 OUT_RING (chan, NV03_SCALED_IMAGE_FROM_MEMORY_OPERATION_SRCCOPY);
180 OUT_RING (chan, (x + dx) | ((y + dy) << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_POINT_Y_SHIFT));
181 OUT_RING (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_CLIP_SIZE_H_SHIFT | sub_w);
182 OUT_RING (chan, (x + dx) | ((y + dy) << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_POINT_Y_SHIFT));
183 OUT_RING (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_OUT_SIZE_H_SHIFT | sub_w);
184 OUT_RING (chan, 1 << 20);
185 OUT_RING (chan, 1 << 20);
186
187 BEGIN_RING(chan, sifm, NV03_SCALED_IMAGE_FROM_MEMORY_SIZE, 4);
188 OUT_RING (chan, sub_h << NV03_SCALED_IMAGE_FROM_MEMORY_SIZE_H_SHIFT | sub_w);
189 OUT_RING (chan, src_pitch |
190 NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_ORIGIN_CENTER |
191 NV03_SCALED_IMAGE_FROM_MEMORY_FORMAT_FILTER_POINT_SAMPLE);
192 OUT_RELOCl(chan, src_bo, src->offset + (sy+y) * src_pitch + (sx+x) * util_format_get_blocksize(src->texture->format),
193 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
194 OUT_RING (chan, 0);
195 }
196 }
197
198 return 0;
199 }
200
201 static int
202 nv04_surface_copy_m2mf(struct nv04_surface_2d *ctx,
203 struct pipe_surface *dst, int dx, int dy,
204 struct pipe_surface *src, int sx, int sy, int w, int h)
205 {
206 struct nouveau_channel *chan = ctx->m2mf->channel;
207 struct nouveau_grobj *m2mf = ctx->m2mf;
208 struct nouveau_bo *src_bo = ctx->buf(src);
209 struct nouveau_bo *dst_bo = ctx->buf(dst);
210 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
211 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
212 unsigned dst_offset = dst->offset + dy * dst_pitch +
213 dx * util_format_get_blocksize(dst->texture->format);
214 unsigned src_offset = src->offset + sy * src_pitch +
215 sx * util_format_get_blocksize(src->texture->format);
216
217 MARK_RING (chan, 3 + ((h / 2047) + 1) * 9, 2 + ((h / 2047) + 1) * 2);
218 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_BUFFER_IN, 2);
219 OUT_RELOCo(chan, src_bo,
220 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
221 OUT_RELOCo(chan, dst_bo,
222 NOUVEAU_BO_GART | NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
223
224 while (h) {
225 int count = (h > 2047) ? 2047 : h;
226
227 BEGIN_RING(chan, m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
228 OUT_RELOCl(chan, src_bo, src_offset,
229 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_RD);
230 OUT_RELOCl(chan, dst_bo, dst_offset,
231 NOUVEAU_BO_VRAM | NOUVEAU_BO_GART | NOUVEAU_BO_WR);
232 OUT_RING (chan, src_pitch);
233 OUT_RING (chan, dst_pitch);
234 OUT_RING (chan, w * util_format_get_blocksize(src->texture->format));
235 OUT_RING (chan, count);
236 OUT_RING (chan, 0x0101);
237 OUT_RING (chan, 0);
238
239 h -= count;
240 src_offset += src_pitch * count;
241 dst_offset += dst_pitch * count;
242 }
243
244 return 0;
245 }
246
247 static int
248 nv04_surface_copy_blit(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
249 int dx, int dy, struct pipe_surface *src, int sx, int sy,
250 int w, int h)
251 {
252 struct nouveau_channel *chan = ctx->surf2d->channel;
253 struct nouveau_grobj *surf2d = ctx->surf2d;
254 struct nouveau_grobj *blit = ctx->blit;
255 struct nouveau_bo *src_bo = ctx->buf(src);
256 struct nouveau_bo *dst_bo = ctx->buf(dst);
257 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
258 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
259 int format;
260
261 format = nv04_surface_format(dst->format);
262 if (format < 0)
263 return 1;
264
265 MARK_RING (chan, 12, 4);
266 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
267 OUT_RELOCo(chan, src_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
268 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
269 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
270 OUT_RING (chan, format);
271 OUT_RING (chan, (dst_pitch << 16) | src_pitch);
272 OUT_RELOCl(chan, src_bo, src->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD);
273 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
274
275 BEGIN_RING(chan, blit, 0x0300, 3);
276 OUT_RING (chan, (sy << 16) | sx);
277 OUT_RING (chan, (dy << 16) | dx);
278 OUT_RING (chan, ( h << 16) | w);
279
280 return 0;
281 }
282
283 static void
284 nv04_surface_copy(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
285 int dx, int dy, struct pipe_surface *src, int sx, int sy,
286 int w, int h)
287 {
288 unsigned src_pitch = ((struct nv04_surface *)src)->pitch;
289 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
290 int src_linear = src->texture->flags & NVFX_RESOURCE_FLAG_LINEAR;
291 int dst_linear = dst->texture->flags & NVFX_RESOURCE_FLAG_LINEAR;
292
293 assert(src->format == dst->format);
294
295 /* Setup transfer to swizzle the texture to vram if needed */
296 if (src_linear && !dst_linear && w > 1 && h > 1) {
297 nv04_surface_copy_swizzle(ctx, dst, dx, dy, src, sx, sy, w, h);
298 return;
299 }
300
301 /* Use M2MF instead of the blitter since it always works
302 * Any possible performance drop is likely to be not very significant
303 * and dwarfed anyway by the current buffer management problems
304 */
305 nv04_surface_copy_m2mf(ctx, dst, dx, dy, src, sx, sy, w, h);
306 }
307
308 static void
309 nv04_surface_fill(struct nv04_surface_2d *ctx, struct pipe_surface *dst,
310 int dx, int dy, int w, int h, unsigned value)
311 {
312 struct nouveau_channel *chan = ctx->surf2d->channel;
313 struct nouveau_grobj *surf2d = ctx->surf2d;
314 struct nouveau_grobj *rect = ctx->rect;
315 struct nouveau_bo *dst_bo = ctx->buf(dst);
316 unsigned dst_pitch = ((struct nv04_surface *)dst)->pitch;
317 int cs2d_format, gdirect_format;
318
319 cs2d_format = nv04_surface_format(dst->format);
320 assert(cs2d_format >= 0);
321
322 gdirect_format = nv04_rect_format(dst->format);
323 assert(gdirect_format >= 0);
324
325 MARK_RING (chan, 16, 4);
326 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
327 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
328 OUT_RELOCo(chan, dst_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
329 BEGIN_RING(chan, surf2d, NV04_CONTEXT_SURFACES_2D_FORMAT, 4);
330 OUT_RING (chan, cs2d_format);
331 OUT_RING (chan, (dst_pitch << 16) | dst_pitch);
332 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
333 OUT_RELOCl(chan, dst_bo, dst->offset, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
334
335 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR_FORMAT, 1);
336 OUT_RING (chan, gdirect_format);
337 BEGIN_RING(chan, rect, NV04_GDI_RECTANGLE_TEXT_COLOR1_A, 1);
338 OUT_RING (chan, value);
339 BEGIN_RING(chan, rect,
340 NV04_GDI_RECTANGLE_TEXT_UNCLIPPED_RECTANGLE_POINT(0), 2);
341 OUT_RING (chan, (dx << 16) | dy);
342 OUT_RING (chan, ( w << 16) | h);
343 }
344
345 void
346 nv04_surface_2d_takedown(struct nv04_surface_2d **pctx)
347 {
348 struct nv04_surface_2d *ctx;
349
350 if (!pctx || !*pctx)
351 return;
352 ctx = *pctx;
353 *pctx = NULL;
354
355 nouveau_notifier_free(&ctx->ntfy);
356 nouveau_grobj_free(&ctx->m2mf);
357 nouveau_grobj_free(&ctx->surf2d);
358 nouveau_grobj_free(&ctx->swzsurf);
359 nouveau_grobj_free(&ctx->rect);
360 nouveau_grobj_free(&ctx->blit);
361 nouveau_grobj_free(&ctx->sifm);
362
363 FREE(ctx);
364 }
365
366 struct nv04_surface_2d *
367 nv04_surface_2d_init(struct nouveau_screen *screen)
368 {
369 struct nv04_surface_2d *ctx = CALLOC_STRUCT(nv04_surface_2d);
370 struct nouveau_channel *chan = screen->channel;
371 unsigned handle = 0x88000000, class;
372 int ret;
373
374 if (!ctx)
375 return NULL;
376
377 ret = nouveau_notifier_alloc(chan, handle++, 1, &ctx->ntfy);
378 if (ret) {
379 nv04_surface_2d_takedown(&ctx);
380 return NULL;
381 }
382
383 ret = nouveau_grobj_alloc(chan, handle++, 0x0039, &ctx->m2mf);
384 if (ret) {
385 nv04_surface_2d_takedown(&ctx);
386 return NULL;
387 }
388
389 BEGIN_RING(chan, ctx->m2mf, NV04_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
390 OUT_RING (chan, ctx->ntfy->handle);
391
392 if (chan->device->chipset < 0x10)
393 class = NV04_CONTEXT_SURFACES_2D;
394 else
395 class = NV10_CONTEXT_SURFACES_2D;
396
397 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->surf2d);
398 if (ret) {
399 nv04_surface_2d_takedown(&ctx);
400 return NULL;
401 }
402
403 BEGIN_RING(chan, ctx->surf2d,
404 NV04_CONTEXT_SURFACES_2D_DMA_IMAGE_SOURCE, 2);
405 OUT_RING (chan, chan->vram->handle);
406 OUT_RING (chan, chan->vram->handle);
407
408 if (chan->device->chipset < 0x10)
409 class = NV04_IMAGE_BLIT;
410 else
411 class = NV12_IMAGE_BLIT;
412
413 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->blit);
414 if (ret) {
415 nv04_surface_2d_takedown(&ctx);
416 return NULL;
417 }
418
419 BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_DMA_NOTIFY, 1);
420 OUT_RING (chan, ctx->ntfy->handle);
421 BEGIN_RING(chan, ctx->blit, NV04_IMAGE_BLIT_SURFACE, 1);
422 OUT_RING (chan, ctx->surf2d->handle);
423 BEGIN_RING(chan, ctx->blit, NV01_IMAGE_BLIT_OPERATION, 1);
424 OUT_RING (chan, NV01_IMAGE_BLIT_OPERATION_SRCCOPY);
425
426 ret = nouveau_grobj_alloc(chan, handle++, NV04_GDI_RECTANGLE_TEXT,
427 &ctx->rect);
428 if (ret) {
429 nv04_surface_2d_takedown(&ctx);
430 return NULL;
431 }
432
433 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_DMA_NOTIFY, 1);
434 OUT_RING (chan, ctx->ntfy->handle);
435 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_SURFACE, 1);
436 OUT_RING (chan, ctx->surf2d->handle);
437 BEGIN_RING(chan, ctx->rect, NV04_GDI_RECTANGLE_TEXT_OPERATION, 1);
438 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_OPERATION_SRCCOPY);
439 BEGIN_RING(chan, ctx->rect,
440 NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT, 1);
441 OUT_RING (chan, NV04_GDI_RECTANGLE_TEXT_MONOCHROME_FORMAT_LE);
442
443 switch (chan->device->chipset & 0xf0) {
444 case 0x00:
445 case 0x10:
446 class = NV04_SWIZZLED_SURFACE;
447 break;
448 case 0x20:
449 class = NV20_SWIZZLED_SURFACE;
450 break;
451 case 0x30:
452 class = NV30_SWIZZLED_SURFACE;
453 break;
454 case 0x40:
455 case 0x60:
456 class = NV40_SWIZZLED_SURFACE;
457 break;
458 default:
459 /* Famous last words: this really can't happen.. */
460 assert(0);
461 break;
462 }
463
464 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->swzsurf);
465 if (ret) {
466 nv04_surface_2d_takedown(&ctx);
467 return NULL;
468 }
469
470 switch (chan->device->chipset & 0xf0) {
471 case 0x10:
472 case 0x20:
473 class = NV10_SCALED_IMAGE_FROM_MEMORY;
474 break;
475 case 0x30:
476 class = NV30_SCALED_IMAGE_FROM_MEMORY;
477 break;
478 case 0x40:
479 case 0x60:
480 class = NV40_SCALED_IMAGE_FROM_MEMORY;
481 break;
482 default:
483 class = NV04_SCALED_IMAGE_FROM_MEMORY;
484 break;
485 }
486
487 ret = nouveau_grobj_alloc(chan, handle++, class, &ctx->sifm);
488 if (ret) {
489 nv04_surface_2d_takedown(&ctx);
490 return NULL;
491 }
492
493 ctx->copy = nv04_surface_copy;
494 ctx->fill = nv04_surface_fill;
495 return ctx;
496 }
497
498 struct nv04_surface*
499 nv04_surface_wrap_for_render(struct pipe_screen *pscreen,
500 struct nv04_surface_2d* eng2d, struct nv04_surface* ns)
501 {
502 int temp_flags;
503
504 temp_flags = (ns->base.usage |
505 PIPE_BIND_BLIT_SOURCE |
506 PIPE_BIND_BLIT_DESTINATION);
507
508 ns->base.usage = (PIPE_BIND_BLIT_SOURCE |
509 PIPE_BIND_BLIT_DESTINATION);
510
511 struct pipe_resource templ;
512 memset(&templ, 0, sizeof(templ));
513 templ.format = ns->base.texture->format;
514 templ.target = PIPE_TEXTURE_2D;
515 templ.width0 = ns->base.width;
516 templ.height0 = ns->base.height;
517 templ.depth0 = 1;
518 templ.last_level = 0;
519
520 // TODO: this is probably wrong and we should specifically handle multisampling somehow once it is implemented
521 templ.nr_samples = ns->base.texture->nr_samples;
522
523 templ.bind = ns->base.texture->bind | PIPE_BIND_RENDER_TARGET;
524
525 struct pipe_resource* temp_tex = pscreen->resource_create(pscreen, &templ);
526 struct nv04_surface* temp_ns = (struct nv04_surface*)pscreen->get_tex_surface(pscreen, temp_tex, 0, 0, 0, temp_flags);
527 temp_ns->backing = ns;
528
529 if(ns->base.usage & PIPE_BIND_BLIT_SOURCE)
530 eng2d->copy(eng2d, &temp_ns->backing->base,
531 0, 0, &ns->base,
532 0, 0, ns->base.width, ns->base.height);
533
534 return temp_ns;
535 }