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0a599c62a74dac820d7664baad912afdc55d7dec
[mesa.git] / src / gallium / drivers / nvfx / nvfx_fragprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_util.h"
9
10 #include "nvfx_context.h"
11 #include "nvfx_shader.h"
12 #include "nvfx_resource.h"
13
14 #define MAX_CONSTS 128
15 #define MAX_IMM 32
16 struct nvfx_fpc {
17 struct nvfx_fragment_program *fp;
18
19 unsigned r_temps;
20 unsigned r_temps_discard;
21 struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
22 struct nvfx_sreg *r_temp;
23
24 int num_regs;
25
26 unsigned inst_offset;
27 unsigned have_const;
28
29 struct {
30 int pipe;
31 float vals[4];
32 } consts[MAX_CONSTS];
33 int nr_consts;
34
35 struct nvfx_sreg imm[MAX_IMM];
36 unsigned nr_imm;
37
38 unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
39 };
40
41 static INLINE struct nvfx_sreg
42 temp(struct nvfx_fpc *fpc)
43 {
44 int idx = ffs(~fpc->r_temps) - 1;
45
46 if (idx < 0) {
47 NOUVEAU_ERR("out of temps!!\n");
48 assert(0);
49 return nvfx_sr(NVFXSR_TEMP, 0);
50 }
51
52 fpc->r_temps |= (1 << idx);
53 fpc->r_temps_discard |= (1 << idx);
54 return nvfx_sr(NVFXSR_TEMP, idx);
55 }
56
57 static INLINE void
58 release_temps(struct nvfx_fpc *fpc)
59 {
60 fpc->r_temps &= ~fpc->r_temps_discard;
61 fpc->r_temps_discard = 0;
62 }
63
64 static INLINE struct nvfx_sreg
65 constant(struct nvfx_fpc *fpc, int pipe, float vals[4])
66 {
67 int idx;
68
69 if (fpc->nr_consts == MAX_CONSTS)
70 assert(0);
71 idx = fpc->nr_consts++;
72
73 fpc->consts[idx].pipe = pipe;
74 if (pipe == -1)
75 memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
76 return nvfx_sr(NVFXSR_CONST, idx);
77 }
78
79 #define arith(cc,s,o,d,m,s0,s1,s2) \
80 nvfx_fp_arith((cc), (s), NVFX_FP_OP_OPCODE_##o, \
81 (d), (m), (s0), (s1), (s2))
82 #define tex(cc,s,o,u,d,m,s0,s1,s2) \
83 nvfx_fp_tex((cc), (s), NVFX_FP_OP_OPCODE_##o, (u), \
84 (d), (m), (s0), none, none)
85
86 static void
87 grow_insns(struct nvfx_fpc *fpc, int size)
88 {
89 struct nvfx_fragment_program *fp = fpc->fp;
90
91 fp->insn_len += size;
92 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
93 }
94
95 static void
96 emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_sreg src)
97 {
98 struct nvfx_fragment_program *fp = fpc->fp;
99 uint32_t *hw = &fp->insn[fpc->inst_offset];
100 uint32_t sr = 0;
101
102 switch (src.type) {
103 case NVFXSR_INPUT:
104 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
105 hw[0] |= (src.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
106 break;
107 case NVFXSR_OUTPUT:
108 sr |= NVFX_FP_REG_SRC_HALF;
109 /* fall-through */
110 case NVFXSR_TEMP:
111 sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
112 sr |= (src.index << NVFX_FP_REG_SRC_SHIFT);
113 break;
114 case NVFXSR_RELOCATED:
115 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
116 //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
117 util_dynarray_append(&fpc->fp->slot_relocations[src.index], unsigned, fpc->inst_offset);
118 break;
119 case NVFXSR_CONST:
120 if (!fpc->have_const) {
121 grow_insns(fpc, 4);
122 fpc->have_const = 1;
123 }
124
125 hw = &fp->insn[fpc->inst_offset];
126 if (fpc->consts[src.index].pipe >= 0) {
127 struct nvfx_fragment_program_data *fpd;
128
129 fp->consts = realloc(fp->consts, ++fp->nr_consts *
130 sizeof(*fpd));
131 fpd = &fp->consts[fp->nr_consts - 1];
132 fpd->offset = fpc->inst_offset + 4;
133 fpd->index = fpc->consts[src.index].pipe;
134 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
135 } else {
136 memcpy(&fp->insn[fpc->inst_offset + 4],
137 fpc->consts[src.index].vals,
138 sizeof(uint32_t) * 4);
139 }
140
141 sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT);
142 break;
143 case NVFXSR_NONE:
144 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
145 break;
146 default:
147 assert(0);
148 }
149
150 if (src.negate)
151 sr |= NVFX_FP_REG_NEGATE;
152
153 if (src.abs)
154 hw[1] |= (1 << (29 + pos));
155
156 sr |= ((src.swz[0] << NVFX_FP_REG_SWZ_X_SHIFT) |
157 (src.swz[1] << NVFX_FP_REG_SWZ_Y_SHIFT) |
158 (src.swz[2] << NVFX_FP_REG_SWZ_Z_SHIFT) |
159 (src.swz[3] << NVFX_FP_REG_SWZ_W_SHIFT));
160
161 hw[pos + 1] |= sr;
162 }
163
164 static void
165 emit_dst(struct nvfx_fpc *fpc, struct nvfx_sreg dst)
166 {
167 struct nvfx_fragment_program *fp = fpc->fp;
168 uint32_t *hw = &fp->insn[fpc->inst_offset];
169
170 switch (dst.type) {
171 case NVFXSR_TEMP:
172 if (fpc->num_regs < (dst.index + 1))
173 fpc->num_regs = dst.index + 1;
174 break;
175 case NVFXSR_OUTPUT:
176 if (dst.index == 1) {
177 fp->fp_control |= 0xe;
178 } else {
179 hw[0] |= NVFX_FP_OP_OUT_REG_HALF;
180 }
181 break;
182 case NVFXSR_NONE:
183 hw[0] |= (1 << 30);
184 break;
185 default:
186 assert(0);
187 }
188
189 hw[0] |= (dst.index << NVFX_FP_OP_OUT_REG_SHIFT);
190 }
191
192 static void
193 nvfx_fp_arith(struct nvfx_fpc *fpc, int sat, int op,
194 struct nvfx_sreg dst, int mask,
195 struct nvfx_sreg s0, struct nvfx_sreg s1, struct nvfx_sreg s2)
196 {
197 struct nvfx_fragment_program *fp = fpc->fp;
198 uint32_t *hw;
199
200 fpc->inst_offset = fp->insn_len;
201 fpc->have_const = 0;
202 grow_insns(fpc, 4);
203 hw = &fp->insn[fpc->inst_offset];
204 memset(hw, 0, sizeof(uint32_t) * 4);
205
206 if (op == NVFX_FP_OP_OPCODE_KIL)
207 fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL;
208 hw[0] |= (op << NVFX_FP_OP_OPCODE_SHIFT);
209 hw[0] |= (mask << NVFX_FP_OP_OUTMASK_SHIFT);
210 hw[2] |= (dst.dst_scale << NVFX_FP_OP_DST_SCALE_SHIFT);
211
212 if (sat)
213 hw[0] |= NVFX_FP_OP_OUT_SAT;
214
215 if (dst.cc_update)
216 hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
217 hw[1] |= (dst.cc_test << NVFX_FP_OP_COND_SHIFT);
218 hw[1] |= ((dst.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
219 (dst.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
220 (dst.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
221 (dst.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
222
223 emit_dst(fpc, dst);
224 emit_src(fpc, 0, s0);
225 emit_src(fpc, 1, s1);
226 emit_src(fpc, 2, s2);
227 }
228
229 static void
230 nvfx_fp_tex(struct nvfx_fpc *fpc, int sat, int op, int unit,
231 struct nvfx_sreg dst, int mask,
232 struct nvfx_sreg s0, struct nvfx_sreg s1, struct nvfx_sreg s2)
233 {
234 struct nvfx_fragment_program *fp = fpc->fp;
235
236 nvfx_fp_arith(fpc, sat, op, dst, mask, s0, s1, s2);
237
238 fp->insn[fpc->inst_offset] |= (unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
239 fp->samplers |= (1 << unit);
240 }
241
242 static INLINE struct nvfx_sreg
243 tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
244 {
245 struct nvfx_sreg src = { 0 };
246
247 switch (fsrc->Register.File) {
248 case TGSI_FILE_INPUT:
249 if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
250 assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
251 src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
252 } else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
253 if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0)
254 src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
255 else if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 1)
256 src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
257 else
258 assert(0);
259 } else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
260 assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
261 src = nvfx_sr(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
262 } else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
263 /* TODO: check this has the correct values */
264 /* XXX: what do we do for nv30 here (assuming it lacks facing)?! */
265 assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
266 src = nvfx_sr(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
267 } else {
268 assert(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
269 src = nvfx_sr(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->fp->info.input_semantic_index[fsrc->Register.Index]]);
270 }
271 break;
272 case TGSI_FILE_CONSTANT:
273 src = constant(fpc, fsrc->Register.Index, NULL);
274 break;
275 case TGSI_FILE_IMMEDIATE:
276 assert(fsrc->Register.Index < fpc->nr_imm);
277 src = fpc->imm[fsrc->Register.Index];
278 break;
279 case TGSI_FILE_TEMPORARY:
280 src = fpc->r_temp[fsrc->Register.Index];
281 break;
282 /* NV40 fragprog result regs are just temps, so this is simple */
283 case TGSI_FILE_OUTPUT:
284 src = fpc->r_result[fsrc->Register.Index];
285 break;
286 default:
287 NOUVEAU_ERR("bad src file\n");
288 break;
289 }
290
291 src.abs = fsrc->Register.Absolute;
292 src.negate = fsrc->Register.Negate;
293 src.swz[0] = fsrc->Register.SwizzleX;
294 src.swz[1] = fsrc->Register.SwizzleY;
295 src.swz[2] = fsrc->Register.SwizzleZ;
296 src.swz[3] = fsrc->Register.SwizzleW;
297 return src;
298 }
299
300 static INLINE struct nvfx_sreg
301 tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
302 switch (fdst->Register.File) {
303 case TGSI_FILE_OUTPUT:
304 return fpc->r_result[fdst->Register.Index];
305 case TGSI_FILE_TEMPORARY:
306 return fpc->r_temp[fdst->Register.Index];
307 case TGSI_FILE_NULL:
308 return nvfx_sr(NVFXSR_NONE, 0);
309 default:
310 NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
311 return nvfx_sr(NVFXSR_NONE, 0);
312 }
313 }
314
315 static INLINE int
316 tgsi_mask(uint tgsi)
317 {
318 int mask = 0;
319
320 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_FP_MASK_X;
321 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_FP_MASK_Y;
322 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_FP_MASK_Z;
323 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_FP_MASK_W;
324 return mask;
325 }
326
327 static boolean
328 nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
329 const struct tgsi_full_instruction *finst)
330 {
331 const struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
332 struct nvfx_sreg src[3], dst, tmp;
333 int mask, sat, unit = 0;
334 int ai = -1, ci = -1, ii = -1;
335 int i;
336
337 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
338 return TRUE;
339
340 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
341 const struct tgsi_full_src_register *fsrc;
342
343 fsrc = &finst->Src[i];
344 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
345 src[i] = tgsi_src(fpc, fsrc);
346 }
347 }
348
349 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
350 const struct tgsi_full_src_register *fsrc;
351
352 fsrc = &finst->Src[i];
353
354 switch (fsrc->Register.File) {
355 case TGSI_FILE_INPUT:
356 if (ai == -1 || ai == fsrc->Register.Index) {
357 ai = fsrc->Register.Index;
358 src[i] = tgsi_src(fpc, fsrc);
359 } else {
360 src[i] = temp(fpc);
361 arith(fpc, 0, MOV, src[i], NVFX_FP_MASK_ALL,
362 tgsi_src(fpc, fsrc), none, none);
363 }
364 break;
365 case TGSI_FILE_CONSTANT:
366 if ((ci == -1 && ii == -1) ||
367 ci == fsrc->Register.Index) {
368 ci = fsrc->Register.Index;
369 src[i] = tgsi_src(fpc, fsrc);
370 } else {
371 src[i] = temp(fpc);
372 arith(fpc, 0, MOV, src[i], NVFX_FP_MASK_ALL,
373 tgsi_src(fpc, fsrc), none, none);
374 }
375 break;
376 case TGSI_FILE_IMMEDIATE:
377 if ((ci == -1 && ii == -1) ||
378 ii == fsrc->Register.Index) {
379 ii = fsrc->Register.Index;
380 src[i] = tgsi_src(fpc, fsrc);
381 } else {
382 src[i] = temp(fpc);
383 arith(fpc, 0, MOV, src[i], NVFX_FP_MASK_ALL,
384 tgsi_src(fpc, fsrc), none, none);
385 }
386 break;
387 case TGSI_FILE_TEMPORARY:
388 /* handled above */
389 break;
390 case TGSI_FILE_SAMPLER:
391 unit = fsrc->Register.Index;
392 break;
393 case TGSI_FILE_OUTPUT:
394 break;
395 default:
396 NOUVEAU_ERR("bad src file\n");
397 return FALSE;
398 }
399 }
400
401 dst = tgsi_dst(fpc, &finst->Dst[0]);
402 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
403 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
404
405 switch (finst->Instruction.Opcode) {
406 case TGSI_OPCODE_ABS:
407 arith(fpc, sat, MOV, dst, mask, abs(src[0]), none, none);
408 break;
409 case TGSI_OPCODE_ADD:
410 arith(fpc, sat, ADD, dst, mask, src[0], src[1], none);
411 break;
412 case TGSI_OPCODE_CMP:
413 tmp = nvfx_sr(NVFXSR_NONE, 0);
414 tmp.cc_update = 1;
415 arith(fpc, 0, MOV, tmp, 0xf, src[0], none, none);
416 dst.cc_test = NVFX_COND_GE;
417 arith(fpc, sat, MOV, dst, mask, src[2], none, none);
418 dst.cc_test = NVFX_COND_LT;
419 arith(fpc, sat, MOV, dst, mask, src[1], none, none);
420 break;
421 case TGSI_OPCODE_COS:
422 arith(fpc, sat, COS, dst, mask, src[0], none, none);
423 break;
424 case TGSI_OPCODE_DDX:
425 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
426 tmp = temp(fpc);
427 arith(fpc, sat, DDX, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y,
428 swz(src[0], Z, W, Z, W), none, none);
429 arith(fpc, 0, MOV, tmp, NVFX_FP_MASK_Z | NVFX_FP_MASK_W,
430 swz(tmp, X, Y, X, Y), none, none);
431 arith(fpc, sat, DDX, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0],
432 none, none);
433 arith(fpc, 0, MOV, dst, mask, tmp, none, none);
434 } else {
435 arith(fpc, sat, DDX, dst, mask, src[0], none, none);
436 }
437 break;
438 case TGSI_OPCODE_DDY:
439 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
440 tmp = temp(fpc);
441 arith(fpc, sat, DDY, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y,
442 swz(src[0], Z, W, Z, W), none, none);
443 arith(fpc, 0, MOV, tmp, NVFX_FP_MASK_Z | NVFX_FP_MASK_W,
444 swz(tmp, X, Y, X, Y), none, none);
445 arith(fpc, sat, DDY, tmp, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0],
446 none, none);
447 arith(fpc, 0, MOV, dst, mask, tmp, none, none);
448 } else {
449 arith(fpc, sat, DDY, dst, mask, src[0], none, none);
450 }
451 break;
452 case TGSI_OPCODE_DP3:
453 arith(fpc, sat, DP3, dst, mask, src[0], src[1], none);
454 break;
455 case TGSI_OPCODE_DP4:
456 arith(fpc, sat, DP4, dst, mask, src[0], src[1], none);
457 break;
458 case TGSI_OPCODE_DPH:
459 tmp = temp(fpc);
460 arith(fpc, 0, DP3, tmp, NVFX_FP_MASK_X, src[0], src[1], none);
461 arith(fpc, sat, ADD, dst, mask, swz(tmp, X, X, X, X),
462 swz(src[1], W, W, W, W), none);
463 break;
464 case TGSI_OPCODE_DST:
465 arith(fpc, sat, DST, dst, mask, src[0], src[1], none);
466 break;
467 case TGSI_OPCODE_EX2:
468 arith(fpc, sat, EX2, dst, mask, src[0], none, none);
469 break;
470 case TGSI_OPCODE_FLR:
471 arith(fpc, sat, FLR, dst, mask, src[0], none, none);
472 break;
473 case TGSI_OPCODE_FRC:
474 arith(fpc, sat, FRC, dst, mask, src[0], none, none);
475 break;
476 case TGSI_OPCODE_KILP:
477 arith(fpc, 0, KIL, none, 0, none, none, none);
478 break;
479 case TGSI_OPCODE_KIL:
480 dst = nvfx_sr(NVFXSR_NONE, 0);
481 dst.cc_update = 1;
482 arith(fpc, 0, MOV, dst, NVFX_FP_MASK_ALL, src[0], none, none);
483 dst.cc_update = 0; dst.cc_test = NVFX_COND_LT;
484 arith(fpc, 0, KIL, dst, 0, none, none, none);
485 break;
486 case TGSI_OPCODE_LG2:
487 arith(fpc, sat, LG2, dst, mask, src[0], none, none);
488 break;
489 // case TGSI_OPCODE_LIT:
490 case TGSI_OPCODE_LRP:
491 if(!nvfx->is_nv4x)
492 arith(fpc, sat, LRP_NV30, dst, mask, src[0], src[1], src[2]);
493 else {
494 tmp = temp(fpc);
495 arith(fpc, 0, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
496 arith(fpc, sat, MAD, dst, mask, src[0], src[1], tmp);
497 }
498 break;
499 case TGSI_OPCODE_MAD:
500 arith(fpc, sat, MAD, dst, mask, src[0], src[1], src[2]);
501 break;
502 case TGSI_OPCODE_MAX:
503 arith(fpc, sat, MAX, dst, mask, src[0], src[1], none);
504 break;
505 case TGSI_OPCODE_MIN:
506 arith(fpc, sat, MIN, dst, mask, src[0], src[1], none);
507 break;
508 case TGSI_OPCODE_MOV:
509 arith(fpc, sat, MOV, dst, mask, src[0], none, none);
510 break;
511 case TGSI_OPCODE_MUL:
512 arith(fpc, sat, MUL, dst, mask, src[0], src[1], none);
513 break;
514 case TGSI_OPCODE_POW:
515 if(!nvfx->is_nv4x)
516 arith(fpc, sat, POW_NV30, dst, mask, src[0], src[1], none);
517 else {
518 tmp = temp(fpc);
519 arith(fpc, 0, LG2, tmp, NVFX_FP_MASK_X,
520 swz(src[0], X, X, X, X), none, none);
521 arith(fpc, 0, MUL, tmp, NVFX_FP_MASK_X, swz(tmp, X, X, X, X),
522 swz(src[1], X, X, X, X), none);
523 arith(fpc, sat, EX2, dst, mask,
524 swz(tmp, X, X, X, X), none, none);
525 }
526 break;
527 case TGSI_OPCODE_RCP:
528 arith(fpc, sat, RCP, dst, mask, src[0], none, none);
529 break;
530 case TGSI_OPCODE_RET:
531 assert(0);
532 break;
533 case TGSI_OPCODE_RFL:
534 if(!nvfx->is_nv4x)
535 arith(fpc, 0, RFL_NV30, dst, mask, src[0], src[1], none);
536 else {
537 tmp = temp(fpc);
538 arith(fpc, 0, DP3, tmp, NVFX_FP_MASK_X, src[0], src[0], none);
539 arith(fpc, 0, DP3, tmp, NVFX_FP_MASK_Y, src[0], src[1], none);
540 arith(fpc, 0, DIV, scale(tmp, 2X), NVFX_FP_MASK_Z,
541 swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
542 arith(fpc, sat, MAD, dst, mask,
543 swz(tmp, Z, Z, Z, Z), src[0], neg(src[1]));
544 }
545 break;
546 case TGSI_OPCODE_RSQ:
547 if(!nvfx->is_nv4x)
548 arith(fpc, sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none);
549 else {
550 tmp = temp(fpc);
551 arith(fpc, 0, LG2, scale(tmp, INV_2X), NVFX_FP_MASK_X,
552 abs(swz(src[0], X, X, X, X)), none, none);
553 arith(fpc, sat, EX2, dst, mask,
554 neg(swz(tmp, X, X, X, X)), none, none);
555 }
556 break;
557 case TGSI_OPCODE_SCS:
558 /* avoid overwriting the source */
559 if(src[0].swz[NVFX_SWZ_X] != NVFX_SWZ_X)
560 {
561 if (mask & NVFX_FP_MASK_X) {
562 arith(fpc, sat, COS, dst, NVFX_FP_MASK_X,
563 swz(src[0], X, X, X, X), none, none);
564 }
565 if (mask & NVFX_FP_MASK_Y) {
566 arith(fpc, sat, SIN, dst, NVFX_FP_MASK_Y,
567 swz(src[0], X, X, X, X), none, none);
568 }
569 }
570 else
571 {
572 if (mask & NVFX_FP_MASK_Y) {
573 arith(fpc, sat, SIN, dst, NVFX_FP_MASK_Y,
574 swz(src[0], X, X, X, X), none, none);
575 }
576 if (mask & NVFX_FP_MASK_X) {
577 arith(fpc, sat, COS, dst, NVFX_FP_MASK_X,
578 swz(src[0], X, X, X, X), none, none);
579 }
580 }
581 break;
582 case TGSI_OPCODE_SEQ:
583 arith(fpc, sat, SEQ, dst, mask, src[0], src[1], none);
584 break;
585 case TGSI_OPCODE_SFL:
586 arith(fpc, sat, SFL, dst, mask, src[0], src[1], none);
587 break;
588 case TGSI_OPCODE_SGE:
589 arith(fpc, sat, SGE, dst, mask, src[0], src[1], none);
590 break;
591 case TGSI_OPCODE_SGT:
592 arith(fpc, sat, SGT, dst, mask, src[0], src[1], none);
593 break;
594 case TGSI_OPCODE_SIN:
595 arith(fpc, sat, SIN, dst, mask, src[0], none, none);
596 break;
597 case TGSI_OPCODE_SLE:
598 arith(fpc, sat, SLE, dst, mask, src[0], src[1], none);
599 break;
600 case TGSI_OPCODE_SLT:
601 arith(fpc, sat, SLT, dst, mask, src[0], src[1], none);
602 break;
603 case TGSI_OPCODE_SNE:
604 arith(fpc, sat, SNE, dst, mask, src[0], src[1], none);
605 break;
606 case TGSI_OPCODE_STR:
607 arith(fpc, sat, STR, dst, mask, src[0], src[1], none);
608 break;
609 case TGSI_OPCODE_SUB:
610 arith(fpc, sat, ADD, dst, mask, src[0], neg(src[1]), none);
611 break;
612 case TGSI_OPCODE_TEX:
613 tex(fpc, sat, TEX, unit, dst, mask, src[0], none, none);
614 break;
615 case TGSI_OPCODE_TXB:
616 tex(fpc, sat, TXB, unit, dst, mask, src[0], none, none);
617 break;
618 case TGSI_OPCODE_TXP:
619 tex(fpc, sat, TXP, unit, dst, mask, src[0], none, none);
620 break;
621 case TGSI_OPCODE_XPD:
622 tmp = temp(fpc);
623 arith(fpc, 0, MUL, tmp, mask,
624 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
625 arith(fpc, sat, MAD, dst, (mask & ~NVFX_FP_MASK_W),
626 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
627 neg(tmp));
628 break;
629 default:
630 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
631 return FALSE;
632 }
633
634 release_temps(fpc);
635 return TRUE;
636 }
637
638 static boolean
639 nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
640 const struct tgsi_full_declaration *fdec)
641 {
642 unsigned idx = fdec->Range.First;
643 unsigned hw;
644
645 switch (fdec->Semantic.Name) {
646 case TGSI_SEMANTIC_POSITION:
647 hw = 1;
648 break;
649 case TGSI_SEMANTIC_COLOR:
650 hw = ~0;
651 switch (fdec->Semantic.Index) {
652 case 0: hw = 0; break;
653 case 1: hw = 2; break;
654 case 2: hw = 3; break;
655 case 3: hw = 4; break;
656 }
657 if(hw > ((nvfx->is_nv4x) ? 4 : 2)) {
658 NOUVEAU_ERR("bad rcol index\n");
659 return FALSE;
660 }
661 break;
662 default:
663 NOUVEAU_ERR("bad output semantic\n");
664 return FALSE;
665 }
666
667 fpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
668 fpc->r_temps |= (1 << hw);
669 return TRUE;
670 }
671
672 static boolean
673 nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
674 {
675 struct tgsi_parse_context p;
676 int high_temp = -1, i;
677 struct util_semantic_set set;
678
679 fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->fp->pipe.tokens, TGSI_FILE_INPUT);
680 if(fpc->fp->num_slots > 8)
681 return FALSE;
682 util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, 8);
683 util_semantic_table_from_layout(fpc->generic_to_slot, fpc->fp->slot_to_generic, 0, 8);
684
685 memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input));
686
687 tgsi_parse_init(&p, fpc->fp->pipe.tokens);
688 while (!tgsi_parse_end_of_tokens(&p)) {
689 const union tgsi_full_token *tok = &p.FullToken;
690
691 tgsi_parse_token(&p);
692 switch(tok->Token.Type) {
693 case TGSI_TOKEN_TYPE_DECLARATION:
694 {
695 const struct tgsi_full_declaration *fdec;
696 fdec = &p.FullToken.FullDeclaration;
697 switch (fdec->Declaration.File) {
698 case TGSI_FILE_OUTPUT:
699 if (!nvfx_fragprog_parse_decl_output(nvfx, fpc, fdec))
700 goto out_err;
701 break;
702 case TGSI_FILE_TEMPORARY:
703 if (fdec->Range.Last > high_temp) {
704 high_temp =
705 fdec->Range.Last;
706 }
707 break;
708 default:
709 break;
710 }
711 }
712 break;
713 case TGSI_TOKEN_TYPE_IMMEDIATE:
714 {
715 struct tgsi_full_immediate *imm;
716 float vals[4];
717
718 imm = &p.FullToken.FullImmediate;
719 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
720 assert(fpc->nr_imm < MAX_IMM);
721
722 vals[0] = imm->u[0].Float;
723 vals[1] = imm->u[1].Float;
724 vals[2] = imm->u[2].Float;
725 vals[3] = imm->u[3].Float;
726 fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals);
727 }
728 break;
729 default:
730 break;
731 }
732 }
733 tgsi_parse_free(&p);
734
735 if (++high_temp) {
736 fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
737 for (i = 0; i < high_temp; i++)
738 fpc->r_temp[i] = temp(fpc);
739 fpc->r_temps_discard = 0;
740 }
741
742 return TRUE;
743
744 out_err:
745 if (fpc->r_temp)
746 FREE(fpc->r_temp);
747 tgsi_parse_free(&p);
748 return FALSE;
749 }
750
751 static void
752 nvfx_fragprog_translate(struct nvfx_context *nvfx,
753 struct nvfx_fragment_program *fp)
754 {
755 struct tgsi_parse_context parse;
756 struct nvfx_fpc *fpc = NULL;
757
758 fpc = CALLOC(1, sizeof(struct nvfx_fpc));
759 if (!fpc)
760 return;
761 fpc->fp = fp;
762 fpc->num_regs = 2;
763
764 if (!nvfx_fragprog_prepare(nvfx, fpc)) {
765 FREE(fpc);
766 return;
767 }
768
769 tgsi_parse_init(&parse, fp->pipe.tokens);
770
771 while (!tgsi_parse_end_of_tokens(&parse)) {
772 tgsi_parse_token(&parse);
773
774 switch (parse.FullToken.Token.Type) {
775 case TGSI_TOKEN_TYPE_INSTRUCTION:
776 {
777 const struct tgsi_full_instruction *finst;
778
779 finst = &parse.FullToken.FullInstruction;
780 if (!nvfx_fragprog_parse_instruction(nvfx, fpc, finst))
781 goto out_err;
782 }
783 break;
784 default:
785 break;
786 }
787 }
788
789 if(!nvfx->is_nv4x)
790 fp->fp_control |= (fpc->num_regs-1)/2;
791 else
792 fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT;
793
794 /* Terminate final instruction */
795 if(fp->insn)
796 fp->insn[fpc->inst_offset] |= 0x00000001;
797
798 /* Append NOP + END instruction, may or may not be necessary. */
799 fpc->inst_offset = fp->insn_len;
800 grow_insns(fpc, 4);
801 fp->insn[fpc->inst_offset + 0] = 0x00000001;
802 fp->insn[fpc->inst_offset + 1] = 0x00000000;
803 fp->insn[fpc->inst_offset + 2] = 0x00000000;
804 fp->insn[fpc->inst_offset + 3] = 0x00000000;
805
806 fp->translated = TRUE;
807 out_err:
808 tgsi_parse_free(&parse);
809 if (fpc->r_temp)
810 FREE(fpc->r_temp);
811 FREE(fpc);
812 }
813
814 static inline void
815 nvfx_fp_memcpy(void* dst, const void* src, size_t len)
816 {
817 #ifndef WORDS_BIGENDIAN
818 memcpy(dst, src, len);
819 #else
820 size_t i;
821 for(i = 0; i < len; i += 4) {
822 uint32_t v = (uint32_t*)((char*)src + i);
823 *(uint32_t*)((char*)dst + i) = (v >> 16) | (v << 16);
824 }
825 #endif
826 }
827
828 void
829 nvfx_fragprog_validate(struct nvfx_context *nvfx)
830 {
831 struct nouveau_channel* chan = nvfx->screen->base.channel;
832 struct nvfx_fragment_program *fp = nvfx->fragprog;
833 int update = 0;
834
835 if (!fp->translated)
836 {
837 const int min_size = 4096;
838
839 nvfx_fragprog_translate(nvfx, fp);
840 if (!fp->translated) {
841 static unsigned dummy[8] = {1, 0, 0, 0, 1, 0, 0, 0};
842 static int warned = 0;
843 if(!warned)
844 {
845 fprintf(stderr, "nvfx: failed to translate fragment program!\n");
846 warned = 1;
847 }
848
849 /* use dummy program: we cannot fail here */
850 fp->translated = TRUE;
851 fp->insn = malloc(sizeof(dummy));
852 memcpy(fp->insn, dummy, sizeof(dummy));
853 fp->insn_len = sizeof(dummy) / sizeof(dummy[0]);
854 }
855 update = TRUE;
856
857 fp->prog_size = (fp->insn_len * 4 + 63) & ~63;
858
859 if(fp->prog_size >= min_size)
860 fp->progs_per_bo = 1;
861 else
862 fp->progs_per_bo = min_size / fp->prog_size;
863 fp->bo_prog_idx = fp->progs_per_bo - 1;
864 }
865
866 /* we must update constants even on "just" fragprog changes, because
867 we don't check whether the current constant buffer matches the latest
868 one bound to this fragment program */
869 if (nvfx->dirty & (NVFX_NEW_FRAGCONST | NVFX_NEW_FRAGPROG))
870 update = TRUE;
871
872 struct nvfx_vertex_program* vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
873 if (fp->last_vp_id != vp->id) {
874 char* vp_sem_table = vp->generic_to_fp_input;
875 unsigned char* fp_semantics = fp->slot_to_generic;
876 unsigned diff = 0;
877 fp->last_vp_id = nvfx->vertprog->id;
878 unsigned char* cur_slots = fp->slot_to_fp_input;
879 for(unsigned i = 0; i < fp->num_slots; ++i) {
880 unsigned char slot_mask = vp_sem_table[fp_semantics[i]];
881 diff |= (slot_mask >> 4) & (slot_mask ^ cur_slots[i]);
882 }
883
884 if(diff)
885 {
886 for(unsigned i = 0; i < fp->num_slots; ++i) {
887 /* if 0xff, then this will write to the dummy value at fp->last_layout_mask[0] */
888 fp->slot_to_fp_input[i] = vp_sem_table[fp_semantics[i]] & 0xf;
889 //printf("fp: GENERIC[%i] from fpreg %i\n", fp_semantics[i], fp->slot_to_fp_input[i]);
890 }
891
892 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
893 update = TRUE;
894 }
895 }
896
897 // last_sprite_coord_enable
898 unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
899 if(fp->last_sprite_coord_enable != sprite_coord_enable)
900 {
901 unsigned texcoord_mask = vp->texcoord_ouput_mask;
902 fp->last_sprite_coord_enable = sprite_coord_enable;
903 fp->point_sprite_control = 0;
904 for(unsigned i = 0; i < fp->num_slots; ++i) {
905 if((1 << fp->slot_to_generic[i]) & sprite_coord_enable)
906 {
907 unsigned fpin = fp->slot_to_fp_input[i];
908 //printf("sprite: slot %i generic %i had texcoord %i\n", i, fp->slot_to_generic[i], fpin - NVFX_FP_OP_INPUT_SRC_TC0);
909 if(fpin >= 0x0f)
910 {
911 unsigned tc = __builtin_ctz(~texcoord_mask);
912 texcoord_mask |= (1 << tc);
913 fp->slot_to_fp_input[i] = fpin = NVFX_FP_OP_INPUT_SRC_TC(tc);
914
915 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
916 update = TRUE;
917 }
918 //printf("sprite: slot %i texcoord %i\n", i, fpin - NVFX_FP_OP_INPUT_SRC_TC0);
919 fp->point_sprite_control |= (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
920 }
921 else
922 {
923 unsigned fpin = fp->slot_to_fp_input[i];
924 if(!(vp->texcoord_ouput_mask & (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0))))
925 {
926 fp->slot_to_fp_input[i] = 0x0f;
927
928 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
929 update = TRUE;
930 }
931 }
932 }
933 }
934
935 if(update) {
936 ++fp->bo_prog_idx;
937 if(fp->bo_prog_idx >= fp->progs_per_bo)
938 {
939 if(fp->fpbo && !nouveau_bo_busy(fp->fpbo->next->bo, NOUVEAU_BO_WR))
940 {
941 fp->fpbo = fp->fpbo->next;
942 }
943 else
944 {
945 struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + (fp->prog_size + 8) * fp->progs_per_bo, 16);
946 fpbo->slots = (unsigned char*)&fpbo->insn[(fp->prog_size) * fp->progs_per_bo];
947 memset(fpbo->slots, 0, 8 * fp->progs_per_bo);
948 if(fp->fpbo)
949 {
950 fpbo->next = fp->fpbo->next;
951 fp->fpbo->next = fpbo;
952 }
953 else
954 fpbo->next = fpbo;
955 fp->fpbo = fpbo;
956 fpbo->bo = 0;
957 fp->progs += fp->progs_per_bo;
958 fp->progs_left_with_obsolete_slot_assignments += fp->progs_per_bo;
959 nouveau_bo_new(nvfx->screen->base.device, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, 64, fp->prog_size * fp->progs_per_bo, &fpbo->bo);
960 nouveau_bo_map(fpbo->bo, NOUVEAU_BO_NOSYNC);
961
962 uint8_t* map = fpbo->bo->map;
963 uint8_t* buf = (uint8_t*)fpbo->insn;
964 for(unsigned i = 0; i < fp->progs_per_bo; ++i)
965 {
966 memcpy(buf, fp->insn, fp->insn_len * 4);
967 nvfx_fp_memcpy(map, fp->insn, fp->insn_len * 4);
968 map += fp->prog_size;
969 buf += fp->prog_size;
970 }
971 }
972 fp->bo_prog_idx = 0;
973 }
974
975 int offset = fp->bo_prog_idx * fp->prog_size;
976 uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
977
978 if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) {
979 struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT];
980 uint32_t* map = (uint32_t*)nvfx_buffer(constbuf)->data;
981 uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
982 uint32_t* buf = (uint32_t*)((char*)fp->fpbo->insn + offset);
983 int i;
984 for (i = 0; i < fp->nr_consts; ++i) {
985 unsigned off = fp->consts[i].offset;
986 unsigned idx = fp->consts[i].index * 4;
987
988 /* TODO: is checking a good idea? */
989 if(memcmp(&buf[off], &map[idx], 4 * sizeof(uint32_t))) {
990 memcpy(&buf[off], &map[idx], 4 * sizeof(uint32_t));
991 nvfx_fp_memcpy(&fpmap[off], &map[idx], 4 * sizeof(uint32_t));
992 }
993 }
994 }
995
996 if(fp->progs_left_with_obsolete_slot_assignments) {
997 unsigned char* fpbo_slots = &fp->fpbo->slots[fp->bo_prog_idx * 8];
998 for(unsigned i = 0; i < fp->num_slots; ++i) {
999 unsigned value = fp->slot_to_fp_input[i];;
1000 if(value != fpbo_slots[i]) {
1001 unsigned* p = (unsigned*)fp->slot_relocations[i].data;
1002 unsigned* pend = (unsigned*)((char*)fp->slot_relocations[i].data + fp->slot_relocations[i].size);
1003 for(; p != pend; ++p) {
1004 unsigned off = *p;
1005 unsigned dw = fp->insn[off];
1006 dw = (dw & ~NVFX_FP_OP_INPUT_SRC_MASK) | (value << NVFX_FP_OP_INPUT_SRC_SHIFT);
1007 nvfx_fp_memcpy(&fpmap[*p], &dw, sizeof(dw));
1008 }
1009 fpbo_slots[i] = value;
1010 }
1011 }
1012 --fp->progs_left_with_obsolete_slot_assignments;
1013 }
1014 }
1015
1016 if(update || (nvfx->dirty & NVFX_NEW_FRAGPROG)) {
1017 int offset = fp->bo_prog_idx * fp->prog_size;
1018 MARK_RING(chan, 8, 1);
1019 OUT_RING(chan, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1));
1020 OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
1021 NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
1022 NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
1023 NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
1024 OUT_RING(chan, RING_3D(NV34TCL_FP_CONTROL, 1));
1025 OUT_RING(chan, fp->fp_control);
1026 if(!nvfx->is_nv4x) {
1027 OUT_RING(chan, RING_3D(NV34TCL_FP_REG_CONTROL, 1));
1028 OUT_RING(chan, (1<<16)|0x4);
1029 OUT_RING(chan, RING_3D(NV34TCL_TX_UNITS_ENABLE, 1));
1030 OUT_RING(chan, fp->samplers);
1031 }
1032 }
1033
1034 if(nvfx->dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_SPRITE))
1035 {
1036 WAIT_RING(chan, 2);
1037 OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1));
1038 OUT_RING(chan, fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization);
1039 }
1040 }
1041
1042 void
1043 nvfx_fragprog_relocate(struct nvfx_context *nvfx)
1044 {
1045 struct nouveau_channel* chan = nvfx->screen->base.channel;
1046 struct nvfx_fragment_program *fp = nvfx->fragprog;
1047 struct nouveau_bo* bo = fp->fpbo->bo;
1048 int offset = fp->bo_prog_idx * fp->prog_size;
1049 unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART?
1050 fp_flags |= NOUVEAU_BO_DUMMY;
1051 MARK_RING(chan, 2, 2);
1052 OUT_RELOC(chan, bo, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
1053 OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW |
1054 NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
1055 NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
1056 }
1057
1058 void
1059 nvfx_fragprog_destroy(struct nvfx_context *nvfx,
1060 struct nvfx_fragment_program *fp)
1061 {
1062 unsigned i;
1063 struct nvfx_fragment_program_bo* fpbo = fp->fpbo;
1064 if(fpbo)
1065 {
1066 do
1067 {
1068 struct nvfx_fragment_program_bo* next = fpbo->next;
1069 nouveau_bo_unmap(fpbo->bo);
1070 nouveau_bo_ref(0, &fpbo->bo);
1071 free(fpbo);
1072 fpbo = next;
1073 }
1074 while(fpbo != fp->fpbo);
1075 }
1076
1077 for(i = 0; i < 8; ++i)
1078 util_dynarray_fini(&fp->slot_relocations[i]);
1079
1080 if (fp->insn_len)
1081 FREE(fp->insn);
1082 }