projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
nouveau: rework and simplify nv04/nv05 driver a bit
[mesa.git] / src / gallium / drivers / nvfx / nvfx_fragprog.c
1 #include <float.h>
2 #include "pipe/p_context.h"
3 #include "pipe/p_defines.h"
4 #include "pipe/p_state.h"
5 #include "util/u_inlines.h"
6 #include "util/u_debug.h"
7
8 #include "pipe/p_shader_tokens.h"
9 #include "tgsi/tgsi_parse.h"
10 #include "tgsi/tgsi_util.h"
11 #include "tgsi/tgsi_dump.h"
12 #include "tgsi/tgsi_ureg.h"
13
14 #include "nvfx_context.h"
15 #include "nvfx_shader.h"
16 #include "nvfx_resource.h"
17
18 struct nvfx_fpc {
19 struct nvfx_pipe_fragment_program* pfp;
20 struct nvfx_fragment_program *fp;
21
22 unsigned max_temps;
23 unsigned long long r_temps;
24 unsigned long long r_temps_discard;
25 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
26 struct nvfx_reg *r_temp;
27 unsigned sprite_coord_temp;
28
29 int num_regs;
30
31 unsigned inst_offset;
32 unsigned have_const;
33
34 struct util_dynarray imm_data;
35
36 struct nvfx_reg* r_imm;
37 unsigned nr_imm;
38
39 unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
40
41 struct util_dynarray if_stack;
42 //struct util_dynarray loop_stack;
43 struct util_dynarray label_relocs;
44 };
45
46 static INLINE struct nvfx_reg
47 temp(struct nvfx_fpc *fpc)
48 {
49 int idx = __builtin_ctzll(~fpc->r_temps);
50
51 if (idx >= fpc->max_temps) {
52 NOUVEAU_ERR("out of temps!!\n");
53 assert(0);
54 return nvfx_reg(NVFXSR_TEMP, 0);
55 }
56
57 fpc->r_temps |= (1ULL << idx);
58 fpc->r_temps_discard |= (1ULL << idx);
59 return nvfx_reg(NVFXSR_TEMP, idx);
60 }
61
62 static INLINE void
63 release_temps(struct nvfx_fpc *fpc)
64 {
65 fpc->r_temps &= ~fpc->r_temps_discard;
66 fpc->r_temps_discard = 0ULL;
67 }
68
69 static inline struct nvfx_reg
70 nvfx_fp_imm(struct nvfx_fpc *fpc, float a, float b, float c, float d)
71 {
72 float v[4] = {a, b, c, d};
73 int idx = fpc->imm_data.size >> 4;
74
75 memcpy(util_dynarray_grow(&fpc->imm_data, sizeof(float) * 4), v, 4 * sizeof(float));
76 return nvfx_reg(NVFXSR_IMM, idx);
77 }
78
79 static void
80 grow_insns(struct nvfx_fpc *fpc, int size)
81 {
82 struct nvfx_fragment_program *fp = fpc->fp;
83
84 fp->insn_len += size;
85 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
86 }
87
88 static void
89 emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src)
90 {
91 struct nvfx_fragment_program *fp = fpc->fp;
92 uint32_t *hw = &fp->insn[fpc->inst_offset];
93 uint32_t sr = 0;
94
95 switch (src.reg.type) {
96 case NVFXSR_INPUT:
97 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
98 hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
99 break;
100 case NVFXSR_OUTPUT:
101 sr |= NVFX_FP_REG_SRC_HALF;
102 /* fall-through */
103 case NVFXSR_TEMP:
104 sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
105 sr |= (src.reg.index << NVFX_FP_REG_SRC_SHIFT);
106 break;
107 case NVFXSR_RELOCATED:
108 sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
109 sr |= (fpc->sprite_coord_temp << NVFX_FP_REG_SRC_SHIFT);
110 //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
111 util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset + pos + 1);
112 break;
113 case NVFXSR_IMM:
114 if (!fpc->have_const) {
115 grow_insns(fpc, 4);
116 hw = &fp->insn[fpc->inst_offset];
117 fpc->have_const = 1;
118 }
119
120 memcpy(&fp->insn[fpc->inst_offset + 4],
121 (float*)fpc->imm_data.data + src.reg.index * 4,
122 sizeof(uint32_t) * 4);
123
124 sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT);
125 break;
126 case NVFXSR_CONST:
127 if (!fpc->have_const) {
128 grow_insns(fpc, 4);
129 hw = &fp->insn[fpc->inst_offset];
130 fpc->have_const = 1;
131 }
132
133 {
134 struct nvfx_fragment_program_data *fpd;
135
136 fp->consts = realloc(fp->consts, ++fp->nr_consts *
137 sizeof(*fpd));
138 fpd = &fp->consts[fp->nr_consts - 1];
139 fpd->offset = fpc->inst_offset + 4;
140 fpd->index = src.reg.index;
141 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
142 }
143
144 sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT);
145 break;
146 case NVFXSR_NONE:
147 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
148 break;
149 default:
150 assert(0);
151 }
152
153 if (src.negate)
154 sr |= NVFX_FP_REG_NEGATE;
155
156 if (src.abs)
157 hw[1] |= (1 << (29 + pos));
158
159 sr |= ((src.swz[0] << NVFX_FP_REG_SWZ_X_SHIFT) |
160 (src.swz[1] << NVFX_FP_REG_SWZ_Y_SHIFT) |
161 (src.swz[2] << NVFX_FP_REG_SWZ_Z_SHIFT) |
162 (src.swz[3] << NVFX_FP_REG_SWZ_W_SHIFT));
163
164 hw[pos + 1] |= sr;
165 }
166
167 static void
168 emit_dst(struct nvfx_fpc *fpc, struct nvfx_reg dst)
169 {
170 struct nvfx_fragment_program *fp = fpc->fp;
171 uint32_t *hw = &fp->insn[fpc->inst_offset];
172
173 switch (dst.type) {
174 case NVFXSR_TEMP:
175 if (fpc->num_regs < (dst.index + 1))
176 fpc->num_regs = dst.index + 1;
177 break;
178 case NVFXSR_OUTPUT:
179 if (dst.index == 1) {
180 fp->fp_control |= 0xe;
181 } else {
182 hw[0] |= NVFX_FP_OP_OUT_REG_HALF;
183 }
184 break;
185 case NVFXSR_NONE:
186 hw[0] |= (1 << 30);
187 break;
188 default:
189 assert(0);
190 }
191
192 hw[0] |= (dst.index << NVFX_FP_OP_OUT_REG_SHIFT);
193 }
194
195 static void
196 nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn)
197 {
198 struct nvfx_fragment_program *fp = fpc->fp;
199 uint32_t *hw;
200
201 fpc->inst_offset = fp->insn_len;
202 fpc->have_const = 0;
203 grow_insns(fpc, 4);
204 hw = &fp->insn[fpc->inst_offset];
205 memset(hw, 0, sizeof(uint32_t) * 4);
206
207 if (insn.op == NVFX_FP_OP_OPCODE_KIL)
208 fp->fp_control |= NV30_3D_FP_CONTROL_USES_KIL;
209 hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
210 hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
211 hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
212
213 if (insn.sat)
214 hw[0] |= NVFX_FP_OP_OUT_SAT;
215
216 if (insn.cc_update)
217 hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
218 hw[1] |= (insn.cc_test << NVFX_FP_OP_COND_SHIFT);
219 hw[1] |= ((insn.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
220 (insn.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
221 (insn.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
222 (insn.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
223
224 if(insn.unit >= 0)
225 {
226 hw[0] |= (insn.unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
227 fp->samplers |= (1 << insn.unit);
228 }
229
230 emit_dst(fpc, insn.dst);
231 emit_src(fpc, 0, insn.src[0]);
232 emit_src(fpc, 1, insn.src[1]);
233 emit_src(fpc, 2, insn.src[2]);
234 }
235
236 #define arith(s,o,d,m,s0,s1,s2) \
237 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, -1, \
238 (d), (m), (s0), (s1), (s2))
239
240 #define tex(s,o,u,d,m,s0,s1,s2) \
241 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
242 (d), (m), (s0), none, none)
243
244 /* IF src.x != 0, as TGSI specifies */
245 static void
246 nv40_fp_if(struct nvfx_fpc *fpc, struct nvfx_src src)
247 {
248 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
249 struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none);
250 uint32_t *hw;
251 insn.cc_update = 1;
252 nvfx_fp_emit(fpc, insn);
253
254 fpc->inst_offset = fpc->fp->insn_len;
255 grow_insns(fpc, 4);
256 hw = &fpc->fp->insn[fpc->inst_offset];
257 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
258 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
259 NV40_FP_OP_OUT_NONE |
260 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
261 /* Use .xxxx swizzle so that we check only src[0].x*/
262 hw[1] = (0 << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
263 (0 << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
264 (0 << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
265 (0 << NVFX_FP_OP_COND_SWZ_W_SHIFT) |
266 (NVFX_FP_OP_COND_NE << NVFX_FP_OP_COND_SHIFT);
267 hw[2] = 0; /* | NV40_FP_OP_OPCODE_IS_BRANCH | else_offset */
268 hw[3] = 0; /* | endif_offset */
269 util_dynarray_append(&fpc->if_stack, unsigned, fpc->inst_offset);
270 }
271
272 /* IF src.x != 0, as TGSI specifies */
273 static void
274 nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
275 {
276 struct nvfx_relocation reloc;
277 uint32_t *hw;
278 fpc->inst_offset = fpc->fp->insn_len;
279 grow_insns(fpc, 4);
280 hw = &fpc->fp->insn[fpc->inst_offset];
281 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
282 hw[0] = (NV40_FP_OP_BRA_OPCODE_CAL << NVFX_FP_OP_OPCODE_SHIFT);
283 /* Use .xxxx swizzle so that we check only src[0].x*/
284 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
285 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
286 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
287 hw[3] = 0;
288 reloc.target = target;
289 reloc.location = fpc->inst_offset + 2;
290 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
291 }
292
293 static void
294 nv40_fp_ret(struct nvfx_fpc *fpc)
295 {
296 uint32_t *hw;
297 fpc->inst_offset = fpc->fp->insn_len;
298 grow_insns(fpc, 4);
299 hw = &fpc->fp->insn[fpc->inst_offset];
300 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
301 hw[0] = (NV40_FP_OP_BRA_OPCODE_RET << NVFX_FP_OP_OPCODE_SHIFT);
302 /* Use .xxxx swizzle so that we check only src[0].x*/
303 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
304 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
305 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
306 hw[3] = 0;
307 }
308
309 static void
310 nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
311 {
312 struct nvfx_relocation reloc;
313 uint32_t *hw;
314 fpc->inst_offset = fpc->fp->insn_len;
315 grow_insns(fpc, 4);
316 hw = &fpc->fp->insn[fpc->inst_offset];
317 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
318 hw[0] = (NV40_FP_OP_BRA_OPCODE_REP << NVFX_FP_OP_OPCODE_SHIFT) |
319 NV40_FP_OP_OUT_NONE |
320 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
321 /* Use .xxxx swizzle so that we check only src[0].x*/
322 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
323 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
324 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH |
325 (count << NV40_FP_OP_REP_COUNT1_SHIFT) |
326 (count << NV40_FP_OP_REP_COUNT2_SHIFT) |
327 (count << NV40_FP_OP_REP_COUNT3_SHIFT);
328 hw[3] = 0; /* | end_offset */
329 reloc.target = target;
330 reloc.location = fpc->inst_offset + 3;
331 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
332 //util_dynarray_append(&fpc->loop_stack, unsigned, target);
333 }
334
335 /* warning: this only works forward, and probably only if not inside any IF */
336 static void
337 nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
338 {
339 struct nvfx_relocation reloc;
340 uint32_t *hw;
341 fpc->inst_offset = fpc->fp->insn_len;
342 grow_insns(fpc, 4);
343 hw = &fpc->fp->insn[fpc->inst_offset];
344 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
345 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
346 NV40_FP_OP_OUT_NONE |
347 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
348 /* Use .xxxx swizzle so that we check only src[0].x*/
349 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
350 (NVFX_FP_OP_COND_FL << NVFX_FP_OP_COND_SHIFT);
351 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | else_offset */
352 hw[3] = 0; /* | endif_offset */
353 reloc.target = target;
354 reloc.location = fpc->inst_offset + 2;
355 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
356 reloc.target = target;
357 reloc.location = fpc->inst_offset + 3;
358 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
359 }
360
361 static void
362 nv40_fp_brk(struct nvfx_fpc *fpc)
363 {
364 uint32_t *hw;
365 fpc->inst_offset = fpc->fp->insn_len;
366 grow_insns(fpc, 4);
367 hw = &fpc->fp->insn[fpc->inst_offset];
368 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
369 hw[0] = (NV40_FP_OP_BRA_OPCODE_BRK << NVFX_FP_OP_OPCODE_SHIFT) |
370 NV40_FP_OP_OUT_NONE;
371 /* Use .xxxx swizzle so that we check only src[0].x*/
372 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
373 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
374 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH;
375 hw[3] = 0;
376 }
377
378 static INLINE struct nvfx_src
379 tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
380 {
381 struct nvfx_src src;
382
383 switch (fsrc->Register.File) {
384 case TGSI_FILE_INPUT:
385 if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
386 assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
387 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
388 } else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
389 if(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0)
390 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
391 else if(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 1)
392 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
393 else
394 assert(0);
395 } else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
396 assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
397 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
398 } else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
399 /* TODO: check this has the correct values */
400 /* XXX: what do we do for nv30 here (assuming it lacks facing)?! */
401 assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
402 src.reg = nvfx_reg(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
403 } else {
404 assert(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
405 src.reg = nvfx_reg(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->pfp->info.input_semantic_index[fsrc->Register.Index]]);
406 }
407 break;
408 case TGSI_FILE_CONSTANT:
409 src.reg = nvfx_reg(NVFXSR_CONST, fsrc->Register.Index);
410 break;
411 case TGSI_FILE_IMMEDIATE:
412 assert(fsrc->Register.Index < fpc->nr_imm);
413 src.reg = fpc->r_imm[fsrc->Register.Index];
414 break;
415 case TGSI_FILE_TEMPORARY:
416 src.reg = fpc->r_temp[fsrc->Register.Index];
417 break;
418 /* NV40 fragprog result regs are just temps, so this is simple */
419 case TGSI_FILE_OUTPUT:
420 src.reg = fpc->r_result[fsrc->Register.Index];
421 break;
422 default:
423 NOUVEAU_ERR("bad src file\n");
424 src.reg.index = 0;
425 src.reg.type = 0;
426 break;
427 }
428
429 src.abs = fsrc->Register.Absolute;
430 src.negate = fsrc->Register.Negate;
431 src.swz[0] = fsrc->Register.SwizzleX;
432 src.swz[1] = fsrc->Register.SwizzleY;
433 src.swz[2] = fsrc->Register.SwizzleZ;
434 src.swz[3] = fsrc->Register.SwizzleW;
435 src.indirect = 0;
436 src.indirect_reg = 0;
437 src.indirect_swz = 0;
438 return src;
439 }
440
441 static INLINE struct nvfx_reg
442 tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
443 switch (fdst->Register.File) {
444 case TGSI_FILE_OUTPUT:
445 return fpc->r_result[fdst->Register.Index];
446 case TGSI_FILE_TEMPORARY:
447 return fpc->r_temp[fdst->Register.Index];
448 case TGSI_FILE_NULL:
449 return nvfx_reg(NVFXSR_NONE, 0);
450 default:
451 NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
452 return nvfx_reg(NVFXSR_NONE, 0);
453 }
454 }
455
456 static INLINE int
457 tgsi_mask(uint tgsi)
458 {
459 int mask = 0;
460
461 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_FP_MASK_X;
462 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_FP_MASK_Y;
463 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_FP_MASK_Z;
464 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_FP_MASK_W;
465 return mask;
466 }
467
468 static boolean
469 nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
470 const struct tgsi_full_instruction *finst)
471 {
472 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
473 struct nvfx_insn insn;
474 struct nvfx_src src[3], tmp;
475 struct nvfx_reg dst;
476 int mask, sat, unit = 0;
477 int ai = -1, ci = -1, ii = -1;
478 int i;
479
480 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
481 return TRUE;
482
483 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
484 const struct tgsi_full_src_register *fsrc;
485
486 fsrc = &finst->Src[i];
487 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
488 src[i] = tgsi_src(fpc, fsrc);
489 }
490 }
491
492 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
493 const struct tgsi_full_src_register *fsrc;
494
495 fsrc = &finst->Src[i];
496
497 switch (fsrc->Register.File) {
498 case TGSI_FILE_INPUT:
499 if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG && (0
500 || fsrc->Register.SwizzleX == PIPE_SWIZZLE_ALPHA
501 || fsrc->Register.SwizzleY == PIPE_SWIZZLE_ALPHA
502 || fsrc->Register.SwizzleZ == PIPE_SWIZZLE_ALPHA
503 || fsrc->Register.SwizzleW == PIPE_SWIZZLE_ALPHA
504 )) {
505 /* hardware puts 0 in fogcoord.w, but GL/Gallium want 1 there */
506 struct nvfx_src addend = nvfx_src(nvfx_fp_imm(fpc, 0, 0, 0, 1));
507 addend.swz[0] = fsrc->Register.SwizzleX;
508 addend.swz[1] = fsrc->Register.SwizzleY;
509 addend.swz[2] = fsrc->Register.SwizzleZ;
510 addend.swz[3] = fsrc->Register.SwizzleW;
511 src[i] = nvfx_src(temp(fpc));
512 nvfx_fp_emit(fpc, arith(0, ADD, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), addend, none));
513 } else if (ai == -1 || ai == fsrc->Register.Index) {
514 ai = fsrc->Register.Index;
515 src[i] = tgsi_src(fpc, fsrc);
516 } else {
517 src[i] = nvfx_src(temp(fpc));
518 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
519 }
520 break;
521 case TGSI_FILE_CONSTANT:
522 if ((ci == -1 && ii == -1) ||
523 ci == fsrc->Register.Index) {
524 ci = fsrc->Register.Index;
525 src[i] = tgsi_src(fpc, fsrc);
526 } else {
527 src[i] = nvfx_src(temp(fpc));
528 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
529 }
530 break;
531 case TGSI_FILE_IMMEDIATE:
532 if ((ci == -1 && ii == -1) ||
533 ii == fsrc->Register.Index) {
534 ii = fsrc->Register.Index;
535 src[i] = tgsi_src(fpc, fsrc);
536 } else {
537 src[i] = nvfx_src(temp(fpc));
538 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
539 }
540 break;
541 case TGSI_FILE_TEMPORARY:
542 /* handled above */
543 break;
544 case TGSI_FILE_SAMPLER:
545 unit = fsrc->Register.Index;
546 break;
547 case TGSI_FILE_OUTPUT:
548 break;
549 default:
550 NOUVEAU_ERR("bad src file\n");
551 return FALSE;
552 }
553 }
554
555 dst = tgsi_dst(fpc, &finst->Dst[0]);
556 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
557 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
558
559 switch (finst->Instruction.Opcode) {
560 case TGSI_OPCODE_ABS:
561 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, abs(src[0]), none, none));
562 break;
563 case TGSI_OPCODE_ADD:
564 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
565 break;
566 case TGSI_OPCODE_CMP:
567 insn = arith(0, MOV, none.reg, mask, src[0], none, none);
568 insn.cc_update = 1;
569 nvfx_fp_emit(fpc, insn);
570
571 insn = arith(sat, MOV, dst, mask, src[2], none, none);
572 insn.cc_test = NVFX_COND_GE;
573 nvfx_fp_emit(fpc, insn);
574
575 insn = arith(sat, MOV, dst, mask, src[1], none, none);
576 insn.cc_test = NVFX_COND_LT;
577 nvfx_fp_emit(fpc, insn);
578 break;
579 case TGSI_OPCODE_COS:
580 nvfx_fp_emit(fpc, arith(sat, COS, dst, mask, src[0], none, none));
581 break;
582 case TGSI_OPCODE_DDX:
583 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
584 tmp = nvfx_src(temp(fpc));
585 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
586 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
587 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
588 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
589 } else {
590 nvfx_fp_emit(fpc, arith(sat, DDX, dst, mask, src[0], none, none));
591 }
592 break;
593 case TGSI_OPCODE_DDY:
594 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
595 tmp = nvfx_src(temp(fpc));
596 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
597 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
598 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
599 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
600 } else {
601 nvfx_fp_emit(fpc, arith(sat, DDY, dst, mask, src[0], none, none));
602 }
603 break;
604 case TGSI_OPCODE_DP2:
605 tmp = nvfx_src(temp(fpc));
606 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], src[1], none));
607 nvfx_fp_emit(fpc, arith(0, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none));
608 break;
609 case TGSI_OPCODE_DP3:
610 nvfx_fp_emit(fpc, arith(sat, DP3, dst, mask, src[0], src[1], none));
611 break;
612 case TGSI_OPCODE_DP4:
613 nvfx_fp_emit(fpc, arith(sat, DP4, dst, mask, src[0], src[1], none));
614 break;
615 case TGSI_OPCODE_DPH:
616 tmp = nvfx_src(temp(fpc));
617 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[1], none));
618 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, swz(tmp, X, X, X, X), swz(src[1], W, W, W, W), none));
619 break;
620 case TGSI_OPCODE_DST:
621 nvfx_fp_emit(fpc, arith(sat, DST, dst, mask, src[0], src[1], none));
622 break;
623 case TGSI_OPCODE_EX2:
624 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, src[0], none, none));
625 break;
626 case TGSI_OPCODE_FLR:
627 nvfx_fp_emit(fpc, arith(sat, FLR, dst, mask, src[0], none, none));
628 break;
629 case TGSI_OPCODE_FRC:
630 nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none));
631 break;
632 case TGSI_OPCODE_KILP:
633 nvfx_fp_emit(fpc, arith(0, KIL, none.reg, 0, none, none, none));
634 break;
635 case TGSI_OPCODE_KIL:
636 insn = arith(0, MOV, none.reg, NVFX_FP_MASK_ALL, src[0], none, none);
637 insn.cc_update = 1;
638 nvfx_fp_emit(fpc, insn);
639
640 insn = arith(0, KIL, none.reg, 0, none, none, none);
641 insn.cc_test = NVFX_COND_LT;
642 nvfx_fp_emit(fpc, insn);
643 break;
644 case TGSI_OPCODE_LG2:
645 nvfx_fp_emit(fpc, arith(sat, LG2, dst, mask, src[0], none, none));
646 break;
647 case TGSI_OPCODE_LIT:
648 if(!nvfx->is_nv4x)
649 nvfx_fp_emit(fpc, arith(sat, LIT_NV30, dst, mask, src[0], src[1], src[2]));
650 else {
651 /* we use FLT_MIN, so that log2 never gives -infinity, and thus multiplication by
652 * specular 0 always gives 0, so that ex2 gives 1, to satisfy the 0^0 = 1 requirement
653 *
654 * NOTE: if we start using half precision, we might need an fp16 FLT_MIN here instead
655 */
656 struct nvfx_src maxs = nvfx_src(nvfx_fp_imm(fpc, 0, FLT_MIN, 0, 0));
657 tmp = nvfx_src(temp(fpc));
658 if (ci>= 0 || ii >= 0) {
659 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, maxs, none, none));
660 maxs = tmp;
661 }
662 nvfx_fp_emit(fpc, arith(0, MAX, tmp.reg, NVFX_FP_MASK_Y | NVFX_FP_MASK_W, swz(src[0], X, X, X, Y), swz(maxs, X, X, Y, Y), none));
663 nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), none, none));
664 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), swz(src[0], W, W, W, W), none));
665 nvfx_fp_emit(fpc, arith(sat, LITEX2_NV40, dst, mask, swz(tmp, Y, Y, W, W), none, none));
666 }
667 break;
668 case TGSI_OPCODE_LRP:
669 if(!nvfx->is_nv4x)
670 nvfx_fp_emit(fpc, arith(sat, LRP_NV30, dst, mask, src[0], src[1], src[2]));
671 else {
672 tmp = nvfx_src(temp(fpc));
673 nvfx_fp_emit(fpc, arith(0, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
674 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], tmp));
675 }
676 break;
677 case TGSI_OPCODE_MAD:
678 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], src[2]));
679 break;
680 case TGSI_OPCODE_MAX:
681 nvfx_fp_emit(fpc, arith(sat, MAX, dst, mask, src[0], src[1], none));
682 break;
683 case TGSI_OPCODE_MIN:
684 nvfx_fp_emit(fpc, arith(sat, MIN, dst, mask, src[0], src[1], none));
685 break;
686 case TGSI_OPCODE_MOV:
687 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, src[0], none, none));
688 break;
689 case TGSI_OPCODE_MUL:
690 nvfx_fp_emit(fpc, arith(sat, MUL, dst, mask, src[0], src[1], none));
691 break;
692 case TGSI_OPCODE_NOP:
693 break;
694 case TGSI_OPCODE_POW:
695 if(!nvfx->is_nv4x)
696 nvfx_fp_emit(fpc, arith(sat, POW_NV30, dst, mask, src[0], src[1], none));
697 else {
698 tmp = nvfx_src(temp(fpc));
699 nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
700 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
701 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, swz(tmp, X, X, X, X), none, none));
702 }
703 break;
704 case TGSI_OPCODE_RCP:
705 nvfx_fp_emit(fpc, arith(sat, RCP, dst, mask, src[0], none, none));
706 break;
707 case TGSI_OPCODE_RFL:
708 if(!nvfx->is_nv4x)
709 nvfx_fp_emit(fpc, arith(0, RFL_NV30, dst, mask, src[0], src[1], none));
710 else {
711 tmp = nvfx_src(temp(fpc));
712 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[0], none));
713 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_Y, src[0], src[1], none));
714 insn = arith(0, DIV, tmp.reg, NVFX_FP_MASK_Z, swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
715 insn.scale = NVFX_FP_OP_DST_SCALE_2X;
716 nvfx_fp_emit(fpc, insn);
717 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, swz(tmp, Z, Z, Z, Z), src[0], neg(src[1])));
718 }
719 break;
720 case TGSI_OPCODE_RSQ:
721 if(!nvfx->is_nv4x)
722 nvfx_fp_emit(fpc, arith(sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none));
723 else {
724 tmp = nvfx_src(temp(fpc));
725 insn = arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, abs(swz(src[0], X, X, X, X)), none, none);
726 insn.scale = NVFX_FP_OP_DST_SCALE_INV_2X;
727 nvfx_fp_emit(fpc, insn);
728 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, neg(swz(tmp, X, X, X, X)), none, none));
729 }
730 break;
731 case TGSI_OPCODE_SCS:
732 /* avoid overwriting the source */
733 if(src[0].swz[NVFX_SWZ_X] != NVFX_SWZ_X)
734 {
735 if (mask & NVFX_FP_MASK_X)
736 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
737 if (mask & NVFX_FP_MASK_Y)
738 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
739 }
740 else
741 {
742 if (mask & NVFX_FP_MASK_Y)
743 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
744 if (mask & NVFX_FP_MASK_X)
745 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
746 }
747 break;
748 case TGSI_OPCODE_SEQ:
749 nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
750 break;
751 case TGSI_OPCODE_SFL:
752 nvfx_fp_emit(fpc, arith(sat, SFL, dst, mask, src[0], src[1], none));
753 break;
754 case TGSI_OPCODE_SGE:
755 nvfx_fp_emit(fpc, arith(sat, SGE, dst, mask, src[0], src[1], none));
756 break;
757 case TGSI_OPCODE_SGT:
758 nvfx_fp_emit(fpc, arith(sat, SGT, dst, mask, src[0], src[1], none));
759 break;
760 case TGSI_OPCODE_SIN:
761 nvfx_fp_emit(fpc, arith(sat, SIN, dst, mask, src[0], none, none));
762 break;
763 case TGSI_OPCODE_SLE:
764 nvfx_fp_emit(fpc, arith(sat, SLE, dst, mask, src[0], src[1], none));
765 break;
766 case TGSI_OPCODE_SLT:
767 nvfx_fp_emit(fpc, arith(sat, SLT, dst, mask, src[0], src[1], none));
768 break;
769 case TGSI_OPCODE_SNE:
770 nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none));
771 break;
772 case TGSI_OPCODE_SSG:
773 {
774 struct nvfx_src minones = swz(nvfx_src(nvfx_fp_imm(fpc, -1, -1, -1, -1)), X, X, X, X);
775
776 insn = arith(sat, MOV, dst, mask, src[0], none, none);
777 insn.cc_update = 1;
778 nvfx_fp_emit(fpc, insn);
779
780 insn = arith(0, STR, dst, mask, none, none, none);
781 insn.cc_test = NVFX_COND_GT;
782 nvfx_fp_emit(fpc, insn);
783
784 if(!sat) {
785 insn = arith(0, MOV, dst, mask, minones, none, none);
786 insn.cc_test = NVFX_COND_LT;
787 nvfx_fp_emit(fpc, insn);
788 }
789 break;
790 }
791 case TGSI_OPCODE_STR:
792 nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
793 break;
794 case TGSI_OPCODE_SUB:
795 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
796 break;
797 case TGSI_OPCODE_TEX:
798 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
799 break;
800 case TGSI_OPCODE_TRUNC:
801 tmp = nvfx_src(temp(fpc));
802 insn = arith(0, MOV, none.reg, mask, src[0], none, none);
803 insn.cc_update = 1;
804 nvfx_fp_emit(fpc, insn);
805
806 nvfx_fp_emit(fpc, arith(0, FLR, tmp.reg, mask, abs(src[0]), none, none));
807 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, tmp, none, none));
808
809 insn = arith(sat, MOV, dst, mask, neg(tmp), none, none);
810 insn.cc_test = NVFX_COND_LT;
811 nvfx_fp_emit(fpc, insn);
812 break;
813 case TGSI_OPCODE_TXB:
814 nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
815 break;
816 case TGSI_OPCODE_TXL:
817 if(nvfx->is_nv4x)
818 nvfx_fp_emit(fpc, tex(sat, TXL_NV40, unit, dst, mask, src[0], none, none));
819 else /* unsupported on nv30, use TEX and hope they like it */
820 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
821 break;
822 case TGSI_OPCODE_TXP:
823 nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
824 break;
825 case TGSI_OPCODE_XPD:
826 tmp = nvfx_src(temp(fpc));
827 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
828 nvfx_fp_emit(fpc, arith(sat, MAD, dst, (mask & ~NVFX_FP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
829 break;
830
831 case TGSI_OPCODE_IF:
832 // MOVRC0 R31 (TR0.xyzw), R<src>:
833 // IF (NE.xxxx) ELSE <else> END <end>
834 if(!nvfx->use_nv4x)
835 goto nv3x_cflow;
836 nv40_fp_if(fpc, src[0]);
837 break;
838
839 case TGSI_OPCODE_ELSE:
840 {
841 uint32_t *hw;
842 if(!nvfx->use_nv4x)
843 goto nv3x_cflow;
844 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
845 hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
846 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
847 break;
848 }
849
850 case TGSI_OPCODE_ENDIF:
851 {
852 uint32_t *hw;
853 if(!nvfx->use_nv4x)
854 goto nv3x_cflow;
855 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
856 hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
857 if(!hw[2])
858 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
859 hw[3] = fpc->fp->insn_len;
860 break;
861 }
862
863 case TGSI_OPCODE_BRA:
864 /* This can in limited cases be implemented with an IF with the else and endif labels pointing to the target */
865 /* no state tracker uses this, so don't implement this for now */
866 assert(0);
867 nv40_fp_bra(fpc, finst->Label.Label);
868 break;
869
870 case TGSI_OPCODE_BGNSUB:
871 case TGSI_OPCODE_ENDSUB:
872 /* nothing to do here */
873 break;
874
875 case TGSI_OPCODE_CAL:
876 if(!nvfx->use_nv4x)
877 goto nv3x_cflow;
878 nv40_fp_cal(fpc, finst->Label.Label);
879 break;
880
881 case TGSI_OPCODE_RET:
882 if(!nvfx->use_nv4x)
883 goto nv3x_cflow;
884 nv40_fp_ret(fpc);
885 break;
886
887 case TGSI_OPCODE_BGNLOOP:
888 if(!nvfx->use_nv4x)
889 goto nv3x_cflow;
890 /* TODO: we should support using two nested REPs to allow a > 255 iteration count */
891 nv40_fp_rep(fpc, 255, finst->Label.Label);
892 break;
893
894 case TGSI_OPCODE_ENDLOOP:
895 break;
896
897 case TGSI_OPCODE_BRK:
898 if(!nvfx->use_nv4x)
899 goto nv3x_cflow;
900 nv40_fp_brk(fpc);
901 break;
902
903 case TGSI_OPCODE_CONT:
904 {
905 static int warned = 0;
906 if(!warned) {
907 NOUVEAU_ERR("Sorry, the continue keyword is not implemented: ignoring it.\n");
908 warned = 1;
909 }
910 break;
911 }
912
913 default:
914 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
915 return FALSE;
916 }
917
918 out:
919 release_temps(fpc);
920 return TRUE;
921 nv3x_cflow:
922 {
923 static int warned = 0;
924 if(!warned) {
925 NOUVEAU_ERR(
926 "Sorry, control flow instructions are not supported in hardware on nv3x: ignoring them\n"
927 "If rendering is incorrect, try to disable GLSL support in the application.\n");
928 warned = 1;
929 }
930 }
931 goto out;
932 }
933
934 static boolean
935 nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
936 const struct tgsi_full_declaration *fdec)
937 {
938 unsigned idx = fdec->Range.First;
939 unsigned hw;
940
941 switch (fdec->Semantic.Name) {
942 case TGSI_SEMANTIC_POSITION:
943 hw = 1;
944 break;
945 case TGSI_SEMANTIC_COLOR:
946 hw = ~0;
947 switch (fdec->Semantic.Index) {
948 case 0: hw = 0; break;
949 case 1: hw = 2; break;
950 case 2: hw = 3; break;
951 case 3: hw = 4; break;
952 }
953 if(hw > ((nvfx->use_nv4x) ? 4 : 2)) {
954 NOUVEAU_ERR("bad rcol index\n");
955 return FALSE;
956 }
957 break;
958 default:
959 NOUVEAU_ERR("bad output semantic\n");
960 return FALSE;
961 }
962
963 fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
964 fpc->r_temps |= (1ULL << hw);
965 return TRUE;
966 }
967
968 static boolean
969 nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
970 {
971 struct tgsi_parse_context p;
972 int high_temp = -1, i;
973 struct util_semantic_set set;
974 unsigned num_texcoords = nvfx->use_nv4x ? 10 : 8;
975
976 fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->pfp->pipe.tokens, TGSI_FILE_INPUT);
977 if(fpc->fp->num_slots > num_texcoords)
978 return FALSE;
979 util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, num_texcoords);
980 util_semantic_table_from_layout(fpc->generic_to_slot, sizeof fpc->generic_to_slot,
981 fpc->fp->slot_to_generic, 0, num_texcoords);
982
983 memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input));
984
985 fpc->r_imm = CALLOC(fpc->pfp->info.immediate_count, sizeof(struct nvfx_reg));
986
987 tgsi_parse_init(&p, fpc->pfp->pipe.tokens);
988 while (!tgsi_parse_end_of_tokens(&p)) {
989 const union tgsi_full_token *tok = &p.FullToken;
990
991 tgsi_parse_token(&p);
992 switch(tok->Token.Type) {
993 case TGSI_TOKEN_TYPE_DECLARATION:
994 {
995 const struct tgsi_full_declaration *fdec;
996 fdec = &p.FullToken.FullDeclaration;
997 switch (fdec->Declaration.File) {
998 case TGSI_FILE_OUTPUT:
999 if (!nvfx_fragprog_parse_decl_output(nvfx, fpc, fdec))
1000 goto out_err;
1001 break;
1002 case TGSI_FILE_TEMPORARY:
1003 if (fdec->Range.Last > high_temp) {
1004 high_temp =
1005 fdec->Range.Last;
1006 }
1007 break;
1008 default:
1009 break;
1010 }
1011 }
1012 break;
1013 case TGSI_TOKEN_TYPE_IMMEDIATE:
1014 {
1015 struct tgsi_full_immediate *imm;
1016
1017 imm = &p.FullToken.FullImmediate;
1018 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
1019 assert(fpc->nr_imm < fpc->pfp->info.immediate_count);
1020
1021 fpc->r_imm[fpc->nr_imm++] = nvfx_fp_imm(fpc, imm->u[0].Float, imm->u[1].Float, imm->u[2].Float, imm->u[3].Float);
1022 break;
1023 }
1024 default:
1025 break;
1026 }
1027 }
1028 tgsi_parse_free(&p);
1029
1030 if (++high_temp) {
1031 fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
1032 for (i = 0; i < high_temp; i++)
1033 fpc->r_temp[i] = temp(fpc);
1034 fpc->r_temps_discard = 0ULL;
1035 }
1036
1037 return TRUE;
1038
1039 out_err:
1040 if (fpc->r_temp) {
1041 FREE(fpc->r_temp);
1042 fpc->r_temp = NULL;
1043 }
1044 tgsi_parse_free(&p);
1045 return FALSE;
1046 }
1047
1048 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE)
1049
1050 static struct nvfx_fragment_program*
1051 nvfx_fragprog_translate(struct nvfx_context *nvfx,
1052 struct nvfx_pipe_fragment_program *pfp,
1053 boolean emulate_sprite_flipping)
1054 {
1055 struct tgsi_parse_context parse;
1056 struct nvfx_fpc *fpc = NULL;
1057 struct util_dynarray insns;
1058 struct nvfx_fragment_program* fp = NULL;
1059 const int min_size = 4096;
1060
1061 fp = CALLOC_STRUCT(nvfx_fragment_program);
1062 if(!fp)
1063 goto out_err;
1064
1065 fpc = CALLOC_STRUCT(nvfx_fpc);
1066 if (!fpc)
1067 goto out_err;
1068
1069 fpc->max_temps = nvfx->use_nv4x ? 48 : 32;
1070 fpc->pfp = pfp;
1071 fpc->fp = fp;
1072 fpc->num_regs = 2;
1073
1074 for (unsigned i = 0; i < pfp->info.num_properties; ++i) {
1075 if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_ORIGIN) {
1076 if(pfp->info.properties[i].data[0])
1077 fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED;
1078 } else if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_PIXEL_CENTER) {
1079 if(pfp->info.properties[i].data[0])
1080 fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER;
1081 }
1082 }
1083
1084 if (!nvfx_fragprog_prepare(nvfx, fpc))
1085 goto out_err;
1086
1087 tgsi_parse_init(&parse, pfp->pipe.tokens);
1088 util_dynarray_init(&insns);
1089
1090 if(emulate_sprite_flipping)
1091 {
1092 struct nvfx_reg reg = temp(fpc);
1093 struct nvfx_src sprite_input = nvfx_src(nvfx_reg(NVFXSR_RELOCATED, fp->num_slots));
1094 struct nvfx_src imm = nvfx_src(nvfx_fp_imm(fpc, 1, -1, 0, 0));
1095
1096 fpc->sprite_coord_temp = reg.index;
1097 fpc->r_temps_discard = 0ULL;
1098 nvfx_fp_emit(fpc, arith(0, MAD, reg, NVFX_FP_MASK_ALL, sprite_input, swz(imm, X, Y, X, X), swz(imm, Z, X, Z, Z)));
1099 }
1100
1101 while (!tgsi_parse_end_of_tokens(&parse)) {
1102 tgsi_parse_token(&parse);
1103
1104 switch (parse.FullToken.Token.Type) {
1105 case TGSI_TOKEN_TYPE_INSTRUCTION:
1106 {
1107 const struct tgsi_full_instruction *finst;
1108
1109 util_dynarray_append(&insns, unsigned, fp->insn_len);
1110 finst = &parse.FullToken.FullInstruction;
1111 if (!nvfx_fragprog_parse_instruction(nvfx, fpc, finst))
1112 goto out_err;
1113 }
1114 break;
1115 default:
1116 break;
1117 }
1118 }
1119 util_dynarray_append(&insns, unsigned, fp->insn_len);
1120
1121 for(unsigned i = 0; i < fpc->label_relocs.size; i += sizeof(struct nvfx_relocation))
1122 {
1123 struct nvfx_relocation* label_reloc = (struct nvfx_relocation*)((char*)fpc->label_relocs.data + i);
1124 fp->insn[label_reloc->location] |= ((unsigned*)insns.data)[label_reloc->target];
1125 }
1126 util_dynarray_fini(&insns);
1127
1128 if(!nvfx->is_nv4x)
1129 fp->fp_control |= (fpc->num_regs-1)/2;
1130 else
1131 fp->fp_control |= fpc->num_regs << NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT;
1132
1133 /* Terminate final instruction */
1134 if(fp->insn)
1135 fp->insn[fpc->inst_offset] |= 0x00000001;
1136
1137 /* Append NOP + END instruction for branches to the end of the program */
1138 fpc->inst_offset = fp->insn_len;
1139 grow_insns(fpc, 4);
1140 fp->insn[fpc->inst_offset + 0] = 0x00000001;
1141 fp->insn[fpc->inst_offset + 1] = 0x00000000;
1142 fp->insn[fpc->inst_offset + 2] = 0x00000000;
1143 fp->insn[fpc->inst_offset + 3] = 0x00000000;
1144
1145 if(debug_get_option_nvfx_dump_fp())
1146 {
1147 debug_printf("\n");
1148 tgsi_dump(pfp->pipe.tokens, 0);
1149
1150 debug_printf("\n%s fragment program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
1151 for (unsigned i = 0; i < fp->insn_len; i += 4)
1152 debug_printf("%3u: %08x %08x %08x %08x\n", i >> 2, fp->insn[i], fp->insn[i + 1], fp->insn[i + 2], fp->insn[i + 3]);
1153 debug_printf("\n");
1154 }
1155
1156 fp->prog_size = (fp->insn_len * 4 + 63) & ~63;
1157
1158 if(fp->prog_size >= min_size)
1159 fp->progs_per_bo = 1;
1160 else
1161 fp->progs_per_bo = min_size / fp->prog_size;
1162 fp->bo_prog_idx = fp->progs_per_bo - 1;
1163
1164 out:
1165 tgsi_parse_free(&parse);
1166 if(fpc)
1167 {
1168 if (fpc->r_temp)
1169 FREE(fpc->r_temp);
1170 util_dynarray_fini(&fpc->if_stack);
1171 util_dynarray_fini(&fpc->label_relocs);
1172 util_dynarray_fini(&fpc->imm_data);
1173 //util_dynarray_fini(&fpc->loop_stack);
1174 FREE(fpc);
1175 }
1176 return fp;
1177
1178 out_err:
1179 _debug_printf("Error: failed to compile this fragment program:\n");
1180 tgsi_dump(pfp->pipe.tokens, 0);
1181
1182 if(fp)
1183 {
1184 FREE(fp);
1185 fp = NULL;
1186 }
1187 goto out;
1188 }
1189
1190 static inline void
1191 nvfx_fp_memcpy(void* dst, const void* src, size_t len)
1192 {
1193 #ifndef PIPE_ARCH_BIG_ENDIAN
1194 memcpy(dst, src, len);
1195 #else
1196 size_t i;
1197 for(i = 0; i < len; i += 4) {
1198 uint32_t v = *(uint32_t*)((char*)src + i);
1199 *(uint32_t*)((char*)dst + i) = (v >> 16) | (v << 16);
1200 }
1201 #endif
1202 }
1203
1204 /* The hardware only supports immediate constants inside the fragment program,
1205 * and at least on nv30 doesn't support an indirect linkage table.
1206 *
1207 * Hence, we need to patch the fragment program itself both to update constants
1208 * and update linkage.
1209 *
1210 * Using a single fragment program would entail unacceptable stalls if the GPU is
1211 * already rendering with that fragment program.
1212 * Thus, we instead use a "rotating queue" of buffer objects, each of which is
1213 * packed with multiple versions of the same program.
1214 *
1215 * Whenever we need to patch something, we move to the next program and
1216 * patch it. If all buffer objects are in use by the GPU, we allocate another one,
1217 * expanding the queue.
1218 *
1219 * As an additional optimization, we record when all the programs have the
1220 * current input slot configuration, and at that point we stop patching inputs.
1221 * This happens, for instance, if a given fragment program is always used with
1222 * the same vertex program (i.e. always with GLSL), or if the layouts match
1223 * enough (non-GLSL).
1224 *
1225 * Note that instead of using multiple programs, we could push commands
1226 * on the FIFO to patch a single program: it's not fully clear which option is
1227 * faster, but my guess is that the current way is faster.
1228 *
1229 * We also track the previous slot assignments for each version and don't
1230 * patch if they are the same (this could perhaps be removed).
1231 */
1232
1233 void
1234 nvfx_fragprog_validate(struct nvfx_context *nvfx)
1235 {
1236 struct nouveau_channel* chan = nvfx->screen->base.channel;
1237 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
1238 struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog;
1239 struct nvfx_vertex_program* vp;
1240
1241 // TODO: the multiplication by point_quad_rasterization is probably superfluous
1242 unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
1243
1244 boolean emulate_sprite_flipping = sprite_coord_enable && nvfx->rasterizer->pipe.sprite_coord_mode;
1245 unsigned key = emulate_sprite_flipping;
1246 struct nvfx_fragment_program* fp;
1247
1248 fp = pfp->fps[key];
1249 if (!fp)
1250 {
1251 fp = nvfx_fragprog_translate(nvfx, pfp, emulate_sprite_flipping);
1252
1253 if(!fp)
1254 {
1255 if(!nvfx->dummy_fs)
1256 {
1257 struct ureg_program *ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT );
1258 if (ureg)
1259 {
1260 ureg_END( ureg );
1261 nvfx->dummy_fs = ureg_create_shader_and_destroy( ureg, &nvfx->pipe );
1262 }
1263
1264 if(!nvfx->dummy_fs)
1265 {
1266 _debug_printf("Error: unable to create a dummy fragment shader: aborting.");
1267 abort();
1268 }
1269 }
1270
1271 fp = nvfx_fragprog_translate(nvfx, nvfx->dummy_fs, FALSE);
1272 emulate_sprite_flipping = FALSE;
1273
1274 if(!fp)
1275 {
1276 _debug_printf("Error: unable to compile even a dummy fragment shader: aborting.");
1277 abort();
1278 }
1279 }
1280
1281 pfp->fps[key] = fp;
1282 }
1283
1284 vp = nvfx->hw_vertprog;
1285
1286 if (fp->last_vp_id != vp->id || fp->last_sprite_coord_enable != sprite_coord_enable) {
1287 int sprite_real_input = -1;
1288 int sprite_reloc_input;
1289 unsigned i;
1290 fp->last_vp_id = vp->id;
1291 fp->last_sprite_coord_enable = sprite_coord_enable;
1292
1293 if(sprite_coord_enable)
1294 {
1295 sprite_real_input = vp->sprite_fp_input;
1296 if(sprite_real_input < 0)
1297 {
1298 unsigned used_texcoords = 0;
1299 for(unsigned i = 0; i < fp->num_slots; ++i) {
1300 unsigned generic = fp->slot_to_generic[i];
1301 if((generic < 32) && !((1 << generic) & sprite_coord_enable))
1302 {
1303 unsigned char slot_mask = vp->generic_to_fp_input[generic];
1304 if(slot_mask >= 0xf0)
1305 used_texcoords |= 1 << ((slot_mask & 0xf) - NVFX_FP_OP_INPUT_SRC_TC0);
1306 }
1307 }
1308
1309 sprite_real_input = NVFX_FP_OP_INPUT_SRC_TC(__builtin_ctz(~used_texcoords));
1310 }
1311
1312 fp->point_sprite_control |= (1 << (sprite_real_input - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
1313 }
1314 else
1315 fp->point_sprite_control = 0;
1316
1317 if(emulate_sprite_flipping)
1318 sprite_reloc_input = 0;
1319 else
1320 sprite_reloc_input = sprite_real_input;
1321
1322 for(i = 0; i < fp->num_slots; ++i) {
1323 unsigned generic = fp->slot_to_generic[i];
1324 if((generic < 32) && ((1 << generic) & sprite_coord_enable))
1325 {
1326 if(fp->slot_to_fp_input[i] != sprite_reloc_input)
1327 goto update_slots;
1328 }
1329 else
1330 {
1331 unsigned char slot_mask = vp->generic_to_fp_input[generic];
1332 if((slot_mask >> 4) & (slot_mask ^ fp->slot_to_fp_input[i]))
1333 goto update_slots;
1334 }
1335 }
1336
1337 if(emulate_sprite_flipping)
1338 {
1339 if(fp->slot_to_fp_input[fp->num_slots] != sprite_real_input)
1340 goto update_slots;
1341 }
1342
1343 if(0)
1344 {
1345 update_slots:
1346 /* optimization: we start updating from the slot we found the first difference in */
1347 for(; i < fp->num_slots; ++i)
1348 {
1349 unsigned generic = fp->slot_to_generic[i];
1350 if((generic < 32) && ((1 << generic) & sprite_coord_enable))
1351 fp->slot_to_fp_input[i] = sprite_reloc_input;
1352 else
1353 fp->slot_to_fp_input[i] = vp->generic_to_fp_input[generic] & 0xf;
1354 }
1355
1356 fp->slot_to_fp_input[fp->num_slots] = sprite_real_input;
1357
1358 if(nvfx->is_nv4x)
1359 {
1360 fp->or = 0;
1361 for(i = 0; i <= fp->num_slots; ++i) {
1362 unsigned fp_input = fp->slot_to_fp_input[i];
1363 if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(8))
1364 fp->or |= (1 << 12);
1365 else if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(9))
1366 fp->or |= (1 << 13);
1367 else if(fp_input >= NVFX_FP_OP_INPUT_SRC_TC(0) && fp_input <= NVFX_FP_OP_INPUT_SRC_TC(7))
1368 fp->or |= (1 << (fp_input - NVFX_FP_OP_INPUT_SRC_TC0 + 14));
1369 }
1370 }
1371
1372 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
1373 goto update;
1374 }
1375 }
1376
1377 /* We must update constants even on "just" fragprog changes, because
1378 * we don't check whether the current constant buffer matches the latest
1379 * one bound to this fragment program.
1380 * Doing such a check would likely be a pessimization.
1381 */
1382 if ((nvfx->hw_fragprog != fp) || (nvfx->dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST))) {
1383 int offset;
1384 uint32_t* fpmap;
1385
1386 update:
1387 ++fp->bo_prog_idx;
1388 if(fp->bo_prog_idx >= fp->progs_per_bo)
1389 {
1390 if(fp->fpbo && !nouveau_bo_busy(fp->fpbo->next->bo, NOUVEAU_BO_WR))
1391 {
1392 fp->fpbo = fp->fpbo->next;
1393 }
1394 else
1395 {
1396 struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + (fp->prog_size + 8) * fp->progs_per_bo, 16);
1397 uint8_t* map;
1398 uint8_t* buf;
1399
1400 fpbo->slots = (unsigned char*)&fpbo->insn[(fp->prog_size) * fp->progs_per_bo];
1401 memset(fpbo->slots, 0, 8 * fp->progs_per_bo);
1402 if(fp->fpbo)
1403 {
1404 fpbo->next = fp->fpbo->next;
1405 fp->fpbo->next = fpbo;
1406 }
1407 else
1408 fpbo->next = fpbo;
1409 fp->fpbo = fpbo;
1410 fpbo->bo = 0;
1411 fp->progs += fp->progs_per_bo;
1412 fp->progs_left_with_obsolete_slot_assignments += fp->progs_per_bo;
1413 nouveau_bo_new(nvfx->screen->base.device, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, 64, fp->prog_size * fp->progs_per_bo, &fpbo->bo);
1414 nouveau_bo_map(fpbo->bo, NOUVEAU_BO_NOSYNC);
1415
1416 map = fpbo->bo->map;
1417 buf = (uint8_t*)fpbo->insn;
1418 for(unsigned i = 0; i < fp->progs_per_bo; ++i)
1419 {
1420 memcpy(buf, fp->insn, fp->insn_len * 4);
1421 nvfx_fp_memcpy(map, fp->insn, fp->insn_len * 4);
1422 map += fp->prog_size;
1423 buf += fp->prog_size;
1424 }
1425 }
1426 fp->bo_prog_idx = 0;
1427 }
1428
1429 offset = fp->bo_prog_idx * fp->prog_size;
1430 fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1431
1432 if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) {
1433 struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT];
1434 uint32_t* map = (uint32_t*)nvfx_buffer(constbuf)->data;
1435 uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1436 uint32_t* buf = (uint32_t*)((char*)fp->fpbo->insn + offset);
1437 int i;
1438 for (i = 0; i < fp->nr_consts; ++i) {
1439 unsigned off = fp->consts[i].offset;
1440 unsigned idx = fp->consts[i].index * 4;
1441
1442 /* TODO: is checking a good idea? */
1443 if(memcmp(&buf[off], &map[idx], 4 * sizeof(uint32_t))) {
1444 memcpy(&buf[off], &map[idx], 4 * sizeof(uint32_t));
1445 nvfx_fp_memcpy(&fpmap[off], &map[idx], 4 * sizeof(uint32_t));
1446 }
1447 }
1448 }
1449
1450 /* we only do this if we aren't sure that all program versions have the
1451 * current slot assignments, otherwise we just update constants for speed
1452 */
1453 if(fp->progs_left_with_obsolete_slot_assignments) {
1454 unsigned char* fpbo_slots = &fp->fpbo->slots[fp->bo_prog_idx * 8];
1455 /* also relocate sprite coord slot, if any */
1456 for(unsigned i = 0; i <= fp->num_slots; ++i) {
1457 unsigned value = fp->slot_to_fp_input[i];;
1458 if(value != fpbo_slots[i]) {
1459 unsigned* p;
1460 unsigned* begin = (unsigned*)fp->slot_relocations[i].data;
1461 unsigned* end = (unsigned*)((char*)fp->slot_relocations[i].data + fp->slot_relocations[i].size);
1462 //printf("fp %p reloc slot %u/%u: %u -> %u\n", fp, i, fp->num_slots, fpbo_slots[i], value);
1463 if(value == 0)
1464 {
1465 /* was relocated to an input, switch type to temporary */
1466 for(p = begin; p != end; ++p) {
1467 unsigned off = *p;
1468 unsigned dw = fp->insn[off];
1469 dw &=~ NVFX_FP_REG_TYPE_MASK;
1470 //printf("reloc_tmp at %x\n", off);
1471 nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
1472 }
1473 } else {
1474 if(!fpbo_slots[i])
1475 {
1476 /* was relocated to a temporary, switch type to input */
1477 for(p= begin; p != end; ++p) {
1478 unsigned off = *p;
1479 unsigned dw = fp->insn[off];
1480 //printf("reloc_in at %x\n", off);
1481 dw |= NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT;
1482 nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
1483 }
1484 }
1485
1486 /* set the correct input index */
1487 for(p = begin; p != end; ++p) {
1488 unsigned off = *p & ~3;
1489 unsigned dw = fp->insn[off];
1490 //printf("reloc&~3 at %x\n", off);
1491 dw = (dw & ~NVFX_FP_OP_INPUT_SRC_MASK) | (value << NVFX_FP_OP_INPUT_SRC_SHIFT);
1492 nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
1493 }
1494 }
1495 fpbo_slots[i] = value;
1496 }
1497 }
1498 --fp->progs_left_with_obsolete_slot_assignments;
1499 }
1500
1501 nvfx->hw_fragprog = fp;
1502
1503 MARK_RING(chan, 8, 1);
1504 BEGIN_RING(chan, eng3d, NV30_3D_FP_ACTIVE_PROGRAM, 1);
1505 OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
1506 NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
1507 NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
1508 NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
1509 BEGIN_RING(chan, eng3d, NV30_3D_FP_CONTROL, 1);
1510 OUT_RING(chan, fp->fp_control);
1511 if(!nvfx->is_nv4x) {
1512 BEGIN_RING(chan, eng3d, NV30_3D_FP_REG_CONTROL, 1);
1513 OUT_RING(chan, (1<<16)|0x4);
1514 BEGIN_RING(chan, eng3d, NV30_3D_TEX_UNITS_ENABLE, 1);
1515 OUT_RING(chan, fp->samplers);
1516 }
1517 }
1518
1519 {
1520 unsigned pointsprite_control = fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization;
1521 if(pointsprite_control != nvfx->hw_pointsprite_control)
1522 {
1523 BEGIN_RING(chan, eng3d, NV30_3D_POINT_SPRITE, 1);
1524 OUT_RING(chan, pointsprite_control);
1525 nvfx->hw_pointsprite_control = pointsprite_control;
1526 }
1527 }
1528
1529 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
1530 }
1531
1532 void
1533 nvfx_fragprog_relocate(struct nvfx_context *nvfx)
1534 {
1535 struct nouveau_channel* chan = nvfx->screen->base.channel;
1536 struct nvfx_fragment_program *fp = nvfx->hw_fragprog;
1537 struct nouveau_bo* bo = fp->fpbo->bo;
1538 int offset = fp->bo_prog_idx * fp->prog_size;
1539 unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART?
1540 fp_flags |= NOUVEAU_BO_DUMMY;
1541 MARK_RING(chan, 2, 2);
1542 OUT_RELOC(chan, bo, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
1543 OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW |
1544 NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
1545 NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
1546 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
1547 }
1548
1549 void
1550 nvfx_fragprog_destroy(struct nvfx_context *nvfx,
1551 struct nvfx_fragment_program *fp)
1552 {
1553 unsigned i;
1554 struct nvfx_fragment_program_bo* fpbo = fp->fpbo;
1555 if(fpbo)
1556 {
1557 do
1558 {
1559 struct nvfx_fragment_program_bo* next = fpbo->next;
1560 nouveau_bo_unmap(fpbo->bo);
1561 nouveau_bo_ref(0, &fpbo->bo);
1562 os_free_aligned(fpbo);
1563 fpbo = next;
1564 }
1565 while(fpbo != fp->fpbo);
1566 }
1567
1568 for(i = 0; i < Elements(fp->slot_relocations); ++i)
1569 util_dynarray_fini(&fp->slot_relocations[i]);
1570
1571 if (fp->insn_len)
1572 FREE(fp->insn);
1573 }
1574
1575 static void *
1576 nvfx_fp_state_create(struct pipe_context *pipe,
1577 const struct pipe_shader_state *cso)
1578 {
1579 struct nvfx_pipe_fragment_program *pfp;
1580
1581 pfp = CALLOC(1, sizeof(struct nvfx_pipe_fragment_program));
1582 pfp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
1583
1584 tgsi_scan_shader(pfp->pipe.tokens, &pfp->info);
1585
1586 return (void *)pfp;
1587 }
1588
1589 static void
1590 nvfx_fp_state_bind(struct pipe_context *pipe, void *hwcso)
1591 {
1592 struct nvfx_context *nvfx = nvfx_context(pipe);
1593
1594 nvfx->fragprog = hwcso;
1595 nvfx->dirty |= NVFX_NEW_FRAGPROG;
1596 }
1597
1598 static void
1599 nvfx_fp_state_delete(struct pipe_context *pipe, void *hwcso)
1600 {
1601 struct nvfx_context *nvfx = nvfx_context(pipe);
1602 struct nvfx_pipe_fragment_program *pfp = hwcso;
1603 unsigned i;
1604
1605 for(i = 0; i < Elements(pfp->fps); ++i)
1606 {
1607 if(pfp->fps[i])
1608 {
1609 nvfx_fragprog_destroy(nvfx, pfp->fps[i]);
1610 FREE(pfp->fps[i]);
1611 }
1612 }
1613
1614 FREE((void*)pfp->pipe.tokens);
1615 FREE(pfp);
1616 }
1617
1618 void
1619 nvfx_init_fragprog_functions(struct nvfx_context *nvfx)
1620 {
1621 nvfx->pipe.create_fs_state = nvfx_fp_state_create;
1622 nvfx->pipe.bind_fs_state = nvfx_fp_state_bind;
1623 nvfx->pipe.delete_fs_state = nvfx_fp_state_delete;
1624 }