1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5 #include "util/u_debug.h"
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_util.h"
10 #include "tgsi/tgsi_dump.h"
11 #include "tgsi/tgsi_ureg.h"
13 #include "nvfx_context.h"
14 #include "nvfx_shader.h"
15 #include "nvfx_resource.h"
17 #define MAX_CONSTS 128
21 struct nvfx_pipe_fragment_program
* pfp
;
22 struct nvfx_fragment_program
*fp
;
25 unsigned long long r_temps
;
26 unsigned long long r_temps_discard
;
27 struct nvfx_reg r_result
[PIPE_MAX_SHADER_OUTPUTS
];
28 struct nvfx_reg
*r_temp
;
29 unsigned sprite_coord_temp
;
42 struct nvfx_reg imm
[MAX_IMM
];
45 unsigned char generic_to_slot
[256]; /* semantic idx for each input semantic */
47 struct util_dynarray if_stack
;
48 //struct util_dynarray loop_stack;
49 struct util_dynarray label_relocs
;
52 static INLINE
struct nvfx_reg
53 temp(struct nvfx_fpc
*fpc
)
55 int idx
= __builtin_ctzll(~fpc
->r_temps
);
57 if (idx
>= fpc
->max_temps
) {
58 NOUVEAU_ERR("out of temps!!\n");
60 return nvfx_reg(NVFXSR_TEMP
, 0);
63 fpc
->r_temps
|= (1ULL << idx
);
64 fpc
->r_temps_discard
|= (1ULL << idx
);
65 return nvfx_reg(NVFXSR_TEMP
, idx
);
69 release_temps(struct nvfx_fpc
*fpc
)
71 fpc
->r_temps
&= ~fpc
->r_temps_discard
;
72 fpc
->r_temps_discard
= 0ULL;
75 static INLINE
struct nvfx_reg
76 constant(struct nvfx_fpc
*fpc
, int pipe
, float vals
[4])
80 if (fpc
->nr_consts
== MAX_CONSTS
)
82 idx
= fpc
->nr_consts
++;
84 fpc
->consts
[idx
].pipe
= pipe
;
86 memcpy(fpc
->consts
[idx
].vals
, vals
, 4 * sizeof(float));
87 return nvfx_reg(NVFXSR_CONST
, idx
);
91 grow_insns(struct nvfx_fpc
*fpc
, int size
)
93 struct nvfx_fragment_program
*fp
= fpc
->fp
;
96 fp
->insn
= realloc(fp
->insn
, sizeof(uint32_t) * fp
->insn_len
);
100 emit_src(struct nvfx_fpc
*fpc
, int pos
, struct nvfx_src src
)
102 struct nvfx_fragment_program
*fp
= fpc
->fp
;
103 uint32_t *hw
= &fp
->insn
[fpc
->inst_offset
];
106 switch (src
.reg
.type
) {
108 sr
|= (NVFX_FP_REG_TYPE_INPUT
<< NVFX_FP_REG_TYPE_SHIFT
);
109 hw
[0] |= (src
.reg
.index
<< NVFX_FP_OP_INPUT_SRC_SHIFT
);
112 sr
|= NVFX_FP_REG_SRC_HALF
;
115 sr
|= (NVFX_FP_REG_TYPE_TEMP
<< NVFX_FP_REG_TYPE_SHIFT
);
116 sr
|= (src
.reg
.index
<< NVFX_FP_REG_SRC_SHIFT
);
118 case NVFXSR_RELOCATED
:
119 sr
|= (NVFX_FP_REG_TYPE_TEMP
<< NVFX_FP_REG_TYPE_SHIFT
);
120 sr
|= (fpc
->sprite_coord_temp
<< NVFX_FP_REG_SRC_SHIFT
);
121 //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
122 util_dynarray_append(&fpc
->fp
->slot_relocations
[src
.reg
.index
], unsigned, fpc
->inst_offset
+ pos
+ 1);
125 if (!fpc
->have_const
) {
130 hw
= &fp
->insn
[fpc
->inst_offset
];
131 if (fpc
->consts
[src
.reg
.index
].pipe
>= 0) {
132 struct nvfx_fragment_program_data
*fpd
;
134 fp
->consts
= realloc(fp
->consts
, ++fp
->nr_consts
*
136 fpd
= &fp
->consts
[fp
->nr_consts
- 1];
137 fpd
->offset
= fpc
->inst_offset
+ 4;
138 fpd
->index
= fpc
->consts
[src
.reg
.index
].pipe
;
139 memset(&fp
->insn
[fpd
->offset
], 0, sizeof(uint32_t) * 4);
141 memcpy(&fp
->insn
[fpc
->inst_offset
+ 4],
142 fpc
->consts
[src
.reg
.index
].vals
,
143 sizeof(uint32_t) * 4);
146 sr
|= (NVFX_FP_REG_TYPE_CONST
<< NVFX_FP_REG_TYPE_SHIFT
);
149 sr
|= (NVFX_FP_REG_TYPE_INPUT
<< NVFX_FP_REG_TYPE_SHIFT
);
156 sr
|= NVFX_FP_REG_NEGATE
;
159 hw
[1] |= (1 << (29 + pos
));
161 sr
|= ((src
.swz
[0] << NVFX_FP_REG_SWZ_X_SHIFT
) |
162 (src
.swz
[1] << NVFX_FP_REG_SWZ_Y_SHIFT
) |
163 (src
.swz
[2] << NVFX_FP_REG_SWZ_Z_SHIFT
) |
164 (src
.swz
[3] << NVFX_FP_REG_SWZ_W_SHIFT
));
170 emit_dst(struct nvfx_fpc
*fpc
, struct nvfx_reg dst
)
172 struct nvfx_fragment_program
*fp
= fpc
->fp
;
173 uint32_t *hw
= &fp
->insn
[fpc
->inst_offset
];
177 if (fpc
->num_regs
< (dst
.index
+ 1))
178 fpc
->num_regs
= dst
.index
+ 1;
181 if (dst
.index
== 1) {
182 fp
->fp_control
|= 0xe;
184 hw
[0] |= NVFX_FP_OP_OUT_REG_HALF
;
194 hw
[0] |= (dst
.index
<< NVFX_FP_OP_OUT_REG_SHIFT
);
198 nvfx_fp_emit(struct nvfx_fpc
*fpc
, struct nvfx_insn insn
)
200 struct nvfx_fragment_program
*fp
= fpc
->fp
;
203 fpc
->inst_offset
= fp
->insn_len
;
206 hw
= &fp
->insn
[fpc
->inst_offset
];
207 memset(hw
, 0, sizeof(uint32_t) * 4);
209 if (insn
.op
== NVFX_FP_OP_OPCODE_KIL
)
210 fp
->fp_control
|= NV34TCL_FP_CONTROL_USES_KIL
;
211 hw
[0] |= (insn
.op
<< NVFX_FP_OP_OPCODE_SHIFT
);
212 hw
[0] |= (insn
.mask
<< NVFX_FP_OP_OUTMASK_SHIFT
);
213 hw
[2] |= (insn
.scale
<< NVFX_FP_OP_DST_SCALE_SHIFT
);
216 hw
[0] |= NVFX_FP_OP_OUT_SAT
;
219 hw
[0] |= NVFX_FP_OP_COND_WRITE_ENABLE
;
220 hw
[1] |= (insn
.cc_test
<< NVFX_FP_OP_COND_SHIFT
);
221 hw
[1] |= ((insn
.cc_swz
[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT
) |
222 (insn
.cc_swz
[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT
) |
223 (insn
.cc_swz
[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT
) |
224 (insn
.cc_swz
[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT
));
228 hw
[0] |= (insn
.unit
<< NVFX_FP_OP_TEX_UNIT_SHIFT
);
229 fp
->samplers
|= (1 << insn
.unit
);
232 emit_dst(fpc
, insn
.dst
);
233 emit_src(fpc
, 0, insn
.src
[0]);
234 emit_src(fpc
, 1, insn
.src
[1]);
235 emit_src(fpc
, 2, insn
.src
[2]);
238 #define arith(s,o,d,m,s0,s1,s2) \
239 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, -1, \
240 (d), (m), (s0), (s1), (s2))
242 #define tex(s,o,u,d,m,s0,s1,s2) \
243 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
244 (d), (m), (s0), none, none)
246 /* IF src.x != 0, as TGSI specifies */
248 nv40_fp_if(struct nvfx_fpc
*fpc
, struct nvfx_src src
)
250 const struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
251 struct nvfx_insn insn
= arith(0, MOV
, none
.reg
, NVFX_FP_MASK_X
, src
, none
, none
);
254 nvfx_fp_emit(fpc
, insn
);
256 fpc
->inst_offset
= fpc
->fp
->insn_len
;
258 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
259 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
260 hw
[0] = (NV40_FP_OP_BRA_OPCODE_IF
<< NVFX_FP_OP_OPCODE_SHIFT
) |
261 NV40_FP_OP_OUT_NONE
|
262 (NVFX_FP_PRECISION_FP16
<< NVFX_FP_OP_PRECISION_SHIFT
);
263 /* Use .xxxx swizzle so that we check only src[0].x*/
264 hw
[1] = (0 << NVFX_FP_OP_COND_SWZ_X_SHIFT
) |
265 (0 << NVFX_FP_OP_COND_SWZ_Y_SHIFT
) |
266 (0 << NVFX_FP_OP_COND_SWZ_Z_SHIFT
) |
267 (0 << NVFX_FP_OP_COND_SWZ_W_SHIFT
) |
268 (NVFX_FP_OP_COND_NE
<< NVFX_FP_OP_COND_SHIFT
);
269 hw
[2] = 0; /* | NV40_FP_OP_OPCODE_IS_BRANCH | else_offset */
270 hw
[3] = 0; /* | endif_offset */
271 util_dynarray_append(&fpc
->if_stack
, unsigned, fpc
->inst_offset
);
274 /* IF src.x != 0, as TGSI specifies */
276 nv40_fp_cal(struct nvfx_fpc
*fpc
, unsigned target
)
278 struct nvfx_relocation reloc
;
280 fpc
->inst_offset
= fpc
->fp
->insn_len
;
282 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
283 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
284 hw
[0] = (NV40_FP_OP_BRA_OPCODE_CAL
<< NVFX_FP_OP_OPCODE_SHIFT
);
285 /* Use .xxxx swizzle so that we check only src[0].x*/
286 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_ALL_SHIFT
) |
287 (NVFX_FP_OP_COND_TR
<< NVFX_FP_OP_COND_SHIFT
);
288 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
; /* | call_offset */
290 reloc
.target
= target
;
291 reloc
.location
= fpc
->inst_offset
+ 2;
292 util_dynarray_append(&fpc
->label_relocs
, struct nvfx_relocation
, reloc
);
296 nv40_fp_ret(struct nvfx_fpc
*fpc
)
299 fpc
->inst_offset
= fpc
->fp
->insn_len
;
301 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
302 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
303 hw
[0] = (NV40_FP_OP_BRA_OPCODE_RET
<< NVFX_FP_OP_OPCODE_SHIFT
);
304 /* Use .xxxx swizzle so that we check only src[0].x*/
305 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_ALL_SHIFT
) |
306 (NVFX_FP_OP_COND_TR
<< NVFX_FP_OP_COND_SHIFT
);
307 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
; /* | call_offset */
312 nv40_fp_rep(struct nvfx_fpc
*fpc
, unsigned count
, unsigned target
)
314 struct nvfx_relocation reloc
;
316 fpc
->inst_offset
= fpc
->fp
->insn_len
;
318 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
319 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
320 hw
[0] = (NV40_FP_OP_BRA_OPCODE_REP
<< NVFX_FP_OP_OPCODE_SHIFT
) |
321 NV40_FP_OP_OUT_NONE
|
322 (NVFX_FP_PRECISION_FP16
<< NVFX_FP_OP_PRECISION_SHIFT
);
323 /* Use .xxxx swizzle so that we check only src[0].x*/
324 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_ALL_SHIFT
) |
325 (NVFX_FP_OP_COND_TR
<< NVFX_FP_OP_COND_SHIFT
);
326 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
|
327 (count
<< NV40_FP_OP_REP_COUNT1_SHIFT
) |
328 (count
<< NV40_FP_OP_REP_COUNT2_SHIFT
) |
329 (count
<< NV40_FP_OP_REP_COUNT3_SHIFT
);
330 hw
[3] = 0; /* | end_offset */
331 reloc
.target
= target
;
332 reloc
.location
= fpc
->inst_offset
+ 3;
333 util_dynarray_append(&fpc
->label_relocs
, struct nvfx_relocation
, reloc
);
334 //util_dynarray_append(&fpc->loop_stack, unsigned, target);
337 /* warning: this only works forward, and probably only if not inside any IF */
339 nv40_fp_bra(struct nvfx_fpc
*fpc
, unsigned target
)
341 struct nvfx_relocation reloc
;
343 fpc
->inst_offset
= fpc
->fp
->insn_len
;
345 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
346 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
347 hw
[0] = (NV40_FP_OP_BRA_OPCODE_IF
<< NVFX_FP_OP_OPCODE_SHIFT
) |
348 NV40_FP_OP_OUT_NONE
|
349 (NVFX_FP_PRECISION_FP16
<< NVFX_FP_OP_PRECISION_SHIFT
);
350 /* Use .xxxx swizzle so that we check only src[0].x*/
351 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_X_SHIFT
) |
352 (NVFX_FP_OP_COND_FL
<< NVFX_FP_OP_COND_SHIFT
);
353 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
; /* | else_offset */
354 hw
[3] = 0; /* | endif_offset */
355 reloc
.target
= target
;
356 reloc
.location
= fpc
->inst_offset
+ 2;
357 util_dynarray_append(&fpc
->label_relocs
, struct nvfx_relocation
, reloc
);
358 reloc
.target
= target
;
359 reloc
.location
= fpc
->inst_offset
+ 3;
360 util_dynarray_append(&fpc
->label_relocs
, struct nvfx_relocation
, reloc
);
364 nv40_fp_brk(struct nvfx_fpc
*fpc
)
367 fpc
->inst_offset
= fpc
->fp
->insn_len
;
369 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
370 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
371 hw
[0] = (NV40_FP_OP_BRA_OPCODE_BRK
<< NVFX_FP_OP_OPCODE_SHIFT
) |
373 /* Use .xxxx swizzle so that we check only src[0].x*/
374 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_X_SHIFT
) |
375 (NVFX_FP_OP_COND_TR
<< NVFX_FP_OP_COND_SHIFT
);
376 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
;
380 static INLINE
struct nvfx_src
381 tgsi_src(struct nvfx_fpc
*fpc
, const struct tgsi_full_src_register
*fsrc
)
385 switch (fsrc
->Register
.File
) {
386 case TGSI_FILE_INPUT
:
387 if(fpc
->pfp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_POSITION
) {
388 assert(fpc
->pfp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 0);
389 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NVFX_FP_OP_INPUT_SRC_POSITION
);
390 } else if(fpc
->pfp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_COLOR
) {
391 if(fpc
->pfp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 0)
392 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NVFX_FP_OP_INPUT_SRC_COL0
);
393 else if(fpc
->pfp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 1)
394 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NVFX_FP_OP_INPUT_SRC_COL1
);
397 } else if(fpc
->pfp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_FOG
) {
398 assert(fpc
->pfp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 0);
399 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NVFX_FP_OP_INPUT_SRC_FOGC
);
400 } else if(fpc
->pfp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_FACE
) {
401 /* TODO: check this has the correct values */
402 /* XXX: what do we do for nv30 here (assuming it lacks facing)?! */
403 assert(fpc
->pfp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 0);
404 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NV40_FP_OP_INPUT_SRC_FACING
);
406 assert(fpc
->pfp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_GENERIC
);
407 src
.reg
= nvfx_reg(NVFXSR_RELOCATED
, fpc
->generic_to_slot
[fpc
->pfp
->info
.input_semantic_index
[fsrc
->Register
.Index
]]);
410 case TGSI_FILE_CONSTANT
:
411 src
.reg
= constant(fpc
, fsrc
->Register
.Index
, NULL
);
413 case TGSI_FILE_IMMEDIATE
:
414 assert(fsrc
->Register
.Index
< fpc
->nr_imm
);
415 src
.reg
= fpc
->imm
[fsrc
->Register
.Index
];
417 case TGSI_FILE_TEMPORARY
:
418 src
.reg
= fpc
->r_temp
[fsrc
->Register
.Index
];
420 /* NV40 fragprog result regs are just temps, so this is simple */
421 case TGSI_FILE_OUTPUT
:
422 src
.reg
= fpc
->r_result
[fsrc
->Register
.Index
];
425 NOUVEAU_ERR("bad src file\n");
431 src
.abs
= fsrc
->Register
.Absolute
;
432 src
.negate
= fsrc
->Register
.Negate
;
433 src
.swz
[0] = fsrc
->Register
.SwizzleX
;
434 src
.swz
[1] = fsrc
->Register
.SwizzleY
;
435 src
.swz
[2] = fsrc
->Register
.SwizzleZ
;
436 src
.swz
[3] = fsrc
->Register
.SwizzleW
;
440 static INLINE
struct nvfx_reg
441 tgsi_dst(struct nvfx_fpc
*fpc
, const struct tgsi_full_dst_register
*fdst
) {
442 switch (fdst
->Register
.File
) {
443 case TGSI_FILE_OUTPUT
:
444 return fpc
->r_result
[fdst
->Register
.Index
];
445 case TGSI_FILE_TEMPORARY
:
446 return fpc
->r_temp
[fdst
->Register
.Index
];
448 return nvfx_reg(NVFXSR_NONE
, 0);
450 NOUVEAU_ERR("bad dst file %d\n", fdst
->Register
.File
);
451 return nvfx_reg(NVFXSR_NONE
, 0);
460 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= NVFX_FP_MASK_X
;
461 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= NVFX_FP_MASK_Y
;
462 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= NVFX_FP_MASK_Z
;
463 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= NVFX_FP_MASK_W
;
468 nvfx_fragprog_parse_instruction(struct nvfx_context
* nvfx
, struct nvfx_fpc
*fpc
,
469 const struct tgsi_full_instruction
*finst
)
471 const struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
472 struct nvfx_insn insn
;
473 struct nvfx_src src
[3], tmp
, tmp2
;
475 int mask
, sat
, unit
= 0;
476 int ai
= -1, ci
= -1, ii
= -1;
479 if (finst
->Instruction
.Opcode
== TGSI_OPCODE_END
)
482 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
483 const struct tgsi_full_src_register
*fsrc
;
485 fsrc
= &finst
->Src
[i
];
486 if (fsrc
->Register
.File
== TGSI_FILE_TEMPORARY
) {
487 src
[i
] = tgsi_src(fpc
, fsrc
);
491 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
492 const struct tgsi_full_src_register
*fsrc
;
494 fsrc
= &finst
->Src
[i
];
496 switch (fsrc
->Register
.File
) {
497 case TGSI_FILE_INPUT
:
498 if (ai
== -1 || ai
== fsrc
->Register
.Index
) {
499 ai
= fsrc
->Register
.Index
;
500 src
[i
] = tgsi_src(fpc
, fsrc
);
502 src
[i
] = nvfx_src(temp(fpc
));
503 nvfx_fp_emit(fpc
, arith(0, MOV
, src
[i
].reg
, NVFX_FP_MASK_ALL
, tgsi_src(fpc
, fsrc
), none
, none
));
506 case TGSI_FILE_CONSTANT
:
507 if ((ci
== -1 && ii
== -1) ||
508 ci
== fsrc
->Register
.Index
) {
509 ci
= fsrc
->Register
.Index
;
510 src
[i
] = tgsi_src(fpc
, fsrc
);
512 src
[i
] = nvfx_src(temp(fpc
));
513 nvfx_fp_emit(fpc
, arith(0, MOV
, src
[i
].reg
, NVFX_FP_MASK_ALL
, tgsi_src(fpc
, fsrc
), none
, none
));
516 case TGSI_FILE_IMMEDIATE
:
517 if ((ci
== -1 && ii
== -1) ||
518 ii
== fsrc
->Register
.Index
) {
519 ii
= fsrc
->Register
.Index
;
520 src
[i
] = tgsi_src(fpc
, fsrc
);
522 src
[i
] = nvfx_src(temp(fpc
));
523 nvfx_fp_emit(fpc
, arith(0, MOV
, src
[i
].reg
, NVFX_FP_MASK_ALL
, tgsi_src(fpc
, fsrc
), none
, none
));
526 case TGSI_FILE_TEMPORARY
:
529 case TGSI_FILE_SAMPLER
:
530 unit
= fsrc
->Register
.Index
;
532 case TGSI_FILE_OUTPUT
:
535 NOUVEAU_ERR("bad src file\n");
540 dst
= tgsi_dst(fpc
, &finst
->Dst
[0]);
541 mask
= tgsi_mask(finst
->Dst
[0].Register
.WriteMask
);
542 sat
= (finst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
);
544 switch (finst
->Instruction
.Opcode
) {
545 case TGSI_OPCODE_ABS
:
546 nvfx_fp_emit(fpc
, arith(sat
, MOV
, dst
, mask
, abs(src
[0]), none
, none
));
548 case TGSI_OPCODE_ADD
:
549 nvfx_fp_emit(fpc
, arith(sat
, ADD
, dst
, mask
, src
[0], src
[1], none
));
551 case TGSI_OPCODE_CMP
:
552 insn
= arith(0, MOV
, none
.reg
, mask
, src
[0], none
, none
);
554 nvfx_fp_emit(fpc
, insn
);
556 insn
= arith(sat
, MOV
, dst
, mask
, src
[2], none
, none
);
557 insn
.cc_test
= NVFX_COND_GE
;
558 nvfx_fp_emit(fpc
, insn
);
560 insn
= arith(sat
, MOV
, dst
, mask
, src
[1], none
, none
);
561 insn
.cc_test
= NVFX_COND_LT
;
562 nvfx_fp_emit(fpc
, insn
);
564 case TGSI_OPCODE_COS
:
565 nvfx_fp_emit(fpc
, arith(sat
, COS
, dst
, mask
, src
[0], none
, none
));
567 case TGSI_OPCODE_DDX
:
568 if (mask
& (NVFX_FP_MASK_Z
| NVFX_FP_MASK_W
)) {
569 tmp
= nvfx_src(temp(fpc
));
570 nvfx_fp_emit(fpc
, arith(sat
, DDX
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, swz(src
[0], Z
, W
, Z
, W
), none
, none
));
571 nvfx_fp_emit(fpc
, arith(0, MOV
, tmp
.reg
, NVFX_FP_MASK_Z
| NVFX_FP_MASK_W
, swz(tmp
, X
, Y
, X
, Y
), none
, none
));
572 nvfx_fp_emit(fpc
, arith(sat
, DDX
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, src
[0], none
, none
));
573 nvfx_fp_emit(fpc
, arith(0, MOV
, dst
, mask
, tmp
, none
, none
));
575 nvfx_fp_emit(fpc
, arith(sat
, DDX
, dst
, mask
, src
[0], none
, none
));
578 case TGSI_OPCODE_DDY
:
579 if (mask
& (NVFX_FP_MASK_Z
| NVFX_FP_MASK_W
)) {
580 tmp
= nvfx_src(temp(fpc
));
581 nvfx_fp_emit(fpc
, arith(sat
, DDY
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, swz(src
[0], Z
, W
, Z
, W
), none
, none
));
582 nvfx_fp_emit(fpc
, arith(0, MOV
, tmp
.reg
, NVFX_FP_MASK_Z
| NVFX_FP_MASK_W
, swz(tmp
, X
, Y
, X
, Y
), none
, none
));
583 nvfx_fp_emit(fpc
, arith(sat
, DDY
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, src
[0], none
, none
));
584 nvfx_fp_emit(fpc
, arith(0, MOV
, dst
, mask
, tmp
, none
, none
));
586 nvfx_fp_emit(fpc
, arith(sat
, DDY
, dst
, mask
, src
[0], none
, none
));
589 case TGSI_OPCODE_DP2
:
590 tmp
= nvfx_src(temp(fpc
));
591 nvfx_fp_emit(fpc
, arith(0, MUL
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, src
[0], src
[1], none
));
592 nvfx_fp_emit(fpc
, arith(0, ADD
, dst
, mask
, swz(tmp
, X
, X
, X
, X
), swz(tmp
, Y
, Y
, Y
, Y
), none
));
594 case TGSI_OPCODE_DP3
:
595 nvfx_fp_emit(fpc
, arith(sat
, DP3
, dst
, mask
, src
[0], src
[1], none
));
597 case TGSI_OPCODE_DP4
:
598 nvfx_fp_emit(fpc
, arith(sat
, DP4
, dst
, mask
, src
[0], src
[1], none
));
600 case TGSI_OPCODE_DPH
:
601 tmp
= nvfx_src(temp(fpc
));
602 nvfx_fp_emit(fpc
, arith(0, DP3
, tmp
.reg
, NVFX_FP_MASK_X
, src
[0], src
[1], none
));
603 nvfx_fp_emit(fpc
, arith(sat
, ADD
, dst
, mask
, swz(tmp
, X
, X
, X
, X
), swz(src
[1], W
, W
, W
, W
), none
));
605 case TGSI_OPCODE_DST
:
606 nvfx_fp_emit(fpc
, arith(sat
, DST
, dst
, mask
, src
[0], src
[1], none
));
608 case TGSI_OPCODE_EX2
:
609 nvfx_fp_emit(fpc
, arith(sat
, EX2
, dst
, mask
, src
[0], none
, none
));
611 case TGSI_OPCODE_FLR
:
612 nvfx_fp_emit(fpc
, arith(sat
, FLR
, dst
, mask
, src
[0], none
, none
));
614 case TGSI_OPCODE_FRC
:
615 nvfx_fp_emit(fpc
, arith(sat
, FRC
, dst
, mask
, src
[0], none
, none
));
617 case TGSI_OPCODE_KILP
:
618 nvfx_fp_emit(fpc
, arith(0, KIL
, none
.reg
, 0, none
, none
, none
));
620 case TGSI_OPCODE_KIL
:
621 insn
= arith(0, MOV
, none
.reg
, NVFX_FP_MASK_ALL
, src
[0], none
, none
);
623 nvfx_fp_emit(fpc
, insn
);
625 insn
= arith(0, KIL
, none
.reg
, 0, none
, none
, none
);
626 insn
.cc_test
= NVFX_COND_LT
;
627 nvfx_fp_emit(fpc
, insn
);
629 case TGSI_OPCODE_LG2
:
630 nvfx_fp_emit(fpc
, arith(sat
, LG2
, dst
, mask
, src
[0], none
, none
));
632 // case TGSI_OPCODE_LIT:
633 case TGSI_OPCODE_LRP
:
635 nvfx_fp_emit(fpc
, arith(sat
, LRP_NV30
, dst
, mask
, src
[0], src
[1], src
[2]));
637 tmp
= nvfx_src(temp(fpc
));
638 nvfx_fp_emit(fpc
, arith(0, MAD
, tmp
.reg
, mask
, neg(src
[0]), src
[2], src
[2]));
639 nvfx_fp_emit(fpc
, arith(sat
, MAD
, dst
, mask
, src
[0], src
[1], tmp
));
642 case TGSI_OPCODE_MAD
:
643 nvfx_fp_emit(fpc
, arith(sat
, MAD
, dst
, mask
, src
[0], src
[1], src
[2]));
645 case TGSI_OPCODE_MAX
:
646 nvfx_fp_emit(fpc
, arith(sat
, MAX
, dst
, mask
, src
[0], src
[1], none
));
648 case TGSI_OPCODE_MIN
:
649 nvfx_fp_emit(fpc
, arith(sat
, MIN
, dst
, mask
, src
[0], src
[1], none
));
651 case TGSI_OPCODE_MOV
:
652 nvfx_fp_emit(fpc
, arith(sat
, MOV
, dst
, mask
, src
[0], none
, none
));
654 case TGSI_OPCODE_MUL
:
655 nvfx_fp_emit(fpc
, arith(sat
, MUL
, dst
, mask
, src
[0], src
[1], none
));
657 case TGSI_OPCODE_NOP
:
659 case TGSI_OPCODE_POW
:
661 nvfx_fp_emit(fpc
, arith(sat
, POW_NV30
, dst
, mask
, src
[0], src
[1], none
));
663 tmp
= nvfx_src(temp(fpc
));
664 nvfx_fp_emit(fpc
, arith(0, LG2
, tmp
.reg
, NVFX_FP_MASK_X
, swz(src
[0], X
, X
, X
, X
), none
, none
));
665 nvfx_fp_emit(fpc
, arith(0, MUL
, tmp
.reg
, NVFX_FP_MASK_X
, swz(tmp
, X
, X
, X
, X
), swz(src
[1], X
, X
, X
, X
), none
));
666 nvfx_fp_emit(fpc
, arith(sat
, EX2
, dst
, mask
, swz(tmp
, X
, X
, X
, X
), none
, none
));
669 case TGSI_OPCODE_RCP
:
670 nvfx_fp_emit(fpc
, arith(sat
, RCP
, dst
, mask
, src
[0], none
, none
));
672 case TGSI_OPCODE_RFL
:
674 nvfx_fp_emit(fpc
, arith(0, RFL_NV30
, dst
, mask
, src
[0], src
[1], none
));
676 tmp
= nvfx_src(temp(fpc
));
677 nvfx_fp_emit(fpc
, arith(0, DP3
, tmp
.reg
, NVFX_FP_MASK_X
, src
[0], src
[0], none
));
678 nvfx_fp_emit(fpc
, arith(0, DP3
, tmp
.reg
, NVFX_FP_MASK_Y
, src
[0], src
[1], none
));
679 insn
= arith(0, DIV
, tmp
.reg
, NVFX_FP_MASK_Z
, swz(tmp
, Y
, Y
, Y
, Y
), swz(tmp
, X
, X
, X
, X
), none
);
680 insn
.scale
= NVFX_FP_OP_DST_SCALE_2X
;
681 nvfx_fp_emit(fpc
, insn
);
682 nvfx_fp_emit(fpc
, arith(sat
, MAD
, dst
, mask
, swz(tmp
, Z
, Z
, Z
, Z
), src
[0], neg(src
[1])));
685 case TGSI_OPCODE_RSQ
:
687 nvfx_fp_emit(fpc
, arith(sat
, RSQ_NV30
, dst
, mask
, abs(swz(src
[0], X
, X
, X
, X
)), none
, none
));
689 tmp
= nvfx_src(temp(fpc
));
690 insn
= arith(0, LG2
, tmp
.reg
, NVFX_FP_MASK_X
, abs(swz(src
[0], X
, X
, X
, X
)), none
, none
);
691 insn
.scale
= NVFX_FP_OP_DST_SCALE_INV_2X
;
692 nvfx_fp_emit(fpc
, insn
);
693 nvfx_fp_emit(fpc
, arith(sat
, EX2
, dst
, mask
, neg(swz(tmp
, X
, X
, X
, X
)), none
, none
));
696 case TGSI_OPCODE_SCS
:
697 /* avoid overwriting the source */
698 if(src
[0].swz
[NVFX_SWZ_X
] != NVFX_SWZ_X
)
700 if (mask
& NVFX_FP_MASK_X
)
701 nvfx_fp_emit(fpc
, arith(sat
, COS
, dst
, NVFX_FP_MASK_X
, swz(src
[0], X
, X
, X
, X
), none
, none
));
702 if (mask
& NVFX_FP_MASK_Y
)
703 nvfx_fp_emit(fpc
, arith(sat
, SIN
, dst
, NVFX_FP_MASK_Y
, swz(src
[0], X
, X
, X
, X
), none
, none
));
707 if (mask
& NVFX_FP_MASK_Y
)
708 nvfx_fp_emit(fpc
, arith(sat
, SIN
, dst
, NVFX_FP_MASK_Y
, swz(src
[0], X
, X
, X
, X
), none
, none
));
709 if (mask
& NVFX_FP_MASK_X
)
710 nvfx_fp_emit(fpc
, arith(sat
, COS
, dst
, NVFX_FP_MASK_X
, swz(src
[0], X
, X
, X
, X
), none
, none
));
713 case TGSI_OPCODE_SEQ
:
714 nvfx_fp_emit(fpc
, arith(sat
, SEQ
, dst
, mask
, src
[0], src
[1], none
));
716 case TGSI_OPCODE_SFL
:
717 nvfx_fp_emit(fpc
, arith(sat
, SFL
, dst
, mask
, src
[0], src
[1], none
));
719 case TGSI_OPCODE_SGE
:
720 nvfx_fp_emit(fpc
, arith(sat
, SGE
, dst
, mask
, src
[0], src
[1], none
));
722 case TGSI_OPCODE_SGT
:
723 nvfx_fp_emit(fpc
, arith(sat
, SGT
, dst
, mask
, src
[0], src
[1], none
));
725 case TGSI_OPCODE_SIN
:
726 nvfx_fp_emit(fpc
, arith(sat
, SIN
, dst
, mask
, src
[0], none
, none
));
728 case TGSI_OPCODE_SLE
:
729 nvfx_fp_emit(fpc
, arith(sat
, SLE
, dst
, mask
, src
[0], src
[1], none
));
731 case TGSI_OPCODE_SLT
:
732 nvfx_fp_emit(fpc
, arith(sat
, SLT
, dst
, mask
, src
[0], src
[1], none
));
734 case TGSI_OPCODE_SNE
:
735 nvfx_fp_emit(fpc
, arith(sat
, SNE
, dst
, mask
, src
[0], src
[1], none
));
737 case TGSI_OPCODE_SSG
:
738 tmp
= nvfx_src(temp(fpc
));
739 tmp2
= nvfx_src(temp(fpc
));
740 nvfx_fp_emit(fpc
, arith(0, SGT
, tmp
.reg
, mask
, src
[0], nvfx_src(nvfx_reg(NVFXSR_CONST
, 0)), none
));
741 nvfx_fp_emit(fpc
, arith(0, SLT
, tmp
.reg
, mask
, src
[0], nvfx_src(nvfx_reg(NVFXSR_CONST
, 0)), none
));
742 nvfx_fp_emit(fpc
, arith(sat
, ADD
, dst
, mask
, tmp
, neg(tmp2
), none
));
744 case TGSI_OPCODE_STR
:
745 nvfx_fp_emit(fpc
, arith(sat
, STR
, dst
, mask
, src
[0], src
[1], none
));
747 case TGSI_OPCODE_SUB
:
748 nvfx_fp_emit(fpc
, arith(sat
, ADD
, dst
, mask
, src
[0], neg(src
[1]), none
));
750 case TGSI_OPCODE_TEX
:
751 nvfx_fp_emit(fpc
, tex(sat
, TEX
, unit
, dst
, mask
, src
[0], none
, none
));
753 case TGSI_OPCODE_TRUNC
:
754 tmp
= nvfx_src(temp(fpc
));
755 insn
= arith(0, MOV
, none
.reg
, mask
, src
[0], none
, none
);
757 nvfx_fp_emit(fpc
, insn
);
759 nvfx_fp_emit(fpc
, arith(0, FLR
, tmp
.reg
, mask
, abs(src
[0]), none
, none
));
760 nvfx_fp_emit(fpc
, arith(sat
, MOV
, dst
, mask
, tmp
, none
, none
));
762 insn
= arith(sat
, MOV
, dst
, mask
, neg(tmp
), none
, none
);
763 insn
.cc_test
= NVFX_COND_LT
;
764 nvfx_fp_emit(fpc
, insn
);
766 case TGSI_OPCODE_TXB
:
767 nvfx_fp_emit(fpc
, tex(sat
, TXB
, unit
, dst
, mask
, src
[0], none
, none
));
769 case TGSI_OPCODE_TXL
:
771 nvfx_fp_emit(fpc
, tex(sat
, TXL_NV40
, unit
, dst
, mask
, src
[0], none
, none
));
772 else /* unsupported on nv30, use TEX and hope they like it */
773 nvfx_fp_emit(fpc
, tex(sat
, TEX
, unit
, dst
, mask
, src
[0], none
, none
));
775 case TGSI_OPCODE_TXP
:
776 nvfx_fp_emit(fpc
, tex(sat
, TXP
, unit
, dst
, mask
, src
[0], none
, none
));
778 case TGSI_OPCODE_XPD
:
779 tmp
= nvfx_src(temp(fpc
));
780 nvfx_fp_emit(fpc
, arith(0, MUL
, tmp
.reg
, mask
, swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
));
781 nvfx_fp_emit(fpc
, arith(sat
, MAD
, dst
, (mask
& ~NVFX_FP_MASK_W
), swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
), neg(tmp
)));
785 // MOVRC0 R31 (TR0.xyzw), R<src>:
786 // IF (NE.xxxx) ELSE <else> END <end>
789 nv40_fp_if(fpc
, src
[0]);
792 case TGSI_OPCODE_ELSE
:
797 assert(util_dynarray_contains(&fpc
->if_stack
, unsigned));
798 hw
= &fpc
->fp
->insn
[util_dynarray_top(&fpc
->if_stack
, unsigned)];
799 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
| fpc
->fp
->insn_len
;
803 case TGSI_OPCODE_ENDIF
:
808 assert(util_dynarray_contains(&fpc
->if_stack
, unsigned));
809 hw
= &fpc
->fp
->insn
[util_dynarray_pop(&fpc
->if_stack
, unsigned)];
811 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
| fpc
->fp
->insn_len
;
812 hw
[3] = fpc
->fp
->insn_len
;
816 case TGSI_OPCODE_BRA
:
817 /* This can in limited cases be implemented with an IF with the else and endif labels pointing to the target */
818 /* no state tracker uses this, so don't implement this for now */
820 nv40_fp_bra(fpc
, finst
->Label
.Label
);
823 case TGSI_OPCODE_BGNSUB
:
824 case TGSI_OPCODE_ENDSUB
:
825 /* nothing to do here */
828 case TGSI_OPCODE_CAL
:
831 nv40_fp_cal(fpc
, finst
->Label
.Label
);
834 case TGSI_OPCODE_RET
:
840 case TGSI_OPCODE_BGNLOOP
:
843 /* TODO: we should support using two nested REPs to allow a > 255 iteration count */
844 nv40_fp_rep(fpc
, 255, finst
->Label
.Label
);
847 case TGSI_OPCODE_ENDLOOP
:
850 case TGSI_OPCODE_BRK
:
856 case TGSI_OPCODE_CONT
:
858 static int warned
= 0;
860 NOUVEAU_ERR("Sorry, the continue keyword is not implemented: ignoring it.\n");
867 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
876 static int warned
= 0;
879 "Sorry, control flow instructions are not supported in hardware on nv3x: ignoring them\n"
880 "If rendering is incorrect, try to disable GLSL support in the application.\n");
888 nvfx_fragprog_parse_decl_output(struct nvfx_context
* nvfx
, struct nvfx_fpc
*fpc
,
889 const struct tgsi_full_declaration
*fdec
)
891 unsigned idx
= fdec
->Range
.First
;
894 switch (fdec
->Semantic
.Name
) {
895 case TGSI_SEMANTIC_POSITION
:
898 case TGSI_SEMANTIC_COLOR
:
900 switch (fdec
->Semantic
.Index
) {
901 case 0: hw
= 0; break;
902 case 1: hw
= 2; break;
903 case 2: hw
= 3; break;
904 case 3: hw
= 4; break;
906 if(hw
> ((nvfx
->is_nv4x
) ? 4 : 2)) {
907 NOUVEAU_ERR("bad rcol index\n");
912 NOUVEAU_ERR("bad output semantic\n");
916 fpc
->r_result
[idx
] = nvfx_reg(NVFXSR_OUTPUT
, hw
);
917 fpc
->r_temps
|= (1ULL << hw
);
922 nvfx_fragprog_prepare(struct nvfx_context
* nvfx
, struct nvfx_fpc
*fpc
)
924 struct tgsi_parse_context p
;
925 int high_temp
= -1, i
;
926 struct util_semantic_set set
;
927 float const0v
[4] = {0, 0, 0, 0};
928 struct nvfx_reg const0
;
930 fpc
->fp
->num_slots
= util_semantic_set_from_program_file(&set
, fpc
->pfp
->pipe
.tokens
, TGSI_FILE_INPUT
);
931 if(fpc
->fp
->num_slots
> 8)
933 util_semantic_layout_from_set(fpc
->fp
->slot_to_generic
, &set
, 0, 8);
934 util_semantic_table_from_layout(fpc
->generic_to_slot
, fpc
->fp
->slot_to_generic
, 0, 8);
936 memset(fpc
->fp
->slot_to_fp_input
, 0xff, sizeof(fpc
->fp
->slot_to_fp_input
));
938 const0
= constant(fpc
, -1, const0v
);
939 assert(const0
.index
== 0);
941 tgsi_parse_init(&p
, fpc
->pfp
->pipe
.tokens
);
942 while (!tgsi_parse_end_of_tokens(&p
)) {
943 const union tgsi_full_token
*tok
= &p
.FullToken
;
945 tgsi_parse_token(&p
);
946 switch(tok
->Token
.Type
) {
947 case TGSI_TOKEN_TYPE_DECLARATION
:
949 const struct tgsi_full_declaration
*fdec
;
950 fdec
= &p
.FullToken
.FullDeclaration
;
951 switch (fdec
->Declaration
.File
) {
952 case TGSI_FILE_OUTPUT
:
953 if (!nvfx_fragprog_parse_decl_output(nvfx
, fpc
, fdec
))
956 case TGSI_FILE_TEMPORARY
:
957 if (fdec
->Range
.Last
> high_temp
) {
967 case TGSI_TOKEN_TYPE_IMMEDIATE
:
969 struct tgsi_full_immediate
*imm
;
972 imm
= &p
.FullToken
.FullImmediate
;
973 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
974 assert(fpc
->nr_imm
< MAX_IMM
);
976 vals
[0] = imm
->u
[0].Float
;
977 vals
[1] = imm
->u
[1].Float
;
978 vals
[2] = imm
->u
[2].Float
;
979 vals
[3] = imm
->u
[3].Float
;
980 fpc
->imm
[fpc
->nr_imm
++] = constant(fpc
, -1, vals
);
990 fpc
->r_temp
= CALLOC(high_temp
, sizeof(struct nvfx_reg
));
991 for (i
= 0; i
< high_temp
; i
++)
992 fpc
->r_temp
[i
] = temp(fpc
);
993 fpc
->r_temps_discard
= 0ULL;
1003 tgsi_parse_free(&p
);
1007 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp
, "NVFX_DUMP_FP", FALSE
)
1009 static struct nvfx_fragment_program
*
1010 nvfx_fragprog_translate(struct nvfx_context
*nvfx
,
1011 struct nvfx_pipe_fragment_program
*pfp
,
1012 boolean emulate_sprite_flipping
)
1014 struct tgsi_parse_context parse
;
1015 struct nvfx_fpc
*fpc
= NULL
;
1016 struct util_dynarray insns
;
1017 struct nvfx_fragment_program
* fp
= NULL
;
1018 const int min_size
= 4096;
1020 fp
= CALLOC_STRUCT(nvfx_fragment_program
);
1024 fpc
= CALLOC_STRUCT(nvfx_fpc
);
1028 fpc
->max_temps
= nvfx
->is_nv4x
? 48 : 32;
1033 if (!nvfx_fragprog_prepare(nvfx
, fpc
))
1036 tgsi_parse_init(&parse
, pfp
->pipe
.tokens
);
1037 util_dynarray_init(&insns
);
1039 if(emulate_sprite_flipping
)
1041 struct nvfx_reg reg
= temp(fpc
);
1042 struct nvfx_src sprite_input
= nvfx_src(nvfx_reg(NVFXSR_RELOCATED
, fp
->num_slots
));
1043 float v
[4] = {1, -1, 0, 0};
1044 struct nvfx_src imm
= nvfx_src(constant(fpc
, -1, v
));
1046 fpc
->sprite_coord_temp
= reg
.index
;
1047 fpc
->r_temps_discard
= 0ULL;
1048 nvfx_fp_emit(fpc
, arith(0, MAD
, reg
, NVFX_FP_MASK_ALL
, sprite_input
, swz(imm
, X
, Y
, X
, X
), swz(imm
, Z
, X
, Z
, Z
)));
1051 while (!tgsi_parse_end_of_tokens(&parse
)) {
1052 tgsi_parse_token(&parse
);
1054 switch (parse
.FullToken
.Token
.Type
) {
1055 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1057 const struct tgsi_full_instruction
*finst
;
1059 util_dynarray_append(&insns
, unsigned, fp
->insn_len
);
1060 finst
= &parse
.FullToken
.FullInstruction
;
1061 if (!nvfx_fragprog_parse_instruction(nvfx
, fpc
, finst
))
1069 util_dynarray_append(&insns
, unsigned, fp
->insn_len
);
1071 for(unsigned i
= 0; i
< fpc
->label_relocs
.size
; i
+= sizeof(struct nvfx_relocation
))
1073 struct nvfx_relocation
* label_reloc
= (struct nvfx_relocation
*)((char*)fpc
->label_relocs
.data
+ i
);
1074 fp
->insn
[label_reloc
->location
] |= ((unsigned*)insns
.data
)[label_reloc
->target
];
1076 util_dynarray_fini(&insns
);
1079 fp
->fp_control
|= (fpc
->num_regs
-1)/2;
1081 fp
->fp_control
|= fpc
->num_regs
<< NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT
;
1083 /* Terminate final instruction */
1085 fp
->insn
[fpc
->inst_offset
] |= 0x00000001;
1087 /* Append NOP + END instruction for branches to the end of the program */
1088 fpc
->inst_offset
= fp
->insn_len
;
1090 fp
->insn
[fpc
->inst_offset
+ 0] = 0x00000001;
1091 fp
->insn
[fpc
->inst_offset
+ 1] = 0x00000000;
1092 fp
->insn
[fpc
->inst_offset
+ 2] = 0x00000000;
1093 fp
->insn
[fpc
->inst_offset
+ 3] = 0x00000000;
1095 if(debug_get_option_nvfx_dump_fp())
1098 tgsi_dump(pfp
->pipe
.tokens
, 0);
1100 debug_printf("\n%s fragment program:\n", nvfx
->is_nv4x
? "nv4x" : "nv3x");
1101 for (unsigned i
= 0; i
< fp
->insn_len
; i
+= 4)
1102 debug_printf("%3u: %08x %08x %08x %08x\n", i
>> 2, fp
->insn
[i
], fp
->insn
[i
+ 1], fp
->insn
[i
+ 2], fp
->insn
[i
+ 3]);
1106 fp
->prog_size
= (fp
->insn_len
* 4 + 63) & ~63;
1108 if(fp
->prog_size
>= min_size
)
1109 fp
->progs_per_bo
= 1;
1111 fp
->progs_per_bo
= min_size
/ fp
->prog_size
;
1112 fp
->bo_prog_idx
= fp
->progs_per_bo
- 1;
1115 tgsi_parse_free(&parse
);
1120 util_dynarray_fini(&fpc
->if_stack
);
1121 util_dynarray_fini(&fpc
->label_relocs
);
1122 //util_dynarray_fini(&fpc->loop_stack);
1128 _debug_printf("Error: failed to compile this fragment program:\n");
1129 tgsi_dump(pfp
->pipe
.tokens
, 0);
1140 nvfx_fp_memcpy(void* dst
, const void* src
, size_t len
)
1142 #ifndef WORDS_BIGENDIAN
1143 memcpy(dst
, src
, len
);
1146 for(i
= 0; i
< len
; i
+= 4) {
1147 uint32_t v
= (uint32_t*)((char*)src
+ i
);
1148 *(uint32_t*)((char*)dst
+ i
) = (v
>> 16) | (v
<< 16);
1153 /* The hardware only supports immediate constants inside the fragment program,
1154 * and at least on nv30 doesn't support an indirect linkage table.
1156 * Hence, we need to patch the fragment program itself both to update constants
1157 * and update linkage.
1159 * Using a single fragment program would entail unacceptable stalls if the GPU is
1160 * already rendering with that fragment program.
1161 * Thus, we instead use a "rotating queue" of buffer objects, each of which is
1162 * packed with multiple versions of the same program.
1164 * Whenever we need to patch something, we move to the next program and
1165 * patch it. If all buffer objects are in use by the GPU, we allocate another one,
1166 * expanding the queue.
1168 * As an additional optimization, we record when all the programs have the
1169 * current input slot configuration, and at that point we stop patching inputs.
1170 * This happens, for instance, if a given fragment program is always used with
1171 * the same vertex program (i.e. always with GLSL), or if the layouts match
1172 * enough (non-GLSL).
1174 * Note that instead of using multiple programs, we could push commands
1175 * on the FIFO to patch a single program: it's not fully clear which option is
1176 * faster, but my guess is that the current way is faster.
1178 * We also track the previous slot assignments for each version and don't
1179 * patch if they are the same (this could perhaps be removed).
1183 nvfx_fragprog_validate(struct nvfx_context
*nvfx
)
1185 struct nouveau_channel
* chan
= nvfx
->screen
->base
.channel
;
1186 struct nvfx_pipe_fragment_program
*pfp
= nvfx
->fragprog
;
1187 struct nvfx_vertex_program
* vp
;
1188 /* Gallium always puts the point coord in GENERIC[0]
1189 * TODO: this is wrong, Gallium needs to be fixed
1191 unsigned sprite_coord_enable
= nvfx
->rasterizer
->pipe
.point_quad_rasterization
* (nvfx
->rasterizer
->pipe
.sprite_coord_enable
| 1);
1193 boolean emulate_sprite_flipping
= sprite_coord_enable
&& nvfx
->rasterizer
->pipe
.sprite_coord_mode
;
1194 unsigned key
= emulate_sprite_flipping
;
1195 struct nvfx_fragment_program
* fp
;
1200 fp
= nvfx_fragprog_translate(nvfx
, pfp
, emulate_sprite_flipping
);
1206 struct ureg_program
*ureg
= ureg_create( TGSI_PROCESSOR_FRAGMENT
);
1210 nvfx
->dummy_fs
= ureg_create_shader_and_destroy( ureg
, &nvfx
->pipe
);
1215 _debug_printf("Error: unable to create a dummy fragment shader: aborting.");
1220 fp
= nvfx_fragprog_translate(nvfx
, nvfx
->dummy_fs
, FALSE
);
1221 emulate_sprite_flipping
= FALSE
;
1225 _debug_printf("Error: unable to compile even a dummy fragment shader: aborting.");
1233 vp
= nvfx
->render_mode
== HW
? nvfx
->vertprog
: nvfx
->swtnl
.vertprog
;
1235 if (fp
->last_vp_id
!= vp
->id
|| fp
->last_sprite_coord_enable
!= sprite_coord_enable
) {
1236 int sprite_real_input
= -1;
1237 int sprite_reloc_input
;
1239 fp
->last_vp_id
= vp
->id
;
1240 fp
->last_sprite_coord_enable
= sprite_coord_enable
;
1242 if(sprite_coord_enable
)
1244 sprite_real_input
= vp
->sprite_fp_input
;
1245 if(sprite_real_input
< 0)
1247 unsigned used_texcoords
= 0;
1248 for(unsigned i
= 0; i
< fp
->num_slots
; ++i
) {
1249 unsigned generic
= fp
->slot_to_generic
[i
];
1250 if(!((1 << generic
) & sprite_coord_enable
))
1252 unsigned char slot_mask
= vp
->generic_to_fp_input
[generic
];
1253 if(slot_mask
>= 0xf0)
1254 used_texcoords
|= 1 << ((slot_mask
& 0xf) - NVFX_FP_OP_INPUT_SRC_TC0
);
1258 sprite_real_input
= NVFX_FP_OP_INPUT_SRC_TC(__builtin_ctz(~used_texcoords
));
1261 fp
->point_sprite_control
|= (1 << (sprite_real_input
- NVFX_FP_OP_INPUT_SRC_TC0
+ 8));
1264 fp
->point_sprite_control
= 0;
1266 if(emulate_sprite_flipping
)
1267 sprite_reloc_input
= 0;
1269 sprite_reloc_input
= sprite_real_input
;
1271 for(i
= 0; i
< fp
->num_slots
; ++i
) {
1272 unsigned generic
= fp
->slot_to_generic
[i
];
1273 if((1 << generic
) & sprite_coord_enable
)
1275 if(fp
->slot_to_fp_input
[i
] != sprite_reloc_input
)
1280 unsigned char slot_mask
= vp
->generic_to_fp_input
[generic
];
1281 if((slot_mask
>> 4) & (slot_mask
^ fp
->slot_to_fp_input
[i
]))
1286 if(emulate_sprite_flipping
)
1288 if(fp
->slot_to_fp_input
[fp
->num_slots
] != sprite_real_input
)
1295 /* optimization: we start updating from the slot we found the first difference in */
1296 for(; i
< fp
->num_slots
; ++i
)
1298 unsigned generic
= fp
->slot_to_generic
[i
];
1299 if((1 << generic
) & sprite_coord_enable
)
1300 fp
->slot_to_fp_input
[i
] = sprite_reloc_input
;
1302 fp
->slot_to_fp_input
[i
] = vp
->generic_to_fp_input
[generic
] & 0xf;
1305 fp
->slot_to_fp_input
[fp
->num_slots
] = sprite_real_input
;
1310 for(i
= 0; i
<= fp
->num_slots
; ++i
) {
1311 unsigned fp_input
= fp
->slot_to_fp_input
[i
];
1312 if(fp_input
== NVFX_FP_OP_INPUT_SRC_TC(8))
1313 fp
->or |= (1 << 12);
1314 else if(fp_input
== NVFX_FP_OP_INPUT_SRC_TC(9))
1315 fp
->or |= (1 << 13);
1316 else if(fp_input
>= NVFX_FP_OP_INPUT_SRC_TC(0) && fp_input
<= NVFX_FP_OP_INPUT_SRC_TC(7))
1317 fp
->or |= (1 << (fp_input
- NVFX_FP_OP_INPUT_SRC_TC0
+ 14));
1321 fp
->progs_left_with_obsolete_slot_assignments
= fp
->progs
;
1326 /* We must update constants even on "just" fragprog changes, because
1327 * we don't check whether the current constant buffer matches the latest
1328 * one bound to this fragment program.
1329 * Doing such a check would likely be a pessimization.
1331 if ((nvfx
->hw_fragprog
!= fp
) || (nvfx
->dirty
& (NVFX_NEW_FRAGPROG
| NVFX_NEW_FRAGCONST
))) {
1337 if(fp
->bo_prog_idx
>= fp
->progs_per_bo
)
1339 if(fp
->fpbo
&& !nouveau_bo_busy(fp
->fpbo
->next
->bo
, NOUVEAU_BO_WR
))
1341 fp
->fpbo
= fp
->fpbo
->next
;
1345 struct nvfx_fragment_program_bo
* fpbo
= os_malloc_aligned(sizeof(struct nvfx_fragment_program
) + (fp
->prog_size
+ 8) * fp
->progs_per_bo
, 16);
1349 fpbo
->slots
= (unsigned char*)&fpbo
->insn
[(fp
->prog_size
) * fp
->progs_per_bo
];
1350 memset(fpbo
->slots
, 0, 8 * fp
->progs_per_bo
);
1353 fpbo
->next
= fp
->fpbo
->next
;
1354 fp
->fpbo
->next
= fpbo
;
1360 fp
->progs
+= fp
->progs_per_bo
;
1361 fp
->progs_left_with_obsolete_slot_assignments
+= fp
->progs_per_bo
;
1362 nouveau_bo_new(nvfx
->screen
->base
.device
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_MAP
, 64, fp
->prog_size
* fp
->progs_per_bo
, &fpbo
->bo
);
1363 nouveau_bo_map(fpbo
->bo
, NOUVEAU_BO_NOSYNC
);
1365 map
= fpbo
->bo
->map
;
1366 buf
= (uint8_t*)fpbo
->insn
;
1367 for(unsigned i
= 0; i
< fp
->progs_per_bo
; ++i
)
1369 memcpy(buf
, fp
->insn
, fp
->insn_len
* 4);
1370 nvfx_fp_memcpy(map
, fp
->insn
, fp
->insn_len
* 4);
1371 map
+= fp
->prog_size
;
1372 buf
+= fp
->prog_size
;
1375 fp
->bo_prog_idx
= 0;
1378 offset
= fp
->bo_prog_idx
* fp
->prog_size
;
1379 fpmap
= (uint32_t*)((char*)fp
->fpbo
->bo
->map
+ offset
);
1381 if(nvfx
->constbuf
[PIPE_SHADER_FRAGMENT
]) {
1382 struct pipe_resource
* constbuf
= nvfx
->constbuf
[PIPE_SHADER_FRAGMENT
];
1383 uint32_t* map
= (uint32_t*)nvfx_buffer(constbuf
)->data
;
1384 uint32_t* fpmap
= (uint32_t*)((char*)fp
->fpbo
->bo
->map
+ offset
);
1385 uint32_t* buf
= (uint32_t*)((char*)fp
->fpbo
->insn
+ offset
);
1387 for (i
= 0; i
< fp
->nr_consts
; ++i
) {
1388 unsigned off
= fp
->consts
[i
].offset
;
1389 unsigned idx
= fp
->consts
[i
].index
* 4;
1391 /* TODO: is checking a good idea? */
1392 if(memcmp(&buf
[off
], &map
[idx
], 4 * sizeof(uint32_t))) {
1393 memcpy(&buf
[off
], &map
[idx
], 4 * sizeof(uint32_t));
1394 nvfx_fp_memcpy(&fpmap
[off
], &map
[idx
], 4 * sizeof(uint32_t));
1399 /* we only do this if we aren't sure that all program versions have the
1400 * current slot assignments, otherwise we just update constants for speed
1402 if(fp
->progs_left_with_obsolete_slot_assignments
) {
1403 unsigned char* fpbo_slots
= &fp
->fpbo
->slots
[fp
->bo_prog_idx
* 8];
1404 /* also relocate sprite coord slot, if any */
1405 for(unsigned i
= 0; i
<= fp
->num_slots
; ++i
) {
1406 unsigned value
= fp
->slot_to_fp_input
[i
];;
1407 if(value
!= fpbo_slots
[i
]) {
1409 unsigned* begin
= (unsigned*)fp
->slot_relocations
[i
].data
;
1410 unsigned* end
= (unsigned*)((char*)fp
->slot_relocations
[i
].data
+ fp
->slot_relocations
[i
].size
);
1411 //printf("fp %p reloc slot %u/%u: %u -> %u\n", fp, i, fp->num_slots, fpbo_slots[i], value);
1414 /* was relocated to an input, switch type to temporary */
1415 for(p
= begin
; p
!= end
; ++p
) {
1417 unsigned dw
= fp
->insn
[off
];
1418 dw
&=~ NVFX_FP_REG_TYPE_MASK
;
1419 //printf("reloc_tmp at %x\n", off);
1420 nvfx_fp_memcpy(&fpmap
[off
], &dw
, sizeof(dw
));
1425 /* was relocated to a temporary, switch type to input */
1426 for(p
= begin
; p
!= end
; ++p
) {
1428 unsigned dw
= fp
->insn
[off
];
1429 //printf("reloc_in at %x\n", off);
1430 dw
|= NVFX_FP_REG_TYPE_INPUT
<< NVFX_FP_REG_TYPE_SHIFT
;
1431 nvfx_fp_memcpy(&fpmap
[off
], &dw
, sizeof(dw
));
1435 /* set the correct input index */
1436 for(p
= begin
; p
!= end
; ++p
) {
1437 unsigned off
= *p
& ~3;
1438 unsigned dw
= fp
->insn
[off
];
1439 //printf("reloc&~3 at %x\n", off);
1440 dw
= (dw
& ~NVFX_FP_OP_INPUT_SRC_MASK
) | (value
<< NVFX_FP_OP_INPUT_SRC_SHIFT
);
1441 nvfx_fp_memcpy(&fpmap
[off
], &dw
, sizeof(dw
));
1444 fpbo_slots
[i
] = value
;
1447 --fp
->progs_left_with_obsolete_slot_assignments
;
1450 nvfx
->hw_fragprog
= fp
;
1452 MARK_RING(chan
, 8, 1);
1453 OUT_RING(chan
, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM
, 1));
1454 OUT_RELOC(chan
, fp
->fpbo
->bo
, offset
, NOUVEAU_BO_VRAM
|
1455 NOUVEAU_BO_GART
| NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
|
1456 NOUVEAU_BO_OR
, NV34TCL_FP_ACTIVE_PROGRAM_DMA0
,
1457 NV34TCL_FP_ACTIVE_PROGRAM_DMA1
);
1458 OUT_RING(chan
, RING_3D(NV34TCL_FP_CONTROL
, 1));
1459 OUT_RING(chan
, fp
->fp_control
);
1460 if(!nvfx
->is_nv4x
) {
1461 OUT_RING(chan
, RING_3D(NV34TCL_FP_REG_CONTROL
, 1));
1462 OUT_RING(chan
, (1<<16)|0x4);
1463 OUT_RING(chan
, RING_3D(NV34TCL_TX_UNITS_ENABLE
, 1));
1464 OUT_RING(chan
, fp
->samplers
);
1469 unsigned pointsprite_control
= fp
->point_sprite_control
| nvfx
->rasterizer
->pipe
.point_quad_rasterization
;
1470 if(pointsprite_control
!= nvfx
->hw_pointsprite_control
)
1473 OUT_RING(chan
, RING_3D(NV34TCL_POINT_SPRITE
, 1));
1474 OUT_RING(chan
, pointsprite_control
);
1475 nvfx
->hw_pointsprite_control
= pointsprite_control
;
1479 nvfx
->relocs_needed
&=~ NVFX_RELOCATE_FRAGPROG
;
1483 nvfx_fragprog_relocate(struct nvfx_context
*nvfx
)
1485 struct nouveau_channel
* chan
= nvfx
->screen
->base
.channel
;
1486 struct nvfx_fragment_program
*fp
= nvfx
->hw_fragprog
;
1487 struct nouveau_bo
* bo
= fp
->fpbo
->bo
;
1488 int offset
= fp
->bo_prog_idx
* fp
->prog_size
;
1489 unsigned fp_flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
; // TODO: GART?
1490 fp_flags
|= NOUVEAU_BO_DUMMY
;
1491 MARK_RING(chan
, 2, 2);
1492 OUT_RELOC(chan
, bo
, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM
, 1), fp_flags
, 0, 0);
1493 OUT_RELOC(chan
, bo
, offset
, fp_flags
| NOUVEAU_BO_LOW
|
1494 NOUVEAU_BO_OR
, NV34TCL_FP_ACTIVE_PROGRAM_DMA0
,
1495 NV34TCL_FP_ACTIVE_PROGRAM_DMA1
);
1496 nvfx
->relocs_needed
&=~ NVFX_RELOCATE_FRAGPROG
;
1500 nvfx_fragprog_destroy(struct nvfx_context
*nvfx
,
1501 struct nvfx_fragment_program
*fp
)
1504 struct nvfx_fragment_program_bo
* fpbo
= fp
->fpbo
;
1509 struct nvfx_fragment_program_bo
* next
= fpbo
->next
;
1510 nouveau_bo_unmap(fpbo
->bo
);
1511 nouveau_bo_ref(0, &fpbo
->bo
);
1515 while(fpbo
!= fp
->fpbo
);
1518 for(i
= 0; i
< Elements(fp
->slot_relocations
); ++i
)
1519 util_dynarray_fini(&fp
->slot_relocations
[i
]);
1526 nvfx_fp_state_create(struct pipe_context
*pipe
,
1527 const struct pipe_shader_state
*cso
)
1529 struct nvfx_pipe_fragment_program
*pfp
;
1531 pfp
= CALLOC(1, sizeof(struct nvfx_pipe_fragment_program
));
1532 pfp
->pipe
.tokens
= tgsi_dup_tokens(cso
->tokens
);
1534 tgsi_scan_shader(pfp
->pipe
.tokens
, &pfp
->info
);
1540 nvfx_fp_state_bind(struct pipe_context
*pipe
, void *hwcso
)
1542 struct nvfx_context
*nvfx
= nvfx_context(pipe
);
1544 nvfx
->fragprog
= hwcso
;
1545 nvfx
->dirty
|= NVFX_NEW_FRAGPROG
;
1549 nvfx_fp_state_delete(struct pipe_context
*pipe
, void *hwcso
)
1551 struct nvfx_context
*nvfx
= nvfx_context(pipe
);
1552 struct nvfx_pipe_fragment_program
*pfp
= hwcso
;
1555 for(i
= 0; i
< Elements(pfp
->fps
); ++i
)
1559 nvfx_fragprog_destroy(nvfx
, pfp
->fps
[i
]);
1564 FREE((void*)pfp
->pipe
.tokens
);
1569 nvfx_init_fragprog_functions(struct nvfx_context
*nvfx
)
1571 nvfx
->pipe
.create_fs_state
= nvfx_fp_state_create
;
1572 nvfx
->pipe
.bind_fs_state
= nvfx_fp_state_bind
;
1573 nvfx
->pipe
.delete_fs_state
= nvfx_fp_state_delete
;