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2c24d523c473195854da3ad1a6b83cf294e16b7d
[mesa.git] / src / gallium / drivers / nvfx / nvfx_fragprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5 #include "util/u_debug.h"
6
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_util.h"
10 #include "tgsi/tgsi_dump.h"
11
12 #include "nvfx_context.h"
13 #include "nvfx_shader.h"
14 #include "nvfx_resource.h"
15
16 #define MAX_CONSTS 128
17 #define MAX_IMM 32
18
19 struct nvfx_fpc {
20 struct nvfx_fragment_program *fp;
21
22 unsigned r_temps;
23 unsigned r_temps_discard;
24 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
25 struct nvfx_reg *r_temp;
26
27 int num_regs;
28
29 unsigned inst_offset;
30 unsigned have_const;
31
32 struct {
33 int pipe;
34 float vals[4];
35 } consts[MAX_CONSTS];
36 int nr_consts;
37
38 struct nvfx_reg imm[MAX_IMM];
39 unsigned nr_imm;
40
41 unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
42
43 struct util_dynarray if_stack;
44 //struct util_dynarray loop_stack;
45 struct util_dynarray label_relocs;
46 };
47
48 static INLINE struct nvfx_reg
49 temp(struct nvfx_fpc *fpc)
50 {
51 int idx = ffs(~fpc->r_temps) - 1;
52
53 if (idx < 0) {
54 NOUVEAU_ERR("out of temps!!\n");
55 assert(0);
56 return nvfx_reg(NVFXSR_TEMP, 0);
57 }
58
59 fpc->r_temps |= (1 << idx);
60 fpc->r_temps_discard |= (1 << idx);
61 return nvfx_reg(NVFXSR_TEMP, idx);
62 }
63
64 static INLINE void
65 release_temps(struct nvfx_fpc *fpc)
66 {
67 fpc->r_temps &= ~fpc->r_temps_discard;
68 fpc->r_temps_discard = 0;
69 }
70
71 static INLINE struct nvfx_reg
72 constant(struct nvfx_fpc *fpc, int pipe, float vals[4])
73 {
74 int idx;
75
76 if (fpc->nr_consts == MAX_CONSTS)
77 assert(0);
78 idx = fpc->nr_consts++;
79
80 fpc->consts[idx].pipe = pipe;
81 if (pipe == -1)
82 memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
83 return nvfx_reg(NVFXSR_CONST, idx);
84 }
85
86 static void
87 grow_insns(struct nvfx_fpc *fpc, int size)
88 {
89 struct nvfx_fragment_program *fp = fpc->fp;
90
91 fp->insn_len += size;
92 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
93 }
94
95 static void
96 emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src)
97 {
98 struct nvfx_fragment_program *fp = fpc->fp;
99 uint32_t *hw = &fp->insn[fpc->inst_offset];
100 uint32_t sr = 0;
101
102 switch (src.reg.type) {
103 case NVFXSR_INPUT:
104 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
105 hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
106 break;
107 case NVFXSR_OUTPUT:
108 sr |= NVFX_FP_REG_SRC_HALF;
109 /* fall-through */
110 case NVFXSR_TEMP:
111 sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
112 sr |= (src.reg.index << NVFX_FP_REG_SRC_SHIFT);
113 break;
114 case NVFXSR_RELOCATED:
115 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
116 //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
117 util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset);
118 break;
119 case NVFXSR_CONST:
120 if (!fpc->have_const) {
121 grow_insns(fpc, 4);
122 fpc->have_const = 1;
123 }
124
125 hw = &fp->insn[fpc->inst_offset];
126 if (fpc->consts[src.reg.index].pipe >= 0) {
127 struct nvfx_fragment_program_data *fpd;
128
129 fp->consts = realloc(fp->consts, ++fp->nr_consts *
130 sizeof(*fpd));
131 fpd = &fp->consts[fp->nr_consts - 1];
132 fpd->offset = fpc->inst_offset + 4;
133 fpd->index = fpc->consts[src.reg.index].pipe;
134 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
135 } else {
136 memcpy(&fp->insn[fpc->inst_offset + 4],
137 fpc->consts[src.reg.index].vals,
138 sizeof(uint32_t) * 4);
139 }
140
141 sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT);
142 break;
143 case NVFXSR_NONE:
144 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
145 break;
146 default:
147 assert(0);
148 }
149
150 if (src.negate)
151 sr |= NVFX_FP_REG_NEGATE;
152
153 if (src.abs)
154 hw[1] |= (1 << (29 + pos));
155
156 sr |= ((src.swz[0] << NVFX_FP_REG_SWZ_X_SHIFT) |
157 (src.swz[1] << NVFX_FP_REG_SWZ_Y_SHIFT) |
158 (src.swz[2] << NVFX_FP_REG_SWZ_Z_SHIFT) |
159 (src.swz[3] << NVFX_FP_REG_SWZ_W_SHIFT));
160
161 hw[pos + 1] |= sr;
162 }
163
164 static void
165 emit_dst(struct nvfx_fpc *fpc, struct nvfx_reg dst)
166 {
167 struct nvfx_fragment_program *fp = fpc->fp;
168 uint32_t *hw = &fp->insn[fpc->inst_offset];
169
170 switch (dst.type) {
171 case NVFXSR_TEMP:
172 if (fpc->num_regs < (dst.index + 1))
173 fpc->num_regs = dst.index + 1;
174 break;
175 case NVFXSR_OUTPUT:
176 if (dst.index == 1) {
177 fp->fp_control |= 0xe;
178 } else {
179 hw[0] |= NVFX_FP_OP_OUT_REG_HALF;
180 }
181 break;
182 case NVFXSR_NONE:
183 hw[0] |= (1 << 30);
184 break;
185 default:
186 assert(0);
187 }
188
189 hw[0] |= (dst.index << NVFX_FP_OP_OUT_REG_SHIFT);
190 }
191
192 static void
193 nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn)
194 {
195 struct nvfx_fragment_program *fp = fpc->fp;
196 uint32_t *hw;
197
198 fpc->inst_offset = fp->insn_len;
199 fpc->have_const = 0;
200 grow_insns(fpc, 4);
201 hw = &fp->insn[fpc->inst_offset];
202 memset(hw, 0, sizeof(uint32_t) * 4);
203
204 if (insn.op == NVFX_FP_OP_OPCODE_KIL)
205 fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL;
206 hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
207 hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
208 hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
209
210 if (insn.sat)
211 hw[0] |= NVFX_FP_OP_OUT_SAT;
212
213 if (insn.cc_update)
214 hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
215 hw[1] |= (insn.cc_test << NVFX_FP_OP_COND_SHIFT);
216 hw[1] |= ((insn.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
217 (insn.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
218 (insn.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
219 (insn.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
220
221 if(insn.unit >= 0)
222 {
223 hw[0] |= (insn.unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
224 fp->samplers |= (1 << insn.unit);
225 }
226
227 emit_dst(fpc, insn.dst);
228 emit_src(fpc, 0, insn.src[0]);
229 emit_src(fpc, 1, insn.src[1]);
230 emit_src(fpc, 2, insn.src[2]);
231 }
232
233 #define arith(s,o,d,m,s0,s1,s2) \
234 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, -1, \
235 (d), (m), (s0), (s1), (s2))
236
237 #define tex(s,o,u,d,m,s0,s1,s2) \
238 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
239 (d), (m), (s0), none, none)
240
241 /* IF src.x != 0, as TGSI specifies */
242 static void
243 nv40_fp_if(struct nvfx_fpc *fpc, struct nvfx_src src)
244 {
245 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
246 struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none);
247 insn.cc_update = 1;
248 nvfx_fp_emit(fpc, insn);
249
250 fpc->inst_offset = fpc->fp->insn_len;
251 grow_insns(fpc, 4);
252 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
253 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
254 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
255 NV40_FP_OP_OUT_NONE |
256 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
257 /* Use .xxxx swizzle so that we check only src[0].x*/
258 hw[1] = (0 << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
259 (0 << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
260 (0 << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
261 (0 << NVFX_FP_OP_COND_SWZ_W_SHIFT) |
262 (NVFX_FP_OP_COND_NE << NVFX_FP_OP_COND_SHIFT);
263 hw[2] = 0; /* | NV40_FP_OP_OPCODE_IS_BRANCH | else_offset */
264 hw[3] = 0; /* | endif_offset */
265 util_dynarray_append(&fpc->if_stack, unsigned, fpc->inst_offset);
266 }
267
268 /* IF src.x != 0, as TGSI specifies */
269 static void
270 nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
271 {
272 struct nvfx_label_relocation reloc;
273 fpc->inst_offset = fpc->fp->insn_len;
274 grow_insns(fpc, 4);
275 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
276 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
277 hw[0] = (NV40_FP_OP_BRA_OPCODE_CAL << NVFX_FP_OP_OPCODE_SHIFT);
278 /* Use .xxxx swizzle so that we check only src[0].x*/
279 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
280 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
281 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
282 hw[3] = 0;
283 reloc.target = target;
284 reloc.location = fpc->inst_offset + 2;
285 util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
286 }
287
288 static void
289 nv40_fp_ret(struct nvfx_fpc *fpc)
290 {
291 fpc->inst_offset = fpc->fp->insn_len;
292 grow_insns(fpc, 4);
293 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
294 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
295 hw[0] = (NV40_FP_OP_BRA_OPCODE_RET << NVFX_FP_OP_OPCODE_SHIFT);
296 /* Use .xxxx swizzle so that we check only src[0].x*/
297 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
298 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
299 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
300 hw[3] = 0;
301 }
302
303 static void
304 nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
305 {
306 struct nvfx_label_relocation reloc;
307 fpc->inst_offset = fpc->fp->insn_len;
308 grow_insns(fpc, 4);
309 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
310 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
311 hw[0] = (NV40_FP_OP_BRA_OPCODE_REP << NVFX_FP_OP_OPCODE_SHIFT) |
312 NV40_FP_OP_OUT_NONE |
313 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
314 /* Use .xxxx swizzle so that we check only src[0].x*/
315 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
316 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
317 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH |
318 (count << NV40_FP_OP_REP_COUNT1_SHIFT) |
319 (count << NV40_FP_OP_REP_COUNT2_SHIFT) |
320 (count << NV40_FP_OP_REP_COUNT3_SHIFT);
321 hw[3] = 0; /* | end_offset */
322 reloc.target = target;
323 reloc.location = fpc->inst_offset + 3;
324 util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
325 //util_dynarray_append(&fpc->loop_stack, unsigned, target);
326 }
327
328 /* warning: this only works forward, and probably only if not inside any IF */
329 static void
330 nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
331 {
332 struct nvfx_label_relocation reloc;
333 fpc->inst_offset = fpc->fp->insn_len;
334 grow_insns(fpc, 4);
335 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
336 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
337 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
338 NV40_FP_OP_OUT_NONE |
339 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
340 /* Use .xxxx swizzle so that we check only src[0].x*/
341 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
342 (NVFX_FP_OP_COND_FL << NVFX_FP_OP_COND_SHIFT);
343 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | else_offset */
344 hw[3] = 0; /* | endif_offset */
345 reloc.target = target;
346 reloc.location = fpc->inst_offset + 2;
347 util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
348 reloc.target = target;
349 reloc.location = fpc->inst_offset + 3;
350 util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
351 }
352
353 static void
354 nv40_fp_brk(struct nvfx_fpc *fpc)
355 {
356 fpc->inst_offset = fpc->fp->insn_len;
357 grow_insns(fpc, 4);
358 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
359 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
360 hw[0] = (NV40_FP_OP_BRA_OPCODE_BRK << NVFX_FP_OP_OPCODE_SHIFT) |
361 NV40_FP_OP_OUT_NONE;
362 /* Use .xxxx swizzle so that we check only src[0].x*/
363 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
364 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
365 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH;
366 hw[3] = 0;
367 }
368
369 static INLINE struct nvfx_src
370 tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
371 {
372 struct nvfx_src src;
373
374 switch (fsrc->Register.File) {
375 case TGSI_FILE_INPUT:
376 if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
377 assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
378 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
379 } else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
380 if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0)
381 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
382 else if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 1)
383 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
384 else
385 assert(0);
386 } else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
387 assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
388 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
389 } else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
390 /* TODO: check this has the correct values */
391 /* XXX: what do we do for nv30 here (assuming it lacks facing)?! */
392 assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
393 src.reg = nvfx_reg(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
394 } else {
395 assert(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
396 src.reg = nvfx_reg(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->fp->info.input_semantic_index[fsrc->Register.Index]]);
397 }
398 break;
399 case TGSI_FILE_CONSTANT:
400 src.reg = constant(fpc, fsrc->Register.Index, NULL);
401 break;
402 case TGSI_FILE_IMMEDIATE:
403 assert(fsrc->Register.Index < fpc->nr_imm);
404 src.reg = fpc->imm[fsrc->Register.Index];
405 break;
406 case TGSI_FILE_TEMPORARY:
407 src.reg = fpc->r_temp[fsrc->Register.Index];
408 break;
409 /* NV40 fragprog result regs are just temps, so this is simple */
410 case TGSI_FILE_OUTPUT:
411 src.reg = fpc->r_result[fsrc->Register.Index];
412 break;
413 default:
414 NOUVEAU_ERR("bad src file\n");
415 break;
416 }
417
418 src.abs = fsrc->Register.Absolute;
419 src.negate = fsrc->Register.Negate;
420 src.swz[0] = fsrc->Register.SwizzleX;
421 src.swz[1] = fsrc->Register.SwizzleY;
422 src.swz[2] = fsrc->Register.SwizzleZ;
423 src.swz[3] = fsrc->Register.SwizzleW;
424 return src;
425 }
426
427 static INLINE struct nvfx_reg
428 tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
429 switch (fdst->Register.File) {
430 case TGSI_FILE_OUTPUT:
431 return fpc->r_result[fdst->Register.Index];
432 case TGSI_FILE_TEMPORARY:
433 return fpc->r_temp[fdst->Register.Index];
434 case TGSI_FILE_NULL:
435 return nvfx_reg(NVFXSR_NONE, 0);
436 default:
437 NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
438 return nvfx_reg(NVFXSR_NONE, 0);
439 }
440 }
441
442 static INLINE int
443 tgsi_mask(uint tgsi)
444 {
445 int mask = 0;
446
447 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_FP_MASK_X;
448 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_FP_MASK_Y;
449 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_FP_MASK_Z;
450 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_FP_MASK_W;
451 return mask;
452 }
453
454 static boolean
455 nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
456 const struct tgsi_full_instruction *finst)
457 {
458 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
459 struct nvfx_insn insn;
460 struct nvfx_src src[3], tmp;
461 struct nvfx_reg dst;
462 int mask, sat, unit = 0;
463 int ai = -1, ci = -1, ii = -1;
464 int i;
465
466 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
467 return TRUE;
468
469 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
470 const struct tgsi_full_src_register *fsrc;
471
472 fsrc = &finst->Src[i];
473 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
474 src[i] = tgsi_src(fpc, fsrc);
475 }
476 }
477
478 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
479 const struct tgsi_full_src_register *fsrc;
480
481 fsrc = &finst->Src[i];
482
483 switch (fsrc->Register.File) {
484 case TGSI_FILE_INPUT:
485 if (ai == -1 || ai == fsrc->Register.Index) {
486 ai = fsrc->Register.Index;
487 src[i] = tgsi_src(fpc, fsrc);
488 } else {
489 src[i] = nvfx_src(temp(fpc));
490 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
491 }
492 break;
493 case TGSI_FILE_CONSTANT:
494 if ((ci == -1 && ii == -1) ||
495 ci == fsrc->Register.Index) {
496 ci = fsrc->Register.Index;
497 src[i] = tgsi_src(fpc, fsrc);
498 } else {
499 src[i] = nvfx_src(temp(fpc));
500 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
501 }
502 break;
503 case TGSI_FILE_IMMEDIATE:
504 if ((ci == -1 && ii == -1) ||
505 ii == fsrc->Register.Index) {
506 ii = fsrc->Register.Index;
507 src[i] = tgsi_src(fpc, fsrc);
508 } else {
509 src[i] = nvfx_src(temp(fpc));
510 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
511 }
512 break;
513 case TGSI_FILE_TEMPORARY:
514 /* handled above */
515 break;
516 case TGSI_FILE_SAMPLER:
517 unit = fsrc->Register.Index;
518 break;
519 case TGSI_FILE_OUTPUT:
520 break;
521 default:
522 NOUVEAU_ERR("bad src file\n");
523 return FALSE;
524 }
525 }
526
527 dst = tgsi_dst(fpc, &finst->Dst[0]);
528 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
529 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
530
531 switch (finst->Instruction.Opcode) {
532 case TGSI_OPCODE_ABS:
533 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, abs(src[0]), none, none));
534 break;
535 case TGSI_OPCODE_ADD:
536 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
537 break;
538 case TGSI_OPCODE_CMP:
539 insn = arith(0, MOV, none.reg, 0xf, src[0], none, none);
540 insn.cc_update = 1;
541 nvfx_fp_emit(fpc, insn);
542
543 insn = arith(sat, MOV, dst, mask, src[2], none, none);
544 insn.cc_test = NVFX_COND_GE;
545 nvfx_fp_emit(fpc, insn);
546
547 insn = arith(sat, MOV, dst, mask, src[1], none, none);
548 insn.cc_test = NVFX_COND_LT;
549 nvfx_fp_emit(fpc, insn);
550 break;
551 case TGSI_OPCODE_COS:
552 nvfx_fp_emit(fpc, arith(sat, COS, dst, mask, src[0], none, none));
553 break;
554 case TGSI_OPCODE_DDX:
555 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
556 tmp = nvfx_src(temp(fpc));
557 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
558 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
559 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
560 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
561 } else {
562 nvfx_fp_emit(fpc, arith(sat, DDX, dst, mask, src[0], none, none));
563 }
564 break;
565 case TGSI_OPCODE_DDY:
566 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
567 tmp = nvfx_src(temp(fpc));
568 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
569 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
570 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
571 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
572 } else {
573 nvfx_fp_emit(fpc, arith(sat, DDY, dst, mask, src[0], none, none));
574 }
575 break;
576 case TGSI_OPCODE_DP3:
577 nvfx_fp_emit(fpc, arith(sat, DP3, dst, mask, src[0], src[1], none));
578 break;
579 case TGSI_OPCODE_DP4:
580 nvfx_fp_emit(fpc, arith(sat, DP4, dst, mask, src[0], src[1], none));
581 break;
582 case TGSI_OPCODE_DPH:
583 tmp = nvfx_src(temp(fpc));
584 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[1], none));
585 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, swz(tmp, X, X, X, X), swz(src[1], W, W, W, W), none));
586 break;
587 case TGSI_OPCODE_DST:
588 nvfx_fp_emit(fpc, arith(sat, DST, dst, mask, src[0], src[1], none));
589 break;
590 case TGSI_OPCODE_EX2:
591 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, src[0], none, none));
592 break;
593 case TGSI_OPCODE_FLR:
594 nvfx_fp_emit(fpc, arith(sat, FLR, dst, mask, src[0], none, none));
595 break;
596 case TGSI_OPCODE_FRC:
597 nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none));
598 break;
599 case TGSI_OPCODE_KILP:
600 nvfx_fp_emit(fpc, arith(0, KIL, none.reg, 0, none, none, none));
601 break;
602 case TGSI_OPCODE_KIL:
603 insn = arith(0, MOV, none.reg, NVFX_FP_MASK_ALL, src[0], none, none);
604 insn.cc_update = 1;
605 nvfx_fp_emit(fpc, insn);
606
607 insn = arith(0, KIL, none.reg, 0, none, none, none);
608 insn.cc_test = NVFX_COND_LT;
609 nvfx_fp_emit(fpc, insn);
610 break;
611 case TGSI_OPCODE_LG2:
612 nvfx_fp_emit(fpc, arith(sat, LG2, dst, mask, src[0], none, none));
613 break;
614 // case TGSI_OPCODE_LIT:
615 case TGSI_OPCODE_LRP:
616 if(!nvfx->is_nv4x)
617 nvfx_fp_emit(fpc, arith(sat, LRP_NV30, dst, mask, src[0], src[1], src[2]));
618 else {
619 tmp = nvfx_src(temp(fpc));
620 nvfx_fp_emit(fpc, arith(0, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
621 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], tmp));
622 }
623 break;
624 case TGSI_OPCODE_MAD:
625 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], src[2]));
626 break;
627 case TGSI_OPCODE_MAX:
628 nvfx_fp_emit(fpc, arith(sat, MAX, dst, mask, src[0], src[1], none));
629 break;
630 case TGSI_OPCODE_MIN:
631 nvfx_fp_emit(fpc, arith(sat, MIN, dst, mask, src[0], src[1], none));
632 break;
633 case TGSI_OPCODE_MOV:
634 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, src[0], none, none));
635 break;
636 case TGSI_OPCODE_MUL:
637 nvfx_fp_emit(fpc, arith(sat, MUL, dst, mask, src[0], src[1], none));
638 break;
639 case TGSI_OPCODE_NOP:
640 break;
641 case TGSI_OPCODE_POW:
642 if(!nvfx->is_nv4x)
643 nvfx_fp_emit(fpc, arith(sat, POW_NV30, dst, mask, src[0], src[1], none));
644 else {
645 tmp = nvfx_src(temp(fpc));
646 nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
647 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
648 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, swz(tmp, X, X, X, X), none, none));
649 }
650 break;
651 case TGSI_OPCODE_RCP:
652 nvfx_fp_emit(fpc, arith(sat, RCP, dst, mask, src[0], none, none));
653 break;
654 case TGSI_OPCODE_RFL:
655 if(!nvfx->is_nv4x)
656 nvfx_fp_emit(fpc, arith(0, RFL_NV30, dst, mask, src[0], src[1], none));
657 else {
658 tmp = nvfx_src(temp(fpc));
659 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[0], none));
660 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_Y, src[0], src[1], none));
661 insn = arith(0, DIV, tmp.reg, NVFX_FP_MASK_Z, swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
662 insn.scale = NVFX_FP_OP_DST_SCALE_2X;
663 nvfx_fp_emit(fpc, insn);
664 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, swz(tmp, Z, Z, Z, Z), src[0], neg(src[1])));
665 }
666 break;
667 case TGSI_OPCODE_RSQ:
668 if(!nvfx->is_nv4x)
669 nvfx_fp_emit(fpc, arith(sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none));
670 else {
671 tmp = nvfx_src(temp(fpc));
672 insn = arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, abs(swz(src[0], X, X, X, X)), none, none);
673 insn.scale = NVFX_FP_OP_DST_SCALE_INV_2X;
674 nvfx_fp_emit(fpc, insn);
675 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, neg(swz(tmp, X, X, X, X)), none, none));
676 }
677 break;
678 case TGSI_OPCODE_SCS:
679 /* avoid overwriting the source */
680 if(src[0].swz[NVFX_SWZ_X] != NVFX_SWZ_X)
681 {
682 if (mask & NVFX_FP_MASK_X)
683 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
684 if (mask & NVFX_FP_MASK_Y)
685 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
686 }
687 else
688 {
689 if (mask & NVFX_FP_MASK_Y)
690 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
691 if (mask & NVFX_FP_MASK_X)
692 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
693 }
694 break;
695 case TGSI_OPCODE_SEQ:
696 nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
697 break;
698 case TGSI_OPCODE_SFL:
699 nvfx_fp_emit(fpc, arith(sat, SFL, dst, mask, src[0], src[1], none));
700 break;
701 case TGSI_OPCODE_SGE:
702 nvfx_fp_emit(fpc, arith(sat, SGE, dst, mask, src[0], src[1], none));
703 break;
704 case TGSI_OPCODE_SGT:
705 nvfx_fp_emit(fpc, arith(sat, SGT, dst, mask, src[0], src[1], none));
706 break;
707 case TGSI_OPCODE_SIN:
708 nvfx_fp_emit(fpc, arith(sat, SIN, dst, mask, src[0], none, none));
709 break;
710 case TGSI_OPCODE_SLE:
711 nvfx_fp_emit(fpc, arith(sat, SLE, dst, mask, src[0], src[1], none));
712 break;
713 case TGSI_OPCODE_SLT:
714 nvfx_fp_emit(fpc, arith(sat, SLT, dst, mask, src[0], src[1], none));
715 break;
716 case TGSI_OPCODE_SNE:
717 nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none));
718 break;
719 case TGSI_OPCODE_STR:
720 nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
721 break;
722 case TGSI_OPCODE_SUB:
723 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
724 break;
725 case TGSI_OPCODE_TEX:
726 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
727 break;
728 case TGSI_OPCODE_TRUNC:
729 tmp = nvfx_src(temp(fpc));
730 insn = arith(0, MOV, none.reg, mask, src[0], none, none);
731 insn.cc_update = 1;
732 nvfx_fp_emit(fpc, insn);
733
734 nvfx_fp_emit(fpc, arith(0, FLR, tmp.reg, mask, abs(src[0]), none, none));
735 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, tmp, none, none));
736
737 insn = arith(sat, MOV, dst, mask, neg(tmp), none, none);
738 insn.cc_test = NVFX_COND_LT;
739 nvfx_fp_emit(fpc, insn);
740 break;
741 case TGSI_OPCODE_TXB:
742 nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
743 break;
744 case TGSI_OPCODE_TXP:
745 nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
746 break;
747 case TGSI_OPCODE_XPD:
748 tmp = nvfx_src(temp(fpc));
749 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
750 nvfx_fp_emit(fpc, arith(sat, MAD, dst, (mask & ~NVFX_FP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
751 break;
752
753 case TGSI_OPCODE_IF:
754 // MOVRC0 R31 (TR0.xyzw), R<src>:
755 // IF (NE.xxxx) ELSE <else> END <end>
756 if(!nvfx->is_nv4x)
757 goto nv3x_cflow;
758 nv40_fp_if(fpc, src[0]);
759 break;
760
761 case TGSI_OPCODE_ELSE:
762 {
763 if(!nvfx->is_nv4x)
764 goto nv3x_cflow;
765 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
766 uint32_t *hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
767 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
768 break;
769 }
770
771 case TGSI_OPCODE_ENDIF:
772 {
773 if(!nvfx->is_nv4x)
774 goto nv3x_cflow;
775 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
776 uint32_t *hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
777 if(!hw[2])
778 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
779 hw[3] = fpc->fp->insn_len;
780 break;
781 }
782
783 case TGSI_OPCODE_BRA:
784 /* This can in limited cases be implemented with an IF with the else and endif labels pointing to the target */
785 /* no state tracker uses this, so don't implement this for now */
786 assert(0);
787 nv40_fp_bra(fpc, finst->Label.Label);
788 break;
789
790 case TGSI_OPCODE_BGNSUB:
791 case TGSI_OPCODE_ENDSUB:
792 /* nothing to do here */
793 break;
794
795 case TGSI_OPCODE_CAL:
796 if(!nvfx->is_nv4x)
797 goto nv3x_cflow;
798 nv40_fp_cal(fpc, finst->Label.Label);
799 break;
800
801 case TGSI_OPCODE_RET:
802 if(!nvfx->is_nv4x)
803 goto nv3x_cflow;
804 nv40_fp_ret(fpc);
805 break;
806
807 case TGSI_OPCODE_BGNLOOP:
808 if(!nvfx->is_nv4x)
809 goto nv3x_cflow;
810 /* TODO: we should support using two nested REPs to allow a > 255 iteration count */
811 nv40_fp_rep(fpc, 255, finst->Label.Label);
812 break;
813
814 case TGSI_OPCODE_ENDLOOP:
815 break;
816
817 case TGSI_OPCODE_BRK:
818 if(!nvfx->is_nv4x)
819 goto nv3x_cflow;
820 nv40_fp_brk(fpc);
821 break;
822
823 case TGSI_OPCODE_CONT:
824 {
825 static int warned = 0;
826 if(!warned) {
827 NOUVEAU_ERR("Sorry, the continue keyword is not implemented: ignoring it.\n");
828 warned = 1;
829 }
830 break;
831 }
832
833 default:
834 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
835 return FALSE;
836 }
837
838 out:
839 release_temps(fpc);
840 return TRUE;
841 nv3x_cflow:
842 {
843 static int warned = 0;
844 if(!warned) {
845 NOUVEAU_ERR(
846 "Sorry, control flow instructions are not supported in hardware on nv3x: ignoring them\n"
847 "If rendering is incorrect, try to disable GLSL support in the application.\n");
848 warned = 1;
849 }
850 }
851 goto out;
852 }
853
854 static boolean
855 nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
856 const struct tgsi_full_declaration *fdec)
857 {
858 unsigned idx = fdec->Range.First;
859 unsigned hw;
860
861 switch (fdec->Semantic.Name) {
862 case TGSI_SEMANTIC_POSITION:
863 hw = 1;
864 break;
865 case TGSI_SEMANTIC_COLOR:
866 hw = ~0;
867 switch (fdec->Semantic.Index) {
868 case 0: hw = 0; break;
869 case 1: hw = 2; break;
870 case 2: hw = 3; break;
871 case 3: hw = 4; break;
872 }
873 if(hw > ((nvfx->is_nv4x) ? 4 : 2)) {
874 NOUVEAU_ERR("bad rcol index\n");
875 return FALSE;
876 }
877 break;
878 default:
879 NOUVEAU_ERR("bad output semantic\n");
880 return FALSE;
881 }
882
883 fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
884 fpc->r_temps |= (1 << hw);
885 return TRUE;
886 }
887
888 static boolean
889 nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
890 {
891 struct tgsi_parse_context p;
892 int high_temp = -1, i;
893 struct util_semantic_set set;
894
895 fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->fp->pipe.tokens, TGSI_FILE_INPUT);
896 if(fpc->fp->num_slots > 8)
897 return FALSE;
898 util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, 8);
899 util_semantic_table_from_layout(fpc->generic_to_slot, fpc->fp->slot_to_generic, 0, 8);
900
901 memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input));
902
903 tgsi_parse_init(&p, fpc->fp->pipe.tokens);
904 while (!tgsi_parse_end_of_tokens(&p)) {
905 const union tgsi_full_token *tok = &p.FullToken;
906
907 tgsi_parse_token(&p);
908 switch(tok->Token.Type) {
909 case TGSI_TOKEN_TYPE_DECLARATION:
910 {
911 const struct tgsi_full_declaration *fdec;
912 fdec = &p.FullToken.FullDeclaration;
913 switch (fdec->Declaration.File) {
914 case TGSI_FILE_OUTPUT:
915 if (!nvfx_fragprog_parse_decl_output(nvfx, fpc, fdec))
916 goto out_err;
917 break;
918 case TGSI_FILE_TEMPORARY:
919 if (fdec->Range.Last > high_temp) {
920 high_temp =
921 fdec->Range.Last;
922 }
923 break;
924 default:
925 break;
926 }
927 }
928 break;
929 case TGSI_TOKEN_TYPE_IMMEDIATE:
930 {
931 struct tgsi_full_immediate *imm;
932 float vals[4];
933
934 imm = &p.FullToken.FullImmediate;
935 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
936 assert(fpc->nr_imm < MAX_IMM);
937
938 vals[0] = imm->u[0].Float;
939 vals[1] = imm->u[1].Float;
940 vals[2] = imm->u[2].Float;
941 vals[3] = imm->u[3].Float;
942 fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals);
943 }
944 break;
945 default:
946 break;
947 }
948 }
949 tgsi_parse_free(&p);
950
951 if (++high_temp) {
952 fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
953 for (i = 0; i < high_temp; i++)
954 fpc->r_temp[i] = temp(fpc);
955 fpc->r_temps_discard = 0;
956 }
957
958 return TRUE;
959
960 out_err:
961 if (fpc->r_temp)
962 FREE(fpc->r_temp);
963 tgsi_parse_free(&p);
964 return FALSE;
965 }
966
967 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE)
968
969 static void
970 nvfx_fragprog_translate(struct nvfx_context *nvfx,
971 struct nvfx_fragment_program *fp)
972 {
973 struct tgsi_parse_context parse;
974 struct nvfx_fpc *fpc = NULL;
975 struct util_dynarray insns;
976
977 fpc = CALLOC(1, sizeof(struct nvfx_fpc));
978 if (!fpc)
979 return;
980 fpc->fp = fp;
981 fpc->num_regs = 2;
982
983 if (!nvfx_fragprog_prepare(nvfx, fpc)) {
984 FREE(fpc);
985 return;
986 }
987
988 tgsi_parse_init(&parse, fp->pipe.tokens);
989
990 util_dynarray_init(&insns);
991 while (!tgsi_parse_end_of_tokens(&parse)) {
992 tgsi_parse_token(&parse);
993
994 switch (parse.FullToken.Token.Type) {
995 case TGSI_TOKEN_TYPE_INSTRUCTION:
996 {
997 const struct tgsi_full_instruction *finst;
998
999 util_dynarray_append(&insns, unsigned, fp->insn_len);
1000 finst = &parse.FullToken.FullInstruction;
1001 if (!nvfx_fragprog_parse_instruction(nvfx, fpc, finst))
1002 goto out_err;
1003 }
1004 break;
1005 default:
1006 break;
1007 }
1008 }
1009 util_dynarray_append(&insns, unsigned, fp->insn_len);
1010
1011 for(unsigned i = 0; i < fpc->label_relocs.size; i += sizeof(struct nvfx_label_relocation))
1012 {
1013 struct nvfx_label_relocation* label_reloc = (struct nvfx_label_relocation*)((char*)fpc->label_relocs.data + i);
1014 fp->insn[label_reloc->location] |= ((unsigned*)insns.data)[label_reloc->target];
1015 }
1016 util_dynarray_fini(&insns);
1017
1018 if(!nvfx->is_nv4x)
1019 fp->fp_control |= (fpc->num_regs-1)/2;
1020 else
1021 fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT;
1022
1023 /* Terminate final instruction */
1024 if(fp->insn)
1025 fp->insn[fpc->inst_offset] |= 0x00000001;
1026
1027 /* Append NOP + END instruction for branches to the end of the program */
1028 fpc->inst_offset = fp->insn_len;
1029 grow_insns(fpc, 4);
1030 fp->insn[fpc->inst_offset + 0] = 0x00000001;
1031 fp->insn[fpc->inst_offset + 1] = 0x00000000;
1032 fp->insn[fpc->inst_offset + 2] = 0x00000000;
1033 fp->insn[fpc->inst_offset + 3] = 0x00000000;
1034
1035 if(debug_get_option_nvfx_dump_fp())
1036 {
1037 debug_printf("\n");
1038 tgsi_dump(fp->pipe.tokens, 0);
1039
1040 debug_printf("\n%s fragment program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
1041 for (unsigned i = 0; i < fp->insn_len; i += 4)
1042 debug_printf("%3u: %08x %08x %08x %08x\n", i >> 2, fp->insn[i], fp->insn[i + 1], fp->insn[i + 2], fp->insn[i + 3]);
1043 debug_printf("\n");
1044 }
1045
1046 fp->translated = TRUE;
1047 out_err:
1048 tgsi_parse_free(&parse);
1049 if (fpc->r_temp)
1050 FREE(fpc->r_temp);
1051 util_dynarray_fini(&fpc->if_stack);
1052 util_dynarray_fini(&fpc->label_relocs);
1053 //util_dynarray_fini(&fpc->loop_stack);
1054 FREE(fpc);
1055 }
1056
1057 static inline void
1058 nvfx_fp_memcpy(void* dst, const void* src, size_t len)
1059 {
1060 #ifndef WORDS_BIGENDIAN
1061 memcpy(dst, src, len);
1062 #else
1063 size_t i;
1064 for(i = 0; i < len; i += 4) {
1065 uint32_t v = (uint32_t*)((char*)src + i);
1066 *(uint32_t*)((char*)dst + i) = (v >> 16) | (v << 16);
1067 }
1068 #endif
1069 }
1070
1071 void
1072 nvfx_fragprog_validate(struct nvfx_context *nvfx)
1073 {
1074 struct nouveau_channel* chan = nvfx->screen->base.channel;
1075 struct nvfx_fragment_program *fp = nvfx->fragprog;
1076 int update = 0;
1077
1078 if (!fp->translated)
1079 {
1080 const int min_size = 4096;
1081
1082 nvfx_fragprog_translate(nvfx, fp);
1083 if (!fp->translated) {
1084 static unsigned dummy[8] = {1, 0, 0, 0, 1, 0, 0, 0};
1085 static int warned = 0;
1086 if(!warned)
1087 {
1088 fprintf(stderr, "nvfx: failed to translate fragment program!\n");
1089 warned = 1;
1090 }
1091
1092 /* use dummy program: we cannot fail here */
1093 fp->translated = TRUE;
1094 fp->insn = malloc(sizeof(dummy));
1095 memcpy(fp->insn, dummy, sizeof(dummy));
1096 fp->insn_len = sizeof(dummy) / sizeof(dummy[0]);
1097 }
1098 update = TRUE;
1099
1100 fp->prog_size = (fp->insn_len * 4 + 63) & ~63;
1101
1102 if(fp->prog_size >= min_size)
1103 fp->progs_per_bo = 1;
1104 else
1105 fp->progs_per_bo = min_size / fp->prog_size;
1106 fp->bo_prog_idx = fp->progs_per_bo - 1;
1107 }
1108
1109 /* we must update constants even on "just" fragprog changes, because
1110 we don't check whether the current constant buffer matches the latest
1111 one bound to this fragment program */
1112 if (nvfx->dirty & (NVFX_NEW_FRAGCONST | NVFX_NEW_FRAGPROG))
1113 update = TRUE;
1114
1115 struct nvfx_vertex_program* vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
1116 if (fp->last_vp_id != vp->id) {
1117 char* vp_sem_table = vp->generic_to_fp_input;
1118 unsigned char* fp_semantics = fp->slot_to_generic;
1119 unsigned diff = 0;
1120 fp->last_vp_id = nvfx->vertprog->id;
1121 unsigned char* cur_slots = fp->slot_to_fp_input;
1122 for(unsigned i = 0; i < fp->num_slots; ++i) {
1123 unsigned char slot_mask = vp_sem_table[fp_semantics[i]];
1124 diff |= (slot_mask >> 4) & (slot_mask ^ cur_slots[i]);
1125 }
1126
1127 if(diff)
1128 {
1129 for(unsigned i = 0; i < fp->num_slots; ++i) {
1130 /* if 0xff, then this will write to the dummy value at fp->last_layout_mask[0] */
1131 fp->slot_to_fp_input[i] = vp_sem_table[fp_semantics[i]] & 0xf;
1132 //printf("fp: GENERIC[%i] from fpreg %i\n", fp_semantics[i], fp->slot_to_fp_input[i]);
1133 }
1134
1135 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
1136 update = TRUE;
1137 }
1138 }
1139
1140 // last_sprite_coord_enable
1141 unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
1142 if(fp->last_sprite_coord_enable != sprite_coord_enable)
1143 {
1144 unsigned texcoord_mask = vp->texcoord_ouput_mask;
1145 fp->last_sprite_coord_enable = sprite_coord_enable;
1146 fp->point_sprite_control = 0;
1147 for(unsigned i = 0; i < fp->num_slots; ++i) {
1148 if((1 << fp->slot_to_generic[i]) & sprite_coord_enable)
1149 {
1150 unsigned fpin = fp->slot_to_fp_input[i];
1151 //printf("sprite: slot %i generic %i had texcoord %i\n", i, fp->slot_to_generic[i], fpin - NVFX_FP_OP_INPUT_SRC_TC0);
1152 if(fpin >= 0x0f)
1153 {
1154 unsigned tc = __builtin_ctz(~texcoord_mask);
1155 texcoord_mask |= (1 << tc);
1156 fp->slot_to_fp_input[i] = fpin = NVFX_FP_OP_INPUT_SRC_TC(tc);
1157
1158 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
1159 update = TRUE;
1160 }
1161 //printf("sprite: slot %i texcoord %i\n", i, fpin - NVFX_FP_OP_INPUT_SRC_TC0);
1162 fp->point_sprite_control |= (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
1163 }
1164 else
1165 {
1166 unsigned fpin = fp->slot_to_fp_input[i];
1167 if(!(vp->texcoord_ouput_mask & (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0))))
1168 {
1169 fp->slot_to_fp_input[i] = 0x0f;
1170
1171 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
1172 update = TRUE;
1173 }
1174 }
1175 }
1176 }
1177
1178 if(update) {
1179 ++fp->bo_prog_idx;
1180 if(fp->bo_prog_idx >= fp->progs_per_bo)
1181 {
1182 if(fp->fpbo && !nouveau_bo_busy(fp->fpbo->next->bo, NOUVEAU_BO_WR))
1183 {
1184 fp->fpbo = fp->fpbo->next;
1185 }
1186 else
1187 {
1188 struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + (fp->prog_size + 8) * fp->progs_per_bo, 16);
1189 fpbo->slots = (unsigned char*)&fpbo->insn[(fp->prog_size) * fp->progs_per_bo];
1190 memset(fpbo->slots, 0, 8 * fp->progs_per_bo);
1191 if(fp->fpbo)
1192 {
1193 fpbo->next = fp->fpbo->next;
1194 fp->fpbo->next = fpbo;
1195 }
1196 else
1197 fpbo->next = fpbo;
1198 fp->fpbo = fpbo;
1199 fpbo->bo = 0;
1200 fp->progs += fp->progs_per_bo;
1201 fp->progs_left_with_obsolete_slot_assignments += fp->progs_per_bo;
1202 nouveau_bo_new(nvfx->screen->base.device, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, 64, fp->prog_size * fp->progs_per_bo, &fpbo->bo);
1203 nouveau_bo_map(fpbo->bo, NOUVEAU_BO_NOSYNC);
1204
1205 uint8_t* map = fpbo->bo->map;
1206 uint8_t* buf = (uint8_t*)fpbo->insn;
1207 for(unsigned i = 0; i < fp->progs_per_bo; ++i)
1208 {
1209 memcpy(buf, fp->insn, fp->insn_len * 4);
1210 nvfx_fp_memcpy(map, fp->insn, fp->insn_len * 4);
1211 map += fp->prog_size;
1212 buf += fp->prog_size;
1213 }
1214 }
1215 fp->bo_prog_idx = 0;
1216 }
1217
1218 int offset = fp->bo_prog_idx * fp->prog_size;
1219 uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1220
1221 if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) {
1222 struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT];
1223 uint32_t* map = (uint32_t*)nvfx_buffer(constbuf)->data;
1224 uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1225 uint32_t* buf = (uint32_t*)((char*)fp->fpbo->insn + offset);
1226 int i;
1227 for (i = 0; i < fp->nr_consts; ++i) {
1228 unsigned off = fp->consts[i].offset;
1229 unsigned idx = fp->consts[i].index * 4;
1230
1231 /* TODO: is checking a good idea? */
1232 if(memcmp(&buf[off], &map[idx], 4 * sizeof(uint32_t))) {
1233 memcpy(&buf[off], &map[idx], 4 * sizeof(uint32_t));
1234 nvfx_fp_memcpy(&fpmap[off], &map[idx], 4 * sizeof(uint32_t));
1235 }
1236 }
1237 }
1238
1239 if(fp->progs_left_with_obsolete_slot_assignments) {
1240 unsigned char* fpbo_slots = &fp->fpbo->slots[fp->bo_prog_idx * 8];
1241 for(unsigned i = 0; i < fp->num_slots; ++i) {
1242 unsigned value = fp->slot_to_fp_input[i];;
1243 if(value != fpbo_slots[i]) {
1244 unsigned* p = (unsigned*)fp->slot_relocations[i].data;
1245 unsigned* pend = (unsigned*)((char*)fp->slot_relocations[i].data + fp->slot_relocations[i].size);
1246 for(; p != pend; ++p) {
1247 unsigned off = *p;
1248 unsigned dw = fp->insn[off];
1249 dw = (dw & ~NVFX_FP_OP_INPUT_SRC_MASK) | (value << NVFX_FP_OP_INPUT_SRC_SHIFT);
1250 nvfx_fp_memcpy(&fpmap[*p], &dw, sizeof(dw));
1251 }
1252 fpbo_slots[i] = value;
1253 }
1254 }
1255 --fp->progs_left_with_obsolete_slot_assignments;
1256 }
1257 }
1258
1259 if(update || (nvfx->dirty & NVFX_NEW_FRAGPROG)) {
1260 int offset = fp->bo_prog_idx * fp->prog_size;
1261 MARK_RING(chan, 8, 1);
1262 OUT_RING(chan, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1));
1263 OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
1264 NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
1265 NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
1266 NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
1267 OUT_RING(chan, RING_3D(NV34TCL_FP_CONTROL, 1));
1268 OUT_RING(chan, fp->fp_control);
1269 if(!nvfx->is_nv4x) {
1270 OUT_RING(chan, RING_3D(NV34TCL_FP_REG_CONTROL, 1));
1271 OUT_RING(chan, (1<<16)|0x4);
1272 OUT_RING(chan, RING_3D(NV34TCL_TX_UNITS_ENABLE, 1));
1273 OUT_RING(chan, fp->samplers);
1274 }
1275 }
1276
1277 if(nvfx->dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_SPRITE))
1278 {
1279 WAIT_RING(chan, 2);
1280 OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1));
1281 OUT_RING(chan, fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization);
1282 }
1283 }
1284
1285 void
1286 nvfx_fragprog_relocate(struct nvfx_context *nvfx)
1287 {
1288 struct nouveau_channel* chan = nvfx->screen->base.channel;
1289 struct nvfx_fragment_program *fp = nvfx->fragprog;
1290 struct nouveau_bo* bo = fp->fpbo->bo;
1291 int offset = fp->bo_prog_idx * fp->prog_size;
1292 unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART?
1293 fp_flags |= NOUVEAU_BO_DUMMY;
1294 MARK_RING(chan, 2, 2);
1295 OUT_RELOC(chan, bo, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
1296 OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW |
1297 NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
1298 NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
1299 }
1300
1301 void
1302 nvfx_fragprog_destroy(struct nvfx_context *nvfx,
1303 struct nvfx_fragment_program *fp)
1304 {
1305 unsigned i;
1306 struct nvfx_fragment_program_bo* fpbo = fp->fpbo;
1307 if(fpbo)
1308 {
1309 do
1310 {
1311 struct nvfx_fragment_program_bo* next = fpbo->next;
1312 nouveau_bo_unmap(fpbo->bo);
1313 nouveau_bo_ref(0, &fpbo->bo);
1314 free(fpbo);
1315 fpbo = next;
1316 }
1317 while(fpbo != fp->fpbo);
1318 }
1319
1320 for(i = 0; i < 8; ++i)
1321 util_dynarray_fini(&fp->slot_relocations[i]);
1322
1323 if (fp->insn_len)
1324 FREE(fp->insn);
1325 }