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44c7968d88e4babd2661361426e572b5409d135c
[mesa.git] / src / gallium / drivers / nvfx / nvfx_fragprog.c
1 #include <float.h>
2 #include "pipe/p_context.h"
3 #include "pipe/p_defines.h"
4 #include "pipe/p_state.h"
5 #include "util/u_inlines.h"
6 #include "util/u_debug.h"
7
8 #include "pipe/p_shader_tokens.h"
9 #include "tgsi/tgsi_parse.h"
10 #include "tgsi/tgsi_util.h"
11 #include "tgsi/tgsi_dump.h"
12 #include "tgsi/tgsi_ureg.h"
13
14 #include "nvfx_context.h"
15 #include "nvfx_shader.h"
16 #include "nvfx_resource.h"
17
18 struct nvfx_fpc {
19 struct nvfx_pipe_fragment_program* pfp;
20 struct nvfx_fragment_program *fp;
21
22 unsigned max_temps;
23 unsigned long long r_temps;
24 unsigned long long r_temps_discard;
25 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
26 struct nvfx_reg *r_temp;
27 unsigned sprite_coord_temp;
28
29 int num_regs;
30
31 unsigned inst_offset;
32 unsigned have_const;
33
34 struct util_dynarray imm_data;
35
36 struct nvfx_reg* r_imm;
37 unsigned nr_imm;
38
39 unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
40
41 struct util_dynarray if_stack;
42 //struct util_dynarray loop_stack;
43 struct util_dynarray label_relocs;
44 };
45
46 static INLINE struct nvfx_reg
47 temp(struct nvfx_fpc *fpc)
48 {
49 int idx = __builtin_ctzll(~fpc->r_temps);
50
51 if (idx >= fpc->max_temps) {
52 NOUVEAU_ERR("out of temps!!\n");
53 assert(0);
54 return nvfx_reg(NVFXSR_TEMP, 0);
55 }
56
57 fpc->r_temps |= (1ULL << idx);
58 fpc->r_temps_discard |= (1ULL << idx);
59 return nvfx_reg(NVFXSR_TEMP, idx);
60 }
61
62 static INLINE void
63 release_temps(struct nvfx_fpc *fpc)
64 {
65 fpc->r_temps &= ~fpc->r_temps_discard;
66 fpc->r_temps_discard = 0ULL;
67 }
68
69 static inline struct nvfx_reg
70 nvfx_fp_imm(struct nvfx_fpc *fpc, float a, float b, float c, float d)
71 {
72 float v[4] = {a, b, c, d};
73 int idx = fpc->imm_data.size >> 4;
74
75 memcpy(util_dynarray_grow(&fpc->imm_data, sizeof(float) * 4), v, 4 * sizeof(float));
76 return nvfx_reg(NVFXSR_IMM, idx);
77 }
78
79 static void
80 grow_insns(struct nvfx_fpc *fpc, int size)
81 {
82 struct nvfx_fragment_program *fp = fpc->fp;
83
84 fp->insn_len += size;
85 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
86 }
87
88 static void
89 emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src)
90 {
91 struct nvfx_fragment_program *fp = fpc->fp;
92 uint32_t *hw = &fp->insn[fpc->inst_offset];
93 uint32_t sr = 0;
94
95 switch (src.reg.type) {
96 case NVFXSR_INPUT:
97 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
98 hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
99 break;
100 case NVFXSR_OUTPUT:
101 sr |= NVFX_FP_REG_SRC_HALF;
102 /* fall-through */
103 case NVFXSR_TEMP:
104 sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
105 sr |= (src.reg.index << NVFX_FP_REG_SRC_SHIFT);
106 break;
107 case NVFXSR_RELOCATED:
108 sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
109 sr |= (fpc->sprite_coord_temp << NVFX_FP_REG_SRC_SHIFT);
110 //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
111 util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset + pos + 1);
112 break;
113 case NVFXSR_IMM:
114 if (!fpc->have_const) {
115 grow_insns(fpc, 4);
116 hw = &fp->insn[fpc->inst_offset];
117 fpc->have_const = 1;
118 }
119
120 memcpy(&fp->insn[fpc->inst_offset + 4],
121 (float*)fpc->imm_data.data + src.reg.index * 4,
122 sizeof(uint32_t) * 4);
123
124 sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT);
125 break;
126 case NVFXSR_CONST:
127 if (!fpc->have_const) {
128 grow_insns(fpc, 4);
129 hw = &fp->insn[fpc->inst_offset];
130 fpc->have_const = 1;
131 }
132
133 {
134 struct nvfx_fragment_program_data *fpd;
135
136 fp->consts = realloc(fp->consts, ++fp->nr_consts *
137 sizeof(*fpd));
138 fpd = &fp->consts[fp->nr_consts - 1];
139 fpd->offset = fpc->inst_offset + 4;
140 fpd->index = src.reg.index;
141 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
142 }
143
144 sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT);
145 break;
146 case NVFXSR_NONE:
147 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
148 break;
149 default:
150 assert(0);
151 }
152
153 if (src.negate)
154 sr |= NVFX_FP_REG_NEGATE;
155
156 if (src.abs)
157 hw[1] |= (1 << (29 + pos));
158
159 sr |= ((src.swz[0] << NVFX_FP_REG_SWZ_X_SHIFT) |
160 (src.swz[1] << NVFX_FP_REG_SWZ_Y_SHIFT) |
161 (src.swz[2] << NVFX_FP_REG_SWZ_Z_SHIFT) |
162 (src.swz[3] << NVFX_FP_REG_SWZ_W_SHIFT));
163
164 hw[pos + 1] |= sr;
165 }
166
167 static void
168 emit_dst(struct nvfx_fpc *fpc, struct nvfx_reg dst)
169 {
170 struct nvfx_fragment_program *fp = fpc->fp;
171 uint32_t *hw = &fp->insn[fpc->inst_offset];
172
173 switch (dst.type) {
174 case NVFXSR_TEMP:
175 if (fpc->num_regs < (dst.index + 1))
176 fpc->num_regs = dst.index + 1;
177 break;
178 case NVFXSR_OUTPUT:
179 if (dst.index == 1) {
180 fp->fp_control |= 0xe;
181 } else {
182 hw[0] |= NVFX_FP_OP_OUT_REG_HALF;
183 }
184 break;
185 case NVFXSR_NONE:
186 hw[0] |= (1 << 30);
187 break;
188 default:
189 assert(0);
190 }
191
192 hw[0] |= (dst.index << NVFX_FP_OP_OUT_REG_SHIFT);
193 }
194
195 static void
196 nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn)
197 {
198 struct nvfx_fragment_program *fp = fpc->fp;
199 uint32_t *hw;
200
201 fpc->inst_offset = fp->insn_len;
202 fpc->have_const = 0;
203 grow_insns(fpc, 4);
204 hw = &fp->insn[fpc->inst_offset];
205 memset(hw, 0, sizeof(uint32_t) * 4);
206
207 if (insn.op == NVFX_FP_OP_OPCODE_KIL)
208 fp->fp_control |= NV30_3D_FP_CONTROL_USES_KIL;
209 hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
210 hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
211 hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
212
213 if (insn.sat)
214 hw[0] |= NVFX_FP_OP_OUT_SAT;
215
216 if (insn.cc_update)
217 hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
218 hw[1] |= (insn.cc_test << NVFX_FP_OP_COND_SHIFT);
219 hw[1] |= ((insn.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
220 (insn.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
221 (insn.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
222 (insn.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
223
224 if(insn.unit >= 0)
225 {
226 hw[0] |= (insn.unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
227 fp->samplers |= (1 << insn.unit);
228 }
229
230 emit_dst(fpc, insn.dst);
231 emit_src(fpc, 0, insn.src[0]);
232 emit_src(fpc, 1, insn.src[1]);
233 emit_src(fpc, 2, insn.src[2]);
234 }
235
236 #define arith(s,o,d,m,s0,s1,s2) \
237 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, -1, \
238 (d), (m), (s0), (s1), (s2))
239
240 #define tex(s,o,u,d,m,s0,s1,s2) \
241 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
242 (d), (m), (s0), none, none)
243
244 /* IF src.x != 0, as TGSI specifies */
245 static void
246 nv40_fp_if(struct nvfx_fpc *fpc, struct nvfx_src src)
247 {
248 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
249 struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none);
250 uint32_t *hw;
251 insn.cc_update = 1;
252 nvfx_fp_emit(fpc, insn);
253
254 fpc->inst_offset = fpc->fp->insn_len;
255 grow_insns(fpc, 4);
256 hw = &fpc->fp->insn[fpc->inst_offset];
257 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
258 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
259 NV40_FP_OP_OUT_NONE |
260 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
261 /* Use .xxxx swizzle so that we check only src[0].x*/
262 hw[1] = (0 << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
263 (0 << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
264 (0 << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
265 (0 << NVFX_FP_OP_COND_SWZ_W_SHIFT) |
266 (NVFX_FP_OP_COND_NE << NVFX_FP_OP_COND_SHIFT);
267 hw[2] = 0; /* | NV40_FP_OP_OPCODE_IS_BRANCH | else_offset */
268 hw[3] = 0; /* | endif_offset */
269 util_dynarray_append(&fpc->if_stack, unsigned, fpc->inst_offset);
270 }
271
272 /* IF src.x != 0, as TGSI specifies */
273 static void
274 nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
275 {
276 struct nvfx_relocation reloc;
277 uint32_t *hw;
278 fpc->inst_offset = fpc->fp->insn_len;
279 grow_insns(fpc, 4);
280 hw = &fpc->fp->insn[fpc->inst_offset];
281 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
282 hw[0] = (NV40_FP_OP_BRA_OPCODE_CAL << NVFX_FP_OP_OPCODE_SHIFT);
283 /* Use .xxxx swizzle so that we check only src[0].x*/
284 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
285 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
286 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
287 hw[3] = 0;
288 reloc.target = target;
289 reloc.location = fpc->inst_offset + 2;
290 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
291 }
292
293 static void
294 nv40_fp_ret(struct nvfx_fpc *fpc)
295 {
296 uint32_t *hw;
297 fpc->inst_offset = fpc->fp->insn_len;
298 grow_insns(fpc, 4);
299 hw = &fpc->fp->insn[fpc->inst_offset];
300 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
301 hw[0] = (NV40_FP_OP_BRA_OPCODE_RET << NVFX_FP_OP_OPCODE_SHIFT);
302 /* Use .xxxx swizzle so that we check only src[0].x*/
303 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
304 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
305 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
306 hw[3] = 0;
307 }
308
309 static void
310 nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
311 {
312 struct nvfx_relocation reloc;
313 uint32_t *hw;
314 fpc->inst_offset = fpc->fp->insn_len;
315 grow_insns(fpc, 4);
316 hw = &fpc->fp->insn[fpc->inst_offset];
317 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
318 hw[0] = (NV40_FP_OP_BRA_OPCODE_REP << NVFX_FP_OP_OPCODE_SHIFT) |
319 NV40_FP_OP_OUT_NONE |
320 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
321 /* Use .xxxx swizzle so that we check only src[0].x*/
322 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
323 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
324 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH |
325 (count << NV40_FP_OP_REP_COUNT1_SHIFT) |
326 (count << NV40_FP_OP_REP_COUNT2_SHIFT) |
327 (count << NV40_FP_OP_REP_COUNT3_SHIFT);
328 hw[3] = 0; /* | end_offset */
329 reloc.target = target;
330 reloc.location = fpc->inst_offset + 3;
331 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
332 //util_dynarray_append(&fpc->loop_stack, unsigned, target);
333 }
334
335 /* warning: this only works forward, and probably only if not inside any IF */
336 static void
337 nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
338 {
339 struct nvfx_relocation reloc;
340 uint32_t *hw;
341 fpc->inst_offset = fpc->fp->insn_len;
342 grow_insns(fpc, 4);
343 hw = &fpc->fp->insn[fpc->inst_offset];
344 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
345 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
346 NV40_FP_OP_OUT_NONE |
347 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
348 /* Use .xxxx swizzle so that we check only src[0].x*/
349 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
350 (NVFX_FP_OP_COND_FL << NVFX_FP_OP_COND_SHIFT);
351 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | else_offset */
352 hw[3] = 0; /* | endif_offset */
353 reloc.target = target;
354 reloc.location = fpc->inst_offset + 2;
355 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
356 reloc.target = target;
357 reloc.location = fpc->inst_offset + 3;
358 util_dynarray_append(&fpc->label_relocs, struct nvfx_relocation, reloc);
359 }
360
361 static void
362 nv40_fp_brk(struct nvfx_fpc *fpc)
363 {
364 uint32_t *hw;
365 fpc->inst_offset = fpc->fp->insn_len;
366 grow_insns(fpc, 4);
367 hw = &fpc->fp->insn[fpc->inst_offset];
368 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
369 hw[0] = (NV40_FP_OP_BRA_OPCODE_BRK << NVFX_FP_OP_OPCODE_SHIFT) |
370 NV40_FP_OP_OUT_NONE;
371 /* Use .xxxx swizzle so that we check only src[0].x*/
372 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
373 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
374 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH;
375 hw[3] = 0;
376 }
377
378 static INLINE struct nvfx_src
379 tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
380 {
381 struct nvfx_src src;
382
383 switch (fsrc->Register.File) {
384 case TGSI_FILE_INPUT:
385 if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
386 assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
387 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
388 } else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
389 if(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0)
390 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
391 else if(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 1)
392 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
393 else
394 assert(0);
395 } else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
396 assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
397 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
398 } else if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
399 /* TODO: check this has the correct values */
400 /* XXX: what do we do for nv30 here (assuming it lacks facing)?! */
401 assert(fpc->pfp->info.input_semantic_index[fsrc->Register.Index] == 0);
402 src.reg = nvfx_reg(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
403 } else {
404 assert(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
405 src.reg = nvfx_reg(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->pfp->info.input_semantic_index[fsrc->Register.Index]]);
406 }
407 break;
408 case TGSI_FILE_CONSTANT:
409 src.reg = nvfx_reg(NVFXSR_CONST, fsrc->Register.Index);
410 break;
411 case TGSI_FILE_IMMEDIATE:
412 assert(fsrc->Register.Index < fpc->nr_imm);
413 src.reg = fpc->r_imm[fsrc->Register.Index];
414 break;
415 case TGSI_FILE_TEMPORARY:
416 src.reg = fpc->r_temp[fsrc->Register.Index];
417 break;
418 /* NV40 fragprog result regs are just temps, so this is simple */
419 case TGSI_FILE_OUTPUT:
420 src.reg = fpc->r_result[fsrc->Register.Index];
421 break;
422 default:
423 NOUVEAU_ERR("bad src file\n");
424 src.reg.index = 0;
425 src.reg.type = 0;
426 break;
427 }
428
429 src.abs = fsrc->Register.Absolute;
430 src.negate = fsrc->Register.Negate;
431 src.swz[0] = fsrc->Register.SwizzleX;
432 src.swz[1] = fsrc->Register.SwizzleY;
433 src.swz[2] = fsrc->Register.SwizzleZ;
434 src.swz[3] = fsrc->Register.SwizzleW;
435 return src;
436 }
437
438 static INLINE struct nvfx_reg
439 tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
440 switch (fdst->Register.File) {
441 case TGSI_FILE_OUTPUT:
442 return fpc->r_result[fdst->Register.Index];
443 case TGSI_FILE_TEMPORARY:
444 return fpc->r_temp[fdst->Register.Index];
445 case TGSI_FILE_NULL:
446 return nvfx_reg(NVFXSR_NONE, 0);
447 default:
448 NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
449 return nvfx_reg(NVFXSR_NONE, 0);
450 }
451 }
452
453 static INLINE int
454 tgsi_mask(uint tgsi)
455 {
456 int mask = 0;
457
458 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_FP_MASK_X;
459 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_FP_MASK_Y;
460 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_FP_MASK_Z;
461 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_FP_MASK_W;
462 return mask;
463 }
464
465 static boolean
466 nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
467 const struct tgsi_full_instruction *finst)
468 {
469 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
470 struct nvfx_insn insn;
471 struct nvfx_src src[3], tmp, tmp2;
472 struct nvfx_reg dst;
473 int mask, sat, unit = 0;
474 int ai = -1, ci = -1, ii = -1;
475 int i;
476
477 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
478 return TRUE;
479
480 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
481 const struct tgsi_full_src_register *fsrc;
482
483 fsrc = &finst->Src[i];
484 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
485 src[i] = tgsi_src(fpc, fsrc);
486 }
487 }
488
489 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
490 const struct tgsi_full_src_register *fsrc;
491
492 fsrc = &finst->Src[i];
493
494 switch (fsrc->Register.File) {
495 case TGSI_FILE_INPUT:
496 if(fpc->pfp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG && (0
497 || fsrc->Register.SwizzleX == PIPE_SWIZZLE_ALPHA
498 || fsrc->Register.SwizzleY == PIPE_SWIZZLE_ALPHA
499 || fsrc->Register.SwizzleZ == PIPE_SWIZZLE_ALPHA
500 || fsrc->Register.SwizzleW == PIPE_SWIZZLE_ALPHA
501 )) {
502 /* hardware puts 0 in fogcoord.w, but GL/Gallium want 1 there */
503 struct nvfx_src addend = nvfx_src(nvfx_fp_imm(fpc, 0, 0, 0, 1));
504 addend.swz[0] = fsrc->Register.SwizzleX;
505 addend.swz[1] = fsrc->Register.SwizzleY;
506 addend.swz[2] = fsrc->Register.SwizzleZ;
507 addend.swz[3] = fsrc->Register.SwizzleW;
508 src[i] = nvfx_src(temp(fpc));
509 nvfx_fp_emit(fpc, arith(0, ADD, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), addend, none));
510 } else if (ai == -1 || ai == fsrc->Register.Index) {
511 ai = fsrc->Register.Index;
512 src[i] = tgsi_src(fpc, fsrc);
513 } else {
514 src[i] = nvfx_src(temp(fpc));
515 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
516 }
517 break;
518 case TGSI_FILE_CONSTANT:
519 if ((ci == -1 && ii == -1) ||
520 ci == fsrc->Register.Index) {
521 ci = fsrc->Register.Index;
522 src[i] = tgsi_src(fpc, fsrc);
523 } else {
524 src[i] = nvfx_src(temp(fpc));
525 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
526 }
527 break;
528 case TGSI_FILE_IMMEDIATE:
529 if ((ci == -1 && ii == -1) ||
530 ii == fsrc->Register.Index) {
531 ii = fsrc->Register.Index;
532 src[i] = tgsi_src(fpc, fsrc);
533 } else {
534 src[i] = nvfx_src(temp(fpc));
535 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
536 }
537 break;
538 case TGSI_FILE_TEMPORARY:
539 /* handled above */
540 break;
541 case TGSI_FILE_SAMPLER:
542 unit = fsrc->Register.Index;
543 break;
544 case TGSI_FILE_OUTPUT:
545 break;
546 default:
547 NOUVEAU_ERR("bad src file\n");
548 return FALSE;
549 }
550 }
551
552 dst = tgsi_dst(fpc, &finst->Dst[0]);
553 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
554 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
555
556 switch (finst->Instruction.Opcode) {
557 case TGSI_OPCODE_ABS:
558 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, abs(src[0]), none, none));
559 break;
560 case TGSI_OPCODE_ADD:
561 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
562 break;
563 case TGSI_OPCODE_CMP:
564 insn = arith(0, MOV, none.reg, mask, src[0], none, none);
565 insn.cc_update = 1;
566 nvfx_fp_emit(fpc, insn);
567
568 insn = arith(sat, MOV, dst, mask, src[2], none, none);
569 insn.cc_test = NVFX_COND_GE;
570 nvfx_fp_emit(fpc, insn);
571
572 insn = arith(sat, MOV, dst, mask, src[1], none, none);
573 insn.cc_test = NVFX_COND_LT;
574 nvfx_fp_emit(fpc, insn);
575 break;
576 case TGSI_OPCODE_COS:
577 nvfx_fp_emit(fpc, arith(sat, COS, dst, mask, src[0], none, none));
578 break;
579 case TGSI_OPCODE_DDX:
580 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
581 tmp = nvfx_src(temp(fpc));
582 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
583 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
584 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
585 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
586 } else {
587 nvfx_fp_emit(fpc, arith(sat, DDX, dst, mask, src[0], none, none));
588 }
589 break;
590 case TGSI_OPCODE_DDY:
591 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
592 tmp = nvfx_src(temp(fpc));
593 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
594 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
595 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
596 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
597 } else {
598 nvfx_fp_emit(fpc, arith(sat, DDY, dst, mask, src[0], none, none));
599 }
600 break;
601 case TGSI_OPCODE_DP2:
602 tmp = nvfx_src(temp(fpc));
603 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], src[1], none));
604 nvfx_fp_emit(fpc, arith(0, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none));
605 break;
606 case TGSI_OPCODE_DP3:
607 nvfx_fp_emit(fpc, arith(sat, DP3, dst, mask, src[0], src[1], none));
608 break;
609 case TGSI_OPCODE_DP4:
610 nvfx_fp_emit(fpc, arith(sat, DP4, dst, mask, src[0], src[1], none));
611 break;
612 case TGSI_OPCODE_DPH:
613 tmp = nvfx_src(temp(fpc));
614 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[1], none));
615 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, swz(tmp, X, X, X, X), swz(src[1], W, W, W, W), none));
616 break;
617 case TGSI_OPCODE_DST:
618 nvfx_fp_emit(fpc, arith(sat, DST, dst, mask, src[0], src[1], none));
619 break;
620 case TGSI_OPCODE_EX2:
621 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, src[0], none, none));
622 break;
623 case TGSI_OPCODE_FLR:
624 nvfx_fp_emit(fpc, arith(sat, FLR, dst, mask, src[0], none, none));
625 break;
626 case TGSI_OPCODE_FRC:
627 nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none));
628 break;
629 case TGSI_OPCODE_KILP:
630 nvfx_fp_emit(fpc, arith(0, KIL, none.reg, 0, none, none, none));
631 break;
632 case TGSI_OPCODE_KIL:
633 insn = arith(0, MOV, none.reg, NVFX_FP_MASK_ALL, src[0], none, none);
634 insn.cc_update = 1;
635 nvfx_fp_emit(fpc, insn);
636
637 insn = arith(0, KIL, none.reg, 0, none, none, none);
638 insn.cc_test = NVFX_COND_LT;
639 nvfx_fp_emit(fpc, insn);
640 break;
641 case TGSI_OPCODE_LG2:
642 nvfx_fp_emit(fpc, arith(sat, LG2, dst, mask, src[0], none, none));
643 break;
644 case TGSI_OPCODE_LIT:
645 if(!nvfx->is_nv4x)
646 nvfx_fp_emit(fpc, arith(sat, LIT_NV30, dst, mask, src[0], src[1], src[2]));
647 else {
648 /* we use FLT_MIN, so that log2 never gives -infinity, and thus multiplication by
649 * specular 0 always gives 0, so that ex2 gives 1, to satisfy the 0^0 = 1 requirement
650 *
651 * NOTE: if we start using half precision, we might need an fp16 FLT_MIN here instead
652 */
653 struct nvfx_src maxs = nvfx_src(nvfx_fp_imm(fpc, 0, FLT_MIN, 0, 0));
654 tmp = nvfx_src(temp(fpc));
655 if (ci>= 0 || ii >= 0) {
656 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, maxs, none, none));
657 maxs = tmp;
658 }
659 nvfx_fp_emit(fpc, arith(0, MAX, tmp.reg, NVFX_FP_MASK_Y | NVFX_FP_MASK_W, swz(src[0], X, X, X, Y), swz(maxs, X, X, Y, Y), none));
660 nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), none, none));
661 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_W, swz(tmp, W, W, W, W), swz(src[0], W, W, W, W), none));
662 nvfx_fp_emit(fpc, arith(sat, LITEX2_NV40, dst, mask, swz(tmp, Y, Y, W, W), none, none));
663 }
664 break;
665 case TGSI_OPCODE_LRP:
666 if(!nvfx->is_nv4x)
667 nvfx_fp_emit(fpc, arith(sat, LRP_NV30, dst, mask, src[0], src[1], src[2]));
668 else {
669 tmp = nvfx_src(temp(fpc));
670 nvfx_fp_emit(fpc, arith(0, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
671 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], tmp));
672 }
673 break;
674 case TGSI_OPCODE_MAD:
675 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], src[2]));
676 break;
677 case TGSI_OPCODE_MAX:
678 nvfx_fp_emit(fpc, arith(sat, MAX, dst, mask, src[0], src[1], none));
679 break;
680 case TGSI_OPCODE_MIN:
681 nvfx_fp_emit(fpc, arith(sat, MIN, dst, mask, src[0], src[1], none));
682 break;
683 case TGSI_OPCODE_MOV:
684 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, src[0], none, none));
685 break;
686 case TGSI_OPCODE_MUL:
687 nvfx_fp_emit(fpc, arith(sat, MUL, dst, mask, src[0], src[1], none));
688 break;
689 case TGSI_OPCODE_NOP:
690 break;
691 case TGSI_OPCODE_POW:
692 if(!nvfx->is_nv4x)
693 nvfx_fp_emit(fpc, arith(sat, POW_NV30, dst, mask, src[0], src[1], none));
694 else {
695 tmp = nvfx_src(temp(fpc));
696 nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
697 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
698 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, swz(tmp, X, X, X, X), none, none));
699 }
700 break;
701 case TGSI_OPCODE_RCP:
702 nvfx_fp_emit(fpc, arith(sat, RCP, dst, mask, src[0], none, none));
703 break;
704 case TGSI_OPCODE_RFL:
705 if(!nvfx->is_nv4x)
706 nvfx_fp_emit(fpc, arith(0, RFL_NV30, dst, mask, src[0], src[1], none));
707 else {
708 tmp = nvfx_src(temp(fpc));
709 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[0], none));
710 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_Y, src[0], src[1], none));
711 insn = arith(0, DIV, tmp.reg, NVFX_FP_MASK_Z, swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
712 insn.scale = NVFX_FP_OP_DST_SCALE_2X;
713 nvfx_fp_emit(fpc, insn);
714 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, swz(tmp, Z, Z, Z, Z), src[0], neg(src[1])));
715 }
716 break;
717 case TGSI_OPCODE_RSQ:
718 if(!nvfx->is_nv4x)
719 nvfx_fp_emit(fpc, arith(sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none));
720 else {
721 tmp = nvfx_src(temp(fpc));
722 insn = arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, abs(swz(src[0], X, X, X, X)), none, none);
723 insn.scale = NVFX_FP_OP_DST_SCALE_INV_2X;
724 nvfx_fp_emit(fpc, insn);
725 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, neg(swz(tmp, X, X, X, X)), none, none));
726 }
727 break;
728 case TGSI_OPCODE_SCS:
729 /* avoid overwriting the source */
730 if(src[0].swz[NVFX_SWZ_X] != NVFX_SWZ_X)
731 {
732 if (mask & NVFX_FP_MASK_X)
733 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
734 if (mask & NVFX_FP_MASK_Y)
735 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
736 }
737 else
738 {
739 if (mask & NVFX_FP_MASK_Y)
740 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
741 if (mask & NVFX_FP_MASK_X)
742 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
743 }
744 break;
745 case TGSI_OPCODE_SEQ:
746 nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
747 break;
748 case TGSI_OPCODE_SFL:
749 nvfx_fp_emit(fpc, arith(sat, SFL, dst, mask, src[0], src[1], none));
750 break;
751 case TGSI_OPCODE_SGE:
752 nvfx_fp_emit(fpc, arith(sat, SGE, dst, mask, src[0], src[1], none));
753 break;
754 case TGSI_OPCODE_SGT:
755 nvfx_fp_emit(fpc, arith(sat, SGT, dst, mask, src[0], src[1], none));
756 break;
757 case TGSI_OPCODE_SIN:
758 nvfx_fp_emit(fpc, arith(sat, SIN, dst, mask, src[0], none, none));
759 break;
760 case TGSI_OPCODE_SLE:
761 nvfx_fp_emit(fpc, arith(sat, SLE, dst, mask, src[0], src[1], none));
762 break;
763 case TGSI_OPCODE_SLT:
764 nvfx_fp_emit(fpc, arith(sat, SLT, dst, mask, src[0], src[1], none));
765 break;
766 case TGSI_OPCODE_SNE:
767 nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none));
768 break;
769 case TGSI_OPCODE_SSG:
770 {
771 struct nvfx_src minones = swz(nvfx_src(nvfx_fp_imm(fpc, -1, -1, -1, -1)), X, X, X, X);
772
773 insn = arith(sat, MOV, dst, mask, src[0], none, none);
774 insn.cc_update = 1;
775 nvfx_fp_emit(fpc, insn);
776
777 insn = arith(0, STR, dst, mask, none, none, none);
778 insn.cc_test = NVFX_COND_GT;
779 nvfx_fp_emit(fpc, insn);
780
781 if(!sat) {
782 insn = arith(0, MOV, dst, mask, minones, none, none);
783 insn.cc_test = NVFX_COND_LT;
784 nvfx_fp_emit(fpc, insn);
785 }
786 break;
787 }
788 case TGSI_OPCODE_STR:
789 nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
790 break;
791 case TGSI_OPCODE_SUB:
792 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
793 break;
794 case TGSI_OPCODE_TEX:
795 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
796 break;
797 case TGSI_OPCODE_TRUNC:
798 tmp = nvfx_src(temp(fpc));
799 insn = arith(0, MOV, none.reg, mask, src[0], none, none);
800 insn.cc_update = 1;
801 nvfx_fp_emit(fpc, insn);
802
803 nvfx_fp_emit(fpc, arith(0, FLR, tmp.reg, mask, abs(src[0]), none, none));
804 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, tmp, none, none));
805
806 insn = arith(sat, MOV, dst, mask, neg(tmp), none, none);
807 insn.cc_test = NVFX_COND_LT;
808 nvfx_fp_emit(fpc, insn);
809 break;
810 case TGSI_OPCODE_TXB:
811 nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
812 break;
813 case TGSI_OPCODE_TXL:
814 if(nvfx->is_nv4x)
815 nvfx_fp_emit(fpc, tex(sat, TXL_NV40, unit, dst, mask, src[0], none, none));
816 else /* unsupported on nv30, use TEX and hope they like it */
817 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
818 break;
819 case TGSI_OPCODE_TXP:
820 nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
821 break;
822 case TGSI_OPCODE_XPD:
823 tmp = nvfx_src(temp(fpc));
824 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
825 nvfx_fp_emit(fpc, arith(sat, MAD, dst, (mask & ~NVFX_FP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
826 break;
827
828 case TGSI_OPCODE_IF:
829 // MOVRC0 R31 (TR0.xyzw), R<src>:
830 // IF (NE.xxxx) ELSE <else> END <end>
831 if(!nvfx->is_nv4x)
832 goto nv3x_cflow;
833 nv40_fp_if(fpc, src[0]);
834 break;
835
836 case TGSI_OPCODE_ELSE:
837 {
838 uint32_t *hw;
839 if(!nvfx->is_nv4x)
840 goto nv3x_cflow;
841 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
842 hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
843 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
844 break;
845 }
846
847 case TGSI_OPCODE_ENDIF:
848 {
849 uint32_t *hw;
850 if(!nvfx->is_nv4x)
851 goto nv3x_cflow;
852 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
853 hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
854 if(!hw[2])
855 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
856 hw[3] = fpc->fp->insn_len;
857 break;
858 }
859
860 case TGSI_OPCODE_BRA:
861 /* This can in limited cases be implemented with an IF with the else and endif labels pointing to the target */
862 /* no state tracker uses this, so don't implement this for now */
863 assert(0);
864 nv40_fp_bra(fpc, finst->Label.Label);
865 break;
866
867 case TGSI_OPCODE_BGNSUB:
868 case TGSI_OPCODE_ENDSUB:
869 /* nothing to do here */
870 break;
871
872 case TGSI_OPCODE_CAL:
873 if(!nvfx->is_nv4x)
874 goto nv3x_cflow;
875 nv40_fp_cal(fpc, finst->Label.Label);
876 break;
877
878 case TGSI_OPCODE_RET:
879 if(!nvfx->is_nv4x)
880 goto nv3x_cflow;
881 nv40_fp_ret(fpc);
882 break;
883
884 case TGSI_OPCODE_BGNLOOP:
885 if(!nvfx->is_nv4x)
886 goto nv3x_cflow;
887 /* TODO: we should support using two nested REPs to allow a > 255 iteration count */
888 nv40_fp_rep(fpc, 255, finst->Label.Label);
889 break;
890
891 case TGSI_OPCODE_ENDLOOP:
892 break;
893
894 case TGSI_OPCODE_BRK:
895 if(!nvfx->is_nv4x)
896 goto nv3x_cflow;
897 nv40_fp_brk(fpc);
898 break;
899
900 case TGSI_OPCODE_CONT:
901 {
902 static int warned = 0;
903 if(!warned) {
904 NOUVEAU_ERR("Sorry, the continue keyword is not implemented: ignoring it.\n");
905 warned = 1;
906 }
907 break;
908 }
909
910 default:
911 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
912 return FALSE;
913 }
914
915 out:
916 release_temps(fpc);
917 return TRUE;
918 nv3x_cflow:
919 {
920 static int warned = 0;
921 if(!warned) {
922 NOUVEAU_ERR(
923 "Sorry, control flow instructions are not supported in hardware on nv3x: ignoring them\n"
924 "If rendering is incorrect, try to disable GLSL support in the application.\n");
925 warned = 1;
926 }
927 }
928 goto out;
929 }
930
931 static boolean
932 nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
933 const struct tgsi_full_declaration *fdec)
934 {
935 unsigned idx = fdec->Range.First;
936 unsigned hw;
937
938 switch (fdec->Semantic.Name) {
939 case TGSI_SEMANTIC_POSITION:
940 hw = 1;
941 break;
942 case TGSI_SEMANTIC_COLOR:
943 hw = ~0;
944 switch (fdec->Semantic.Index) {
945 case 0: hw = 0; break;
946 case 1: hw = 2; break;
947 case 2: hw = 3; break;
948 case 3: hw = 4; break;
949 }
950 if(hw > ((nvfx->is_nv4x) ? 4 : 2)) {
951 NOUVEAU_ERR("bad rcol index\n");
952 return FALSE;
953 }
954 break;
955 default:
956 NOUVEAU_ERR("bad output semantic\n");
957 return FALSE;
958 }
959
960 fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
961 fpc->r_temps |= (1ULL << hw);
962 return TRUE;
963 }
964
965 static boolean
966 nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
967 {
968 struct tgsi_parse_context p;
969 int high_temp = -1, i;
970 struct util_semantic_set set;
971 unsigned num_texcoords = nvfx->is_nv4x ? 10 : 8;
972
973 fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->pfp->pipe.tokens, TGSI_FILE_INPUT);
974 if(fpc->fp->num_slots > num_texcoords)
975 return FALSE;
976 util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, num_texcoords);
977 util_semantic_table_from_layout(fpc->generic_to_slot, fpc->fp->slot_to_generic, 0, num_texcoords);
978
979 memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input));
980
981 fpc->r_imm = CALLOC(fpc->pfp->info.immediate_count, sizeof(struct nvfx_reg));
982
983 tgsi_parse_init(&p, fpc->pfp->pipe.tokens);
984 while (!tgsi_parse_end_of_tokens(&p)) {
985 const union tgsi_full_token *tok = &p.FullToken;
986
987 tgsi_parse_token(&p);
988 switch(tok->Token.Type) {
989 case TGSI_TOKEN_TYPE_DECLARATION:
990 {
991 const struct tgsi_full_declaration *fdec;
992 fdec = &p.FullToken.FullDeclaration;
993 switch (fdec->Declaration.File) {
994 case TGSI_FILE_OUTPUT:
995 if (!nvfx_fragprog_parse_decl_output(nvfx, fpc, fdec))
996 goto out_err;
997 break;
998 case TGSI_FILE_TEMPORARY:
999 if (fdec->Range.Last > high_temp) {
1000 high_temp =
1001 fdec->Range.Last;
1002 }
1003 break;
1004 default:
1005 break;
1006 }
1007 }
1008 break;
1009 case TGSI_TOKEN_TYPE_IMMEDIATE:
1010 {
1011 struct tgsi_full_immediate *imm;
1012
1013 imm = &p.FullToken.FullImmediate;
1014 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
1015 assert(fpc->nr_imm < fpc->pfp->info.immediate_count);
1016
1017 fpc->r_imm[fpc->nr_imm++] = nvfx_fp_imm(fpc, imm->u[0].Float, imm->u[1].Float, imm->u[2].Float, imm->u[3].Float);
1018 break;
1019 }
1020 default:
1021 break;
1022 }
1023 }
1024 tgsi_parse_free(&p);
1025
1026 if (++high_temp) {
1027 fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
1028 for (i = 0; i < high_temp; i++)
1029 fpc->r_temp[i] = temp(fpc);
1030 fpc->r_temps_discard = 0ULL;
1031 }
1032
1033 return TRUE;
1034
1035 out_err:
1036 if (fpc->r_temp) {
1037 FREE(fpc->r_temp);
1038 fpc->r_temp = NULL;
1039 }
1040 tgsi_parse_free(&p);
1041 return FALSE;
1042 }
1043
1044 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE)
1045
1046 static struct nvfx_fragment_program*
1047 nvfx_fragprog_translate(struct nvfx_context *nvfx,
1048 struct nvfx_pipe_fragment_program *pfp,
1049 boolean emulate_sprite_flipping)
1050 {
1051 struct tgsi_parse_context parse;
1052 struct nvfx_fpc *fpc = NULL;
1053 struct util_dynarray insns;
1054 struct nvfx_fragment_program* fp = NULL;
1055 const int min_size = 4096;
1056
1057 fp = CALLOC_STRUCT(nvfx_fragment_program);
1058 if(!fp)
1059 goto out_err;
1060
1061 fpc = CALLOC_STRUCT(nvfx_fpc);
1062 if (!fpc)
1063 goto out_err;
1064
1065 fpc->max_temps = nvfx->is_nv4x ? 48 : 32;
1066 fpc->pfp = pfp;
1067 fpc->fp = fp;
1068 fpc->num_regs = 2;
1069
1070 for (unsigned i = 0; i < pfp->info.num_properties; ++i) {
1071 if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_ORIGIN) {
1072 if(pfp->info.properties[i].data[0])
1073 fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_ORIGIN_INVERTED;
1074 } else if (pfp->info.properties[i].name == TGSI_PROPERTY_FS_COORD_PIXEL_CENTER) {
1075 if(pfp->info.properties[i].data[0])
1076 fp->coord_conventions |= NV30_3D_COORD_CONVENTIONS_CENTER_INTEGER;
1077 }
1078 }
1079
1080 if (!nvfx_fragprog_prepare(nvfx, fpc))
1081 goto out_err;
1082
1083 tgsi_parse_init(&parse, pfp->pipe.tokens);
1084 util_dynarray_init(&insns);
1085
1086 if(emulate_sprite_flipping)
1087 {
1088 struct nvfx_reg reg = temp(fpc);
1089 struct nvfx_src sprite_input = nvfx_src(nvfx_reg(NVFXSR_RELOCATED, fp->num_slots));
1090 struct nvfx_src imm = nvfx_src(nvfx_fp_imm(fpc, 1, -1, 0, 0));
1091
1092 fpc->sprite_coord_temp = reg.index;
1093 fpc->r_temps_discard = 0ULL;
1094 nvfx_fp_emit(fpc, arith(0, MAD, reg, NVFX_FP_MASK_ALL, sprite_input, swz(imm, X, Y, X, X), swz(imm, Z, X, Z, Z)));
1095 }
1096
1097 while (!tgsi_parse_end_of_tokens(&parse)) {
1098 tgsi_parse_token(&parse);
1099
1100 switch (parse.FullToken.Token.Type) {
1101 case TGSI_TOKEN_TYPE_INSTRUCTION:
1102 {
1103 const struct tgsi_full_instruction *finst;
1104
1105 util_dynarray_append(&insns, unsigned, fp->insn_len);
1106 finst = &parse.FullToken.FullInstruction;
1107 if (!nvfx_fragprog_parse_instruction(nvfx, fpc, finst))
1108 goto out_err;
1109 }
1110 break;
1111 default:
1112 break;
1113 }
1114 }
1115 util_dynarray_append(&insns, unsigned, fp->insn_len);
1116
1117 for(unsigned i = 0; i < fpc->label_relocs.size; i += sizeof(struct nvfx_relocation))
1118 {
1119 struct nvfx_relocation* label_reloc = (struct nvfx_relocation*)((char*)fpc->label_relocs.data + i);
1120 fp->insn[label_reloc->location] |= ((unsigned*)insns.data)[label_reloc->target];
1121 }
1122 util_dynarray_fini(&insns);
1123
1124 if(!nvfx->is_nv4x)
1125 fp->fp_control |= (fpc->num_regs-1)/2;
1126 else
1127 fp->fp_control |= fpc->num_regs << NV40_3D_FP_CONTROL_TEMP_COUNT__SHIFT;
1128
1129 /* Terminate final instruction */
1130 if(fp->insn)
1131 fp->insn[fpc->inst_offset] |= 0x00000001;
1132
1133 /* Append NOP + END instruction for branches to the end of the program */
1134 fpc->inst_offset = fp->insn_len;
1135 grow_insns(fpc, 4);
1136 fp->insn[fpc->inst_offset + 0] = 0x00000001;
1137 fp->insn[fpc->inst_offset + 1] = 0x00000000;
1138 fp->insn[fpc->inst_offset + 2] = 0x00000000;
1139 fp->insn[fpc->inst_offset + 3] = 0x00000000;
1140
1141 if(debug_get_option_nvfx_dump_fp())
1142 {
1143 debug_printf("\n");
1144 tgsi_dump(pfp->pipe.tokens, 0);
1145
1146 debug_printf("\n%s fragment program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
1147 for (unsigned i = 0; i < fp->insn_len; i += 4)
1148 debug_printf("%3u: %08x %08x %08x %08x\n", i >> 2, fp->insn[i], fp->insn[i + 1], fp->insn[i + 2], fp->insn[i + 3]);
1149 debug_printf("\n");
1150 }
1151
1152 fp->prog_size = (fp->insn_len * 4 + 63) & ~63;
1153
1154 if(fp->prog_size >= min_size)
1155 fp->progs_per_bo = 1;
1156 else
1157 fp->progs_per_bo = min_size / fp->prog_size;
1158 fp->bo_prog_idx = fp->progs_per_bo - 1;
1159
1160 out:
1161 tgsi_parse_free(&parse);
1162 if(fpc)
1163 {
1164 if (fpc->r_temp)
1165 FREE(fpc->r_temp);
1166 util_dynarray_fini(&fpc->if_stack);
1167 util_dynarray_fini(&fpc->label_relocs);
1168 util_dynarray_fini(&fpc->imm_data);
1169 //util_dynarray_fini(&fpc->loop_stack);
1170 FREE(fpc);
1171 }
1172 return fp;
1173
1174 out_err:
1175 _debug_printf("Error: failed to compile this fragment program:\n");
1176 tgsi_dump(pfp->pipe.tokens, 0);
1177
1178 if(fp)
1179 {
1180 FREE(fp);
1181 fp = NULL;
1182 }
1183 goto out;
1184 }
1185
1186 static inline void
1187 nvfx_fp_memcpy(void* dst, const void* src, size_t len)
1188 {
1189 #ifndef WORDS_BIGENDIAN
1190 memcpy(dst, src, len);
1191 #else
1192 size_t i;
1193 for(i = 0; i < len; i += 4) {
1194 uint32_t v = (uint32_t*)((char*)src + i);
1195 *(uint32_t*)((char*)dst + i) = (v >> 16) | (v << 16);
1196 }
1197 #endif
1198 }
1199
1200 /* The hardware only supports immediate constants inside the fragment program,
1201 * and at least on nv30 doesn't support an indirect linkage table.
1202 *
1203 * Hence, we need to patch the fragment program itself both to update constants
1204 * and update linkage.
1205 *
1206 * Using a single fragment program would entail unacceptable stalls if the GPU is
1207 * already rendering with that fragment program.
1208 * Thus, we instead use a "rotating queue" of buffer objects, each of which is
1209 * packed with multiple versions of the same program.
1210 *
1211 * Whenever we need to patch something, we move to the next program and
1212 * patch it. If all buffer objects are in use by the GPU, we allocate another one,
1213 * expanding the queue.
1214 *
1215 * As an additional optimization, we record when all the programs have the
1216 * current input slot configuration, and at that point we stop patching inputs.
1217 * This happens, for instance, if a given fragment program is always used with
1218 * the same vertex program (i.e. always with GLSL), or if the layouts match
1219 * enough (non-GLSL).
1220 *
1221 * Note that instead of using multiple programs, we could push commands
1222 * on the FIFO to patch a single program: it's not fully clear which option is
1223 * faster, but my guess is that the current way is faster.
1224 *
1225 * We also track the previous slot assignments for each version and don't
1226 * patch if they are the same (this could perhaps be removed).
1227 */
1228
1229 void
1230 nvfx_fragprog_validate(struct nvfx_context *nvfx)
1231 {
1232 struct nouveau_channel* chan = nvfx->screen->base.channel;
1233 struct nvfx_pipe_fragment_program *pfp = nvfx->fragprog;
1234 struct nvfx_vertex_program* vp;
1235 /* Gallium always puts the point coord in GENERIC[0]
1236 * TODO: this is wrong, Gallium needs to be fixed
1237 */
1238 unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * (nvfx->rasterizer->pipe.sprite_coord_enable | 1);
1239
1240 boolean emulate_sprite_flipping = sprite_coord_enable && nvfx->rasterizer->pipe.sprite_coord_mode;
1241 unsigned key = emulate_sprite_flipping;
1242 struct nvfx_fragment_program* fp;
1243
1244 fp = pfp->fps[key];
1245 if (!fp)
1246 {
1247 fp = nvfx_fragprog_translate(nvfx, pfp, emulate_sprite_flipping);
1248
1249 if(!fp)
1250 {
1251 if(!nvfx->dummy_fs)
1252 {
1253 struct ureg_program *ureg = ureg_create( TGSI_PROCESSOR_FRAGMENT );
1254 if (ureg)
1255 {
1256 ureg_END( ureg );
1257 nvfx->dummy_fs = ureg_create_shader_and_destroy( ureg, &nvfx->pipe );
1258 }
1259
1260 if(!nvfx->dummy_fs)
1261 {
1262 _debug_printf("Error: unable to create a dummy fragment shader: aborting.");
1263 abort();
1264 }
1265 }
1266
1267 fp = nvfx_fragprog_translate(nvfx, nvfx->dummy_fs, FALSE);
1268 emulate_sprite_flipping = FALSE;
1269
1270 if(!fp)
1271 {
1272 _debug_printf("Error: unable to compile even a dummy fragment shader: aborting.");
1273 abort();
1274 }
1275 }
1276
1277 pfp->fps[key] = fp;
1278 }
1279
1280 vp = nvfx->hw_vertprog;
1281
1282 if (fp->last_vp_id != vp->id || fp->last_sprite_coord_enable != sprite_coord_enable) {
1283 int sprite_real_input = -1;
1284 int sprite_reloc_input;
1285 unsigned i;
1286 fp->last_vp_id = vp->id;
1287 fp->last_sprite_coord_enable = sprite_coord_enable;
1288
1289 if(sprite_coord_enable)
1290 {
1291 sprite_real_input = vp->sprite_fp_input;
1292 if(sprite_real_input < 0)
1293 {
1294 unsigned used_texcoords = 0;
1295 for(unsigned i = 0; i < fp->num_slots; ++i) {
1296 unsigned generic = fp->slot_to_generic[i];
1297 if(!((1 << generic) & sprite_coord_enable))
1298 {
1299 unsigned char slot_mask = vp->generic_to_fp_input[generic];
1300 if(slot_mask >= 0xf0)
1301 used_texcoords |= 1 << ((slot_mask & 0xf) - NVFX_FP_OP_INPUT_SRC_TC0);
1302 }
1303 }
1304
1305 sprite_real_input = NVFX_FP_OP_INPUT_SRC_TC(__builtin_ctz(~used_texcoords));
1306 }
1307
1308 fp->point_sprite_control |= (1 << (sprite_real_input - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
1309 }
1310 else
1311 fp->point_sprite_control = 0;
1312
1313 if(emulate_sprite_flipping)
1314 sprite_reloc_input = 0;
1315 else
1316 sprite_reloc_input = sprite_real_input;
1317
1318 for(i = 0; i < fp->num_slots; ++i) {
1319 unsigned generic = fp->slot_to_generic[i];
1320 if((1 << generic) & sprite_coord_enable)
1321 {
1322 if(fp->slot_to_fp_input[i] != sprite_reloc_input)
1323 goto update_slots;
1324 }
1325 else
1326 {
1327 unsigned char slot_mask = vp->generic_to_fp_input[generic];
1328 if((slot_mask >> 4) & (slot_mask ^ fp->slot_to_fp_input[i]))
1329 goto update_slots;
1330 }
1331 }
1332
1333 if(emulate_sprite_flipping)
1334 {
1335 if(fp->slot_to_fp_input[fp->num_slots] != sprite_real_input)
1336 goto update_slots;
1337 }
1338
1339 if(0)
1340 {
1341 update_slots:
1342 /* optimization: we start updating from the slot we found the first difference in */
1343 for(; i < fp->num_slots; ++i)
1344 {
1345 unsigned generic = fp->slot_to_generic[i];
1346 if((1 << generic) & sprite_coord_enable)
1347 fp->slot_to_fp_input[i] = sprite_reloc_input;
1348 else
1349 fp->slot_to_fp_input[i] = vp->generic_to_fp_input[generic] & 0xf;
1350 }
1351
1352 fp->slot_to_fp_input[fp->num_slots] = sprite_real_input;
1353
1354 if(nvfx->is_nv4x)
1355 {
1356 fp->or = 0;
1357 for(i = 0; i <= fp->num_slots; ++i) {
1358 unsigned fp_input = fp->slot_to_fp_input[i];
1359 if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(8))
1360 fp->or |= (1 << 12);
1361 else if(fp_input == NVFX_FP_OP_INPUT_SRC_TC(9))
1362 fp->or |= (1 << 13);
1363 else if(fp_input >= NVFX_FP_OP_INPUT_SRC_TC(0) && fp_input <= NVFX_FP_OP_INPUT_SRC_TC(7))
1364 fp->or |= (1 << (fp_input - NVFX_FP_OP_INPUT_SRC_TC0 + 14));
1365 }
1366 }
1367
1368 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
1369 goto update;
1370 }
1371 }
1372
1373 /* We must update constants even on "just" fragprog changes, because
1374 * we don't check whether the current constant buffer matches the latest
1375 * one bound to this fragment program.
1376 * Doing such a check would likely be a pessimization.
1377 */
1378 if ((nvfx->hw_fragprog != fp) || (nvfx->dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_FRAGCONST))) {
1379 int offset;
1380 uint32_t* fpmap;
1381
1382 update:
1383 ++fp->bo_prog_idx;
1384 if(fp->bo_prog_idx >= fp->progs_per_bo)
1385 {
1386 if(fp->fpbo && !nouveau_bo_busy(fp->fpbo->next->bo, NOUVEAU_BO_WR))
1387 {
1388 fp->fpbo = fp->fpbo->next;
1389 }
1390 else
1391 {
1392 struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + (fp->prog_size + 8) * fp->progs_per_bo, 16);
1393 uint8_t* map;
1394 uint8_t* buf;
1395
1396 fpbo->slots = (unsigned char*)&fpbo->insn[(fp->prog_size) * fp->progs_per_bo];
1397 memset(fpbo->slots, 0, 8 * fp->progs_per_bo);
1398 if(fp->fpbo)
1399 {
1400 fpbo->next = fp->fpbo->next;
1401 fp->fpbo->next = fpbo;
1402 }
1403 else
1404 fpbo->next = fpbo;
1405 fp->fpbo = fpbo;
1406 fpbo->bo = 0;
1407 fp->progs += fp->progs_per_bo;
1408 fp->progs_left_with_obsolete_slot_assignments += fp->progs_per_bo;
1409 nouveau_bo_new(nvfx->screen->base.device, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, 64, fp->prog_size * fp->progs_per_bo, &fpbo->bo);
1410 nouveau_bo_map(fpbo->bo, NOUVEAU_BO_NOSYNC);
1411
1412 map = fpbo->bo->map;
1413 buf = (uint8_t*)fpbo->insn;
1414 for(unsigned i = 0; i < fp->progs_per_bo; ++i)
1415 {
1416 memcpy(buf, fp->insn, fp->insn_len * 4);
1417 nvfx_fp_memcpy(map, fp->insn, fp->insn_len * 4);
1418 map += fp->prog_size;
1419 buf += fp->prog_size;
1420 }
1421 }
1422 fp->bo_prog_idx = 0;
1423 }
1424
1425 offset = fp->bo_prog_idx * fp->prog_size;
1426 fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1427
1428 if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) {
1429 struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT];
1430 uint32_t* map = (uint32_t*)nvfx_buffer(constbuf)->data;
1431 uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1432 uint32_t* buf = (uint32_t*)((char*)fp->fpbo->insn + offset);
1433 int i;
1434 for (i = 0; i < fp->nr_consts; ++i) {
1435 unsigned off = fp->consts[i].offset;
1436 unsigned idx = fp->consts[i].index * 4;
1437
1438 /* TODO: is checking a good idea? */
1439 if(memcmp(&buf[off], &map[idx], 4 * sizeof(uint32_t))) {
1440 memcpy(&buf[off], &map[idx], 4 * sizeof(uint32_t));
1441 nvfx_fp_memcpy(&fpmap[off], &map[idx], 4 * sizeof(uint32_t));
1442 }
1443 }
1444 }
1445
1446 /* we only do this if we aren't sure that all program versions have the
1447 * current slot assignments, otherwise we just update constants for speed
1448 */
1449 if(fp->progs_left_with_obsolete_slot_assignments) {
1450 unsigned char* fpbo_slots = &fp->fpbo->slots[fp->bo_prog_idx * 8];
1451 /* also relocate sprite coord slot, if any */
1452 for(unsigned i = 0; i <= fp->num_slots; ++i) {
1453 unsigned value = fp->slot_to_fp_input[i];;
1454 if(value != fpbo_slots[i]) {
1455 unsigned* p;
1456 unsigned* begin = (unsigned*)fp->slot_relocations[i].data;
1457 unsigned* end = (unsigned*)((char*)fp->slot_relocations[i].data + fp->slot_relocations[i].size);
1458 //printf("fp %p reloc slot %u/%u: %u -> %u\n", fp, i, fp->num_slots, fpbo_slots[i], value);
1459 if(value == 0)
1460 {
1461 /* was relocated to an input, switch type to temporary */
1462 for(p = begin; p != end; ++p) {
1463 unsigned off = *p;
1464 unsigned dw = fp->insn[off];
1465 dw &=~ NVFX_FP_REG_TYPE_MASK;
1466 //printf("reloc_tmp at %x\n", off);
1467 nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
1468 }
1469 } else {
1470 if(!fpbo_slots[i])
1471 {
1472 /* was relocated to a temporary, switch type to input */
1473 for(p= begin; p != end; ++p) {
1474 unsigned off = *p;
1475 unsigned dw = fp->insn[off];
1476 //printf("reloc_in at %x\n", off);
1477 dw |= NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT;
1478 nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
1479 }
1480 }
1481
1482 /* set the correct input index */
1483 for(p = begin; p != end; ++p) {
1484 unsigned off = *p & ~3;
1485 unsigned dw = fp->insn[off];
1486 //printf("reloc&~3 at %x\n", off);
1487 dw = (dw & ~NVFX_FP_OP_INPUT_SRC_MASK) | (value << NVFX_FP_OP_INPUT_SRC_SHIFT);
1488 nvfx_fp_memcpy(&fpmap[off], &dw, sizeof(dw));
1489 }
1490 }
1491 fpbo_slots[i] = value;
1492 }
1493 }
1494 --fp->progs_left_with_obsolete_slot_assignments;
1495 }
1496
1497 nvfx->hw_fragprog = fp;
1498
1499 MARK_RING(chan, 8, 1);
1500 OUT_RING(chan, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1));
1501 OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
1502 NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
1503 NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
1504 NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
1505 OUT_RING(chan, RING_3D(NV30_3D_FP_CONTROL, 1));
1506 OUT_RING(chan, fp->fp_control);
1507 if(!nvfx->is_nv4x) {
1508 OUT_RING(chan, RING_3D(NV30_3D_FP_REG_CONTROL, 1));
1509 OUT_RING(chan, (1<<16)|0x4);
1510 OUT_RING(chan, RING_3D(NV30_3D_TEX_UNITS_ENABLE, 1));
1511 OUT_RING(chan, fp->samplers);
1512 }
1513 }
1514
1515 {
1516 unsigned pointsprite_control = fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization;
1517 if(pointsprite_control != nvfx->hw_pointsprite_control)
1518 {
1519 WAIT_RING(chan, 2);
1520 OUT_RING(chan, RING_3D(NV30_3D_POINT_SPRITE, 1));
1521 OUT_RING(chan, pointsprite_control);
1522 nvfx->hw_pointsprite_control = pointsprite_control;
1523 }
1524 }
1525
1526 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
1527 }
1528
1529 void
1530 nvfx_fragprog_relocate(struct nvfx_context *nvfx)
1531 {
1532 struct nouveau_channel* chan = nvfx->screen->base.channel;
1533 struct nvfx_fragment_program *fp = nvfx->hw_fragprog;
1534 struct nouveau_bo* bo = fp->fpbo->bo;
1535 int offset = fp->bo_prog_idx * fp->prog_size;
1536 unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART?
1537 fp_flags |= NOUVEAU_BO_DUMMY;
1538 MARK_RING(chan, 2, 2);
1539 OUT_RELOC(chan, bo, RING_3D(NV30_3D_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
1540 OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW |
1541 NOUVEAU_BO_OR, NV30_3D_FP_ACTIVE_PROGRAM_DMA0,
1542 NV30_3D_FP_ACTIVE_PROGRAM_DMA1);
1543 nvfx->relocs_needed &=~ NVFX_RELOCATE_FRAGPROG;
1544 }
1545
1546 void
1547 nvfx_fragprog_destroy(struct nvfx_context *nvfx,
1548 struct nvfx_fragment_program *fp)
1549 {
1550 unsigned i;
1551 struct nvfx_fragment_program_bo* fpbo = fp->fpbo;
1552 if(fpbo)
1553 {
1554 do
1555 {
1556 struct nvfx_fragment_program_bo* next = fpbo->next;
1557 nouveau_bo_unmap(fpbo->bo);
1558 nouveau_bo_ref(0, &fpbo->bo);
1559 free(fpbo);
1560 fpbo = next;
1561 }
1562 while(fpbo != fp->fpbo);
1563 }
1564
1565 for(i = 0; i < Elements(fp->slot_relocations); ++i)
1566 util_dynarray_fini(&fp->slot_relocations[i]);
1567
1568 if (fp->insn_len)
1569 FREE(fp->insn);
1570 }
1571
1572 static void *
1573 nvfx_fp_state_create(struct pipe_context *pipe,
1574 const struct pipe_shader_state *cso)
1575 {
1576 struct nvfx_pipe_fragment_program *pfp;
1577
1578 pfp = CALLOC(1, sizeof(struct nvfx_pipe_fragment_program));
1579 pfp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
1580
1581 tgsi_scan_shader(pfp->pipe.tokens, &pfp->info);
1582
1583 return (void *)pfp;
1584 }
1585
1586 static void
1587 nvfx_fp_state_bind(struct pipe_context *pipe, void *hwcso)
1588 {
1589 struct nvfx_context *nvfx = nvfx_context(pipe);
1590
1591 nvfx->fragprog = hwcso;
1592 nvfx->dirty |= NVFX_NEW_FRAGPROG;
1593 }
1594
1595 static void
1596 nvfx_fp_state_delete(struct pipe_context *pipe, void *hwcso)
1597 {
1598 struct nvfx_context *nvfx = nvfx_context(pipe);
1599 struct nvfx_pipe_fragment_program *pfp = hwcso;
1600 unsigned i;
1601
1602 for(i = 0; i < Elements(pfp->fps); ++i)
1603 {
1604 if(pfp->fps[i])
1605 {
1606 nvfx_fragprog_destroy(nvfx, pfp->fps[i]);
1607 FREE(pfp->fps[i]);
1608 }
1609 }
1610
1611 FREE((void*)pfp->pipe.tokens);
1612 FREE(pfp);
1613 }
1614
1615 void
1616 nvfx_init_fragprog_functions(struct nvfx_context *nvfx)
1617 {
1618 nvfx->pipe.create_fs_state = nvfx_fp_state_create;
1619 nvfx->pipe.bind_fs_state = nvfx_fp_state_bind;
1620 nvfx->pipe.delete_fs_state = nvfx_fp_state_delete;
1621 }