1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5 #include "util/u_debug.h"
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_util.h"
10 #include "tgsi/tgsi_dump.h"
12 #include "nvfx_context.h"
13 #include "nvfx_shader.h"
14 #include "nvfx_resource.h"
16 #define MAX_CONSTS 128
20 struct nvfx_fragment_program
*fp
;
23 unsigned r_temps_discard
;
24 struct nvfx_reg r_result
[PIPE_MAX_SHADER_OUTPUTS
];
25 struct nvfx_reg
*r_temp
;
38 struct nvfx_reg imm
[MAX_IMM
];
41 unsigned char generic_to_slot
[256]; /* semantic idx for each input semantic */
43 struct util_dynarray if_stack
;
44 //struct util_dynarray loop_stack;
45 struct util_dynarray label_relocs
;
48 static INLINE
struct nvfx_reg
49 temp(struct nvfx_fpc
*fpc
)
51 int idx
= ffs(~fpc
->r_temps
) - 1;
54 NOUVEAU_ERR("out of temps!!\n");
56 return nvfx_reg(NVFXSR_TEMP
, 0);
59 fpc
->r_temps
|= (1 << idx
);
60 fpc
->r_temps_discard
|= (1 << idx
);
61 return nvfx_reg(NVFXSR_TEMP
, idx
);
65 release_temps(struct nvfx_fpc
*fpc
)
67 fpc
->r_temps
&= ~fpc
->r_temps_discard
;
68 fpc
->r_temps_discard
= 0;
71 static INLINE
struct nvfx_reg
72 constant(struct nvfx_fpc
*fpc
, int pipe
, float vals
[4])
76 if (fpc
->nr_consts
== MAX_CONSTS
)
78 idx
= fpc
->nr_consts
++;
80 fpc
->consts
[idx
].pipe
= pipe
;
82 memcpy(fpc
->consts
[idx
].vals
, vals
, 4 * sizeof(float));
83 return nvfx_reg(NVFXSR_CONST
, idx
);
87 grow_insns(struct nvfx_fpc
*fpc
, int size
)
89 struct nvfx_fragment_program
*fp
= fpc
->fp
;
92 fp
->insn
= realloc(fp
->insn
, sizeof(uint32_t) * fp
->insn_len
);
96 emit_src(struct nvfx_fpc
*fpc
, int pos
, struct nvfx_src src
)
98 struct nvfx_fragment_program
*fp
= fpc
->fp
;
99 uint32_t *hw
= &fp
->insn
[fpc
->inst_offset
];
102 switch (src
.reg
.type
) {
104 sr
|= (NVFX_FP_REG_TYPE_INPUT
<< NVFX_FP_REG_TYPE_SHIFT
);
105 hw
[0] |= (src
.reg
.index
<< NVFX_FP_OP_INPUT_SRC_SHIFT
);
108 sr
|= NVFX_FP_REG_SRC_HALF
;
111 sr
|= (NVFX_FP_REG_TYPE_TEMP
<< NVFX_FP_REG_TYPE_SHIFT
);
112 sr
|= (src
.reg
.index
<< NVFX_FP_REG_SRC_SHIFT
);
114 case NVFXSR_RELOCATED
:
115 sr
|= (NVFX_FP_REG_TYPE_INPUT
<< NVFX_FP_REG_TYPE_SHIFT
);
116 //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
117 util_dynarray_append(&fpc
->fp
->slot_relocations
[src
.reg
.index
], unsigned, fpc
->inst_offset
);
120 if (!fpc
->have_const
) {
125 hw
= &fp
->insn
[fpc
->inst_offset
];
126 if (fpc
->consts
[src
.reg
.index
].pipe
>= 0) {
127 struct nvfx_fragment_program_data
*fpd
;
129 fp
->consts
= realloc(fp
->consts
, ++fp
->nr_consts
*
131 fpd
= &fp
->consts
[fp
->nr_consts
- 1];
132 fpd
->offset
= fpc
->inst_offset
+ 4;
133 fpd
->index
= fpc
->consts
[src
.reg
.index
].pipe
;
134 memset(&fp
->insn
[fpd
->offset
], 0, sizeof(uint32_t) * 4);
136 memcpy(&fp
->insn
[fpc
->inst_offset
+ 4],
137 fpc
->consts
[src
.reg
.index
].vals
,
138 sizeof(uint32_t) * 4);
141 sr
|= (NVFX_FP_REG_TYPE_CONST
<< NVFX_FP_REG_TYPE_SHIFT
);
144 sr
|= (NVFX_FP_REG_TYPE_INPUT
<< NVFX_FP_REG_TYPE_SHIFT
);
151 sr
|= NVFX_FP_REG_NEGATE
;
154 hw
[1] |= (1 << (29 + pos
));
156 sr
|= ((src
.swz
[0] << NVFX_FP_REG_SWZ_X_SHIFT
) |
157 (src
.swz
[1] << NVFX_FP_REG_SWZ_Y_SHIFT
) |
158 (src
.swz
[2] << NVFX_FP_REG_SWZ_Z_SHIFT
) |
159 (src
.swz
[3] << NVFX_FP_REG_SWZ_W_SHIFT
));
165 emit_dst(struct nvfx_fpc
*fpc
, struct nvfx_reg dst
)
167 struct nvfx_fragment_program
*fp
= fpc
->fp
;
168 uint32_t *hw
= &fp
->insn
[fpc
->inst_offset
];
172 if (fpc
->num_regs
< (dst
.index
+ 1))
173 fpc
->num_regs
= dst
.index
+ 1;
176 if (dst
.index
== 1) {
177 fp
->fp_control
|= 0xe;
179 hw
[0] |= NVFX_FP_OP_OUT_REG_HALF
;
189 hw
[0] |= (dst
.index
<< NVFX_FP_OP_OUT_REG_SHIFT
);
193 nvfx_fp_emit(struct nvfx_fpc
*fpc
, struct nvfx_insn insn
)
195 struct nvfx_fragment_program
*fp
= fpc
->fp
;
198 fpc
->inst_offset
= fp
->insn_len
;
201 hw
= &fp
->insn
[fpc
->inst_offset
];
202 memset(hw
, 0, sizeof(uint32_t) * 4);
204 if (insn
.op
== NVFX_FP_OP_OPCODE_KIL
)
205 fp
->fp_control
|= NV34TCL_FP_CONTROL_USES_KIL
;
206 hw
[0] |= (insn
.op
<< NVFX_FP_OP_OPCODE_SHIFT
);
207 hw
[0] |= (insn
.mask
<< NVFX_FP_OP_OUTMASK_SHIFT
);
208 hw
[2] |= (insn
.scale
<< NVFX_FP_OP_DST_SCALE_SHIFT
);
211 hw
[0] |= NVFX_FP_OP_OUT_SAT
;
214 hw
[0] |= NVFX_FP_OP_COND_WRITE_ENABLE
;
215 hw
[1] |= (insn
.cc_test
<< NVFX_FP_OP_COND_SHIFT
);
216 hw
[1] |= ((insn
.cc_swz
[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT
) |
217 (insn
.cc_swz
[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT
) |
218 (insn
.cc_swz
[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT
) |
219 (insn
.cc_swz
[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT
));
223 hw
[0] |= (insn
.unit
<< NVFX_FP_OP_TEX_UNIT_SHIFT
);
224 fp
->samplers
|= (1 << insn
.unit
);
227 emit_dst(fpc
, insn
.dst
);
228 emit_src(fpc
, 0, insn
.src
[0]);
229 emit_src(fpc
, 1, insn
.src
[1]);
230 emit_src(fpc
, 2, insn
.src
[2]);
233 #define arith(s,o,d,m,s0,s1,s2) \
234 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, -1, \
235 (d), (m), (s0), (s1), (s2))
237 #define tex(s,o,u,d,m,s0,s1,s2) \
238 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
239 (d), (m), (s0), none, none)
241 /* IF src.x != 0, as TGSI specifies */
243 nv40_fp_if(struct nvfx_fpc
*fpc
, struct nvfx_src src
)
245 const struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
246 struct nvfx_insn insn
= arith(0, MOV
, none
.reg
, NVFX_FP_MASK_X
, src
, none
, none
);
249 nvfx_fp_emit(fpc
, insn
);
251 fpc
->inst_offset
= fpc
->fp
->insn_len
;
253 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
254 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
255 hw
[0] = (NV40_FP_OP_BRA_OPCODE_IF
<< NVFX_FP_OP_OPCODE_SHIFT
) |
256 NV40_FP_OP_OUT_NONE
|
257 (NVFX_FP_PRECISION_FP16
<< NVFX_FP_OP_PRECISION_SHIFT
);
258 /* Use .xxxx swizzle so that we check only src[0].x*/
259 hw
[1] = (0 << NVFX_FP_OP_COND_SWZ_X_SHIFT
) |
260 (0 << NVFX_FP_OP_COND_SWZ_Y_SHIFT
) |
261 (0 << NVFX_FP_OP_COND_SWZ_Z_SHIFT
) |
262 (0 << NVFX_FP_OP_COND_SWZ_W_SHIFT
) |
263 (NVFX_FP_OP_COND_NE
<< NVFX_FP_OP_COND_SHIFT
);
264 hw
[2] = 0; /* | NV40_FP_OP_OPCODE_IS_BRANCH | else_offset */
265 hw
[3] = 0; /* | endif_offset */
266 util_dynarray_append(&fpc
->if_stack
, unsigned, fpc
->inst_offset
);
269 /* IF src.x != 0, as TGSI specifies */
271 nv40_fp_cal(struct nvfx_fpc
*fpc
, unsigned target
)
273 struct nvfx_relocation reloc
;
275 fpc
->inst_offset
= fpc
->fp
->insn_len
;
277 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
278 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
279 hw
[0] = (NV40_FP_OP_BRA_OPCODE_CAL
<< NVFX_FP_OP_OPCODE_SHIFT
);
280 /* Use .xxxx swizzle so that we check only src[0].x*/
281 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_ALL_SHIFT
) |
282 (NVFX_FP_OP_COND_TR
<< NVFX_FP_OP_COND_SHIFT
);
283 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
; /* | call_offset */
285 reloc
.target
= target
;
286 reloc
.location
= fpc
->inst_offset
+ 2;
287 util_dynarray_append(&fpc
->label_relocs
, struct nvfx_relocation
, reloc
);
291 nv40_fp_ret(struct nvfx_fpc
*fpc
)
294 fpc
->inst_offset
= fpc
->fp
->insn_len
;
296 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
297 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
298 hw
[0] = (NV40_FP_OP_BRA_OPCODE_RET
<< NVFX_FP_OP_OPCODE_SHIFT
);
299 /* Use .xxxx swizzle so that we check only src[0].x*/
300 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_ALL_SHIFT
) |
301 (NVFX_FP_OP_COND_TR
<< NVFX_FP_OP_COND_SHIFT
);
302 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
; /* | call_offset */
307 nv40_fp_rep(struct nvfx_fpc
*fpc
, unsigned count
, unsigned target
)
309 struct nvfx_relocation reloc
;
311 fpc
->inst_offset
= fpc
->fp
->insn_len
;
313 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
314 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
315 hw
[0] = (NV40_FP_OP_BRA_OPCODE_REP
<< NVFX_FP_OP_OPCODE_SHIFT
) |
316 NV40_FP_OP_OUT_NONE
|
317 (NVFX_FP_PRECISION_FP16
<< NVFX_FP_OP_PRECISION_SHIFT
);
318 /* Use .xxxx swizzle so that we check only src[0].x*/
319 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_ALL_SHIFT
) |
320 (NVFX_FP_OP_COND_TR
<< NVFX_FP_OP_COND_SHIFT
);
321 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
|
322 (count
<< NV40_FP_OP_REP_COUNT1_SHIFT
) |
323 (count
<< NV40_FP_OP_REP_COUNT2_SHIFT
) |
324 (count
<< NV40_FP_OP_REP_COUNT3_SHIFT
);
325 hw
[3] = 0; /* | end_offset */
326 reloc
.target
= target
;
327 reloc
.location
= fpc
->inst_offset
+ 3;
328 util_dynarray_append(&fpc
->label_relocs
, struct nvfx_relocation
, reloc
);
329 //util_dynarray_append(&fpc->loop_stack, unsigned, target);
332 /* warning: this only works forward, and probably only if not inside any IF */
334 nv40_fp_bra(struct nvfx_fpc
*fpc
, unsigned target
)
336 struct nvfx_relocation reloc
;
338 fpc
->inst_offset
= fpc
->fp
->insn_len
;
340 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
341 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
342 hw
[0] = (NV40_FP_OP_BRA_OPCODE_IF
<< NVFX_FP_OP_OPCODE_SHIFT
) |
343 NV40_FP_OP_OUT_NONE
|
344 (NVFX_FP_PRECISION_FP16
<< NVFX_FP_OP_PRECISION_SHIFT
);
345 /* Use .xxxx swizzle so that we check only src[0].x*/
346 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_X_SHIFT
) |
347 (NVFX_FP_OP_COND_FL
<< NVFX_FP_OP_COND_SHIFT
);
348 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
; /* | else_offset */
349 hw
[3] = 0; /* | endif_offset */
350 reloc
.target
= target
;
351 reloc
.location
= fpc
->inst_offset
+ 2;
352 util_dynarray_append(&fpc
->label_relocs
, struct nvfx_relocation
, reloc
);
353 reloc
.target
= target
;
354 reloc
.location
= fpc
->inst_offset
+ 3;
355 util_dynarray_append(&fpc
->label_relocs
, struct nvfx_relocation
, reloc
);
359 nv40_fp_brk(struct nvfx_fpc
*fpc
)
362 fpc
->inst_offset
= fpc
->fp
->insn_len
;
364 hw
= &fpc
->fp
->insn
[fpc
->inst_offset
];
365 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
366 hw
[0] = (NV40_FP_OP_BRA_OPCODE_BRK
<< NVFX_FP_OP_OPCODE_SHIFT
) |
368 /* Use .xxxx swizzle so that we check only src[0].x*/
369 hw
[1] = (NVFX_SWZ_IDENTITY
<< NVFX_FP_OP_COND_SWZ_X_SHIFT
) |
370 (NVFX_FP_OP_COND_TR
<< NVFX_FP_OP_COND_SHIFT
);
371 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
;
375 static INLINE
struct nvfx_src
376 tgsi_src(struct nvfx_fpc
*fpc
, const struct tgsi_full_src_register
*fsrc
)
380 switch (fsrc
->Register
.File
) {
381 case TGSI_FILE_INPUT
:
382 if(fpc
->fp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_POSITION
) {
383 assert(fpc
->fp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 0);
384 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NVFX_FP_OP_INPUT_SRC_POSITION
);
385 } else if(fpc
->fp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_COLOR
) {
386 if(fpc
->fp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 0)
387 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NVFX_FP_OP_INPUT_SRC_COL0
);
388 else if(fpc
->fp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 1)
389 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NVFX_FP_OP_INPUT_SRC_COL1
);
392 } else if(fpc
->fp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_FOG
) {
393 assert(fpc
->fp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 0);
394 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NVFX_FP_OP_INPUT_SRC_FOGC
);
395 } else if(fpc
->fp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_FACE
) {
396 /* TODO: check this has the correct values */
397 /* XXX: what do we do for nv30 here (assuming it lacks facing)?! */
398 assert(fpc
->fp
->info
.input_semantic_index
[fsrc
->Register
.Index
] == 0);
399 src
.reg
= nvfx_reg(NVFXSR_INPUT
, NV40_FP_OP_INPUT_SRC_FACING
);
401 assert(fpc
->fp
->info
.input_semantic_name
[fsrc
->Register
.Index
] == TGSI_SEMANTIC_GENERIC
);
402 src
.reg
= nvfx_reg(NVFXSR_RELOCATED
, fpc
->generic_to_slot
[fpc
->fp
->info
.input_semantic_index
[fsrc
->Register
.Index
]]);
405 case TGSI_FILE_CONSTANT
:
406 src
.reg
= constant(fpc
, fsrc
->Register
.Index
, NULL
);
408 case TGSI_FILE_IMMEDIATE
:
409 assert(fsrc
->Register
.Index
< fpc
->nr_imm
);
410 src
.reg
= fpc
->imm
[fsrc
->Register
.Index
];
412 case TGSI_FILE_TEMPORARY
:
413 src
.reg
= fpc
->r_temp
[fsrc
->Register
.Index
];
415 /* NV40 fragprog result regs are just temps, so this is simple */
416 case TGSI_FILE_OUTPUT
:
417 src
.reg
= fpc
->r_result
[fsrc
->Register
.Index
];
420 NOUVEAU_ERR("bad src file\n");
426 src
.abs
= fsrc
->Register
.Absolute
;
427 src
.negate
= fsrc
->Register
.Negate
;
428 src
.swz
[0] = fsrc
->Register
.SwizzleX
;
429 src
.swz
[1] = fsrc
->Register
.SwizzleY
;
430 src
.swz
[2] = fsrc
->Register
.SwizzleZ
;
431 src
.swz
[3] = fsrc
->Register
.SwizzleW
;
435 static INLINE
struct nvfx_reg
436 tgsi_dst(struct nvfx_fpc
*fpc
, const struct tgsi_full_dst_register
*fdst
) {
437 switch (fdst
->Register
.File
) {
438 case TGSI_FILE_OUTPUT
:
439 return fpc
->r_result
[fdst
->Register
.Index
];
440 case TGSI_FILE_TEMPORARY
:
441 return fpc
->r_temp
[fdst
->Register
.Index
];
443 return nvfx_reg(NVFXSR_NONE
, 0);
445 NOUVEAU_ERR("bad dst file %d\n", fdst
->Register
.File
);
446 return nvfx_reg(NVFXSR_NONE
, 0);
455 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= NVFX_FP_MASK_X
;
456 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= NVFX_FP_MASK_Y
;
457 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= NVFX_FP_MASK_Z
;
458 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= NVFX_FP_MASK_W
;
463 nvfx_fragprog_parse_instruction(struct nvfx_context
* nvfx
, struct nvfx_fpc
*fpc
,
464 const struct tgsi_full_instruction
*finst
)
466 const struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
467 struct nvfx_insn insn
;
468 struct nvfx_src src
[3], tmp
, tmp2
;
470 int mask
, sat
, unit
= 0;
471 int ai
= -1, ci
= -1, ii
= -1;
474 if (finst
->Instruction
.Opcode
== TGSI_OPCODE_END
)
477 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
478 const struct tgsi_full_src_register
*fsrc
;
480 fsrc
= &finst
->Src
[i
];
481 if (fsrc
->Register
.File
== TGSI_FILE_TEMPORARY
) {
482 src
[i
] = tgsi_src(fpc
, fsrc
);
486 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
487 const struct tgsi_full_src_register
*fsrc
;
489 fsrc
= &finst
->Src
[i
];
491 switch (fsrc
->Register
.File
) {
492 case TGSI_FILE_INPUT
:
493 if (ai
== -1 || ai
== fsrc
->Register
.Index
) {
494 ai
= fsrc
->Register
.Index
;
495 src
[i
] = tgsi_src(fpc
, fsrc
);
497 src
[i
] = nvfx_src(temp(fpc
));
498 nvfx_fp_emit(fpc
, arith(0, MOV
, src
[i
].reg
, NVFX_FP_MASK_ALL
, tgsi_src(fpc
, fsrc
), none
, none
));
501 case TGSI_FILE_CONSTANT
:
502 if ((ci
== -1 && ii
== -1) ||
503 ci
== fsrc
->Register
.Index
) {
504 ci
= fsrc
->Register
.Index
;
505 src
[i
] = tgsi_src(fpc
, fsrc
);
507 src
[i
] = nvfx_src(temp(fpc
));
508 nvfx_fp_emit(fpc
, arith(0, MOV
, src
[i
].reg
, NVFX_FP_MASK_ALL
, tgsi_src(fpc
, fsrc
), none
, none
));
511 case TGSI_FILE_IMMEDIATE
:
512 if ((ci
== -1 && ii
== -1) ||
513 ii
== fsrc
->Register
.Index
) {
514 ii
= fsrc
->Register
.Index
;
515 src
[i
] = tgsi_src(fpc
, fsrc
);
517 src
[i
] = nvfx_src(temp(fpc
));
518 nvfx_fp_emit(fpc
, arith(0, MOV
, src
[i
].reg
, NVFX_FP_MASK_ALL
, tgsi_src(fpc
, fsrc
), none
, none
));
521 case TGSI_FILE_TEMPORARY
:
524 case TGSI_FILE_SAMPLER
:
525 unit
= fsrc
->Register
.Index
;
527 case TGSI_FILE_OUTPUT
:
530 NOUVEAU_ERR("bad src file\n");
535 dst
= tgsi_dst(fpc
, &finst
->Dst
[0]);
536 mask
= tgsi_mask(finst
->Dst
[0].Register
.WriteMask
);
537 sat
= (finst
->Instruction
.Saturate
== TGSI_SAT_ZERO_ONE
);
539 switch (finst
->Instruction
.Opcode
) {
540 case TGSI_OPCODE_ABS
:
541 nvfx_fp_emit(fpc
, arith(sat
, MOV
, dst
, mask
, abs(src
[0]), none
, none
));
543 case TGSI_OPCODE_ADD
:
544 nvfx_fp_emit(fpc
, arith(sat
, ADD
, dst
, mask
, src
[0], src
[1], none
));
546 case TGSI_OPCODE_CMP
:
547 insn
= arith(0, MOV
, none
.reg
, mask
, src
[0], none
, none
);
549 nvfx_fp_emit(fpc
, insn
);
551 insn
= arith(sat
, MOV
, dst
, mask
, src
[2], none
, none
);
552 insn
.cc_test
= NVFX_COND_GE
;
553 nvfx_fp_emit(fpc
, insn
);
555 insn
= arith(sat
, MOV
, dst
, mask
, src
[1], none
, none
);
556 insn
.cc_test
= NVFX_COND_LT
;
557 nvfx_fp_emit(fpc
, insn
);
559 case TGSI_OPCODE_COS
:
560 nvfx_fp_emit(fpc
, arith(sat
, COS
, dst
, mask
, src
[0], none
, none
));
562 case TGSI_OPCODE_DDX
:
563 if (mask
& (NVFX_FP_MASK_Z
| NVFX_FP_MASK_W
)) {
564 tmp
= nvfx_src(temp(fpc
));
565 nvfx_fp_emit(fpc
, arith(sat
, DDX
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, swz(src
[0], Z
, W
, Z
, W
), none
, none
));
566 nvfx_fp_emit(fpc
, arith(0, MOV
, tmp
.reg
, NVFX_FP_MASK_Z
| NVFX_FP_MASK_W
, swz(tmp
, X
, Y
, X
, Y
), none
, none
));
567 nvfx_fp_emit(fpc
, arith(sat
, DDX
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, src
[0], none
, none
));
568 nvfx_fp_emit(fpc
, arith(0, MOV
, dst
, mask
, tmp
, none
, none
));
570 nvfx_fp_emit(fpc
, arith(sat
, DDX
, dst
, mask
, src
[0], none
, none
));
573 case TGSI_OPCODE_DDY
:
574 if (mask
& (NVFX_FP_MASK_Z
| NVFX_FP_MASK_W
)) {
575 tmp
= nvfx_src(temp(fpc
));
576 nvfx_fp_emit(fpc
, arith(sat
, DDY
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, swz(src
[0], Z
, W
, Z
, W
), none
, none
));
577 nvfx_fp_emit(fpc
, arith(0, MOV
, tmp
.reg
, NVFX_FP_MASK_Z
| NVFX_FP_MASK_W
, swz(tmp
, X
, Y
, X
, Y
), none
, none
));
578 nvfx_fp_emit(fpc
, arith(sat
, DDY
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, src
[0], none
, none
));
579 nvfx_fp_emit(fpc
, arith(0, MOV
, dst
, mask
, tmp
, none
, none
));
581 nvfx_fp_emit(fpc
, arith(sat
, DDY
, dst
, mask
, src
[0], none
, none
));
584 case TGSI_OPCODE_DP2
:
585 tmp
= nvfx_src(temp(fpc
));
586 nvfx_fp_emit(fpc
, arith(0, MUL
, tmp
.reg
, NVFX_FP_MASK_X
| NVFX_FP_MASK_Y
, src
[0], src
[1], none
));
587 nvfx_fp_emit(fpc
, arith(0, ADD
, dst
, mask
, swz(tmp
, X
, X
, X
, X
), swz(tmp
, Y
, Y
, Y
, Y
), none
));
589 case TGSI_OPCODE_DP3
:
590 nvfx_fp_emit(fpc
, arith(sat
, DP3
, dst
, mask
, src
[0], src
[1], none
));
592 case TGSI_OPCODE_DP4
:
593 nvfx_fp_emit(fpc
, arith(sat
, DP4
, dst
, mask
, src
[0], src
[1], none
));
595 case TGSI_OPCODE_DPH
:
596 tmp
= nvfx_src(temp(fpc
));
597 nvfx_fp_emit(fpc
, arith(0, DP3
, tmp
.reg
, NVFX_FP_MASK_X
, src
[0], src
[1], none
));
598 nvfx_fp_emit(fpc
, arith(sat
, ADD
, dst
, mask
, swz(tmp
, X
, X
, X
, X
), swz(src
[1], W
, W
, W
, W
), none
));
600 case TGSI_OPCODE_DST
:
601 nvfx_fp_emit(fpc
, arith(sat
, DST
, dst
, mask
, src
[0], src
[1], none
));
603 case TGSI_OPCODE_EX2
:
604 nvfx_fp_emit(fpc
, arith(sat
, EX2
, dst
, mask
, src
[0], none
, none
));
606 case TGSI_OPCODE_FLR
:
607 nvfx_fp_emit(fpc
, arith(sat
, FLR
, dst
, mask
, src
[0], none
, none
));
609 case TGSI_OPCODE_FRC
:
610 nvfx_fp_emit(fpc
, arith(sat
, FRC
, dst
, mask
, src
[0], none
, none
));
612 case TGSI_OPCODE_KILP
:
613 nvfx_fp_emit(fpc
, arith(0, KIL
, none
.reg
, 0, none
, none
, none
));
615 case TGSI_OPCODE_KIL
:
616 insn
= arith(0, MOV
, none
.reg
, NVFX_FP_MASK_ALL
, src
[0], none
, none
);
618 nvfx_fp_emit(fpc
, insn
);
620 insn
= arith(0, KIL
, none
.reg
, 0, none
, none
, none
);
621 insn
.cc_test
= NVFX_COND_LT
;
622 nvfx_fp_emit(fpc
, insn
);
624 case TGSI_OPCODE_LG2
:
625 nvfx_fp_emit(fpc
, arith(sat
, LG2
, dst
, mask
, src
[0], none
, none
));
627 // case TGSI_OPCODE_LIT:
628 case TGSI_OPCODE_LRP
:
630 nvfx_fp_emit(fpc
, arith(sat
, LRP_NV30
, dst
, mask
, src
[0], src
[1], src
[2]));
632 tmp
= nvfx_src(temp(fpc
));
633 nvfx_fp_emit(fpc
, arith(0, MAD
, tmp
.reg
, mask
, neg(src
[0]), src
[2], src
[2]));
634 nvfx_fp_emit(fpc
, arith(sat
, MAD
, dst
, mask
, src
[0], src
[1], tmp
));
637 case TGSI_OPCODE_MAD
:
638 nvfx_fp_emit(fpc
, arith(sat
, MAD
, dst
, mask
, src
[0], src
[1], src
[2]));
640 case TGSI_OPCODE_MAX
:
641 nvfx_fp_emit(fpc
, arith(sat
, MAX
, dst
, mask
, src
[0], src
[1], none
));
643 case TGSI_OPCODE_MIN
:
644 nvfx_fp_emit(fpc
, arith(sat
, MIN
, dst
, mask
, src
[0], src
[1], none
));
646 case TGSI_OPCODE_MOV
:
647 nvfx_fp_emit(fpc
, arith(sat
, MOV
, dst
, mask
, src
[0], none
, none
));
649 case TGSI_OPCODE_MUL
:
650 nvfx_fp_emit(fpc
, arith(sat
, MUL
, dst
, mask
, src
[0], src
[1], none
));
652 case TGSI_OPCODE_NOP
:
654 case TGSI_OPCODE_POW
:
656 nvfx_fp_emit(fpc
, arith(sat
, POW_NV30
, dst
, mask
, src
[0], src
[1], none
));
658 tmp
= nvfx_src(temp(fpc
));
659 nvfx_fp_emit(fpc
, arith(0, LG2
, tmp
.reg
, NVFX_FP_MASK_X
, swz(src
[0], X
, X
, X
, X
), none
, none
));
660 nvfx_fp_emit(fpc
, arith(0, MUL
, tmp
.reg
, NVFX_FP_MASK_X
, swz(tmp
, X
, X
, X
, X
), swz(src
[1], X
, X
, X
, X
), none
));
661 nvfx_fp_emit(fpc
, arith(sat
, EX2
, dst
, mask
, swz(tmp
, X
, X
, X
, X
), none
, none
));
664 case TGSI_OPCODE_RCP
:
665 nvfx_fp_emit(fpc
, arith(sat
, RCP
, dst
, mask
, src
[0], none
, none
));
667 case TGSI_OPCODE_RFL
:
669 nvfx_fp_emit(fpc
, arith(0, RFL_NV30
, dst
, mask
, src
[0], src
[1], none
));
671 tmp
= nvfx_src(temp(fpc
));
672 nvfx_fp_emit(fpc
, arith(0, DP3
, tmp
.reg
, NVFX_FP_MASK_X
, src
[0], src
[0], none
));
673 nvfx_fp_emit(fpc
, arith(0, DP3
, tmp
.reg
, NVFX_FP_MASK_Y
, src
[0], src
[1], none
));
674 insn
= arith(0, DIV
, tmp
.reg
, NVFX_FP_MASK_Z
, swz(tmp
, Y
, Y
, Y
, Y
), swz(tmp
, X
, X
, X
, X
), none
);
675 insn
.scale
= NVFX_FP_OP_DST_SCALE_2X
;
676 nvfx_fp_emit(fpc
, insn
);
677 nvfx_fp_emit(fpc
, arith(sat
, MAD
, dst
, mask
, swz(tmp
, Z
, Z
, Z
, Z
), src
[0], neg(src
[1])));
680 case TGSI_OPCODE_RSQ
:
682 nvfx_fp_emit(fpc
, arith(sat
, RSQ_NV30
, dst
, mask
, abs(swz(src
[0], X
, X
, X
, X
)), none
, none
));
684 tmp
= nvfx_src(temp(fpc
));
685 insn
= arith(0, LG2
, tmp
.reg
, NVFX_FP_MASK_X
, abs(swz(src
[0], X
, X
, X
, X
)), none
, none
);
686 insn
.scale
= NVFX_FP_OP_DST_SCALE_INV_2X
;
687 nvfx_fp_emit(fpc
, insn
);
688 nvfx_fp_emit(fpc
, arith(sat
, EX2
, dst
, mask
, neg(swz(tmp
, X
, X
, X
, X
)), none
, none
));
691 case TGSI_OPCODE_SCS
:
692 /* avoid overwriting the source */
693 if(src
[0].swz
[NVFX_SWZ_X
] != NVFX_SWZ_X
)
695 if (mask
& NVFX_FP_MASK_X
)
696 nvfx_fp_emit(fpc
, arith(sat
, COS
, dst
, NVFX_FP_MASK_X
, swz(src
[0], X
, X
, X
, X
), none
, none
));
697 if (mask
& NVFX_FP_MASK_Y
)
698 nvfx_fp_emit(fpc
, arith(sat
, SIN
, dst
, NVFX_FP_MASK_Y
, swz(src
[0], X
, X
, X
, X
), none
, none
));
702 if (mask
& NVFX_FP_MASK_Y
)
703 nvfx_fp_emit(fpc
, arith(sat
, SIN
, dst
, NVFX_FP_MASK_Y
, swz(src
[0], X
, X
, X
, X
), none
, none
));
704 if (mask
& NVFX_FP_MASK_X
)
705 nvfx_fp_emit(fpc
, arith(sat
, COS
, dst
, NVFX_FP_MASK_X
, swz(src
[0], X
, X
, X
, X
), none
, none
));
708 case TGSI_OPCODE_SEQ
:
709 nvfx_fp_emit(fpc
, arith(sat
, SEQ
, dst
, mask
, src
[0], src
[1], none
));
711 case TGSI_OPCODE_SFL
:
712 nvfx_fp_emit(fpc
, arith(sat
, SFL
, dst
, mask
, src
[0], src
[1], none
));
714 case TGSI_OPCODE_SGE
:
715 nvfx_fp_emit(fpc
, arith(sat
, SGE
, dst
, mask
, src
[0], src
[1], none
));
717 case TGSI_OPCODE_SGT
:
718 nvfx_fp_emit(fpc
, arith(sat
, SGT
, dst
, mask
, src
[0], src
[1], none
));
720 case TGSI_OPCODE_SIN
:
721 nvfx_fp_emit(fpc
, arith(sat
, SIN
, dst
, mask
, src
[0], none
, none
));
723 case TGSI_OPCODE_SLE
:
724 nvfx_fp_emit(fpc
, arith(sat
, SLE
, dst
, mask
, src
[0], src
[1], none
));
726 case TGSI_OPCODE_SLT
:
727 nvfx_fp_emit(fpc
, arith(sat
, SLT
, dst
, mask
, src
[0], src
[1], none
));
729 case TGSI_OPCODE_SNE
:
730 nvfx_fp_emit(fpc
, arith(sat
, SNE
, dst
, mask
, src
[0], src
[1], none
));
732 case TGSI_OPCODE_SSG
:
733 tmp
= nvfx_src(temp(fpc
));
734 tmp2
= nvfx_src(temp(fpc
));
735 nvfx_fp_emit(fpc
, arith(0, SGT
, tmp
.reg
, mask
, src
[0], nvfx_src(nvfx_reg(NVFXSR_CONST
, 0)), none
));
736 nvfx_fp_emit(fpc
, arith(0, SLT
, tmp
.reg
, mask
, src
[0], nvfx_src(nvfx_reg(NVFXSR_CONST
, 0)), none
));
737 nvfx_fp_emit(fpc
, arith(sat
, ADD
, dst
, mask
, tmp
, neg(tmp2
), none
));
739 case TGSI_OPCODE_STR
:
740 nvfx_fp_emit(fpc
, arith(sat
, STR
, dst
, mask
, src
[0], src
[1], none
));
742 case TGSI_OPCODE_SUB
:
743 nvfx_fp_emit(fpc
, arith(sat
, ADD
, dst
, mask
, src
[0], neg(src
[1]), none
));
745 case TGSI_OPCODE_TEX
:
746 nvfx_fp_emit(fpc
, tex(sat
, TEX
, unit
, dst
, mask
, src
[0], none
, none
));
748 case TGSI_OPCODE_TRUNC
:
749 tmp
= nvfx_src(temp(fpc
));
750 insn
= arith(0, MOV
, none
.reg
, mask
, src
[0], none
, none
);
752 nvfx_fp_emit(fpc
, insn
);
754 nvfx_fp_emit(fpc
, arith(0, FLR
, tmp
.reg
, mask
, abs(src
[0]), none
, none
));
755 nvfx_fp_emit(fpc
, arith(sat
, MOV
, dst
, mask
, tmp
, none
, none
));
757 insn
= arith(sat
, MOV
, dst
, mask
, neg(tmp
), none
, none
);
758 insn
.cc_test
= NVFX_COND_LT
;
759 nvfx_fp_emit(fpc
, insn
);
761 case TGSI_OPCODE_TXB
:
762 nvfx_fp_emit(fpc
, tex(sat
, TXB
, unit
, dst
, mask
, src
[0], none
, none
));
764 case TGSI_OPCODE_TXL
:
766 nvfx_fp_emit(fpc
, tex(sat
, TXL_NV40
, unit
, dst
, mask
, src
[0], none
, none
));
767 else /* unsupported on nv30, use TEX and hope they like it */
768 nvfx_fp_emit(fpc
, tex(sat
, TEX
, unit
, dst
, mask
, src
[0], none
, none
));
770 case TGSI_OPCODE_TXP
:
771 nvfx_fp_emit(fpc
, tex(sat
, TXP
, unit
, dst
, mask
, src
[0], none
, none
));
773 case TGSI_OPCODE_XPD
:
774 tmp
= nvfx_src(temp(fpc
));
775 nvfx_fp_emit(fpc
, arith(0, MUL
, tmp
.reg
, mask
, swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
));
776 nvfx_fp_emit(fpc
, arith(sat
, MAD
, dst
, (mask
& ~NVFX_FP_MASK_W
), swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
), neg(tmp
)));
780 // MOVRC0 R31 (TR0.xyzw), R<src>:
781 // IF (NE.xxxx) ELSE <else> END <end>
784 nv40_fp_if(fpc
, src
[0]);
787 case TGSI_OPCODE_ELSE
:
792 assert(util_dynarray_contains(&fpc
->if_stack
, unsigned));
793 hw
= &fpc
->fp
->insn
[util_dynarray_top(&fpc
->if_stack
, unsigned)];
794 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
| fpc
->fp
->insn_len
;
798 case TGSI_OPCODE_ENDIF
:
803 assert(util_dynarray_contains(&fpc
->if_stack
, unsigned));
804 hw
= &fpc
->fp
->insn
[util_dynarray_pop(&fpc
->if_stack
, unsigned)];
806 hw
[2] = NV40_FP_OP_OPCODE_IS_BRANCH
| fpc
->fp
->insn_len
;
807 hw
[3] = fpc
->fp
->insn_len
;
811 case TGSI_OPCODE_BRA
:
812 /* This can in limited cases be implemented with an IF with the else and endif labels pointing to the target */
813 /* no state tracker uses this, so don't implement this for now */
815 nv40_fp_bra(fpc
, finst
->Label
.Label
);
818 case TGSI_OPCODE_BGNSUB
:
819 case TGSI_OPCODE_ENDSUB
:
820 /* nothing to do here */
823 case TGSI_OPCODE_CAL
:
826 nv40_fp_cal(fpc
, finst
->Label
.Label
);
829 case TGSI_OPCODE_RET
:
835 case TGSI_OPCODE_BGNLOOP
:
838 /* TODO: we should support using two nested REPs to allow a > 255 iteration count */
839 nv40_fp_rep(fpc
, 255, finst
->Label
.Label
);
842 case TGSI_OPCODE_ENDLOOP
:
845 case TGSI_OPCODE_BRK
:
851 case TGSI_OPCODE_CONT
:
853 static int warned
= 0;
855 NOUVEAU_ERR("Sorry, the continue keyword is not implemented: ignoring it.\n");
862 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
871 static int warned
= 0;
874 "Sorry, control flow instructions are not supported in hardware on nv3x: ignoring them\n"
875 "If rendering is incorrect, try to disable GLSL support in the application.\n");
883 nvfx_fragprog_parse_decl_output(struct nvfx_context
* nvfx
, struct nvfx_fpc
*fpc
,
884 const struct tgsi_full_declaration
*fdec
)
886 unsigned idx
= fdec
->Range
.First
;
889 switch (fdec
->Semantic
.Name
) {
890 case TGSI_SEMANTIC_POSITION
:
893 case TGSI_SEMANTIC_COLOR
:
895 switch (fdec
->Semantic
.Index
) {
896 case 0: hw
= 0; break;
897 case 1: hw
= 2; break;
898 case 2: hw
= 3; break;
899 case 3: hw
= 4; break;
901 if(hw
> ((nvfx
->is_nv4x
) ? 4 : 2)) {
902 NOUVEAU_ERR("bad rcol index\n");
907 NOUVEAU_ERR("bad output semantic\n");
911 fpc
->r_result
[idx
] = nvfx_reg(NVFXSR_OUTPUT
, hw
);
912 fpc
->r_temps
|= (1 << hw
);
917 nvfx_fragprog_prepare(struct nvfx_context
* nvfx
, struct nvfx_fpc
*fpc
)
919 struct tgsi_parse_context p
;
920 int high_temp
= -1, i
;
921 struct util_semantic_set set
;
922 float const0v
[4] = {0, 0, 0, 0};
923 struct nvfx_reg const0
;
925 fpc
->fp
->num_slots
= util_semantic_set_from_program_file(&set
, fpc
->fp
->pipe
.tokens
, TGSI_FILE_INPUT
);
926 if(fpc
->fp
->num_slots
> 8)
928 util_semantic_layout_from_set(fpc
->fp
->slot_to_generic
, &set
, 0, 8);
929 util_semantic_table_from_layout(fpc
->generic_to_slot
, fpc
->fp
->slot_to_generic
, 0, 8);
931 memset(fpc
->fp
->slot_to_fp_input
, 0xff, sizeof(fpc
->fp
->slot_to_fp_input
));
933 const0
= constant(fpc
, -1, const0v
);
934 assert(const0
.index
== 0);
936 tgsi_parse_init(&p
, fpc
->fp
->pipe
.tokens
);
937 while (!tgsi_parse_end_of_tokens(&p
)) {
938 const union tgsi_full_token
*tok
= &p
.FullToken
;
940 tgsi_parse_token(&p
);
941 switch(tok
->Token
.Type
) {
942 case TGSI_TOKEN_TYPE_DECLARATION
:
944 const struct tgsi_full_declaration
*fdec
;
945 fdec
= &p
.FullToken
.FullDeclaration
;
946 switch (fdec
->Declaration
.File
) {
947 case TGSI_FILE_OUTPUT
:
948 if (!nvfx_fragprog_parse_decl_output(nvfx
, fpc
, fdec
))
951 case TGSI_FILE_TEMPORARY
:
952 if (fdec
->Range
.Last
> high_temp
) {
962 case TGSI_TOKEN_TYPE_IMMEDIATE
:
964 struct tgsi_full_immediate
*imm
;
967 imm
= &p
.FullToken
.FullImmediate
;
968 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
969 assert(fpc
->nr_imm
< MAX_IMM
);
971 vals
[0] = imm
->u
[0].Float
;
972 vals
[1] = imm
->u
[1].Float
;
973 vals
[2] = imm
->u
[2].Float
;
974 vals
[3] = imm
->u
[3].Float
;
975 fpc
->imm
[fpc
->nr_imm
++] = constant(fpc
, -1, vals
);
985 fpc
->r_temp
= CALLOC(high_temp
, sizeof(struct nvfx_reg
));
986 for (i
= 0; i
< high_temp
; i
++)
987 fpc
->r_temp
[i
] = temp(fpc
);
988 fpc
->r_temps_discard
= 0;
1000 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp
, "NVFX_DUMP_FP", FALSE
)
1003 nvfx_fragprog_translate(struct nvfx_context
*nvfx
,
1004 struct nvfx_fragment_program
*fp
)
1006 struct tgsi_parse_context parse
;
1007 struct nvfx_fpc
*fpc
= NULL
;
1008 struct util_dynarray insns
;
1010 fpc
= CALLOC(1, sizeof(struct nvfx_fpc
));
1016 if (!nvfx_fragprog_prepare(nvfx
, fpc
)) {
1021 tgsi_parse_init(&parse
, fp
->pipe
.tokens
);
1023 util_dynarray_init(&insns
);
1024 while (!tgsi_parse_end_of_tokens(&parse
)) {
1025 tgsi_parse_token(&parse
);
1027 switch (parse
.FullToken
.Token
.Type
) {
1028 case TGSI_TOKEN_TYPE_INSTRUCTION
:
1030 const struct tgsi_full_instruction
*finst
;
1032 util_dynarray_append(&insns
, unsigned, fp
->insn_len
);
1033 finst
= &parse
.FullToken
.FullInstruction
;
1034 if (!nvfx_fragprog_parse_instruction(nvfx
, fpc
, finst
))
1042 util_dynarray_append(&insns
, unsigned, fp
->insn_len
);
1044 for(unsigned i
= 0; i
< fpc
->label_relocs
.size
; i
+= sizeof(struct nvfx_relocation
))
1046 struct nvfx_relocation
* label_reloc
= (struct nvfx_relocation
*)((char*)fpc
->label_relocs
.data
+ i
);
1047 fp
->insn
[label_reloc
->location
] |= ((unsigned*)insns
.data
)[label_reloc
->target
];
1049 util_dynarray_fini(&insns
);
1052 fp
->fp_control
|= (fpc
->num_regs
-1)/2;
1054 fp
->fp_control
|= fpc
->num_regs
<< NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT
;
1056 /* Terminate final instruction */
1058 fp
->insn
[fpc
->inst_offset
] |= 0x00000001;
1060 /* Append NOP + END instruction for branches to the end of the program */
1061 fpc
->inst_offset
= fp
->insn_len
;
1063 fp
->insn
[fpc
->inst_offset
+ 0] = 0x00000001;
1064 fp
->insn
[fpc
->inst_offset
+ 1] = 0x00000000;
1065 fp
->insn
[fpc
->inst_offset
+ 2] = 0x00000000;
1066 fp
->insn
[fpc
->inst_offset
+ 3] = 0x00000000;
1068 if(debug_get_option_nvfx_dump_fp())
1071 tgsi_dump(fp
->pipe
.tokens
, 0);
1073 debug_printf("\n%s fragment program:\n", nvfx
->is_nv4x
? "nv4x" : "nv3x");
1074 for (unsigned i
= 0; i
< fp
->insn_len
; i
+= 4)
1075 debug_printf("%3u: %08x %08x %08x %08x\n", i
>> 2, fp
->insn
[i
], fp
->insn
[i
+ 1], fp
->insn
[i
+ 2], fp
->insn
[i
+ 3]);
1079 fp
->translated
= TRUE
;
1081 tgsi_parse_free(&parse
);
1084 util_dynarray_fini(&fpc
->if_stack
);
1085 util_dynarray_fini(&fpc
->label_relocs
);
1086 //util_dynarray_fini(&fpc->loop_stack);
1091 nvfx_fp_memcpy(void* dst
, const void* src
, size_t len
)
1093 #ifndef WORDS_BIGENDIAN
1094 memcpy(dst
, src
, len
);
1097 for(i
= 0; i
< len
; i
+= 4) {
1098 uint32_t v
= (uint32_t*)((char*)src
+ i
);
1099 *(uint32_t*)((char*)dst
+ i
) = (v
>> 16) | (v
<< 16);
1104 /* The hardware only supports immediate constants inside the fragment program,
1105 * and at least on nv30 doesn't support an indirect linkage table.
1107 * Hence, we need to patch the fragment program itself both to update constants
1108 * and update linkage.
1110 * Using a single fragment program would entail unacceptable stalls if the GPU is
1111 * already rendering with that fragment program.
1112 * Thus, we instead use a "rotating queue" of buffer objects, each of which is
1113 * packed with multiple versions of the same program.
1115 * Whenever we need to patch something, we move to the next program and
1116 * patch it. If all buffer objects are in use by the GPU, we allocate another one,
1117 * expanding the queue.
1119 * As an additional optimization, we record when all the programs have the
1120 * current input slot configuration, and at that point we stop patching inputs.
1121 * This happens, for instance, if a given fragment program is always used with
1122 * the same vertex program (i.e. always with GLSL), or if the layouts match
1123 * enough (non-GLSL).
1125 * Note that instead of using multiple programs, we could push commands
1126 * on the FIFO to patch a single program: it's not fully clear which option is
1127 * faster, but my guess is that the current way is faster.
1129 * We also track the previous slot assignments for each version and don't
1130 * patch if they are the same (this could perhaps be removed).
1134 nvfx_fragprog_validate(struct nvfx_context
*nvfx
)
1136 struct nouveau_channel
* chan
= nvfx
->screen
->base
.channel
;
1137 struct nvfx_fragment_program
*fp
= nvfx
->fragprog
;
1139 struct nvfx_vertex_program
* vp
;
1140 unsigned sprite_coord_enable
;
1141 boolean update_pointsprite
= !!(nvfx
->dirty
& NVFX_NEW_FRAGPROG
);
1143 if (!fp
->translated
)
1145 const int min_size
= 4096;
1147 nvfx_fragprog_translate(nvfx
, fp
);
1148 if (!fp
->translated
) {
1149 static unsigned dummy
[8] = {1, 0, 0, 0, 1, 0, 0, 0};
1150 static int warned
= 0;
1153 fprintf(stderr
, "nvfx: failed to translate fragment program!\n");
1157 /* use dummy program: we cannot fail here */
1158 fp
->translated
= TRUE
;
1159 fp
->insn
= malloc(sizeof(dummy
));
1160 memcpy(fp
->insn
, dummy
, sizeof(dummy
));
1161 fp
->insn_len
= sizeof(dummy
) / sizeof(dummy
[0]);
1165 fp
->prog_size
= (fp
->insn_len
* 4 + 63) & ~63;
1167 if(fp
->prog_size
>= min_size
)
1168 fp
->progs_per_bo
= 1;
1170 fp
->progs_per_bo
= min_size
/ fp
->prog_size
;
1171 fp
->bo_prog_idx
= fp
->progs_per_bo
- 1;
1174 vp
= nvfx
->render_mode
== HW
? nvfx
->vertprog
: nvfx
->swtnl
.vertprog
;
1175 sprite_coord_enable
= nvfx
->rasterizer
->pipe
.point_quad_rasterization
* nvfx
->rasterizer
->pipe
.sprite_coord_enable
;
1177 if (fp
->last_vp_id
!= vp
->id
|| fp
->last_sprite_coord_enable
!= sprite_coord_enable
) {
1178 int sprite_input
= -1;
1180 fp
->last_vp_id
= vp
->id
;
1181 fp
->last_sprite_coord_enable
= sprite_coord_enable
;
1183 if(sprite_coord_enable
)
1185 sprite_input
= vp
->sprite_fp_input
;
1186 if(sprite_input
< 0)
1188 unsigned used_texcoords
= 0;
1189 for(unsigned i
= 0; i
< fp
->num_slots
; ++i
) {
1190 unsigned generic
= fp
->slot_to_generic
[i
];
1191 if(!((1 << generic
) & sprite_coord_enable
))
1193 unsigned char slot_mask
= vp
->generic_to_fp_input
[generic
];
1194 if(slot_mask
>= 0xf0)
1195 used_texcoords
|= 1 << ((slot_mask
& 0xf) - NVFX_FP_OP_INPUT_SRC_TC0
);
1199 sprite_input
= NVFX_FP_OP_INPUT_SRC_TC(__builtin_ctz(~used_texcoords
));
1202 fp
->point_sprite_control
|= (1 << (sprite_input
- NVFX_FP_OP_INPUT_SRC_TC0
+ 8));
1205 fp
->point_sprite_control
= 0;
1207 for(i
= 0; i
< fp
->num_slots
; ++i
) {
1208 unsigned generic
= fp
->slot_to_generic
[i
];
1209 if((1 << generic
) & sprite_coord_enable
)
1211 if(fp
->slot_to_fp_input
[i
] != sprite_input
)
1216 unsigned char slot_mask
= vp
->generic_to_fp_input
[generic
];
1217 if((slot_mask
>> 4) & (slot_mask
^ fp
->slot_to_fp_input
[i
]))
1225 /* optimization: we start updating from the slot we found the first difference in */
1226 for(; i
< fp
->num_slots
; ++i
)
1228 unsigned generic
= fp
->slot_to_generic
[i
];
1229 if((1 << generic
) & sprite_coord_enable
)
1230 fp
->slot_to_fp_input
[i
] = sprite_input
;
1232 fp
->slot_to_fp_input
[i
] = vp
->generic_to_fp_input
[generic
] & 0xf;
1238 for(i
= 0; i
< fp
->num_slots
; ++i
) {
1239 unsigned fp_input
= fp
->slot_to_fp_input
[i
];
1240 if(fp_input
== NVFX_FP_OP_INPUT_SRC_TC(8))
1241 fp
->or |= (1 << 12);
1242 else if(fp_input
== NVFX_FP_OP_INPUT_SRC_TC(9))
1243 fp
->or |= (1 << 13);
1244 else if(fp_input
!= 0xf)
1245 fp
->or |= (1 << (fp_input
- NVFX_FP_OP_INPUT_SRC_TC0
+ 14));
1249 fp
->progs_left_with_obsolete_slot_assignments
= fp
->progs
;
1254 /* We must update constants even on "just" fragprog changes, because
1255 * we don't check whether the current constant buffer matches the latest
1256 * one bound to this fragment program.
1257 * Doing such a check would likely be a pessimization.
1259 if (nvfx
->dirty
& (NVFX_NEW_FRAGCONST
| NVFX_NEW_FRAGPROG
)) {
1265 if(fp
->bo_prog_idx
>= fp
->progs_per_bo
)
1267 if(fp
->fpbo
&& !nouveau_bo_busy(fp
->fpbo
->next
->bo
, NOUVEAU_BO_WR
))
1269 fp
->fpbo
= fp
->fpbo
->next
;
1273 struct nvfx_fragment_program_bo
* fpbo
= os_malloc_aligned(sizeof(struct nvfx_fragment_program
) + (fp
->prog_size
+ 8) * fp
->progs_per_bo
, 16);
1277 fpbo
->slots
= (unsigned char*)&fpbo
->insn
[(fp
->prog_size
) * fp
->progs_per_bo
];
1278 memset(fpbo
->slots
, 0, 8 * fp
->progs_per_bo
);
1281 fpbo
->next
= fp
->fpbo
->next
;
1282 fp
->fpbo
->next
= fpbo
;
1288 fp
->progs
+= fp
->progs_per_bo
;
1289 fp
->progs_left_with_obsolete_slot_assignments
+= fp
->progs_per_bo
;
1290 nouveau_bo_new(nvfx
->screen
->base
.device
, NOUVEAU_BO_VRAM
| NOUVEAU_BO_MAP
, 64, fp
->prog_size
* fp
->progs_per_bo
, &fpbo
->bo
);
1291 nouveau_bo_map(fpbo
->bo
, NOUVEAU_BO_NOSYNC
);
1293 map
= fpbo
->bo
->map
;
1294 buf
= (uint8_t*)fpbo
->insn
;
1295 for(unsigned i
= 0; i
< fp
->progs_per_bo
; ++i
)
1297 memcpy(buf
, fp
->insn
, fp
->insn_len
* 4);
1298 nvfx_fp_memcpy(map
, fp
->insn
, fp
->insn_len
* 4);
1299 map
+= fp
->prog_size
;
1300 buf
+= fp
->prog_size
;
1303 fp
->bo_prog_idx
= 0;
1306 offset
= fp
->bo_prog_idx
* fp
->prog_size
;
1307 fpmap
= (uint32_t*)((char*)fp
->fpbo
->bo
->map
+ offset
);
1309 if(nvfx
->constbuf
[PIPE_SHADER_FRAGMENT
]) {
1310 struct pipe_resource
* constbuf
= nvfx
->constbuf
[PIPE_SHADER_FRAGMENT
];
1311 uint32_t* map
= (uint32_t*)nvfx_buffer(constbuf
)->data
;
1312 uint32_t* fpmap
= (uint32_t*)((char*)fp
->fpbo
->bo
->map
+ offset
);
1313 uint32_t* buf
= (uint32_t*)((char*)fp
->fpbo
->insn
+ offset
);
1315 for (i
= 0; i
< fp
->nr_consts
; ++i
) {
1316 unsigned off
= fp
->consts
[i
].offset
;
1317 unsigned idx
= fp
->consts
[i
].index
* 4;
1319 /* TODO: is checking a good idea? */
1320 if(memcmp(&buf
[off
], &map
[idx
], 4 * sizeof(uint32_t))) {
1321 memcpy(&buf
[off
], &map
[idx
], 4 * sizeof(uint32_t));
1322 nvfx_fp_memcpy(&fpmap
[off
], &map
[idx
], 4 * sizeof(uint32_t));
1327 /* we only do this if we aren't sure that all program versions have the
1328 * current slot assignments, otherwise we just update constants for speed
1330 if(fp
->progs_left_with_obsolete_slot_assignments
) {
1331 unsigned char* fpbo_slots
= &fp
->fpbo
->slots
[fp
->bo_prog_idx
* 8];
1332 for(unsigned i
= 0; i
< fp
->num_slots
; ++i
) {
1333 unsigned value
= fp
->slot_to_fp_input
[i
];;
1334 if(value
!= fpbo_slots
[i
]) {
1335 unsigned* p
= (unsigned*)fp
->slot_relocations
[i
].data
;
1336 unsigned* pend
= (unsigned*)((char*)fp
->slot_relocations
[i
].data
+ fp
->slot_relocations
[i
].size
);
1337 for(; p
!= pend
; ++p
) {
1339 unsigned dw
= fp
->insn
[off
];
1340 dw
= (dw
& ~NVFX_FP_OP_INPUT_SRC_MASK
) | (value
<< NVFX_FP_OP_INPUT_SRC_SHIFT
);
1341 nvfx_fp_memcpy(&fpmap
[*p
], &dw
, sizeof(dw
));
1343 fpbo_slots
[i
] = value
;
1346 --fp
->progs_left_with_obsolete_slot_assignments
;
1349 MARK_RING(chan
, 8, 1);
1350 OUT_RING(chan
, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM
, 1));
1351 OUT_RELOC(chan
, fp
->fpbo
->bo
, offset
, NOUVEAU_BO_VRAM
|
1352 NOUVEAU_BO_GART
| NOUVEAU_BO_RD
| NOUVEAU_BO_LOW
|
1353 NOUVEAU_BO_OR
, NV34TCL_FP_ACTIVE_PROGRAM_DMA0
,
1354 NV34TCL_FP_ACTIVE_PROGRAM_DMA1
);
1355 OUT_RING(chan
, RING_3D(NV34TCL_FP_CONTROL
, 1));
1356 OUT_RING(chan
, fp
->fp_control
);
1357 if(!nvfx
->is_nv4x
) {
1358 OUT_RING(chan
, RING_3D(NV34TCL_FP_REG_CONTROL
, 1));
1359 OUT_RING(chan
, (1<<16)|0x4);
1360 OUT_RING(chan
, RING_3D(NV34TCL_TX_UNITS_ENABLE
, 1));
1361 OUT_RING(chan
, fp
->samplers
);
1366 unsigned pointsprite_control
= fp
->point_sprite_control
| nvfx
->rasterizer
->pipe
.point_quad_rasterization
;
1367 if(pointsprite_control
!= nvfx
->hw_pointsprite_control
)
1370 OUT_RING(chan
, RING_3D(NV34TCL_POINT_SPRITE
, 1));
1371 OUT_RING(chan
, pointsprite_control
);
1372 nvfx
->hw_pointsprite_control
= pointsprite_control
;
1378 unsigned vp_output
= vp
->or | fp
->or;
1380 if(vp_output
!= nvfx
->hw_vp_output
)
1383 OUT_RING(chan
, RING_3D(NV40TCL_VP_RESULT_EN
, 1));
1384 OUT_RING(chan
, vp_output
);
1385 nvfx
->hw_vp_output
= vp_output
;
1391 nvfx_fragprog_relocate(struct nvfx_context
*nvfx
)
1393 struct nouveau_channel
* chan
= nvfx
->screen
->base
.channel
;
1394 struct nvfx_fragment_program
*fp
= nvfx
->fragprog
;
1395 struct nouveau_bo
* bo
= fp
->fpbo
->bo
;
1396 int offset
= fp
->bo_prog_idx
* fp
->prog_size
;
1397 unsigned fp_flags
= NOUVEAU_BO_VRAM
| NOUVEAU_BO_RD
; // TODO: GART?
1398 fp_flags
|= NOUVEAU_BO_DUMMY
;
1399 MARK_RING(chan
, 2, 2);
1400 OUT_RELOC(chan
, bo
, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM
, 1), fp_flags
, 0, 0);
1401 OUT_RELOC(chan
, bo
, offset
, fp_flags
| NOUVEAU_BO_LOW
|
1402 NOUVEAU_BO_OR
, NV34TCL_FP_ACTIVE_PROGRAM_DMA0
,
1403 NV34TCL_FP_ACTIVE_PROGRAM_DMA1
);
1407 nvfx_fragprog_destroy(struct nvfx_context
*nvfx
,
1408 struct nvfx_fragment_program
*fp
)
1411 struct nvfx_fragment_program_bo
* fpbo
= fp
->fpbo
;
1416 struct nvfx_fragment_program_bo
* next
= fpbo
->next
;
1417 nouveau_bo_unmap(fpbo
->bo
);
1418 nouveau_bo_ref(0, &fpbo
->bo
);
1422 while(fpbo
!= fp
->fpbo
);
1425 for(i
= 0; i
< 8; ++i
)
1426 util_dynarray_fini(&fp
->slot_relocations
[i
]);