projects / mesa.git / blob
? search:


ebd3eb88c1cddfa6c34744340f9204c35743f009
[mesa.git] / src / gallium / drivers / nvfx / nvfx_fragprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5 #include "util/u_debug.h"
6
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_util.h"
10 #include "tgsi/tgsi_dump.h"
11
12 #include "nvfx_context.h"
13 #include "nvfx_shader.h"
14 #include "nvfx_resource.h"
15
16 #define MAX_CONSTS 128
17 #define MAX_IMM 32
18
19 struct nvfx_fpc {
20 struct nvfx_fragment_program *fp;
21
22 unsigned r_temps;
23 unsigned r_temps_discard;
24 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
25 struct nvfx_reg *r_temp;
26
27 int num_regs;
28
29 unsigned inst_offset;
30 unsigned have_const;
31
32 struct {
33 int pipe;
34 float vals[4];
35 } consts[MAX_CONSTS];
36 int nr_consts;
37
38 struct nvfx_reg imm[MAX_IMM];
39 unsigned nr_imm;
40
41 unsigned char generic_to_slot[256]; /* semantic idx for each input semantic */
42
43 struct util_dynarray if_stack;
44 //struct util_dynarray loop_stack;
45 struct util_dynarray label_relocs;
46 };
47
48 static INLINE struct nvfx_reg
49 temp(struct nvfx_fpc *fpc)
50 {
51 int idx = ffs(~fpc->r_temps) - 1;
52
53 if (idx < 0) {
54 NOUVEAU_ERR("out of temps!!\n");
55 assert(0);
56 return nvfx_reg(NVFXSR_TEMP, 0);
57 }
58
59 fpc->r_temps |= (1 << idx);
60 fpc->r_temps_discard |= (1 << idx);
61 return nvfx_reg(NVFXSR_TEMP, idx);
62 }
63
64 static INLINE void
65 release_temps(struct nvfx_fpc *fpc)
66 {
67 fpc->r_temps &= ~fpc->r_temps_discard;
68 fpc->r_temps_discard = 0;
69 }
70
71 static INLINE struct nvfx_reg
72 constant(struct nvfx_fpc *fpc, int pipe, float vals[4])
73 {
74 int idx;
75
76 if (fpc->nr_consts == MAX_CONSTS)
77 assert(0);
78 idx = fpc->nr_consts++;
79
80 fpc->consts[idx].pipe = pipe;
81 if (pipe == -1)
82 memcpy(fpc->consts[idx].vals, vals, 4 * sizeof(float));
83 return nvfx_reg(NVFXSR_CONST, idx);
84 }
85
86 static void
87 grow_insns(struct nvfx_fpc *fpc, int size)
88 {
89 struct nvfx_fragment_program *fp = fpc->fp;
90
91 fp->insn_len += size;
92 fp->insn = realloc(fp->insn, sizeof(uint32_t) * fp->insn_len);
93 }
94
95 static void
96 emit_src(struct nvfx_fpc *fpc, int pos, struct nvfx_src src)
97 {
98 struct nvfx_fragment_program *fp = fpc->fp;
99 uint32_t *hw = &fp->insn[fpc->inst_offset];
100 uint32_t sr = 0;
101
102 switch (src.reg.type) {
103 case NVFXSR_INPUT:
104 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
105 hw[0] |= (src.reg.index << NVFX_FP_OP_INPUT_SRC_SHIFT);
106 break;
107 case NVFXSR_OUTPUT:
108 sr |= NVFX_FP_REG_SRC_HALF;
109 /* fall-through */
110 case NVFXSR_TEMP:
111 sr |= (NVFX_FP_REG_TYPE_TEMP << NVFX_FP_REG_TYPE_SHIFT);
112 sr |= (src.reg.index << NVFX_FP_REG_SRC_SHIFT);
113 break;
114 case NVFXSR_RELOCATED:
115 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
116 //printf("adding relocation at %x for %x\n", fpc->inst_offset, src.index);
117 util_dynarray_append(&fpc->fp->slot_relocations[src.reg.index], unsigned, fpc->inst_offset);
118 break;
119 case NVFXSR_CONST:
120 if (!fpc->have_const) {
121 grow_insns(fpc, 4);
122 fpc->have_const = 1;
123 }
124
125 hw = &fp->insn[fpc->inst_offset];
126 if (fpc->consts[src.reg.index].pipe >= 0) {
127 struct nvfx_fragment_program_data *fpd;
128
129 fp->consts = realloc(fp->consts, ++fp->nr_consts *
130 sizeof(*fpd));
131 fpd = &fp->consts[fp->nr_consts - 1];
132 fpd->offset = fpc->inst_offset + 4;
133 fpd->index = fpc->consts[src.reg.index].pipe;
134 memset(&fp->insn[fpd->offset], 0, sizeof(uint32_t) * 4);
135 } else {
136 memcpy(&fp->insn[fpc->inst_offset + 4],
137 fpc->consts[src.reg.index].vals,
138 sizeof(uint32_t) * 4);
139 }
140
141 sr |= (NVFX_FP_REG_TYPE_CONST << NVFX_FP_REG_TYPE_SHIFT);
142 break;
143 case NVFXSR_NONE:
144 sr |= (NVFX_FP_REG_TYPE_INPUT << NVFX_FP_REG_TYPE_SHIFT);
145 break;
146 default:
147 assert(0);
148 }
149
150 if (src.negate)
151 sr |= NVFX_FP_REG_NEGATE;
152
153 if (src.abs)
154 hw[1] |= (1 << (29 + pos));
155
156 sr |= ((src.swz[0] << NVFX_FP_REG_SWZ_X_SHIFT) |
157 (src.swz[1] << NVFX_FP_REG_SWZ_Y_SHIFT) |
158 (src.swz[2] << NVFX_FP_REG_SWZ_Z_SHIFT) |
159 (src.swz[3] << NVFX_FP_REG_SWZ_W_SHIFT));
160
161 hw[pos + 1] |= sr;
162 }
163
164 static void
165 emit_dst(struct nvfx_fpc *fpc, struct nvfx_reg dst)
166 {
167 struct nvfx_fragment_program *fp = fpc->fp;
168 uint32_t *hw = &fp->insn[fpc->inst_offset];
169
170 switch (dst.type) {
171 case NVFXSR_TEMP:
172 if (fpc->num_regs < (dst.index + 1))
173 fpc->num_regs = dst.index + 1;
174 break;
175 case NVFXSR_OUTPUT:
176 if (dst.index == 1) {
177 fp->fp_control |= 0xe;
178 } else {
179 hw[0] |= NVFX_FP_OP_OUT_REG_HALF;
180 }
181 break;
182 case NVFXSR_NONE:
183 hw[0] |= (1 << 30);
184 break;
185 default:
186 assert(0);
187 }
188
189 hw[0] |= (dst.index << NVFX_FP_OP_OUT_REG_SHIFT);
190 }
191
192 static void
193 nvfx_fp_emit(struct nvfx_fpc *fpc, struct nvfx_insn insn)
194 {
195 struct nvfx_fragment_program *fp = fpc->fp;
196 uint32_t *hw;
197
198 fpc->inst_offset = fp->insn_len;
199 fpc->have_const = 0;
200 grow_insns(fpc, 4);
201 hw = &fp->insn[fpc->inst_offset];
202 memset(hw, 0, sizeof(uint32_t) * 4);
203
204 if (insn.op == NVFX_FP_OP_OPCODE_KIL)
205 fp->fp_control |= NV34TCL_FP_CONTROL_USES_KIL;
206 hw[0] |= (insn.op << NVFX_FP_OP_OPCODE_SHIFT);
207 hw[0] |= (insn.mask << NVFX_FP_OP_OUTMASK_SHIFT);
208 hw[2] |= (insn.scale << NVFX_FP_OP_DST_SCALE_SHIFT);
209
210 if (insn.sat)
211 hw[0] |= NVFX_FP_OP_OUT_SAT;
212
213 if (insn.cc_update)
214 hw[0] |= NVFX_FP_OP_COND_WRITE_ENABLE;
215 hw[1] |= (insn.cc_test << NVFX_FP_OP_COND_SHIFT);
216 hw[1] |= ((insn.cc_swz[0] << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
217 (insn.cc_swz[1] << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
218 (insn.cc_swz[2] << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
219 (insn.cc_swz[3] << NVFX_FP_OP_COND_SWZ_W_SHIFT));
220
221 if(insn.unit >= 0)
222 {
223 hw[0] |= (insn.unit << NVFX_FP_OP_TEX_UNIT_SHIFT);
224 fp->samplers |= (1 << insn.unit);
225 }
226
227 emit_dst(fpc, insn.dst);
228 emit_src(fpc, 0, insn.src[0]);
229 emit_src(fpc, 1, insn.src[1]);
230 emit_src(fpc, 2, insn.src[2]);
231 }
232
233 #define arith(s,o,d,m,s0,s1,s2) \
234 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, -1, \
235 (d), (m), (s0), (s1), (s2))
236
237 #define tex(s,o,u,d,m,s0,s1,s2) \
238 nvfx_insn((s), NVFX_FP_OP_OPCODE_##o, (u), \
239 (d), (m), (s0), none, none)
240
241 /* IF src.x != 0, as TGSI specifies */
242 static void
243 nv40_fp_if(struct nvfx_fpc *fpc, struct nvfx_src src)
244 {
245 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
246 struct nvfx_insn insn = arith(0, MOV, none.reg, NVFX_FP_MASK_X, src, none, none);
247 insn.cc_update = 1;
248 nvfx_fp_emit(fpc, insn);
249
250 fpc->inst_offset = fpc->fp->insn_len;
251 grow_insns(fpc, 4);
252 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
253 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
254 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
255 NV40_FP_OP_OUT_NONE |
256 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
257 /* Use .xxxx swizzle so that we check only src[0].x*/
258 hw[1] = (0 << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
259 (0 << NVFX_FP_OP_COND_SWZ_Y_SHIFT) |
260 (0 << NVFX_FP_OP_COND_SWZ_Z_SHIFT) |
261 (0 << NVFX_FP_OP_COND_SWZ_W_SHIFT) |
262 (NVFX_FP_OP_COND_NE << NVFX_FP_OP_COND_SHIFT);
263 hw[2] = 0; /* | NV40_FP_OP_OPCODE_IS_BRANCH | else_offset */
264 hw[3] = 0; /* | endif_offset */
265 util_dynarray_append(&fpc->if_stack, unsigned, fpc->inst_offset);
266 }
267
268 /* IF src.x != 0, as TGSI specifies */
269 static void
270 nv40_fp_cal(struct nvfx_fpc *fpc, unsigned target)
271 {
272 struct nvfx_label_relocation reloc;
273 fpc->inst_offset = fpc->fp->insn_len;
274 grow_insns(fpc, 4);
275 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
276 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
277 hw[0] = (NV40_FP_OP_BRA_OPCODE_CAL << NVFX_FP_OP_OPCODE_SHIFT);
278 /* Use .xxxx swizzle so that we check only src[0].x*/
279 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
280 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
281 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
282 hw[3] = 0;
283 reloc.target = target;
284 reloc.location = fpc->inst_offset + 2;
285 util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
286 }
287
288 static void
289 nv40_fp_ret(struct nvfx_fpc *fpc)
290 {
291 fpc->inst_offset = fpc->fp->insn_len;
292 grow_insns(fpc, 4);
293 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
294 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
295 hw[0] = (NV40_FP_OP_BRA_OPCODE_RET << NVFX_FP_OP_OPCODE_SHIFT);
296 /* Use .xxxx swizzle so that we check only src[0].x*/
297 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
298 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
299 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | call_offset */
300 hw[3] = 0;
301 }
302
303 static void
304 nv40_fp_rep(struct nvfx_fpc *fpc, unsigned count, unsigned target)
305 {
306 struct nvfx_label_relocation reloc;
307 fpc->inst_offset = fpc->fp->insn_len;
308 grow_insns(fpc, 4);
309 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
310 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
311 hw[0] = (NV40_FP_OP_BRA_OPCODE_REP << NVFX_FP_OP_OPCODE_SHIFT) |
312 NV40_FP_OP_OUT_NONE |
313 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
314 /* Use .xxxx swizzle so that we check only src[0].x*/
315 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_ALL_SHIFT) |
316 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
317 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH |
318 (count << NV40_FP_OP_REP_COUNT1_SHIFT) |
319 (count << NV40_FP_OP_REP_COUNT2_SHIFT) |
320 (count << NV40_FP_OP_REP_COUNT3_SHIFT);
321 hw[3] = 0; /* | end_offset */
322 reloc.target = target;
323 reloc.location = fpc->inst_offset + 3;
324 util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
325 //util_dynarray_append(&fpc->loop_stack, unsigned, target);
326 }
327
328 /* warning: this only works forward, and probably only if not inside any IF */
329 static void
330 nv40_fp_bra(struct nvfx_fpc *fpc, unsigned target)
331 {
332 struct nvfx_label_relocation reloc;
333 fpc->inst_offset = fpc->fp->insn_len;
334 grow_insns(fpc, 4);
335 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
336 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
337 hw[0] = (NV40_FP_OP_BRA_OPCODE_IF << NVFX_FP_OP_OPCODE_SHIFT) |
338 NV40_FP_OP_OUT_NONE |
339 (NVFX_FP_PRECISION_FP16 << NVFX_FP_OP_PRECISION_SHIFT);
340 /* Use .xxxx swizzle so that we check only src[0].x*/
341 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
342 (NVFX_FP_OP_COND_FL << NVFX_FP_OP_COND_SHIFT);
343 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH; /* | else_offset */
344 hw[3] = 0; /* | endif_offset */
345 reloc.target = target;
346 reloc.location = fpc->inst_offset + 2;
347 util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
348 reloc.target = target;
349 reloc.location = fpc->inst_offset + 3;
350 util_dynarray_append(&fpc->label_relocs, struct nvfx_label_relocation, reloc);
351 }
352
353 static void
354 nv40_fp_brk(struct nvfx_fpc *fpc)
355 {
356 fpc->inst_offset = fpc->fp->insn_len;
357 grow_insns(fpc, 4);
358 uint32_t *hw = &fpc->fp->insn[fpc->inst_offset];
359 /* I really wonder why fp16 precision is used. Presumably the hardware ignores it? */
360 hw[0] = (NV40_FP_OP_BRA_OPCODE_BRK << NVFX_FP_OP_OPCODE_SHIFT) |
361 NV40_FP_OP_OUT_NONE;
362 /* Use .xxxx swizzle so that we check only src[0].x*/
363 hw[1] = (NVFX_SWZ_IDENTITY << NVFX_FP_OP_COND_SWZ_X_SHIFT) |
364 (NVFX_FP_OP_COND_TR << NVFX_FP_OP_COND_SHIFT);
365 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH;
366 hw[3] = 0;
367 }
368
369 static INLINE struct nvfx_src
370 tgsi_src(struct nvfx_fpc *fpc, const struct tgsi_full_src_register *fsrc)
371 {
372 struct nvfx_src src;
373
374 switch (fsrc->Register.File) {
375 case TGSI_FILE_INPUT:
376 if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_POSITION) {
377 assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
378 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_POSITION);
379 } else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_COLOR) {
380 if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0)
381 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL0);
382 else if(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 1)
383 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_COL1);
384 else
385 assert(0);
386 } else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FOG) {
387 assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
388 src.reg = nvfx_reg(NVFXSR_INPUT, NVFX_FP_OP_INPUT_SRC_FOGC);
389 } else if(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_FACE) {
390 /* TODO: check this has the correct values */
391 /* XXX: what do we do for nv30 here (assuming it lacks facing)?! */
392 assert(fpc->fp->info.input_semantic_index[fsrc->Register.Index] == 0);
393 src.reg = nvfx_reg(NVFXSR_INPUT, NV40_FP_OP_INPUT_SRC_FACING);
394 } else {
395 assert(fpc->fp->info.input_semantic_name[fsrc->Register.Index] == TGSI_SEMANTIC_GENERIC);
396 src.reg = nvfx_reg(NVFXSR_RELOCATED, fpc->generic_to_slot[fpc->fp->info.input_semantic_index[fsrc->Register.Index]]);
397 }
398 break;
399 case TGSI_FILE_CONSTANT:
400 src.reg = constant(fpc, fsrc->Register.Index, NULL);
401 break;
402 case TGSI_FILE_IMMEDIATE:
403 assert(fsrc->Register.Index < fpc->nr_imm);
404 src.reg = fpc->imm[fsrc->Register.Index];
405 break;
406 case TGSI_FILE_TEMPORARY:
407 src.reg = fpc->r_temp[fsrc->Register.Index];
408 break;
409 /* NV40 fragprog result regs are just temps, so this is simple */
410 case TGSI_FILE_OUTPUT:
411 src.reg = fpc->r_result[fsrc->Register.Index];
412 break;
413 default:
414 NOUVEAU_ERR("bad src file\n");
415 break;
416 }
417
418 src.abs = fsrc->Register.Absolute;
419 src.negate = fsrc->Register.Negate;
420 src.swz[0] = fsrc->Register.SwizzleX;
421 src.swz[1] = fsrc->Register.SwizzleY;
422 src.swz[2] = fsrc->Register.SwizzleZ;
423 src.swz[3] = fsrc->Register.SwizzleW;
424 return src;
425 }
426
427 static INLINE struct nvfx_reg
428 tgsi_dst(struct nvfx_fpc *fpc, const struct tgsi_full_dst_register *fdst) {
429 switch (fdst->Register.File) {
430 case TGSI_FILE_OUTPUT:
431 return fpc->r_result[fdst->Register.Index];
432 case TGSI_FILE_TEMPORARY:
433 return fpc->r_temp[fdst->Register.Index];
434 case TGSI_FILE_NULL:
435 return nvfx_reg(NVFXSR_NONE, 0);
436 default:
437 NOUVEAU_ERR("bad dst file %d\n", fdst->Register.File);
438 return nvfx_reg(NVFXSR_NONE, 0);
439 }
440 }
441
442 static INLINE int
443 tgsi_mask(uint tgsi)
444 {
445 int mask = 0;
446
447 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_FP_MASK_X;
448 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_FP_MASK_Y;
449 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_FP_MASK_Z;
450 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_FP_MASK_W;
451 return mask;
452 }
453
454 static boolean
455 nvfx_fragprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
456 const struct tgsi_full_instruction *finst)
457 {
458 const struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
459 struct nvfx_insn insn;
460 struct nvfx_src src[3], tmp, tmp2;
461 struct nvfx_reg dst;
462 int mask, sat, unit = 0;
463 int ai = -1, ci = -1, ii = -1;
464 int i;
465
466 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
467 return TRUE;
468
469 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
470 const struct tgsi_full_src_register *fsrc;
471
472 fsrc = &finst->Src[i];
473 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
474 src[i] = tgsi_src(fpc, fsrc);
475 }
476 }
477
478 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
479 const struct tgsi_full_src_register *fsrc;
480
481 fsrc = &finst->Src[i];
482
483 switch (fsrc->Register.File) {
484 case TGSI_FILE_INPUT:
485 if (ai == -1 || ai == fsrc->Register.Index) {
486 ai = fsrc->Register.Index;
487 src[i] = tgsi_src(fpc, fsrc);
488 } else {
489 src[i] = nvfx_src(temp(fpc));
490 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
491 }
492 break;
493 case TGSI_FILE_CONSTANT:
494 if ((ci == -1 && ii == -1) ||
495 ci == fsrc->Register.Index) {
496 ci = fsrc->Register.Index;
497 src[i] = tgsi_src(fpc, fsrc);
498 } else {
499 src[i] = nvfx_src(temp(fpc));
500 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
501 }
502 break;
503 case TGSI_FILE_IMMEDIATE:
504 if ((ci == -1 && ii == -1) ||
505 ii == fsrc->Register.Index) {
506 ii = fsrc->Register.Index;
507 src[i] = tgsi_src(fpc, fsrc);
508 } else {
509 src[i] = nvfx_src(temp(fpc));
510 nvfx_fp_emit(fpc, arith(0, MOV, src[i].reg, NVFX_FP_MASK_ALL, tgsi_src(fpc, fsrc), none, none));
511 }
512 break;
513 case TGSI_FILE_TEMPORARY:
514 /* handled above */
515 break;
516 case TGSI_FILE_SAMPLER:
517 unit = fsrc->Register.Index;
518 break;
519 case TGSI_FILE_OUTPUT:
520 break;
521 default:
522 NOUVEAU_ERR("bad src file\n");
523 return FALSE;
524 }
525 }
526
527 dst = tgsi_dst(fpc, &finst->Dst[0]);
528 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
529 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
530
531 switch (finst->Instruction.Opcode) {
532 case TGSI_OPCODE_ABS:
533 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, abs(src[0]), none, none));
534 break;
535 case TGSI_OPCODE_ADD:
536 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none));
537 break;
538 case TGSI_OPCODE_CMP:
539 insn = arith(0, MOV, none.reg, 0xf, src[0], none, none);
540 insn.cc_update = 1;
541 nvfx_fp_emit(fpc, insn);
542
543 insn = arith(sat, MOV, dst, mask, src[2], none, none);
544 insn.cc_test = NVFX_COND_GE;
545 nvfx_fp_emit(fpc, insn);
546
547 insn = arith(sat, MOV, dst, mask, src[1], none, none);
548 insn.cc_test = NVFX_COND_LT;
549 nvfx_fp_emit(fpc, insn);
550 break;
551 case TGSI_OPCODE_COS:
552 nvfx_fp_emit(fpc, arith(sat, COS, dst, mask, src[0], none, none));
553 break;
554 case TGSI_OPCODE_DDX:
555 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
556 tmp = nvfx_src(temp(fpc));
557 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
558 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
559 nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
560 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
561 } else {
562 nvfx_fp_emit(fpc, arith(sat, DDX, dst, mask, src[0], none, none));
563 }
564 break;
565 case TGSI_OPCODE_DDY:
566 if (mask & (NVFX_FP_MASK_Z | NVFX_FP_MASK_W)) {
567 tmp = nvfx_src(temp(fpc));
568 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W), none, none));
569 nvfx_fp_emit(fpc, arith(0, MOV, tmp.reg, NVFX_FP_MASK_Z | NVFX_FP_MASK_W, swz(tmp, X, Y, X, Y), none, none));
570 nvfx_fp_emit(fpc, arith(sat, DDY, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], none, none));
571 nvfx_fp_emit(fpc, arith(0, MOV, dst, mask, tmp, none, none));
572 } else {
573 nvfx_fp_emit(fpc, arith(sat, DDY, dst, mask, src[0], none, none));
574 }
575 break;
576 case TGSI_OPCODE_DP2:
577 tmp = nvfx_src(temp(fpc));
578 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, src[0], src[1], none));
579 nvfx_fp_emit(fpc, arith(0, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none));
580 break;
581 case TGSI_OPCODE_DP3:
582 nvfx_fp_emit(fpc, arith(sat, DP3, dst, mask, src[0], src[1], none));
583 break;
584 case TGSI_OPCODE_DP4:
585 nvfx_fp_emit(fpc, arith(sat, DP4, dst, mask, src[0], src[1], none));
586 break;
587 case TGSI_OPCODE_DPH:
588 tmp = nvfx_src(temp(fpc));
589 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[1], none));
590 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, swz(tmp, X, X, X, X), swz(src[1], W, W, W, W), none));
591 break;
592 case TGSI_OPCODE_DST:
593 nvfx_fp_emit(fpc, arith(sat, DST, dst, mask, src[0], src[1], none));
594 break;
595 case TGSI_OPCODE_EX2:
596 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, src[0], none, none));
597 break;
598 case TGSI_OPCODE_FLR:
599 nvfx_fp_emit(fpc, arith(sat, FLR, dst, mask, src[0], none, none));
600 break;
601 case TGSI_OPCODE_FRC:
602 nvfx_fp_emit(fpc, arith(sat, FRC, dst, mask, src[0], none, none));
603 break;
604 case TGSI_OPCODE_KILP:
605 nvfx_fp_emit(fpc, arith(0, KIL, none.reg, 0, none, none, none));
606 break;
607 case TGSI_OPCODE_KIL:
608 insn = arith(0, MOV, none.reg, NVFX_FP_MASK_ALL, src[0], none, none);
609 insn.cc_update = 1;
610 nvfx_fp_emit(fpc, insn);
611
612 insn = arith(0, KIL, none.reg, 0, none, none, none);
613 insn.cc_test = NVFX_COND_LT;
614 nvfx_fp_emit(fpc, insn);
615 break;
616 case TGSI_OPCODE_LG2:
617 nvfx_fp_emit(fpc, arith(sat, LG2, dst, mask, src[0], none, none));
618 break;
619 // case TGSI_OPCODE_LIT:
620 case TGSI_OPCODE_LRP:
621 if(!nvfx->is_nv4x)
622 nvfx_fp_emit(fpc, arith(sat, LRP_NV30, dst, mask, src[0], src[1], src[2]));
623 else {
624 tmp = nvfx_src(temp(fpc));
625 nvfx_fp_emit(fpc, arith(0, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
626 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], tmp));
627 }
628 break;
629 case TGSI_OPCODE_MAD:
630 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, src[0], src[1], src[2]));
631 break;
632 case TGSI_OPCODE_MAX:
633 nvfx_fp_emit(fpc, arith(sat, MAX, dst, mask, src[0], src[1], none));
634 break;
635 case TGSI_OPCODE_MIN:
636 nvfx_fp_emit(fpc, arith(sat, MIN, dst, mask, src[0], src[1], none));
637 break;
638 case TGSI_OPCODE_MOV:
639 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, src[0], none, none));
640 break;
641 case TGSI_OPCODE_MUL:
642 nvfx_fp_emit(fpc, arith(sat, MUL, dst, mask, src[0], src[1], none));
643 break;
644 case TGSI_OPCODE_NOP:
645 break;
646 case TGSI_OPCODE_POW:
647 if(!nvfx->is_nv4x)
648 nvfx_fp_emit(fpc, arith(sat, POW_NV30, dst, mask, src[0], src[1], none));
649 else {
650 tmp = nvfx_src(temp(fpc));
651 nvfx_fp_emit(fpc, arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
652 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, NVFX_FP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
653 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, swz(tmp, X, X, X, X), none, none));
654 }
655 break;
656 case TGSI_OPCODE_RCP:
657 nvfx_fp_emit(fpc, arith(sat, RCP, dst, mask, src[0], none, none));
658 break;
659 case TGSI_OPCODE_RFL:
660 if(!nvfx->is_nv4x)
661 nvfx_fp_emit(fpc, arith(0, RFL_NV30, dst, mask, src[0], src[1], none));
662 else {
663 tmp = nvfx_src(temp(fpc));
664 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_X, src[0], src[0], none));
665 nvfx_fp_emit(fpc, arith(0, DP3, tmp.reg, NVFX_FP_MASK_Y, src[0], src[1], none));
666 insn = arith(0, DIV, tmp.reg, NVFX_FP_MASK_Z, swz(tmp, Y, Y, Y, Y), swz(tmp, X, X, X, X), none);
667 insn.scale = NVFX_FP_OP_DST_SCALE_2X;
668 nvfx_fp_emit(fpc, insn);
669 nvfx_fp_emit(fpc, arith(sat, MAD, dst, mask, swz(tmp, Z, Z, Z, Z), src[0], neg(src[1])));
670 }
671 break;
672 case TGSI_OPCODE_RSQ:
673 if(!nvfx->is_nv4x)
674 nvfx_fp_emit(fpc, arith(sat, RSQ_NV30, dst, mask, abs(swz(src[0], X, X, X, X)), none, none));
675 else {
676 tmp = nvfx_src(temp(fpc));
677 insn = arith(0, LG2, tmp.reg, NVFX_FP_MASK_X, abs(swz(src[0], X, X, X, X)), none, none);
678 insn.scale = NVFX_FP_OP_DST_SCALE_INV_2X;
679 nvfx_fp_emit(fpc, insn);
680 nvfx_fp_emit(fpc, arith(sat, EX2, dst, mask, neg(swz(tmp, X, X, X, X)), none, none));
681 }
682 break;
683 case TGSI_OPCODE_SCS:
684 /* avoid overwriting the source */
685 if(src[0].swz[NVFX_SWZ_X] != NVFX_SWZ_X)
686 {
687 if (mask & NVFX_FP_MASK_X)
688 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
689 if (mask & NVFX_FP_MASK_Y)
690 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
691 }
692 else
693 {
694 if (mask & NVFX_FP_MASK_Y)
695 nvfx_fp_emit(fpc, arith(sat, SIN, dst, NVFX_FP_MASK_Y, swz(src[0], X, X, X, X), none, none));
696 if (mask & NVFX_FP_MASK_X)
697 nvfx_fp_emit(fpc, arith(sat, COS, dst, NVFX_FP_MASK_X, swz(src[0], X, X, X, X), none, none));
698 }
699 break;
700 case TGSI_OPCODE_SEQ:
701 nvfx_fp_emit(fpc, arith(sat, SEQ, dst, mask, src[0], src[1], none));
702 break;
703 case TGSI_OPCODE_SFL:
704 nvfx_fp_emit(fpc, arith(sat, SFL, dst, mask, src[0], src[1], none));
705 break;
706 case TGSI_OPCODE_SGE:
707 nvfx_fp_emit(fpc, arith(sat, SGE, dst, mask, src[0], src[1], none));
708 break;
709 case TGSI_OPCODE_SGT:
710 nvfx_fp_emit(fpc, arith(sat, SGT, dst, mask, src[0], src[1], none));
711 break;
712 case TGSI_OPCODE_SIN:
713 nvfx_fp_emit(fpc, arith(sat, SIN, dst, mask, src[0], none, none));
714 break;
715 case TGSI_OPCODE_SLE:
716 nvfx_fp_emit(fpc, arith(sat, SLE, dst, mask, src[0], src[1], none));
717 break;
718 case TGSI_OPCODE_SLT:
719 nvfx_fp_emit(fpc, arith(sat, SLT, dst, mask, src[0], src[1], none));
720 break;
721 case TGSI_OPCODE_SNE:
722 nvfx_fp_emit(fpc, arith(sat, SNE, dst, mask, src[0], src[1], none));
723 break;
724 case TGSI_OPCODE_SSG:
725 tmp = nvfx_src(temp(fpc));
726 tmp2 = nvfx_src(temp(fpc));
727 nvfx_fp_emit(fpc, arith(0, SGT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none));
728 nvfx_fp_emit(fpc, arith(0, SLT, tmp.reg, mask, src[0], nvfx_src(nvfx_reg(NVFXSR_CONST, 0)), none));
729 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, tmp, neg(tmp2), none));
730 break;
731 case TGSI_OPCODE_STR:
732 nvfx_fp_emit(fpc, arith(sat, STR, dst, mask, src[0], src[1], none));
733 break;
734 case TGSI_OPCODE_SUB:
735 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], neg(src[1]), none));
736 break;
737 case TGSI_OPCODE_TEX:
738 nvfx_fp_emit(fpc, tex(sat, TEX, unit, dst, mask, src[0], none, none));
739 break;
740 case TGSI_OPCODE_TRUNC:
741 tmp = nvfx_src(temp(fpc));
742 insn = arith(0, MOV, none.reg, mask, src[0], none, none);
743 insn.cc_update = 1;
744 nvfx_fp_emit(fpc, insn);
745
746 nvfx_fp_emit(fpc, arith(0, FLR, tmp.reg, mask, abs(src[0]), none, none));
747 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, tmp, none, none));
748
749 insn = arith(sat, MOV, dst, mask, neg(tmp), none, none);
750 insn.cc_test = NVFX_COND_LT;
751 nvfx_fp_emit(fpc, insn);
752 break;
753 case TGSI_OPCODE_TXB:
754 nvfx_fp_emit(fpc, tex(sat, TXB, unit, dst, mask, src[0], none, none));
755 break;
756 case TGSI_OPCODE_TXP:
757 nvfx_fp_emit(fpc, tex(sat, TXP, unit, dst, mask, src[0], none, none));
758 break;
759 case TGSI_OPCODE_XPD:
760 tmp = nvfx_src(temp(fpc));
761 nvfx_fp_emit(fpc, arith(0, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
762 nvfx_fp_emit(fpc, arith(sat, MAD, dst, (mask & ~NVFX_FP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
763 break;
764
765 case TGSI_OPCODE_IF:
766 // MOVRC0 R31 (TR0.xyzw), R<src>:
767 // IF (NE.xxxx) ELSE <else> END <end>
768 if(!nvfx->is_nv4x)
769 goto nv3x_cflow;
770 nv40_fp_if(fpc, src[0]);
771 break;
772
773 case TGSI_OPCODE_ELSE:
774 {
775 if(!nvfx->is_nv4x)
776 goto nv3x_cflow;
777 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
778 uint32_t *hw = &fpc->fp->insn[util_dynarray_top(&fpc->if_stack, unsigned)];
779 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
780 break;
781 }
782
783 case TGSI_OPCODE_ENDIF:
784 {
785 if(!nvfx->is_nv4x)
786 goto nv3x_cflow;
787 assert(util_dynarray_contains(&fpc->if_stack, unsigned));
788 uint32_t *hw = &fpc->fp->insn[util_dynarray_pop(&fpc->if_stack, unsigned)];
789 if(!hw[2])
790 hw[2] = NV40_FP_OP_OPCODE_IS_BRANCH | fpc->fp->insn_len;
791 hw[3] = fpc->fp->insn_len;
792 break;
793 }
794
795 case TGSI_OPCODE_BRA:
796 /* This can in limited cases be implemented with an IF with the else and endif labels pointing to the target */
797 /* no state tracker uses this, so don't implement this for now */
798 assert(0);
799 nv40_fp_bra(fpc, finst->Label.Label);
800 break;
801
802 case TGSI_OPCODE_BGNSUB:
803 case TGSI_OPCODE_ENDSUB:
804 /* nothing to do here */
805 break;
806
807 case TGSI_OPCODE_CAL:
808 if(!nvfx->is_nv4x)
809 goto nv3x_cflow;
810 nv40_fp_cal(fpc, finst->Label.Label);
811 break;
812
813 case TGSI_OPCODE_RET:
814 if(!nvfx->is_nv4x)
815 goto nv3x_cflow;
816 nv40_fp_ret(fpc);
817 break;
818
819 case TGSI_OPCODE_BGNLOOP:
820 if(!nvfx->is_nv4x)
821 goto nv3x_cflow;
822 /* TODO: we should support using two nested REPs to allow a > 255 iteration count */
823 nv40_fp_rep(fpc, 255, finst->Label.Label);
824 break;
825
826 case TGSI_OPCODE_ENDLOOP:
827 break;
828
829 case TGSI_OPCODE_BRK:
830 if(!nvfx->is_nv4x)
831 goto nv3x_cflow;
832 nv40_fp_brk(fpc);
833 break;
834
835 case TGSI_OPCODE_CONT:
836 {
837 static int warned = 0;
838 if(!warned) {
839 NOUVEAU_ERR("Sorry, the continue keyword is not implemented: ignoring it.\n");
840 warned = 1;
841 }
842 break;
843 }
844
845 default:
846 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
847 return FALSE;
848 }
849
850 out:
851 release_temps(fpc);
852 return TRUE;
853 nv3x_cflow:
854 {
855 static int warned = 0;
856 if(!warned) {
857 NOUVEAU_ERR(
858 "Sorry, control flow instructions are not supported in hardware on nv3x: ignoring them\n"
859 "If rendering is incorrect, try to disable GLSL support in the application.\n");
860 warned = 1;
861 }
862 }
863 goto out;
864 }
865
866 static boolean
867 nvfx_fragprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_fpc *fpc,
868 const struct tgsi_full_declaration *fdec)
869 {
870 unsigned idx = fdec->Range.First;
871 unsigned hw;
872
873 switch (fdec->Semantic.Name) {
874 case TGSI_SEMANTIC_POSITION:
875 hw = 1;
876 break;
877 case TGSI_SEMANTIC_COLOR:
878 hw = ~0;
879 switch (fdec->Semantic.Index) {
880 case 0: hw = 0; break;
881 case 1: hw = 2; break;
882 case 2: hw = 3; break;
883 case 3: hw = 4; break;
884 }
885 if(hw > ((nvfx->is_nv4x) ? 4 : 2)) {
886 NOUVEAU_ERR("bad rcol index\n");
887 return FALSE;
888 }
889 break;
890 default:
891 NOUVEAU_ERR("bad output semantic\n");
892 return FALSE;
893 }
894
895 fpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
896 fpc->r_temps |= (1 << hw);
897 return TRUE;
898 }
899
900 static boolean
901 nvfx_fragprog_prepare(struct nvfx_context* nvfx, struct nvfx_fpc *fpc)
902 {
903 struct tgsi_parse_context p;
904 int high_temp = -1, i;
905 struct util_semantic_set set;
906 float const0v[4] = {0, 0, 0, 0};
907 struct nvfx_reg const0;
908
909 fpc->fp->num_slots = util_semantic_set_from_program_file(&set, fpc->fp->pipe.tokens, TGSI_FILE_INPUT);
910 if(fpc->fp->num_slots > 8)
911 return FALSE;
912 util_semantic_layout_from_set(fpc->fp->slot_to_generic, &set, 0, 8);
913 util_semantic_table_from_layout(fpc->generic_to_slot, fpc->fp->slot_to_generic, 0, 8);
914
915 memset(fpc->fp->slot_to_fp_input, 0xff, sizeof(fpc->fp->slot_to_fp_input));
916
917 const0 = constant(fpc, -1, const0v);
918 assert(const0.index == 0);
919
920 tgsi_parse_init(&p, fpc->fp->pipe.tokens);
921 while (!tgsi_parse_end_of_tokens(&p)) {
922 const union tgsi_full_token *tok = &p.FullToken;
923
924 tgsi_parse_token(&p);
925 switch(tok->Token.Type) {
926 case TGSI_TOKEN_TYPE_DECLARATION:
927 {
928 const struct tgsi_full_declaration *fdec;
929 fdec = &p.FullToken.FullDeclaration;
930 switch (fdec->Declaration.File) {
931 case TGSI_FILE_OUTPUT:
932 if (!nvfx_fragprog_parse_decl_output(nvfx, fpc, fdec))
933 goto out_err;
934 break;
935 case TGSI_FILE_TEMPORARY:
936 if (fdec->Range.Last > high_temp) {
937 high_temp =
938 fdec->Range.Last;
939 }
940 break;
941 default:
942 break;
943 }
944 }
945 break;
946 case TGSI_TOKEN_TYPE_IMMEDIATE:
947 {
948 struct tgsi_full_immediate *imm;
949 float vals[4];
950
951 imm = &p.FullToken.FullImmediate;
952 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
953 assert(fpc->nr_imm < MAX_IMM);
954
955 vals[0] = imm->u[0].Float;
956 vals[1] = imm->u[1].Float;
957 vals[2] = imm->u[2].Float;
958 vals[3] = imm->u[3].Float;
959 fpc->imm[fpc->nr_imm++] = constant(fpc, -1, vals);
960 }
961 break;
962 default:
963 break;
964 }
965 }
966 tgsi_parse_free(&p);
967
968 if (++high_temp) {
969 fpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
970 for (i = 0; i < high_temp; i++)
971 fpc->r_temp[i] = temp(fpc);
972 fpc->r_temps_discard = 0;
973 }
974
975 return TRUE;
976
977 out_err:
978 if (fpc->r_temp)
979 FREE(fpc->r_temp);
980 tgsi_parse_free(&p);
981 return FALSE;
982 }
983
984 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_fp, "NVFX_DUMP_FP", FALSE)
985
986 static void
987 nvfx_fragprog_translate(struct nvfx_context *nvfx,
988 struct nvfx_fragment_program *fp)
989 {
990 struct tgsi_parse_context parse;
991 struct nvfx_fpc *fpc = NULL;
992 struct util_dynarray insns;
993
994 fpc = CALLOC(1, sizeof(struct nvfx_fpc));
995 if (!fpc)
996 return;
997 fpc->fp = fp;
998 fpc->num_regs = 2;
999
1000 if (!nvfx_fragprog_prepare(nvfx, fpc)) {
1001 FREE(fpc);
1002 return;
1003 }
1004
1005 tgsi_parse_init(&parse, fp->pipe.tokens);
1006
1007 util_dynarray_init(&insns);
1008 while (!tgsi_parse_end_of_tokens(&parse)) {
1009 tgsi_parse_token(&parse);
1010
1011 switch (parse.FullToken.Token.Type) {
1012 case TGSI_TOKEN_TYPE_INSTRUCTION:
1013 {
1014 const struct tgsi_full_instruction *finst;
1015
1016 util_dynarray_append(&insns, unsigned, fp->insn_len);
1017 finst = &parse.FullToken.FullInstruction;
1018 if (!nvfx_fragprog_parse_instruction(nvfx, fpc, finst))
1019 goto out_err;
1020 }
1021 break;
1022 default:
1023 break;
1024 }
1025 }
1026 util_dynarray_append(&insns, unsigned, fp->insn_len);
1027
1028 for(unsigned i = 0; i < fpc->label_relocs.size; i += sizeof(struct nvfx_label_relocation))
1029 {
1030 struct nvfx_label_relocation* label_reloc = (struct nvfx_label_relocation*)((char*)fpc->label_relocs.data + i);
1031 fp->insn[label_reloc->location] |= ((unsigned*)insns.data)[label_reloc->target];
1032 }
1033 util_dynarray_fini(&insns);
1034
1035 if(!nvfx->is_nv4x)
1036 fp->fp_control |= (fpc->num_regs-1)/2;
1037 else
1038 fp->fp_control |= fpc->num_regs << NV40TCL_FP_CONTROL_TEMP_COUNT_SHIFT;
1039
1040 /* Terminate final instruction */
1041 if(fp->insn)
1042 fp->insn[fpc->inst_offset] |= 0x00000001;
1043
1044 /* Append NOP + END instruction for branches to the end of the program */
1045 fpc->inst_offset = fp->insn_len;
1046 grow_insns(fpc, 4);
1047 fp->insn[fpc->inst_offset + 0] = 0x00000001;
1048 fp->insn[fpc->inst_offset + 1] = 0x00000000;
1049 fp->insn[fpc->inst_offset + 2] = 0x00000000;
1050 fp->insn[fpc->inst_offset + 3] = 0x00000000;
1051
1052 if(debug_get_option_nvfx_dump_fp())
1053 {
1054 debug_printf("\n");
1055 tgsi_dump(fp->pipe.tokens, 0);
1056
1057 debug_printf("\n%s fragment program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
1058 for (unsigned i = 0; i < fp->insn_len; i += 4)
1059 debug_printf("%3u: %08x %08x %08x %08x\n", i >> 2, fp->insn[i], fp->insn[i + 1], fp->insn[i + 2], fp->insn[i + 3]);
1060 debug_printf("\n");
1061 }
1062
1063 fp->translated = TRUE;
1064 out_err:
1065 tgsi_parse_free(&parse);
1066 if (fpc->r_temp)
1067 FREE(fpc->r_temp);
1068 util_dynarray_fini(&fpc->if_stack);
1069 util_dynarray_fini(&fpc->label_relocs);
1070 //util_dynarray_fini(&fpc->loop_stack);
1071 FREE(fpc);
1072 }
1073
1074 static inline void
1075 nvfx_fp_memcpy(void* dst, const void* src, size_t len)
1076 {
1077 #ifndef WORDS_BIGENDIAN
1078 memcpy(dst, src, len);
1079 #else
1080 size_t i;
1081 for(i = 0; i < len; i += 4) {
1082 uint32_t v = (uint32_t*)((char*)src + i);
1083 *(uint32_t*)((char*)dst + i) = (v >> 16) | (v << 16);
1084 }
1085 #endif
1086 }
1087
1088 void
1089 nvfx_fragprog_validate(struct nvfx_context *nvfx)
1090 {
1091 struct nouveau_channel* chan = nvfx->screen->base.channel;
1092 struct nvfx_fragment_program *fp = nvfx->fragprog;
1093 int update = 0;
1094
1095 if (!fp->translated)
1096 {
1097 const int min_size = 4096;
1098
1099 nvfx_fragprog_translate(nvfx, fp);
1100 if (!fp->translated) {
1101 static unsigned dummy[8] = {1, 0, 0, 0, 1, 0, 0, 0};
1102 static int warned = 0;
1103 if(!warned)
1104 {
1105 fprintf(stderr, "nvfx: failed to translate fragment program!\n");
1106 warned = 1;
1107 }
1108
1109 /* use dummy program: we cannot fail here */
1110 fp->translated = TRUE;
1111 fp->insn = malloc(sizeof(dummy));
1112 memcpy(fp->insn, dummy, sizeof(dummy));
1113 fp->insn_len = sizeof(dummy) / sizeof(dummy[0]);
1114 }
1115 update = TRUE;
1116
1117 fp->prog_size = (fp->insn_len * 4 + 63) & ~63;
1118
1119 if(fp->prog_size >= min_size)
1120 fp->progs_per_bo = 1;
1121 else
1122 fp->progs_per_bo = min_size / fp->prog_size;
1123 fp->bo_prog_idx = fp->progs_per_bo - 1;
1124 }
1125
1126 /* we must update constants even on "just" fragprog changes, because
1127 we don't check whether the current constant buffer matches the latest
1128 one bound to this fragment program */
1129 if (nvfx->dirty & (NVFX_NEW_FRAGCONST | NVFX_NEW_FRAGPROG))
1130 update = TRUE;
1131
1132 struct nvfx_vertex_program* vp = nvfx->render_mode == HW ? nvfx->vertprog : nvfx->swtnl.vertprog;
1133 if (fp->last_vp_id != vp->id) {
1134 char* vp_sem_table = vp->generic_to_fp_input;
1135 unsigned char* fp_semantics = fp->slot_to_generic;
1136 unsigned diff = 0;
1137 fp->last_vp_id = nvfx->vertprog->id;
1138 unsigned char* cur_slots = fp->slot_to_fp_input;
1139 for(unsigned i = 0; i < fp->num_slots; ++i) {
1140 unsigned char slot_mask = vp_sem_table[fp_semantics[i]];
1141 diff |= (slot_mask >> 4) & (slot_mask ^ cur_slots[i]);
1142 }
1143
1144 if(diff)
1145 {
1146 for(unsigned i = 0; i < fp->num_slots; ++i) {
1147 /* if 0xff, then this will write to the dummy value at fp->last_layout_mask[0] */
1148 fp->slot_to_fp_input[i] = vp_sem_table[fp_semantics[i]] & 0xf;
1149 //printf("fp: GENERIC[%i] from fpreg %i\n", fp_semantics[i], fp->slot_to_fp_input[i]);
1150 }
1151
1152 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
1153 update = TRUE;
1154 }
1155 }
1156
1157 // last_sprite_coord_enable
1158 unsigned sprite_coord_enable = nvfx->rasterizer->pipe.point_quad_rasterization * nvfx->rasterizer->pipe.sprite_coord_enable;
1159 if(fp->last_sprite_coord_enable != sprite_coord_enable)
1160 {
1161 unsigned texcoord_mask = vp->texcoord_ouput_mask;
1162 fp->last_sprite_coord_enable = sprite_coord_enable;
1163 fp->point_sprite_control = 0;
1164 for(unsigned i = 0; i < fp->num_slots; ++i) {
1165 if((1 << fp->slot_to_generic[i]) & sprite_coord_enable)
1166 {
1167 unsigned fpin = fp->slot_to_fp_input[i];
1168 //printf("sprite: slot %i generic %i had texcoord %i\n", i, fp->slot_to_generic[i], fpin - NVFX_FP_OP_INPUT_SRC_TC0);
1169 if(fpin >= 0x0f)
1170 {
1171 unsigned tc = __builtin_ctz(~texcoord_mask);
1172 texcoord_mask |= (1 << tc);
1173 fp->slot_to_fp_input[i] = fpin = NVFX_FP_OP_INPUT_SRC_TC(tc);
1174
1175 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
1176 update = TRUE;
1177 }
1178 //printf("sprite: slot %i texcoord %i\n", i, fpin - NVFX_FP_OP_INPUT_SRC_TC0);
1179 fp->point_sprite_control |= (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0 + 8));
1180 }
1181 else
1182 {
1183 unsigned fpin = fp->slot_to_fp_input[i];
1184 if(!(vp->texcoord_ouput_mask & (1 << (fpin - NVFX_FP_OP_INPUT_SRC_TC0))))
1185 {
1186 fp->slot_to_fp_input[i] = 0x0f;
1187
1188 fp->progs_left_with_obsolete_slot_assignments = fp->progs;
1189 update = TRUE;
1190 }
1191 }
1192 }
1193 }
1194
1195 if(update) {
1196 ++fp->bo_prog_idx;
1197 if(fp->bo_prog_idx >= fp->progs_per_bo)
1198 {
1199 if(fp->fpbo && !nouveau_bo_busy(fp->fpbo->next->bo, NOUVEAU_BO_WR))
1200 {
1201 fp->fpbo = fp->fpbo->next;
1202 }
1203 else
1204 {
1205 struct nvfx_fragment_program_bo* fpbo = os_malloc_aligned(sizeof(struct nvfx_fragment_program) + (fp->prog_size + 8) * fp->progs_per_bo, 16);
1206 fpbo->slots = (unsigned char*)&fpbo->insn[(fp->prog_size) * fp->progs_per_bo];
1207 memset(fpbo->slots, 0, 8 * fp->progs_per_bo);
1208 if(fp->fpbo)
1209 {
1210 fpbo->next = fp->fpbo->next;
1211 fp->fpbo->next = fpbo;
1212 }
1213 else
1214 fpbo->next = fpbo;
1215 fp->fpbo = fpbo;
1216 fpbo->bo = 0;
1217 fp->progs += fp->progs_per_bo;
1218 fp->progs_left_with_obsolete_slot_assignments += fp->progs_per_bo;
1219 nouveau_bo_new(nvfx->screen->base.device, NOUVEAU_BO_VRAM | NOUVEAU_BO_MAP, 64, fp->prog_size * fp->progs_per_bo, &fpbo->bo);
1220 nouveau_bo_map(fpbo->bo, NOUVEAU_BO_NOSYNC);
1221
1222 uint8_t* map = fpbo->bo->map;
1223 uint8_t* buf = (uint8_t*)fpbo->insn;
1224 for(unsigned i = 0; i < fp->progs_per_bo; ++i)
1225 {
1226 memcpy(buf, fp->insn, fp->insn_len * 4);
1227 nvfx_fp_memcpy(map, fp->insn, fp->insn_len * 4);
1228 map += fp->prog_size;
1229 buf += fp->prog_size;
1230 }
1231 }
1232 fp->bo_prog_idx = 0;
1233 }
1234
1235 int offset = fp->bo_prog_idx * fp->prog_size;
1236 uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1237
1238 if(nvfx->constbuf[PIPE_SHADER_FRAGMENT]) {
1239 struct pipe_resource* constbuf = nvfx->constbuf[PIPE_SHADER_FRAGMENT];
1240 uint32_t* map = (uint32_t*)nvfx_buffer(constbuf)->data;
1241 uint32_t* fpmap = (uint32_t*)((char*)fp->fpbo->bo->map + offset);
1242 uint32_t* buf = (uint32_t*)((char*)fp->fpbo->insn + offset);
1243 int i;
1244 for (i = 0; i < fp->nr_consts; ++i) {
1245 unsigned off = fp->consts[i].offset;
1246 unsigned idx = fp->consts[i].index * 4;
1247
1248 /* TODO: is checking a good idea? */
1249 if(memcmp(&buf[off], &map[idx], 4 * sizeof(uint32_t))) {
1250 memcpy(&buf[off], &map[idx], 4 * sizeof(uint32_t));
1251 nvfx_fp_memcpy(&fpmap[off], &map[idx], 4 * sizeof(uint32_t));
1252 }
1253 }
1254 }
1255
1256 if(fp->progs_left_with_obsolete_slot_assignments) {
1257 unsigned char* fpbo_slots = &fp->fpbo->slots[fp->bo_prog_idx * 8];
1258 for(unsigned i = 0; i < fp->num_slots; ++i) {
1259 unsigned value = fp->slot_to_fp_input[i];;
1260 if(value != fpbo_slots[i]) {
1261 unsigned* p = (unsigned*)fp->slot_relocations[i].data;
1262 unsigned* pend = (unsigned*)((char*)fp->slot_relocations[i].data + fp->slot_relocations[i].size);
1263 for(; p != pend; ++p) {
1264 unsigned off = *p;
1265 unsigned dw = fp->insn[off];
1266 dw = (dw & ~NVFX_FP_OP_INPUT_SRC_MASK) | (value << NVFX_FP_OP_INPUT_SRC_SHIFT);
1267 nvfx_fp_memcpy(&fpmap[*p], &dw, sizeof(dw));
1268 }
1269 fpbo_slots[i] = value;
1270 }
1271 }
1272 --fp->progs_left_with_obsolete_slot_assignments;
1273 }
1274 }
1275
1276 if(update || (nvfx->dirty & NVFX_NEW_FRAGPROG)) {
1277 int offset = fp->bo_prog_idx * fp->prog_size;
1278 MARK_RING(chan, 8, 1);
1279 OUT_RING(chan, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1));
1280 OUT_RELOC(chan, fp->fpbo->bo, offset, NOUVEAU_BO_VRAM |
1281 NOUVEAU_BO_GART | NOUVEAU_BO_RD | NOUVEAU_BO_LOW |
1282 NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
1283 NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
1284 OUT_RING(chan, RING_3D(NV34TCL_FP_CONTROL, 1));
1285 OUT_RING(chan, fp->fp_control);
1286 if(!nvfx->is_nv4x) {
1287 OUT_RING(chan, RING_3D(NV34TCL_FP_REG_CONTROL, 1));
1288 OUT_RING(chan, (1<<16)|0x4);
1289 OUT_RING(chan, RING_3D(NV34TCL_TX_UNITS_ENABLE, 1));
1290 OUT_RING(chan, fp->samplers);
1291 }
1292 }
1293
1294 if(nvfx->dirty & (NVFX_NEW_FRAGPROG | NVFX_NEW_SPRITE))
1295 {
1296 WAIT_RING(chan, 2);
1297 OUT_RING(chan, RING_3D(NV34TCL_POINT_SPRITE, 1));
1298 OUT_RING(chan, fp->point_sprite_control | nvfx->rasterizer->pipe.point_quad_rasterization);
1299 }
1300 }
1301
1302 void
1303 nvfx_fragprog_relocate(struct nvfx_context *nvfx)
1304 {
1305 struct nouveau_channel* chan = nvfx->screen->base.channel;
1306 struct nvfx_fragment_program *fp = nvfx->fragprog;
1307 struct nouveau_bo* bo = fp->fpbo->bo;
1308 int offset = fp->bo_prog_idx * fp->prog_size;
1309 unsigned fp_flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD; // TODO: GART?
1310 fp_flags |= NOUVEAU_BO_DUMMY;
1311 MARK_RING(chan, 2, 2);
1312 OUT_RELOC(chan, bo, RING_3D(NV34TCL_FP_ACTIVE_PROGRAM, 1), fp_flags, 0, 0);
1313 OUT_RELOC(chan, bo, offset, fp_flags | NOUVEAU_BO_LOW |
1314 NOUVEAU_BO_OR, NV34TCL_FP_ACTIVE_PROGRAM_DMA0,
1315 NV34TCL_FP_ACTIVE_PROGRAM_DMA1);
1316 }
1317
1318 void
1319 nvfx_fragprog_destroy(struct nvfx_context *nvfx,
1320 struct nvfx_fragment_program *fp)
1321 {
1322 unsigned i;
1323 struct nvfx_fragment_program_bo* fpbo = fp->fpbo;
1324 if(fpbo)
1325 {
1326 do
1327 {
1328 struct nvfx_fragment_program_bo* next = fpbo->next;
1329 nouveau_bo_unmap(fpbo->bo);
1330 nouveau_bo_ref(0, &fpbo->bo);
1331 free(fpbo);
1332 fpbo = next;
1333 }
1334 while(fpbo != fp->fpbo);
1335 }
1336
1337 for(i = 0; i < 8; ++i)
1338 util_dynarray_fini(&fp->slot_relocations[i]);
1339
1340 if (fp->insn_len)
1341 FREE(fp->insn);
1342 }