1 #include "pipe/p_screen.h"
2 #include "pipe/p_state.h"
3 #include "util/u_format.h"
4 #include "util/u_format_s3tc.h"
5 #include "util/u_simple_screen.h"
7 #include "nouveau/nouveau_screen.h"
8 #include "nouveau/nv_object.xml.h"
9 #include "nvfx_context.h"
10 #include "nvfx_screen.h"
11 #include "nvfx_resource.h"
14 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
15 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
16 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
18 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
19 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
20 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
23 nvfx_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
25 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
28 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
30 case PIPE_CAP_NPOT_TEXTURES
:
31 return screen
->advertise_npot
;
32 case PIPE_CAP_TWO_SIDED_STENCIL
:
36 case PIPE_CAP_ANISOTROPIC_FILTER
:
38 case PIPE_CAP_POINT_SPRITE
:
40 case PIPE_CAP_MAX_RENDER_TARGETS
:
41 return screen
->use_nv4x
? 4 : 1;
42 case PIPE_CAP_OCCLUSION_QUERY
:
44 case PIPE_CAP_TIMER_QUERY
:
46 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
48 case PIPE_CAP_TEXTURE_SWIZZLE
:
50 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
52 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
54 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
56 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
57 return !!screen
->use_nv4x
;
58 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
60 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
61 return 0; /* We have 4 on nv40 - but unsupported currently */
62 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
63 return screen
->advertise_blend_equation_separate
;
64 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
66 case PIPE_CAP_INDEP_BLEND_ENABLE
:
67 /* TODO: on nv40 we have separate color masks */
68 /* TODO: nv40 mrt blending is probably broken */
70 case PIPE_CAP_INDEP_BLEND_FUNC
:
72 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
74 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
75 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
76 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
77 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
79 case PIPE_CAP_DEPTH_CLAMP
:
80 return 0; // TODO: implement depth clamp
81 case PIPE_CAP_PRIMITIVE_RESTART
:
82 return 0; // TODO: implement primitive restart
83 case PIPE_CAP_ARRAY_TEXTURES
:
84 case PIPE_CAP_TGSI_INSTANCEID
:
85 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
86 case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL
:
87 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
88 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
89 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
91 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
94 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param
);
100 nvfx_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
, enum pipe_shader_cap param
)
102 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
105 case PIPE_SHADER_FRAGMENT
:
107 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
108 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
109 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
110 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
112 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
113 /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
114 value (nv30:0/nv40:4) ? */
115 return screen
->use_nv4x
? 4 : 0;
116 case PIPE_SHADER_CAP_MAX_INPUTS
:
117 return screen
->use_nv4x
? 12 : 10;
118 case PIPE_SHADER_CAP_MAX_CONSTS
:
119 return screen
->use_nv4x
? 224 : 32;
120 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
122 case PIPE_SHADER_CAP_MAX_TEMPS
:
124 case PIPE_SHADER_CAP_MAX_ADDRS
:
125 return screen
->use_nv4x
? 1 : 0;
126 case PIPE_SHADER_CAP_MAX_PREDS
:
127 return 0; /* we could expose these, but nothing uses them */
128 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
130 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
131 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
132 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
133 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
135 case PIPE_SHADER_CAP_SUBROUTINES
:
136 return screen
->use_nv4x
? 1 : 0;
141 case PIPE_SHADER_VERTEX
:
143 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
144 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
145 return screen
->use_nv4x
? 512 : 256;
146 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
147 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
148 return screen
->use_nv4x
? 512 : 0;
149 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
150 /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
151 value (nv30:1/nv40:4) ? */
152 return screen
->use_nv4x
? 4 : 1;
153 case PIPE_SHADER_CAP_MAX_INPUTS
:
155 case PIPE_SHADER_CAP_MAX_CONSTS
:
156 /* - 6 is for clip planes; Gallium should be fixed to put
157 * them in the vertex shader itself, so we don't need to reserve these */
158 return (screen
->use_nv4x
? 468 : 256) - 6;
159 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
161 case PIPE_SHADER_CAP_MAX_TEMPS
:
162 return screen
->use_nv4x
? 32 : 13;
163 case PIPE_SHADER_CAP_MAX_ADDRS
:
165 case PIPE_SHADER_CAP_MAX_PREDS
:
166 return 0; /* we could expose these, but nothing uses them */
167 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
169 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
170 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
171 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
173 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
175 case PIPE_SHADER_CAP_SUBROUTINES
:
188 nvfx_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_cap param
)
190 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
193 case PIPE_CAP_MAX_LINE_WIDTH
:
194 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
196 case PIPE_CAP_MAX_POINT_WIDTH
:
197 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
199 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
200 return screen
->use_nv4x
? 16.0 : 8.0;
201 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
204 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
210 nvfx_screen_is_format_supported(struct pipe_screen
*pscreen
,
211 enum pipe_format format
,
212 enum pipe_texture_target target
,
213 unsigned sample_count
,
216 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
218 if (!util_format_is_supported(format
, bind
))
221 if (sample_count
> 1)
224 if (bind
& PIPE_BIND_RENDER_TARGET
) {
226 case PIPE_FORMAT_B8G8R8A8_UNORM
:
227 case PIPE_FORMAT_B8G8R8X8_UNORM
:
228 case PIPE_FORMAT_R8G8B8A8_UNORM
:
229 case PIPE_FORMAT_R8G8B8X8_UNORM
:
230 case PIPE_FORMAT_B5G6R5_UNORM
:
232 case PIPE_FORMAT_R16G16B16A16_FLOAT
:
233 if(!screen
->advertise_fp16
)
236 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
237 if(!screen
->advertise_fp32
)
245 if (bind
& PIPE_BIND_DEPTH_STENCIL
) {
247 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
248 case PIPE_FORMAT_X8Z24_UNORM
:
249 case PIPE_FORMAT_Z16_UNORM
:
256 if (bind
& PIPE_BIND_SAMPLER_VIEW
) {
257 struct nvfx_texture_format
* tf
= &nvfx_texture_formats
[format
];
258 if(util_format_is_s3tc(format
) && !util_format_s3tc_enabled
)
260 if(format
== PIPE_FORMAT_R16G16B16A16_FLOAT
&& !screen
->advertise_fp16
)
262 if(format
== PIPE_FORMAT_R32G32B32A32_FLOAT
&& !screen
->advertise_fp32
)
276 // note that we do actually support everything through translate
277 if (bind
& PIPE_BIND_VERTEX_BUFFER
) {
278 unsigned type
= nvfx_vertex_formats
[format
];
283 if (bind
& PIPE_BIND_INDEX_BUFFER
) {
284 // 8-bit indices supported, but not in hardware index buffer
285 if(format
!= PIPE_FORMAT_R16_USCALED
&& format
!= PIPE_FORMAT_R32_USCALED
)
289 if(bind
& PIPE_BIND_STREAM_OUTPUT
)
296 nvfx_screen_destroy(struct pipe_screen
*pscreen
)
298 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
300 nouveau_resource_destroy(&screen
->vp_exec_heap
);
301 nouveau_resource_destroy(&screen
->vp_data_heap
);
302 nouveau_resource_destroy(&screen
->query_heap
);
303 nouveau_notifier_free(&screen
->query
);
304 nouveau_notifier_free(&screen
->sync
);
305 nouveau_grobj_free(&screen
->eng3d
);
306 nvfx_screen_surface_takedown(pscreen
);
308 nouveau_screen_fini(&screen
->base
);
313 static void nv30_screen_init(struct nvfx_screen
*screen
)
315 struct nouveau_channel
*chan
= screen
->base
.channel
;
316 struct nouveau_grobj
*eng3d
= screen
->eng3d
;
319 /* TODO: perhaps we should do some of this on nv40 too? */
320 for (i
=1; i
<8; i
++) {
321 BEGIN_RING(chan
, eng3d
, NV30_3D_VIEWPORT_CLIP_HORIZ(i
), 1);
323 BEGIN_RING(chan
, eng3d
, NV30_3D_VIEWPORT_CLIP_VERT(i
), 1);
327 BEGIN_RING(chan
, eng3d
, 0x220, 1);
330 BEGIN_RING(chan
, eng3d
, 0x03b0, 1);
331 OUT_RING(chan
, 0x00100000);
332 BEGIN_RING(chan
, eng3d
, 0x1454, 1);
334 BEGIN_RING(chan
, eng3d
, 0x1d80, 1);
336 BEGIN_RING(chan
, eng3d
, 0x1450, 1);
337 OUT_RING(chan
, 0x00030004);
340 BEGIN_RING(chan
, eng3d
, 0x1e98, 1);
342 BEGIN_RING(chan
, eng3d
, 0x17e0, 3);
343 OUT_RING(chan
, fui(0.0));
344 OUT_RING(chan
, fui(0.0));
345 OUT_RING(chan
, fui(1.0));
346 BEGIN_RING(chan
, eng3d
, 0x1f80, 16);
347 for (i
=0; i
<16; i
++) {
348 OUT_RING(chan
, (i
==8) ? 0x0000ffff : 0);
351 BEGIN_RING(chan
, eng3d
, 0x120, 3);
356 BEGIN_RING(chan
, eng3d
, 0x1d88, 1);
357 OUT_RING(chan
, 0x00001200);
359 BEGIN_RING(chan
, eng3d
, NV30_3D_RC_ENABLE
, 1);
362 BEGIN_RING(chan
, eng3d
, NV30_3D_DEPTH_RANGE_NEAR
, 2);
363 OUT_RING(chan
, fui(0.0));
364 OUT_RING(chan
, fui(1.0));
366 BEGIN_RING(chan
, eng3d
, NV30_3D_MULTISAMPLE_CONTROL
, 1);
367 OUT_RING(chan
, 0xffff0000);
369 /* enables use of vp rather than fixed-function somehow */
370 BEGIN_RING(chan
, eng3d
, 0x1e94, 1);
371 OUT_RING(chan
, 0x13);
374 static void nv40_screen_init(struct nvfx_screen
*screen
)
376 struct nouveau_channel
*chan
= screen
->base
.channel
;
377 struct nouveau_grobj
*eng3d
= screen
->eng3d
;
379 BEGIN_RING(chan
, eng3d
, NV40_3D_DMA_COLOR2
, 2);
380 OUT_RING(chan
, screen
->base
.channel
->vram
->handle
);
381 OUT_RING(chan
, screen
->base
.channel
->vram
->handle
);
383 BEGIN_RING(chan
, eng3d
, 0x1450, 1);
384 OUT_RING(chan
, 0x00000004);
386 BEGIN_RING(chan
, eng3d
, 0x1ea4, 3);
387 OUT_RING(chan
, 0x00000010);
388 OUT_RING(chan
, 0x01000100);
389 OUT_RING(chan
, 0xff800006);
391 /* vtxprog output routing */
392 BEGIN_RING(chan
, eng3d
, 0x1fc4, 1);
393 OUT_RING(chan
, 0x06144321);
394 BEGIN_RING(chan
, eng3d
, 0x1fc8, 2);
395 OUT_RING(chan
, 0xedcba987);
396 OUT_RING(chan
, 0x0000006f);
397 BEGIN_RING(chan
, eng3d
, 0x1fd0, 1);
398 OUT_RING(chan
, 0x00171615);
399 BEGIN_RING(chan
, eng3d
, 0x1fd4, 1);
400 OUT_RING(chan
, 0x001b1a19);
402 BEGIN_RING(chan
, eng3d
, 0x1ef8, 1);
403 OUT_RING(chan
, 0x0020ffff);
404 BEGIN_RING(chan
, eng3d
, 0x1d64, 1);
405 OUT_RING(chan
, 0x01d300d4);
406 BEGIN_RING(chan
, eng3d
, 0x1e94, 1);
407 OUT_RING(chan
, 0x00000001);
409 BEGIN_RING(chan
, eng3d
, NV40_3D_MIPMAP_ROUNDING
, 1);
410 OUT_RING(chan
, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN
);
414 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen
* screen
)
416 int vram_hack_default
= 0;
418 // TODO: this is a bit of a guess; also add other cards that may need this hack.
419 // It may also depend on the specific card or the AGP/PCIe chipset.
420 if(screen
->base
.device
->chipset
== 0x47 /* G70 */
421 || screen
->base
.device
->chipset
== 0x49 /* G71 */
422 || screen
->base
.device
->chipset
== 0x46 /* G72 */
424 vram_hack_default
= 1;
425 vram_hack
= debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default
);
427 return vram_hack
? NOUVEAU_BO_VRAM
: NOUVEAU_BO_GART
;
430 static void nvfx_channel_flush_notify(struct nouveau_channel
* chan
)
432 struct nvfx_screen
* screen
= chan
->user_private
;
433 struct nvfx_context
* nvfx
= screen
->cur_ctx
;
435 nvfx
->relocs_needed
= NVFX_RELOCATE_ALL
;
439 nvfx_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
441 static const unsigned query_sizes
[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
442 struct nvfx_screen
*screen
= CALLOC_STRUCT(nvfx_screen
);
443 struct nouveau_channel
*chan
;
444 struct pipe_screen
*pscreen
;
445 unsigned eng3d_class
= 0;
451 pscreen
= &screen
->base
.base
;
453 ret
= nouveau_screen_init(&screen
->base
, dev
);
455 nvfx_screen_destroy(pscreen
);
458 chan
= screen
->base
.channel
;
459 screen
->cur_ctx
= NULL
;
460 chan
->user_private
= screen
;
461 chan
->flush_notify
= nvfx_channel_flush_notify
;
463 pscreen
->winsys
= ws
;
464 pscreen
->destroy
= nvfx_screen_destroy
;
465 pscreen
->get_param
= nvfx_screen_get_param
;
466 pscreen
->get_shader_param
= nvfx_screen_get_shader_param
;
467 pscreen
->get_paramf
= nvfx_screen_get_paramf
;
468 pscreen
->is_format_supported
= nvfx_screen_is_format_supported
;
469 pscreen
->context_create
= nvfx_create
;
471 switch (dev
->chipset
& 0xf0) {
473 if (NV30_3D_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
474 eng3d_class
= NV30_3D
;
475 else if (NV34_3D_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
476 eng3d_class
= NV34_3D
;
477 else if (NV35_3D_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
478 eng3d_class
= NV35_3D
;
481 if (NV4X_GRCLASS4097_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
482 eng3d_class
= NV40_3D
;
483 else if (NV4X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
484 eng3d_class
= NV44_3D
;
485 screen
->is_nv4x
= ~0;
488 if (NV6X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
489 eng3d_class
= NV44_3D
;
490 screen
->is_nv4x
= ~0;
495 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev
->chipset
);
499 screen
->advertise_npot
= !!screen
->is_nv4x
;
500 screen
->advertise_blend_equation_separate
= !!screen
->is_nv4x
;
501 screen
->use_nv4x
= screen
->is_nv4x
;
503 if(screen
->is_nv4x
) {
504 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE
))
505 screen
->use_nv4x
= 0;
506 if(!debug_get_bool_option("NVFX_NPOT", TRUE
))
507 screen
->advertise_npot
= 0;
508 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE
))
509 screen
->advertise_blend_equation_separate
= 0;
512 screen
->force_swtnl
= debug_get_bool_option("NVFX_SWTNL", FALSE
);
513 screen
->trace_draw
= debug_get_bool_option("NVFX_TRACE_DRAW", FALSE
);
515 screen
->buffer_allocation_cost
= debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
516 screen
->inline_cost_per_hardware_cost
= atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
517 screen
->static_reuse_threshold
= atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
519 /* We don't advertise these by default because filtering and blending doesn't work as
520 * it should, due to several restrictions.
521 * The only exception is fp16 on nv40.
523 screen
->advertise_fp16
= debug_get_bool_option("NVFX_FP16", !!screen
->use_nv4x
);
524 screen
->advertise_fp32
= debug_get_bool_option("NVFX_FP32", 0);
526 screen
->vertex_buffer_reloc_flags
= nvfx_screen_get_vertex_buffer_flags(screen
);
528 /* surely both nv3x and nv44 support index buffers too: find out how and test that */
529 if(eng3d_class
== NV40_3D
)
530 screen
->index_buffer_reloc_flags
= screen
->vertex_buffer_reloc_flags
;
532 if(!screen
->force_swtnl
&& screen
->vertex_buffer_reloc_flags
== screen
->index_buffer_reloc_flags
)
533 screen
->base
.vertex_buffer_flags
= screen
->base
.index_buffer_flags
= screen
->vertex_buffer_reloc_flags
;
535 nvfx_screen_init_resource_functions(pscreen
);
537 ret
= nouveau_grobj_alloc(chan
, 0xbeef3097, eng3d_class
, &screen
->eng3d
);
539 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
543 /* 2D engine setup */
544 nvfx_screen_surface_init(pscreen
);
546 /* Notifier for sync purposes */
547 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
549 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
550 nvfx_screen_destroy(pscreen
);
555 for(i
= 0; i
< sizeof(query_sizes
) / sizeof(query_sizes
[0]); ++i
)
557 ret
= nouveau_notifier_alloc(chan
, 0xbeef0302, query_sizes
[i
], &screen
->query
);
563 NOUVEAU_ERR("Error initialising query objects: %d\n", ret
);
564 nvfx_screen_destroy(pscreen
);
568 ret
= nouveau_resource_init(&screen
->query_heap
, 0, query_sizes
[i
]);
570 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret
);
571 nvfx_screen_destroy(pscreen
);
575 LIST_INITHEAD(&screen
->query_list
);
577 /* Vtxprog resources */
578 if (nouveau_resource_init(&screen
->vp_exec_heap
, 0, screen
->use_nv4x
? 512 : 256) ||
579 nouveau_resource_init(&screen
->vp_data_heap
, 0, screen
->use_nv4x
? 468 : 256)) {
580 nvfx_screen_destroy(pscreen
);
584 BIND_RING(chan
, screen
->eng3d
, 7);
586 /* Static eng3d initialisation */
587 /* note that we just started using the channel, so we must have space in the pushbuffer */
588 BEGIN_RING(chan
, screen
->eng3d
, NV30_3D_DMA_NOTIFY
, 1);
589 OUT_RING(chan
, screen
->sync
->handle
);
590 BEGIN_RING(chan
, screen
->eng3d
, NV30_3D_DMA_TEXTURE0
, 2);
591 OUT_RING(chan
, chan
->vram
->handle
);
592 OUT_RING(chan
, chan
->gart
->handle
);
593 BEGIN_RING(chan
, screen
->eng3d
, NV30_3D_DMA_COLOR1
, 1);
594 OUT_RING(chan
, chan
->vram
->handle
);
595 BEGIN_RING(chan
, screen
->eng3d
, NV30_3D_DMA_COLOR0
, 2);
596 OUT_RING(chan
, chan
->vram
->handle
);
597 OUT_RING(chan
, chan
->vram
->handle
);
598 BEGIN_RING(chan
, screen
->eng3d
, NV30_3D_DMA_VTXBUF0
, 2);
599 OUT_RING(chan
, chan
->vram
->handle
);
600 OUT_RING(chan
, chan
->gart
->handle
);
602 BEGIN_RING(chan
, screen
->eng3d
, NV30_3D_DMA_FENCE
, 2);
604 OUT_RING(chan
, screen
->query
->handle
);
606 BEGIN_RING(chan
, screen
->eng3d
, NV30_3D_DMA_UNK1AC
, 2);
607 OUT_RING(chan
, chan
->vram
->handle
);
608 OUT_RING(chan
, chan
->vram
->handle
);
611 nv30_screen_init(screen
);
613 nv40_screen_init(screen
);