src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format.h"
   4 #include "util/u_format_s3tc.h"
   5 #include "util/u_simple_screen.h"
   6
   7 #include "nouveau/nouveau_screen.h"
   8 #include "nouveau/nv_object.xml.h"
   9 #include "nvfx_context.h"
  10 #include "nvfx_screen.h"
  11 #include "nvfx_resource.h"
  12 #include "nvfx_tex.h"
  13
  14 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  15 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  16 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  17
  18 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  19 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  20 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  21
  22 static int
  23 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  24 {
  25         struct nvfx_screen *screen = nvfx_screen(pscreen);
  26
  27         switch (param) {
  28         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  29                 return 16;
  30         case PIPE_CAP_NPOT_TEXTURES:
  31                 return screen->advertise_npot;
  32         case PIPE_CAP_TWO_SIDED_STENCIL:
  33                 return 1;
  34         case PIPE_CAP_GLSL:
  35                 return 1;
  36         case PIPE_CAP_ANISOTROPIC_FILTER:
  37                 return 1;
  38         case PIPE_CAP_POINT_SPRITE:
  39                 return 1;
  40         case PIPE_CAP_MAX_RENDER_TARGETS:
  41                 return screen->use_nv4x ? 4 : 1;
  42         case PIPE_CAP_OCCLUSION_QUERY:
  43                 return 1;
  44         case PIPE_CAP_TIMER_QUERY:
  45                 return 0;
  46         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  47                 return 1;
  48         case PIPE_CAP_TEXTURE_SWIZZLE:
  49                 return 1;
  50         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  51                 return 13;
  52         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  53                 return 10;
  54         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  55                 return 13;
  56         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  57                 return !!screen->use_nv4x;
  58         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  59                 return 1;
  60         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  61                 return 0; /* We have 4 on nv40 - but unsupported currently */
  62         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  63                 return screen->advertise_blend_equation_separate;
  64         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  65                 return 16;
  66         case PIPE_CAP_INDEP_BLEND_ENABLE:
  67                 /* TODO: on nv40 we have separate color masks */
  68                 /* TODO: nv40 mrt blending is probably broken */
  69                 return 0;
  70         case PIPE_CAP_INDEP_BLEND_FUNC:
  71                 return 0;
  72         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  73                 return 0;
  74         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  75         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  76         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  77         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  78                 return 1;
  79         case PIPE_CAP_DEPTH_CLAMP:
  80                 return 0; // TODO: implement depth clamp
  81         case PIPE_CAP_PRIMITIVE_RESTART:
  82                 return 0; // TODO: implement primitive restart
  83         case PIPE_CAP_ARRAY_TEXTURES:
  84         case PIPE_CAP_TGSI_INSTANCEID:
  85         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  86         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  87         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  88         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  89         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  90                 return 0;
  91         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  92                 return 0;
  93         default:
  94                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  95                 return 0;
  96         }
  97 }
  98
  99 static int
 100 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 101 {
 102         struct nvfx_screen *screen = nvfx_screen(pscreen);
 103
 104         switch(shader) {
 105         case PIPE_SHADER_FRAGMENT:
 106                 switch(param) {
 107                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 108                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 109                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 110                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 111                         return 4096;
 112                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 113                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 114                          value (nv30:0/nv40:4) ? */
 115                         return screen->use_nv4x ? 4 : 0;
 116                 case PIPE_SHADER_CAP_MAX_INPUTS:
 117                         return screen->use_nv4x ? 12 : 10;
 118                 case PIPE_SHADER_CAP_MAX_CONSTS:
 119                         return screen->use_nv4x ? 224 : 32;
 120                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 121                     return 1;
 122                 case PIPE_SHADER_CAP_MAX_TEMPS:
 123                         return 32;
 124                 case PIPE_SHADER_CAP_MAX_ADDRS:
 125                         return screen->use_nv4x ? 1 : 0;
 126                 case PIPE_SHADER_CAP_MAX_PREDS:
 127                         return 0; /* we could expose these, but nothing uses them */
 128                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 129                     return 0;
 130                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 131                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 132                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 133                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 134                         return 0;
 135                 case PIPE_SHADER_CAP_SUBROUTINES:
 136                         return screen->use_nv4x ? 1 : 0;
 137                 default:
 138                         break;
 139                 }
 140                 break;
 141         case PIPE_SHADER_VERTEX:
 142                 switch(param) {
 143                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 144                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 145                         return screen->use_nv4x ? 512 : 256;
 146                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 147                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 148                         return screen->use_nv4x ? 512 : 0;
 149                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 150                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 151                          value (nv30:1/nv40:4) ? */
 152                         return screen->use_nv4x ? 4 : 1;
 153                 case PIPE_SHADER_CAP_MAX_INPUTS:
 154                         return 16;
 155                 case PIPE_SHADER_CAP_MAX_CONSTS:
 156                         /* - 6 is for clip planes; Gallium should be fixed to put
 157                          * them in the vertex shader itself, so we don't need to reserve these */
 158                         return (screen->use_nv4x ? 468 : 256) - 6;
 159                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 160                             return 1;
 161                 case PIPE_SHADER_CAP_MAX_TEMPS:
 162                         return screen->use_nv4x ? 32 : 13;
 163                 case PIPE_SHADER_CAP_MAX_ADDRS:
 164                         return 2;
 165                 case PIPE_SHADER_CAP_MAX_PREDS:
 166                         return 0; /* we could expose these, but nothing uses them */
 167                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 168                         return 1;
 169                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 170                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 171                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 172                         return 0;
 173                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 174                         return 1;
 175                 case PIPE_SHADER_CAP_SUBROUTINES:
 176                         return 1;
 177                 default:
 178                         break;
 179                 }
 180                 break;
 181         default:
 182                 break;
 183         }
 184         return 0;
 185 }
 186
 187 static float
 188 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 189 {
 190         struct nvfx_screen *screen = nvfx_screen(pscreen);
 191
 192         switch (param) {
 193         case PIPE_CAP_MAX_LINE_WIDTH:
 194         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 195                 return 10.0;
 196         case PIPE_CAP_MAX_POINT_WIDTH:
 197         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 198                 return 64.0;
 199         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 200                 return screen->use_nv4x ? 16.0 : 8.0;
 201         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 202                 return 15.0;
 203         default:
 204                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 205                 return 0.0;
 206         }
 207 }
 208
 209 static boolean
 210 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 211                                      enum pipe_format format,
 212                                      enum pipe_texture_target target,
 213                                      unsigned sample_count,
 214                                      unsigned bind)
 215 {
 216         struct nvfx_screen *screen = nvfx_screen(pscreen);
 217
 218         if (!util_format_is_supported(format, bind))
 219                 return FALSE;
 220
 221          if (sample_count > 1)
 222                 return FALSE;
 223
 224         if (bind & PIPE_BIND_RENDER_TARGET) {
 225                 switch (format) {
 226                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 227                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 228                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 229                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 230                 case PIPE_FORMAT_B5G6R5_UNORM:
 231                         break;
 232                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 233                         if(!screen->advertise_fp16)
 234                                 return FALSE;
 235                         break;
 236                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 237                         if(!screen->advertise_fp32)
 238                                 return FALSE;
 239                         break;
 240                 default:
 241                         return FALSE;
 242                 }
 243         }
 244
 245         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 246                 switch (format) {
 247                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 248                 case PIPE_FORMAT_X8Z24_UNORM:
 249                 case PIPE_FORMAT_Z16_UNORM:
 250                         break;
 251                 default:
 252                         return FALSE;
 253                 }
 254         }
 255
 256         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 257                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 258                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 259                         return FALSE;
 260                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 261                         return FALSE;
 262                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 263                         return FALSE;
 264                 if(screen->use_nv4x)
 265                 {
 266                         if(tf->fmt[4] < 0)
 267                                 return FALSE;
 268                 }
 269                 else
 270                 {
 271                         if(tf->fmt[0] < 0)
 272                                 return FALSE;
 273                 }
 274         }
 275
 276         // note that we do actually support everything through translate
 277         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 278                 unsigned type = nvfx_vertex_formats[format];
 279                 if(!type)
 280                         return FALSE;
 281         }
 282
 283         if (bind & PIPE_BIND_INDEX_BUFFER) {
 284                 // 8-bit indices supported, but not in hardware index buffer
 285                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 286                         return FALSE;
 287         }
 288
 289         if(bind & PIPE_BIND_STREAM_OUTPUT)
 290                 return FALSE;
 291
 292         return TRUE;
 293 }
 294
 295 static void
 296 nvfx_screen_destroy(struct pipe_screen *pscreen)
 297 {
 298         struct nvfx_screen *screen = nvfx_screen(pscreen);
 299
 300         nouveau_resource_destroy(&screen->vp_exec_heap);
 301         nouveau_resource_destroy(&screen->vp_data_heap);
 302         nouveau_resource_destroy(&screen->query_heap);
 303         nouveau_notifier_free(&screen->query);
 304         nouveau_notifier_free(&screen->sync);
 305         nouveau_grobj_free(&screen->eng3d);
 306         nvfx_screen_surface_takedown(pscreen);
 307
 308         nouveau_screen_fini(&screen->base);
 309
 310         FREE(pscreen);
 311 }
 312
 313 static void nv30_screen_init(struct nvfx_screen *screen)
 314 {
 315         struct nouveau_channel *chan = screen->base.channel;
 316         struct nouveau_grobj *eng3d = screen->eng3d;
 317         int i;
 318
 319         /* TODO: perhaps we should do some of this on nv40 too? */
 320         for (i=1; i<8; i++) {
 321                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 322                 OUT_RING(chan, 0);
 323                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 324                 OUT_RING(chan, 0);
 325         }
 326
 327         BEGIN_RING(chan, eng3d, 0x220, 1);
 328         OUT_RING(chan, 1);
 329
 330         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 331         OUT_RING(chan, 0x00100000);
 332         BEGIN_RING(chan, eng3d, 0x1454, 1);
 333         OUT_RING(chan, 0);
 334         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 335         OUT_RING(chan, 3);
 336         BEGIN_RING(chan, eng3d, 0x1450, 1);
 337         OUT_RING(chan, 0x00030004);
 338
 339         /* NEW */
 340         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 341         OUT_RING(chan, 0);
 342         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 343         OUT_RING(chan, fui(0.0));
 344         OUT_RING(chan, fui(0.0));
 345         OUT_RING(chan, fui(1.0));
 346         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 347         for (i=0; i<16; i++) {
 348                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 349         }
 350
 351         BEGIN_RING(chan, eng3d, 0x120, 3);
 352         OUT_RING(chan, 0);
 353         OUT_RING(chan, 1);
 354         OUT_RING(chan, 2);
 355
 356         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 357         OUT_RING(chan, 0x00001200);
 358
 359         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 360         OUT_RING(chan, 0);
 361
 362         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 363         OUT_RING(chan, fui(0.0));
 364         OUT_RING(chan, fui(1.0));
 365
 366         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 367         OUT_RING(chan, 0xffff0000);
 368
 369         /* enables use of vp rather than fixed-function somehow */
 370         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 371         OUT_RING(chan, 0x13);
 372 }
 373
 374 static void nv40_screen_init(struct nvfx_screen *screen)
 375 {
 376         struct nouveau_channel *chan = screen->base.channel;
 377         struct nouveau_grobj *eng3d = screen->eng3d;
 378
 379         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 380         OUT_RING(chan, screen->base.channel->vram->handle);
 381         OUT_RING(chan, screen->base.channel->vram->handle);
 382
 383         BEGIN_RING(chan, eng3d, 0x1450, 1);
 384         OUT_RING(chan, 0x00000004);
 385
 386         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 387         OUT_RING(chan, 0x00000010);
 388         OUT_RING(chan, 0x01000100);
 389         OUT_RING(chan, 0xff800006);
 390
 391         /* vtxprog output routing */
 392         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 393         OUT_RING(chan, 0x06144321);
 394         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 395         OUT_RING(chan, 0xedcba987);
 396         OUT_RING(chan, 0x0000006f);
 397         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 398         OUT_RING(chan, 0x00171615);
 399         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 400         OUT_RING(chan, 0x001b1a19);
 401
 402         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 403         OUT_RING(chan, 0x0020ffff);
 404         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 405         OUT_RING(chan, 0x01d300d4);
 406         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 407         OUT_RING(chan, 0x00000001);
 408
 409         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 410         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 411 }
 412
 413 static unsigned
 414 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 415 {
 416         int vram_hack_default = 0;
 417         int vram_hack;
 418         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 419         // It may also depend on the specific card or the AGP/PCIe chipset.
 420         if(screen->base.device->chipset == 0x47 /* G70 */
 421                 || screen->base.device->chipset == 0x49 /* G71 */
 422                 || screen->base.device->chipset == 0x46 /* G72 */
 423                 )
 424                 vram_hack_default = 1;
 425         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 426
 427         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 428 }
 429
 430 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 431 {
 432         struct nvfx_screen* screen = chan->user_private;
 433         struct nvfx_context* nvfx = screen->cur_ctx;
 434         if(nvfx)
 435                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 436 }
 437
 438 struct pipe_screen *
 439 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 440 {
 441         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 442         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 443         struct nouveau_channel *chan;
 444         struct pipe_screen *pscreen;
 445         unsigned eng3d_class = 0;
 446         int ret, i;
 447
 448         if (!screen)
 449                 return NULL;
 450
 451         pscreen = &screen->base.base;
 452
 453         ret = nouveau_screen_init(&screen->base, dev);
 454         if (ret) {
 455                 nvfx_screen_destroy(pscreen);
 456                 return NULL;
 457         }
 458         chan = screen->base.channel;
 459         screen->cur_ctx = NULL;
 460         chan->user_private = screen;
 461         chan->flush_notify = nvfx_channel_flush_notify;
 462
 463         pscreen->winsys = ws;
 464         pscreen->destroy = nvfx_screen_destroy;
 465         pscreen->get_param = nvfx_screen_get_param;
 466         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 467         pscreen->get_paramf = nvfx_screen_get_paramf;
 468         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 469         pscreen->context_create = nvfx_create;
 470
 471         switch (dev->chipset & 0xf0) {
 472         case 0x30:
 473                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 474                         eng3d_class = NV30_3D;
 475                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 476                         eng3d_class = NV34_3D;
 477                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 478                         eng3d_class = NV35_3D;
 479                 break;
 480         case 0x40:
 481                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 482                         eng3d_class = NV40_3D;
 483                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 484                         eng3d_class = NV44_3D;
 485                 screen->is_nv4x = ~0;
 486                 break;
 487         case 0x60:
 488                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 489                         eng3d_class = NV44_3D;
 490                 screen->is_nv4x = ~0;
 491                 break;
 492         }
 493
 494         if (!eng3d_class) {
 495                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 496                 return NULL;
 497         }
 498
 499         screen->advertise_npot = !!screen->is_nv4x;
 500         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 501         screen->use_nv4x = screen->is_nv4x;
 502
 503         if(screen->is_nv4x) {
 504                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 505                         screen->use_nv4x = 0;
 506                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 507                         screen->advertise_npot = 0;
 508                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 509                         screen->advertise_blend_equation_separate = 0;
 510         }
 511
 512         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 513         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 514
 515         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 516         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 517         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 518
 519         /* We don't advertise these by default because filtering and blending doesn't work as
 520          * it should, due to several restrictions.
 521          * The only exception is fp16 on nv40.
 522          */
 523         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 524         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 525
 526         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 527
 528         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 529         if(eng3d_class == NV40_3D)
 530                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 531
 532         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 533                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 534
 535         nvfx_screen_init_resource_functions(pscreen);
 536
 537         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 538         if (ret) {
 539                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 540                 return FALSE;
 541         }
 542
 543         /* 2D engine setup */
 544         nvfx_screen_surface_init(pscreen);
 545
 546         /* Notifier for sync purposes */
 547         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 548         if (ret) {
 549                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 550                 nvfx_screen_destroy(pscreen);
 551                 return NULL;
 552         }
 553
 554         /* Query objects */
 555         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 556         {
 557                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 558                 if(!ret)
 559                         break;
 560         }
 561
 562         if (ret) {
 563                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 564                 nvfx_screen_destroy(pscreen);
 565                 return NULL;
 566         }
 567
 568         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 569         if (ret) {
 570                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 571                 nvfx_screen_destroy(pscreen);
 572                 return NULL;
 573         }
 574
 575         LIST_INITHEAD(&screen->query_list);
 576
 577         /* Vtxprog resources */
 578         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 579             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 580                 nvfx_screen_destroy(pscreen);
 581                 return NULL;
 582         }
 583
 584         BIND_RING(chan, screen->eng3d, 7);
 585
 586         /* Static eng3d initialisation */
 587         /* note that we just started using the channel, so we must have space in the pushbuffer */
 588         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 589         OUT_RING(chan, screen->sync->handle);
 590         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 591         OUT_RING(chan, chan->vram->handle);
 592         OUT_RING(chan, chan->gart->handle);
 593         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 594         OUT_RING(chan, chan->vram->handle);
 595         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 596         OUT_RING(chan, chan->vram->handle);
 597         OUT_RING(chan, chan->vram->handle);
 598         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 599         OUT_RING(chan, chan->vram->handle);
 600         OUT_RING(chan, chan->gart->handle);
 601
 602         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 603         OUT_RING(chan, 0);
 604         OUT_RING(chan, screen->query->handle);
 605
 606         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 607         OUT_RING(chan, chan->vram->handle);
 608         OUT_RING(chan, chan->vram->handle);
 609
 610         if(!screen->is_nv4x)
 611                 nv30_screen_init(screen);
 612         else
 613                 nv40_screen_init(screen);
 614
 615         return pscreen;
 616 }