src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format.h"
   4 #include "util/u_format_s3tc.h"
   5 #include "util/u_simple_screen.h"
   6 #include "vl/vl_video_buffer.h"
   7
   8 #include "nouveau/nouveau_screen.h"
   9 #include "nouveau/nv_object.xml.h"
  10 #include "nvfx_context.h"
  11 #include "nvfx_screen.h"
  12 #include "nvfx_resource.h"
  13 #include "nvfx_tex.h"
  14
  15 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  16 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  17 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  18
  19 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  20 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  21 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  22
  23 static int
  24 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  25 {
  26         struct nvfx_screen *screen = nvfx_screen(pscreen);
  27
  28         switch (param) {
  29         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  30                 return 16;
  31         case PIPE_CAP_NPOT_TEXTURES:
  32                 return screen->advertise_npot;
  33         case PIPE_CAP_TWO_SIDED_STENCIL:
  34                 return 1;
  35         case PIPE_CAP_GLSL:
  36                 return 1;
  37         case PIPE_CAP_ANISOTROPIC_FILTER:
  38                 return 1;
  39         case PIPE_CAP_POINT_SPRITE:
  40                 return 1;
  41         case PIPE_CAP_MAX_RENDER_TARGETS:
  42                 return screen->use_nv4x ? 4 : 1;
  43         case PIPE_CAP_OCCLUSION_QUERY:
  44                 return 1;
  45         case PIPE_CAP_TIMER_QUERY:
  46                 return 0;
  47         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  48                 return 1;
  49         case PIPE_CAP_TEXTURE_SWIZZLE:
  50                 return 1;
  51         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  52                 return 13;
  53         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  54                 return 10;
  55         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  56                 return 13;
  57         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  58                 return !!screen->use_nv4x;
  59         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  60                 return 1;
  61         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  62                 return 0; /* We have 4 on nv40 - but unsupported currently */
  63         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64                 return screen->advertise_blend_equation_separate;
  65         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  66                 return 16;
  67         case PIPE_CAP_INDEP_BLEND_ENABLE:
  68                 /* TODO: on nv40 we have separate color masks */
  69                 /* TODO: nv40 mrt blending is probably broken */
  70                 return 0;
  71         case PIPE_CAP_INDEP_BLEND_FUNC:
  72                 return 0;
  73         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  74                 return 0;
  75         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  76         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  77         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  78         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  79                 return 1;
  80         case PIPE_CAP_DEPTH_CLAMP:
  81                 return 0; // TODO: implement depth clamp
  82         case PIPE_CAP_PRIMITIVE_RESTART:
  83                 return 0; // TODO: implement primitive restart
  84         case PIPE_CAP_ARRAY_TEXTURES:
  85         case PIPE_CAP_TGSI_INSTANCEID:
  86         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  87         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  88         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  89         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  90         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  91                 return 0;
  92         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  93                 return 0;
  94         default:
  95                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  96                 return 0;
  97         }
  98 }
  99
 100 static int
 101 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 102 {
 103         struct nvfx_screen *screen = nvfx_screen(pscreen);
 104
 105         switch(shader) {
 106         case PIPE_SHADER_FRAGMENT:
 107                 switch(param) {
 108                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 109                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 110                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 111                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 112                         return 4096;
 113                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 114                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 115                          value (nv30:0/nv40:4) ? */
 116                         return screen->use_nv4x ? 4 : 0;
 117                 case PIPE_SHADER_CAP_MAX_INPUTS:
 118                         return screen->use_nv4x ? 12 : 10;
 119                 case PIPE_SHADER_CAP_MAX_CONSTS:
 120                         return screen->use_nv4x ? 224 : 32;
 121                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 122                     return 1;
 123                 case PIPE_SHADER_CAP_MAX_TEMPS:
 124                         return 32;
 125                 case PIPE_SHADER_CAP_MAX_ADDRS:
 126                         return screen->use_nv4x ? 1 : 0;
 127                 case PIPE_SHADER_CAP_MAX_PREDS:
 128                         return 0; /* we could expose these, but nothing uses them */
 129                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 130                     return 0;
 131                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 132                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 133                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 134                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 135                         return 0;
 136                 case PIPE_SHADER_CAP_SUBROUTINES:
 137                         return screen->use_nv4x ? 1 : 0;
 138                 default:
 139                         break;
 140                 }
 141                 break;
 142         case PIPE_SHADER_VERTEX:
 143                 switch(param) {
 144                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 145                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 146                         return screen->use_nv4x ? 512 : 256;
 147                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 148                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 149                         return screen->use_nv4x ? 512 : 0;
 150                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 151                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 152                          value (nv30:1/nv40:4) ? */
 153                         return screen->use_nv4x ? 4 : 1;
 154                 case PIPE_SHADER_CAP_MAX_INPUTS:
 155                         return 16;
 156                 case PIPE_SHADER_CAP_MAX_CONSTS:
 157                         /* - 6 is for clip planes; Gallium should be fixed to put
 158                          * them in the vertex shader itself, so we don't need to reserve these */
 159                         return (screen->use_nv4x ? 468 : 256) - 6;
 160                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 161                             return 1;
 162                 case PIPE_SHADER_CAP_MAX_TEMPS:
 163                         return screen->use_nv4x ? 32 : 13;
 164                 case PIPE_SHADER_CAP_MAX_ADDRS:
 165                         return 2;
 166                 case PIPE_SHADER_CAP_MAX_PREDS:
 167                         return 0; /* we could expose these, but nothing uses them */
 168                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 169                         return 1;
 170                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 171                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 172                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 173                         return 0;
 174                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 175                         return 1;
 176                 case PIPE_SHADER_CAP_SUBROUTINES:
 177                         return 1;
 178                 default:
 179                         break;
 180                 }
 181                 break;
 182         default:
 183                 break;
 184         }
 185         return 0;
 186 }
 187
 188 static float
 189 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 190 {
 191         struct nvfx_screen *screen = nvfx_screen(pscreen);
 192
 193         switch (param) {
 194         case PIPE_CAP_MAX_LINE_WIDTH:
 195         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 196                 return 10.0;
 197         case PIPE_CAP_MAX_POINT_WIDTH:
 198         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 199                 return 64.0;
 200         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 201                 return screen->use_nv4x ? 16.0 : 8.0;
 202         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 203                 return 15.0;
 204         default:
 205                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 206                 return 0.0;
 207         }
 208 }
 209
 210 static int
 211 nvfx_screen_get_video_param(struct pipe_screen *screen,
 212                                 enum pipe_video_profile profile,
 213                                 enum pipe_video_cap param)
 214 {
 215         switch (param) {
 216         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 217                 return 0;
 218         default:
 219                 return 0;
 220         }
 221 }
 222
 223 static boolean
 224 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 225                                      enum pipe_format format,
 226                                      enum pipe_texture_target target,
 227                                      unsigned sample_count,
 228                                      unsigned bind)
 229 {
 230         struct nvfx_screen *screen = nvfx_screen(pscreen);
 231
 232         if (!util_format_is_supported(format, bind))
 233                 return FALSE;
 234
 235          if (sample_count > 1)
 236                 return FALSE;
 237
 238         if (bind & PIPE_BIND_RENDER_TARGET) {
 239                 switch (format) {
 240                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 241                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 242                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 243                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 244                 case PIPE_FORMAT_B5G6R5_UNORM:
 245                         break;
 246                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 247                         if(!screen->advertise_fp16)
 248                                 return FALSE;
 249                         break;
 250                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 251                         if(!screen->advertise_fp32)
 252                                 return FALSE;
 253                         break;
 254                 default:
 255                         return FALSE;
 256                 }
 257         }
 258
 259         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 260                 switch (format) {
 261                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 262                 case PIPE_FORMAT_X8Z24_UNORM:
 263                 case PIPE_FORMAT_Z16_UNORM:
 264                         break;
 265                 default:
 266                         return FALSE;
 267                 }
 268         }
 269
 270         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 271                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 272                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 273                         return FALSE;
 274                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 275                         return FALSE;
 276                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 277                         return FALSE;
 278                 if(screen->use_nv4x)
 279                 {
 280                         if(tf->fmt[4] < 0)
 281                                 return FALSE;
 282                 }
 283                 else
 284                 {
 285                         if(tf->fmt[0] < 0)
 286                                 return FALSE;
 287                 }
 288         }
 289
 290         // note that we do actually support everything through translate
 291         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 292                 unsigned type = nvfx_vertex_formats[format];
 293                 if(!type)
 294                         return FALSE;
 295         }
 296
 297         if (bind & PIPE_BIND_INDEX_BUFFER) {
 298                 // 8-bit indices supported, but not in hardware index buffer
 299                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 300                         return FALSE;
 301         }
 302
 303         if(bind & PIPE_BIND_STREAM_OUTPUT)
 304                 return FALSE;
 305
 306         return TRUE;
 307 }
 308
 309 static void
 310 nvfx_screen_destroy(struct pipe_screen *pscreen)
 311 {
 312         struct nvfx_screen *screen = nvfx_screen(pscreen);
 313
 314         nouveau_resource_destroy(&screen->vp_exec_heap);
 315         nouveau_resource_destroy(&screen->vp_data_heap);
 316         nouveau_resource_destroy(&screen->query_heap);
 317         nouveau_notifier_free(&screen->query);
 318         nouveau_notifier_free(&screen->sync);
 319         nouveau_grobj_free(&screen->eng3d);
 320         nvfx_screen_surface_takedown(pscreen);
 321         nouveau_bo_ref(NULL, &screen->fence);
 322
 323         nouveau_screen_fini(&screen->base);
 324
 325         FREE(pscreen);
 326 }
 327
 328 static void nv30_screen_init(struct nvfx_screen *screen)
 329 {
 330         struct nouveau_channel *chan = screen->base.channel;
 331         struct nouveau_grobj *eng3d = screen->eng3d;
 332         int i;
 333
 334         /* TODO: perhaps we should do some of this on nv40 too? */
 335         for (i=1; i<8; i++) {
 336                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 337                 OUT_RING(chan, 0);
 338                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 339                 OUT_RING(chan, 0);
 340         }
 341
 342         BEGIN_RING(chan, eng3d, 0x220, 1);
 343         OUT_RING(chan, 1);
 344
 345         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 346         OUT_RING(chan, 0x00100000);
 347         BEGIN_RING(chan, eng3d, 0x1454, 1);
 348         OUT_RING(chan, 0);
 349         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 350         OUT_RING(chan, 3);
 351         BEGIN_RING(chan, eng3d, 0x1450, 1);
 352         OUT_RING(chan, 0x00030004);
 353
 354         /* NEW */
 355         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 356         OUT_RING(chan, 0);
 357         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 358         OUT_RING(chan, fui(0.0));
 359         OUT_RING(chan, fui(0.0));
 360         OUT_RING(chan, fui(1.0));
 361         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 362         for (i=0; i<16; i++) {
 363                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 364         }
 365
 366         BEGIN_RING(chan, eng3d, 0x120, 3);
 367         OUT_RING(chan, 0);
 368         OUT_RING(chan, 1);
 369         OUT_RING(chan, 2);
 370
 371         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 372         OUT_RING(chan, 0x00001200);
 373
 374         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 375         OUT_RING(chan, 0);
 376
 377         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 378         OUT_RING(chan, fui(0.0));
 379         OUT_RING(chan, fui(1.0));
 380
 381         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 382         OUT_RING(chan, 0xffff0000);
 383
 384         /* enables use of vp rather than fixed-function somehow */
 385         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 386         OUT_RING(chan, 0x13);
 387 }
 388
 389 static void nv40_screen_init(struct nvfx_screen *screen)
 390 {
 391         struct nouveau_channel *chan = screen->base.channel;
 392         struct nouveau_grobj *eng3d = screen->eng3d;
 393
 394         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 395         OUT_RING(chan, screen->base.channel->vram->handle);
 396         OUT_RING(chan, screen->base.channel->vram->handle);
 397
 398         BEGIN_RING(chan, eng3d, 0x1450, 1);
 399         OUT_RING(chan, 0x00000004);
 400
 401         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 402         OUT_RING(chan, 0x00000010);
 403         OUT_RING(chan, 0x01000100);
 404         OUT_RING(chan, 0xff800006);
 405
 406         /* vtxprog output routing */
 407         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 408         OUT_RING(chan, 0x06144321);
 409         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 410         OUT_RING(chan, 0xedcba987);
 411         OUT_RING(chan, 0x0000006f);
 412         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 413         OUT_RING(chan, 0x00171615);
 414         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 415         OUT_RING(chan, 0x001b1a19);
 416
 417         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 418         OUT_RING(chan, 0x0020ffff);
 419         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 420         OUT_RING(chan, 0x01d300d4);
 421         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 422         OUT_RING(chan, 0x00000001);
 423
 424         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 425         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 426 }
 427
 428 static unsigned
 429 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 430 {
 431         int vram_hack_default = 0;
 432         int vram_hack;
 433         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 434         // It may also depend on the specific card or the AGP/PCIe chipset.
 435         if(screen->base.device->chipset == 0x47 /* G70 */
 436                 || screen->base.device->chipset == 0x49 /* G71 */
 437                 || screen->base.device->chipset == 0x46 /* G72 */
 438                 )
 439                 vram_hack_default = 1;
 440         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 441
 442         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 443 }
 444
 445 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 446 {
 447         struct nvfx_screen* screen = chan->user_private;
 448         struct nvfx_context* nvfx = screen->cur_ctx;
 449         if(nvfx)
 450                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 451 }
 452
 453 struct pipe_screen *
 454 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 455 {
 456         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 457         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 458         struct nouveau_channel *chan;
 459         struct pipe_screen *pscreen;
 460         unsigned eng3d_class = 0;
 461         int ret, i;
 462
 463         if (!screen)
 464                 return NULL;
 465
 466         pscreen = &screen->base.base;
 467
 468         ret = nouveau_screen_init(&screen->base, dev);
 469         if (ret) {
 470                 nvfx_screen_destroy(pscreen);
 471                 return NULL;
 472         }
 473         chan = screen->base.channel;
 474         screen->cur_ctx = NULL;
 475         chan->user_private = screen;
 476         chan->flush_notify = nvfx_channel_flush_notify;
 477
 478         pscreen->winsys = ws;
 479         pscreen->destroy = nvfx_screen_destroy;
 480         pscreen->get_param = nvfx_screen_get_param;
 481         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 482         pscreen->get_paramf = nvfx_screen_get_paramf;
 483         pscreen->get_video_param = nvfx_screen_get_video_param;
 484         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 485         pscreen->is_video_format_supported = vl_video_buffer_is_format_supported;
 486         pscreen->context_create = nvfx_create;
 487
 488         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 4096, &screen->fence);
 489         if (ret) {
 490                 nvfx_screen_destroy(pscreen);
 491                 return NULL;
 492         }
 493
 494         switch (dev->chipset & 0xf0) {
 495         case 0x30:
 496                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 497                         eng3d_class = NV30_3D;
 498                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 499                         eng3d_class = NV34_3D;
 500                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 501                         eng3d_class = NV35_3D;
 502                 break;
 503         case 0x40:
 504                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 505                         eng3d_class = NV40_3D;
 506                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 507                         eng3d_class = NV44_3D;
 508                 screen->is_nv4x = ~0;
 509                 break;
 510         case 0x60:
 511                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 512                         eng3d_class = NV44_3D;
 513                 screen->is_nv4x = ~0;
 514                 break;
 515         }
 516
 517         if (!eng3d_class) {
 518                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 519                 return NULL;
 520         }
 521
 522         screen->advertise_npot = !!screen->is_nv4x;
 523         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 524         screen->use_nv4x = screen->is_nv4x;
 525
 526         if(screen->is_nv4x) {
 527                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 528                         screen->use_nv4x = 0;
 529                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 530                         screen->advertise_npot = 0;
 531                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 532                         screen->advertise_blend_equation_separate = 0;
 533         }
 534
 535         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 536         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 537
 538         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 539         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 540         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 541
 542         /* We don't advertise these by default because filtering and blending doesn't work as
 543          * it should, due to several restrictions.
 544          * The only exception is fp16 on nv40.
 545          */
 546         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 547         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 548
 549         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 550
 551         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 552         if(eng3d_class == NV40_3D)
 553                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 554
 555         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 556                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 557
 558         nvfx_screen_init_resource_functions(pscreen);
 559
 560         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 561         if (ret) {
 562                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 563                 return FALSE;
 564         }
 565
 566         /* 2D engine setup */
 567         nvfx_screen_surface_init(pscreen);
 568
 569         /* Notifier for sync purposes */
 570         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 571         if (ret) {
 572                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 573                 nvfx_screen_destroy(pscreen);
 574                 return NULL;
 575         }
 576
 577         /* Query objects */
 578         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 579         {
 580                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 581                 if(!ret)
 582                         break;
 583         }
 584
 585         if (ret) {
 586                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 587                 nvfx_screen_destroy(pscreen);
 588                 return NULL;
 589         }
 590
 591         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 592         if (ret) {
 593                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 594                 nvfx_screen_destroy(pscreen);
 595                 return NULL;
 596         }
 597
 598         LIST_INITHEAD(&screen->query_list);
 599
 600         /* Vtxprog resources */
 601         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 602             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 603                 nvfx_screen_destroy(pscreen);
 604                 return NULL;
 605         }
 606
 607         BIND_RING(chan, screen->eng3d, 7);
 608
 609         /* Static eng3d initialisation */
 610         /* note that we just started using the channel, so we must have space in the pushbuffer */
 611         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 612         OUT_RING(chan, screen->sync->handle);
 613         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 614         OUT_RING(chan, chan->vram->handle);
 615         OUT_RING(chan, chan->gart->handle);
 616         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 617         OUT_RING(chan, chan->vram->handle);
 618         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 619         OUT_RING(chan, chan->vram->handle);
 620         OUT_RING(chan, chan->vram->handle);
 621         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 622         OUT_RING(chan, chan->vram->handle);
 623         OUT_RING(chan, chan->gart->handle);
 624
 625         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 626         OUT_RING(chan, 0);
 627         OUT_RING(chan, screen->query->handle);
 628
 629         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 630         OUT_RING(chan, chan->vram->handle);
 631         OUT_RING(chan, chan->vram->handle);
 632
 633         if(!screen->is_nv4x)
 634                 nv30_screen_init(screen);
 635         else
 636                 nv40_screen_init(screen);
 637
 638         return pscreen;
 639 }