src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format.h"
   4 #include "util/u_format_s3tc.h"
   5 #include "util/u_simple_screen.h"
   6
   7 #include "nouveau/nouveau_screen.h"
   8 #include "nouveau/nv_object.xml.h"
   9 #include "nvfx_context.h"
  10 #include "nvfx_video_context.h"
  11 #include "nvfx_screen.h"
  12 #include "nvfx_resource.h"
  13 #include "nvfx_tex.h"
  14
  15 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  16 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  17 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  18
  19 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  20 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  21 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  22
  23 static int
  24 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  25 {
  26         struct nvfx_screen *screen = nvfx_screen(pscreen);
  27
  28         switch (param) {
  29         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  30                 return 16;
  31         case PIPE_CAP_NPOT_TEXTURES:
  32                 return screen->advertise_npot;
  33         case PIPE_CAP_TWO_SIDED_STENCIL:
  34                 return 1;
  35         case PIPE_CAP_GLSL:
  36                 return 1;
  37         case PIPE_CAP_ANISOTROPIC_FILTER:
  38                 return 1;
  39         case PIPE_CAP_POINT_SPRITE:
  40                 return 1;
  41         case PIPE_CAP_MAX_RENDER_TARGETS:
  42                 return screen->use_nv4x ? 4 : 1;
  43         case PIPE_CAP_OCCLUSION_QUERY:
  44                 return 1;
  45         case PIPE_CAP_TIMER_QUERY:
  46                 return 0;
  47         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  48                 return 1;
  49         case PIPE_CAP_TEXTURE_SWIZZLE:
  50                 return 1;
  51         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  52                 return 13;
  53         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  54                 return 10;
  55         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  56                 return 13;
  57         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  58                 return !!screen->use_nv4x;
  59         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  60                 return 1;
  61         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  62                 return 0; /* We have 4 on nv40 - but unsupported currently */
  63         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  64                 return screen->advertise_blend_equation_separate;
  65         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  66                 return 16;
  67         case PIPE_CAP_INDEP_BLEND_ENABLE:
  68                 /* TODO: on nv40 we have separate color masks */
  69                 /* TODO: nv40 mrt blending is probably broken */
  70                 return 0;
  71         case PIPE_CAP_INDEP_BLEND_FUNC:
  72                 return 0;
  73         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  74                 return 0;
  75         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  76         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  77         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  78         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  79                 return 1;
  80         case PIPE_CAP_DEPTH_CLAMP:
  81                 return 0; // TODO: implement depth clamp
  82         case PIPE_CAP_PRIMITIVE_RESTART:
  83                 return 0; // TODO: implement primitive restart
  84         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  85                 return 0;
  86         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  87                 return 0;
  88         default:
  89                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  90                 return 0;
  91         }
  92 }
  93
  94 static int
  95 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
  96 {
  97         struct nvfx_screen *screen = nvfx_screen(pscreen);
  98
  99         switch(shader) {
 100         case PIPE_SHADER_FRAGMENT:
 101                 switch(param) {
 102                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 103                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 104                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 105                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 106                         return 4096;
 107                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 108                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 109                          value (nv30:0/nv40:4) ? */
 110                         return screen->use_nv4x ? 4 : 0;
 111                 case PIPE_SHADER_CAP_MAX_INPUTS:
 112                         return screen->use_nv4x ? 12 : 10;
 113                 case PIPE_SHADER_CAP_MAX_CONSTS:
 114                         return screen->use_nv4x ? 224 : 32;
 115                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 116                     return 1;
 117                 case PIPE_SHADER_CAP_MAX_TEMPS:
 118                         return 32;
 119                 case PIPE_SHADER_CAP_MAX_ADDRS:
 120                         return screen->use_nv4x ? 1 : 0;
 121                 case PIPE_SHADER_CAP_MAX_PREDS:
 122                         return 0; /* we could expose these, but nothing uses them */
 123                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 124                     return 0;
 125                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 126                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 127                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 128                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 129                         return 0;
 130                 case PIPE_SHADER_CAP_SUBROUTINES:
 131                         return screen->use_nv4x ? 1 : 0;
 132                 default:
 133                         break;
 134                 }
 135                 break;
 136         case PIPE_SHADER_VERTEX:
 137                 switch(param) {
 138                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 139                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 140                         return screen->use_nv4x ? 512 : 256;
 141                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 142                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 143                         return screen->use_nv4x ? 512 : 0;
 144                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 145                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 146                          value (nv30:1/nv40:4) ? */
 147                         return screen->use_nv4x ? 4 : 1;
 148                 case PIPE_SHADER_CAP_MAX_INPUTS:
 149                         return 16;
 150                 case PIPE_SHADER_CAP_MAX_CONSTS:
 151                         /* - 6 is for clip planes; Gallium should be fixed to put
 152                          * them in the vertex shader itself, so we don't need to reserve these */
 153                         return (screen->use_nv4x ? 468 : 256) - 6;
 154                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 155                             return 1;
 156                 case PIPE_SHADER_CAP_MAX_TEMPS:
 157                         return screen->use_nv4x ? 32 : 13;
 158                 case PIPE_SHADER_CAP_MAX_ADDRS:
 159                         return 2;
 160                 case PIPE_SHADER_CAP_MAX_PREDS:
 161                         return 0; /* we could expose these, but nothing uses them */
 162                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 163                         return 1;
 164                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 165                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 166                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 167                         return 0;
 168                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 169                         return 1;
 170                 case PIPE_SHADER_CAP_SUBROUTINES:
 171                         return 1;
 172                 default:
 173                         break;
 174                 }
 175                 break;
 176         default:
 177                 break;
 178         }
 179         return 0;
 180 }
 181
 182 static float
 183 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 184 {
 185         struct nvfx_screen *screen = nvfx_screen(pscreen);
 186
 187         switch (param) {
 188         case PIPE_CAP_MAX_LINE_WIDTH:
 189         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 190                 return 10.0;
 191         case PIPE_CAP_MAX_POINT_WIDTH:
 192         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 193                 return 64.0;
 194         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 195                 return screen->use_nv4x ? 16.0 : 8.0;
 196         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 197                 return 15.0;
 198         default:
 199                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 200                 return 0.0;
 201         }
 202 }
 203
 204 static boolean
 205 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 206                                      enum pipe_format format,
 207                                      enum pipe_texture_target target,
 208                                      unsigned sample_count,
 209                                      unsigned bind)
 210 {
 211         struct nvfx_screen *screen = nvfx_screen(pscreen);
 212
 213         if (!util_format_is_supported(format, bind))
 214                 return FALSE;
 215
 216          if (sample_count > 1)
 217                 return FALSE;
 218
 219         if (bind & PIPE_BIND_RENDER_TARGET) {
 220                 switch (format) {
 221                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 222                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 223                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 224                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 225                 case PIPE_FORMAT_B5G6R5_UNORM:
 226                         break;
 227                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 228                         if(!screen->advertise_fp16)
 229                                 return FALSE;
 230                         break;
 231                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 232                         if(!screen->advertise_fp32)
 233                                 return FALSE;
 234                         break;
 235                 default:
 236                         return FALSE;
 237                 }
 238         }
 239
 240         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 241                 switch (format) {
 242                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 243                 case PIPE_FORMAT_X8Z24_UNORM:
 244                 case PIPE_FORMAT_Z16_UNORM:
 245                         break;
 246                 default:
 247                         return FALSE;
 248                 }
 249         }
 250
 251         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 252                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 253                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 254                         return FALSE;
 255                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 256                         return FALSE;
 257                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 258                         return FALSE;
 259                 if(screen->use_nv4x)
 260                 {
 261                         if(tf->fmt[4] < 0)
 262                                 return FALSE;
 263                 }
 264                 else
 265                 {
 266                         if(tf->fmt[0] < 0)
 267                                 return FALSE;
 268                 }
 269         }
 270
 271         // note that we do actually support everything through translate
 272         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 273                 unsigned type = nvfx_vertex_formats[format];
 274                 if(!type)
 275                         return FALSE;
 276         }
 277
 278         if (bind & PIPE_BIND_INDEX_BUFFER) {
 279                 // 8-bit indices supported, but not in hardware index buffer
 280                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 281                         return FALSE;
 282         }
 283
 284         if(bind & PIPE_BIND_STREAM_OUTPUT)
 285                 return FALSE;
 286
 287         return TRUE;
 288 }
 289
 290 static void
 291 nvfx_screen_destroy(struct pipe_screen *pscreen)
 292 {
 293         struct nvfx_screen *screen = nvfx_screen(pscreen);
 294
 295         nouveau_resource_destroy(&screen->vp_exec_heap);
 296         nouveau_resource_destroy(&screen->vp_data_heap);
 297         nouveau_resource_destroy(&screen->query_heap);
 298         nouveau_notifier_free(&screen->query);
 299         nouveau_notifier_free(&screen->sync);
 300         nouveau_grobj_free(&screen->eng3d);
 301         nvfx_screen_surface_takedown(pscreen);
 302
 303         nouveau_screen_fini(&screen->base);
 304
 305         FREE(pscreen);
 306 }
 307
 308 static void nv30_screen_init(struct nvfx_screen *screen)
 309 {
 310         struct nouveau_channel *chan = screen->base.channel;
 311         struct nouveau_grobj *eng3d = screen->eng3d;
 312         int i;
 313
 314         /* TODO: perhaps we should do some of this on nv40 too? */
 315         for (i=1; i<8; i++) {
 316                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 317                 OUT_RING(chan, 0);
 318                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 319                 OUT_RING(chan, 0);
 320         }
 321
 322         BEGIN_RING(chan, eng3d, 0x220, 1);
 323         OUT_RING(chan, 1);
 324
 325         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 326         OUT_RING(chan, 0x00100000);
 327         BEGIN_RING(chan, eng3d, 0x1454, 1);
 328         OUT_RING(chan, 0);
 329         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 330         OUT_RING(chan, 3);
 331         BEGIN_RING(chan, eng3d, 0x1450, 1);
 332         OUT_RING(chan, 0x00030004);
 333
 334         /* NEW */
 335         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 336         OUT_RING(chan, 0);
 337         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 338         OUT_RING(chan, fui(0.0));
 339         OUT_RING(chan, fui(0.0));
 340         OUT_RING(chan, fui(1.0));
 341         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 342         for (i=0; i<16; i++) {
 343                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 344         }
 345
 346         BEGIN_RING(chan, eng3d, 0x120, 3);
 347         OUT_RING(chan, 0);
 348         OUT_RING(chan, 1);
 349         OUT_RING(chan, 2);
 350
 351         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 352         OUT_RING(chan, 0x00001200);
 353
 354         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 355         OUT_RING(chan, 0);
 356
 357         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 358         OUT_RING(chan, fui(0.0));
 359         OUT_RING(chan, fui(1.0));
 360
 361         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 362         OUT_RING(chan, 0xffff0000);
 363
 364         /* enables use of vp rather than fixed-function somehow */
 365         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 366         OUT_RING(chan, 0x13);
 367 }
 368
 369 static void nv40_screen_init(struct nvfx_screen *screen)
 370 {
 371         struct nouveau_channel *chan = screen->base.channel;
 372         struct nouveau_grobj *eng3d = screen->eng3d;
 373
 374         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 375         OUT_RING(chan, screen->base.channel->vram->handle);
 376         OUT_RING(chan, screen->base.channel->vram->handle);
 377
 378         BEGIN_RING(chan, eng3d, 0x1450, 1);
 379         OUT_RING(chan, 0x00000004);
 380
 381         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 382         OUT_RING(chan, 0x00000010);
 383         OUT_RING(chan, 0x01000100);
 384         OUT_RING(chan, 0xff800006);
 385
 386         /* vtxprog output routing */
 387         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 388         OUT_RING(chan, 0x06144321);
 389         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 390         OUT_RING(chan, 0xedcba987);
 391         OUT_RING(chan, 0x0000006f);
 392         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 393         OUT_RING(chan, 0x00171615);
 394         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 395         OUT_RING(chan, 0x001b1a19);
 396
 397         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 398         OUT_RING(chan, 0x0020ffff);
 399         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 400         OUT_RING(chan, 0x01d300d4);
 401         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 402         OUT_RING(chan, 0x00000001);
 403
 404         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 405         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 406 }
 407
 408 static unsigned
 409 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 410 {
 411         int vram_hack_default = 0;
 412         int vram_hack;
 413         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 414         // It may also depend on the specific card or the AGP/PCIe chipset.
 415         if(screen->base.device->chipset == 0x47 /* G70 */
 416                 || screen->base.device->chipset == 0x49 /* G71 */
 417                 || screen->base.device->chipset == 0x46 /* G72 */
 418                 )
 419                 vram_hack_default = 1;
 420         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 421
 422         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 423 }
 424
 425 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 426 {
 427         struct nvfx_screen* screen = chan->user_private;
 428         struct nvfx_context* nvfx = screen->cur_ctx;
 429         if(nvfx)
 430                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 431 }
 432
 433 struct pipe_screen *
 434 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 435 {
 436         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 437         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 438         struct nouveau_channel *chan;
 439         struct pipe_screen *pscreen;
 440         unsigned eng3d_class = 0;
 441         int ret, i;
 442
 443         if (!screen)
 444                 return NULL;
 445
 446         pscreen = &screen->base.base;
 447
 448         ret = nouveau_screen_init(&screen->base, dev);
 449         if (ret) {
 450                 nvfx_screen_destroy(pscreen);
 451                 return NULL;
 452         }
 453         chan = screen->base.channel;
 454         screen->cur_ctx = NULL;
 455         chan->user_private = screen;
 456         chan->flush_notify = nvfx_channel_flush_notify;
 457
 458         pscreen->winsys = ws;
 459         pscreen->destroy = nvfx_screen_destroy;
 460         pscreen->get_param = nvfx_screen_get_param;
 461         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 462         pscreen->get_paramf = nvfx_screen_get_paramf;
 463         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 464         pscreen->context_create = nvfx_create;
 465         pscreen->video_context_create = nvfx_video_create;
 466
 467         switch (dev->chipset & 0xf0) {
 468         case 0x30:
 469                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 470                         eng3d_class = NV30_3D;
 471                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 472                         eng3d_class = NV34_3D;
 473                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 474                         eng3d_class = NV35_3D;
 475                 break;
 476         case 0x40:
 477                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 478                         eng3d_class = NV40_3D;
 479                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 480                         eng3d_class = NV44_3D;
 481                 screen->is_nv4x = ~0;
 482                 break;
 483         case 0x60:
 484                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 485                         eng3d_class = NV44_3D;
 486                 screen->is_nv4x = ~0;
 487                 break;
 488         }
 489
 490         if (!eng3d_class) {
 491                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 492                 return NULL;
 493         }
 494
 495         screen->advertise_npot = !!screen->is_nv4x;
 496         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 497         screen->use_nv4x = screen->is_nv4x;
 498
 499         if(screen->is_nv4x) {
 500                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 501                         screen->use_nv4x = 0;
 502                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 503                         screen->advertise_npot = 0;
 504                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 505                         screen->advertise_blend_equation_separate = 0;
 506         }
 507
 508         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 509         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 510
 511         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 512         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 513         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 514
 515         /* We don't advertise these by default because filtering and blending doesn't work as
 516          * it should, due to several restrictions.
 517          * The only exception is fp16 on nv40.
 518          */
 519         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 520         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 521
 522         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 523
 524         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 525         if(eng3d_class == NV40_3D)
 526                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 527
 528         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 529                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 530
 531         nvfx_screen_init_resource_functions(pscreen);
 532
 533         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 534         if (ret) {
 535                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 536                 return FALSE;
 537         }
 538
 539         /* 2D engine setup */
 540         nvfx_screen_surface_init(pscreen);
 541
 542         /* Notifier for sync purposes */
 543         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 544         if (ret) {
 545                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 546                 nvfx_screen_destroy(pscreen);
 547                 return NULL;
 548         }
 549
 550         /* Query objects */
 551         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 552         {
 553                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 554                 if(!ret)
 555                         break;
 556         }
 557
 558         if (ret) {
 559                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 560                 nvfx_screen_destroy(pscreen);
 561                 return NULL;
 562         }
 563
 564         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 565         if (ret) {
 566                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 567                 nvfx_screen_destroy(pscreen);
 568                 return NULL;
 569         }
 570
 571         LIST_INITHEAD(&screen->query_list);
 572
 573         /* Vtxprog resources */
 574         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 575             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 576                 nvfx_screen_destroy(pscreen);
 577                 return NULL;
 578         }
 579
 580         BIND_RING(chan, screen->eng3d, 7);
 581
 582         /* Static eng3d initialisation */
 583         /* note that we just started using the channel, so we must have space in the pushbuffer */
 584         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 585         OUT_RING(chan, screen->sync->handle);
 586         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 587         OUT_RING(chan, chan->vram->handle);
 588         OUT_RING(chan, chan->gart->handle);
 589         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 590         OUT_RING(chan, chan->vram->handle);
 591         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 592         OUT_RING(chan, chan->vram->handle);
 593         OUT_RING(chan, chan->vram->handle);
 594         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 595         OUT_RING(chan, chan->vram->handle);
 596         OUT_RING(chan, chan->gart->handle);
 597
 598         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 599         OUT_RING(chan, 0);
 600         OUT_RING(chan, screen->query->handle);
 601
 602         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 603         OUT_RING(chan, chan->vram->handle);
 604         OUT_RING(chan, chan->vram->handle);
 605
 606         if(!screen->is_nv4x)
 607                 nv30_screen_init(screen);
 608         else
 609                 nv40_screen_init(screen);
 610
 611         return pscreen;
 612 }