src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format.h"
   4 #include "util/u_format_s3tc.h"
   5 #include "util/u_simple_screen.h"
   6 #include "vl/vl_decoder.h"
   7 #include "vl/vl_video_buffer.h"
   8
   9 #include "nouveau/nouveau_screen.h"
  10 #include "nouveau/nv_object.xml.h"
  11 #include "nvfx_context.h"
  12 #include "nvfx_screen.h"
  13 #include "nvfx_resource.h"
  14 #include "nvfx_tex.h"
  15
  16 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  17 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  18 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  19
  20 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  21 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  22 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  23
  24 static int
  25 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  26 {
  27         struct nvfx_screen *screen = nvfx_screen(pscreen);
  28
  29         switch (param) {
  30         case PIPE_CAP_NPOT_TEXTURES:
  31                 return screen->advertise_npot;
  32         case PIPE_CAP_TWO_SIDED_STENCIL:
  33                 return 1;
  34         case PIPE_CAP_SM3:
  35                 /* TODO: >= nv4x support Shader Model 3.0 */
  36                 return 0;
  37         case PIPE_CAP_GLSL_FEATURE_LEVEL:
  38                 return 120;
  39         case PIPE_CAP_ANISOTROPIC_FILTER:
  40                 return 1;
  41         case PIPE_CAP_POINT_SPRITE:
  42                 return 1;
  43         case PIPE_CAP_MAX_RENDER_TARGETS:
  44                 return screen->use_nv4x ? 4 : 1;
  45         case PIPE_CAP_OCCLUSION_QUERY:
  46                 return 1;
  47         case PIPE_CAP_TIMER_QUERY:
  48                 return 0;
  49         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  50                 return 1;
  51         case PIPE_CAP_TEXTURE_SWIZZLE:
  52                 return 1;
  53         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  54                 return 13;
  55         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  56                 return 10;
  57         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  58                 return 13;
  59         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  60                 return !!screen->use_nv4x;
  61         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  62                 return screen->advertise_blend_equation_separate;
  63         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  64                 return 16;
  65         case PIPE_CAP_INDEP_BLEND_ENABLE:
  66                 /* TODO: on nv40 we have separate color masks */
  67                 /* TODO: nv40 mrt blending is probably broken */
  68                 return 0;
  69         case PIPE_CAP_INDEP_BLEND_FUNC:
  70                 return 0;
  71         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  72                 return 0;
  73         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  74         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  75         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  76         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  77         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
  78                 return 1;
  79         case PIPE_CAP_DEPTH_CLIP_DISABLE:
  80                 return 0; // TODO: implement depth clamp
  81         case PIPE_CAP_PRIMITIVE_RESTART:
  82                 return 0; // TODO: implement primitive restart
  83         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  84         case PIPE_CAP_TGSI_INSTANCEID:
  85         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  86         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
  87         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
  88         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  89         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  90         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  91         case PIPE_CAP_MIN_TEXEL_OFFSET:
  92         case PIPE_CAP_MAX_TEXEL_OFFSET:
  93         case PIPE_CAP_CONDITIONAL_RENDER:
  94         case PIPE_CAP_TEXTURE_BARRIER:
  95         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  96         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
  97         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
  98         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
  99         case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
 100         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 101                 return 0;
 102         default:
 103                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
 104                 return 0;
 105         }
 106 }
 107
 108 static int
 109 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 110 {
 111         struct nvfx_screen *screen = nvfx_screen(pscreen);
 112
 113         switch(shader) {
 114         case PIPE_SHADER_FRAGMENT:
 115                 switch(param) {
 116                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 117                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 118                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 119                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 120                         return 4096;
 121                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 122                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 123                          value (nv30:0/nv40:4) ? */
 124                         return screen->use_nv4x ? 4 : 0;
 125                 case PIPE_SHADER_CAP_MAX_INPUTS:
 126                         return screen->use_nv4x ? 12 : 10;
 127                 case PIPE_SHADER_CAP_MAX_CONSTS:
 128                         return screen->use_nv4x ? 224 : 32;
 129                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 130                     return 1;
 131                 case PIPE_SHADER_CAP_MAX_TEMPS:
 132                         return 32;
 133                 case PIPE_SHADER_CAP_MAX_ADDRS:
 134                         return screen->use_nv4x ? 1 : 0;
 135                 case PIPE_SHADER_CAP_MAX_PREDS:
 136                         return 0; /* we could expose these, but nothing uses them */
 137                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 138                     return 0;
 139                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 140                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 141                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 142                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 143                         return 0;
 144                 case PIPE_SHADER_CAP_SUBROUTINES:
 145                         return screen->use_nv4x ? 1 : 0;
 146                 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 147                         return 16;
 148                 default:
 149                         break;
 150                 }
 151                 break;
 152         case PIPE_SHADER_VERTEX:
 153                 switch(param) {
 154                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 155                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 156                         return screen->use_nv4x ? 512 : 256;
 157                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 158                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 159                         return screen->use_nv4x ? 512 : 0;
 160                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 161                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 162                          value (nv30:1/nv40:4) ? */
 163                         return screen->use_nv4x ? 4 : 1;
 164                 case PIPE_SHADER_CAP_MAX_INPUTS:
 165                         return 16;
 166                 case PIPE_SHADER_CAP_MAX_CONSTS:
 167                         /* - 6 is for clip planes; Gallium should be fixed to put
 168                          * them in the vertex shader itself, so we don't need to reserve these */
 169                         return (screen->use_nv4x ? 468 : 256) - 6;
 170                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 171                             return 1;
 172                 case PIPE_SHADER_CAP_MAX_TEMPS:
 173                         return screen->use_nv4x ? 32 : 13;
 174                 case PIPE_SHADER_CAP_MAX_ADDRS:
 175                         return 2;
 176                 case PIPE_SHADER_CAP_MAX_PREDS:
 177                         return 0; /* we could expose these, but nothing uses them */
 178                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 179                         return 1;
 180                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 181                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 182                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 183                         return 0;
 184                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 185                         return 1;
 186                 case PIPE_SHADER_CAP_SUBROUTINES:
 187                         return 1;
 188                 case PIPE_SHADER_CAP_INTEGERS:
 189                         return 0;
 190                 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 191                         return 0; /* We have 4 on nv40 - but unsupported currently */
 192                 default:
 193                         break;
 194                 }
 195                 break;
 196         default:
 197                 break;
 198         }
 199         return 0;
 200 }
 201
 202 static float
 203 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 204 {
 205         struct nvfx_screen *screen = nvfx_screen(pscreen);
 206
 207         switch (param) {
 208         case PIPE_CAPF_MAX_LINE_WIDTH:
 209         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 210                 return 10.0;
 211         case PIPE_CAPF_MAX_POINT_WIDTH:
 212         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 213                 return 64.0;
 214         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 215                 return screen->use_nv4x ? 16.0 : 8.0;
 216         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 217                 return 15.0;
 218         default:
 219                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 220                 return 0.0;
 221         }
 222 }
 223
 224 static int
 225 nvfx_screen_get_video_param(struct pipe_screen *screen,
 226                                 enum pipe_video_profile profile,
 227                                 enum pipe_video_cap param)
 228 {
 229         switch (param) {
 230         case PIPE_VIDEO_CAP_SUPPORTED:
 231                 return vl_profile_supported(screen, profile);
 232         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 233                 return 0;
 234         case PIPE_VIDEO_CAP_MAX_WIDTH:
 235         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 236                 return vl_video_buffer_max_size(screen);
 237         case PIPE_VIDEO_CAP_PREFERED_FORMAT:
 238                 return PIPE_FORMAT_NV12;
 239         default:
 240                 return 0;
 241         }
 242 }
 243
 244 static boolean
 245 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 246                                      enum pipe_format format,
 247                                      enum pipe_texture_target target,
 248                                      unsigned sample_count,
 249                                      unsigned bind)
 250 {
 251         struct nvfx_screen *screen = nvfx_screen(pscreen);
 252
 253         if (!util_format_is_supported(format, bind))
 254                 return FALSE;
 255
 256          if (sample_count > 1)
 257                 return FALSE;
 258
 259         if (bind & PIPE_BIND_RENDER_TARGET) {
 260                 switch (format) {
 261                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 262                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 263                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 264                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 265                 case PIPE_FORMAT_B5G6R5_UNORM:
 266                         break;
 267                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 268                         if(!screen->advertise_fp16)
 269                                 return FALSE;
 270                         break;
 271                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 272                         if(!screen->advertise_fp32)
 273                                 return FALSE;
 274                         break;
 275                 default:
 276                         return FALSE;
 277                 }
 278         }
 279
 280         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 281                 switch (format) {
 282                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 283                 case PIPE_FORMAT_X8Z24_UNORM:
 284                 case PIPE_FORMAT_Z16_UNORM:
 285                         break;
 286                 default:
 287                         return FALSE;
 288                 }
 289         }
 290
 291         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 292                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 293                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 294                         return FALSE;
 295                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 296                         return FALSE;
 297                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 298                         return FALSE;
 299                 if(screen->use_nv4x)
 300                 {
 301                         if(tf->fmt[4] < 0)
 302                                 return FALSE;
 303                 }
 304                 else
 305                 {
 306                         if(tf->fmt[0] < 0)
 307                                 return FALSE;
 308                 }
 309         }
 310
 311         // note that we do actually support everything through translate
 312         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 313                 unsigned type = nvfx_vertex_formats[format];
 314                 if(!type)
 315                         return FALSE;
 316         }
 317
 318         if (bind & PIPE_BIND_INDEX_BUFFER) {
 319                 // 8-bit indices supported, but not in hardware index buffer
 320                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 321                         return FALSE;
 322         }
 323
 324         if(bind & PIPE_BIND_STREAM_OUTPUT)
 325                 return FALSE;
 326
 327         return TRUE;
 328 }
 329
 330 static void
 331 nvfx_screen_destroy(struct pipe_screen *pscreen)
 332 {
 333         struct nvfx_screen *screen = nvfx_screen(pscreen);
 334
 335         nouveau_resource_destroy(&screen->vp_exec_heap);
 336         nouveau_resource_destroy(&screen->vp_data_heap);
 337         nouveau_resource_destroy(&screen->query_heap);
 338         nouveau_notifier_free(&screen->query);
 339         nouveau_notifier_free(&screen->sync);
 340         nouveau_grobj_free(&screen->eng3d);
 341         nvfx_screen_surface_takedown(pscreen);
 342         nouveau_bo_ref(NULL, &screen->fence);
 343
 344         nouveau_screen_fini(&screen->base);
 345
 346         FREE(pscreen);
 347 }
 348
 349 static void nv30_screen_init(struct nvfx_screen *screen)
 350 {
 351         struct nouveau_channel *chan = screen->base.channel;
 352         struct nouveau_grobj *eng3d = screen->eng3d;
 353         int i;
 354
 355         /* TODO: perhaps we should do some of this on nv40 too? */
 356         for (i=1; i<8; i++) {
 357                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 358                 OUT_RING(chan, 0);
 359                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 360                 OUT_RING(chan, 0);
 361         }
 362
 363         BEGIN_RING(chan, eng3d, 0x220, 1);
 364         OUT_RING(chan, 1);
 365
 366         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 367         OUT_RING(chan, 0x00100000);
 368         BEGIN_RING(chan, eng3d, 0x1454, 1);
 369         OUT_RING(chan, 0);
 370         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 371         OUT_RING(chan, 3);
 372         BEGIN_RING(chan, eng3d, 0x1450, 1);
 373         OUT_RING(chan, 0x00030004);
 374
 375         /* NEW */
 376         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 377         OUT_RING(chan, 0);
 378         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 379         OUT_RING(chan, fui(0.0));
 380         OUT_RING(chan, fui(0.0));
 381         OUT_RING(chan, fui(1.0));
 382         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 383         for (i=0; i<16; i++) {
 384                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 385         }
 386
 387         BEGIN_RING(chan, eng3d, 0x120, 3);
 388         OUT_RING(chan, 0);
 389         OUT_RING(chan, 1);
 390         OUT_RING(chan, 2);
 391
 392         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 393         OUT_RING(chan, 0x00001200);
 394
 395         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 396         OUT_RING(chan, 0);
 397
 398         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 399         OUT_RING(chan, fui(0.0));
 400         OUT_RING(chan, fui(1.0));
 401
 402         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 403         OUT_RING(chan, 0xffff0000);
 404
 405         /* enables use of vp rather than fixed-function somehow */
 406         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 407         OUT_RING(chan, 0x13);
 408 }
 409
 410 static void nv40_screen_init(struct nvfx_screen *screen)
 411 {
 412         struct nouveau_channel *chan = screen->base.channel;
 413         struct nouveau_grobj *eng3d = screen->eng3d;
 414
 415         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 416         OUT_RING(chan, screen->base.channel->vram->handle);
 417         OUT_RING(chan, screen->base.channel->vram->handle);
 418
 419         BEGIN_RING(chan, eng3d, 0x1450, 1);
 420         OUT_RING(chan, 0x00000004);
 421
 422         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 423         OUT_RING(chan, 0x00000010);
 424         OUT_RING(chan, 0x01000100);
 425         OUT_RING(chan, 0xff800006);
 426
 427         /* vtxprog output routing */
 428         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 429         OUT_RING(chan, 0x06144321);
 430         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 431         OUT_RING(chan, 0xedcba987);
 432         OUT_RING(chan, 0x0000006f);
 433         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 434         OUT_RING(chan, 0x00171615);
 435         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 436         OUT_RING(chan, 0x001b1a19);
 437
 438         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 439         OUT_RING(chan, 0x0020ffff);
 440         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 441         OUT_RING(chan, 0x01d300d4);
 442         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 443         OUT_RING(chan, 0x00000001);
 444
 445         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 446         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 447 }
 448
 449 static unsigned
 450 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 451 {
 452         int vram_hack_default = 0;
 453         int vram_hack;
 454         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 455         // It may also depend on the specific card or the AGP/PCIe chipset.
 456         if(screen->base.device->chipset == 0x47 /* G70 */
 457                 || screen->base.device->chipset == 0x49 /* G71 */
 458                 || screen->base.device->chipset == 0x46 /* G72 */
 459                 )
 460                 vram_hack_default = 1;
 461         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 462
 463         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 464 }
 465
 466 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 467 {
 468         struct nvfx_screen* screen = chan->user_private;
 469         struct nvfx_context* nvfx = screen->cur_ctx;
 470         if(nvfx)
 471                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 472 }
 473
 474 struct pipe_screen *
 475 nvfx_screen_create(struct nouveau_device *dev)
 476 {
 477         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 478         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 479         struct nouveau_channel *chan;
 480         struct pipe_screen *pscreen;
 481         unsigned eng3d_class = 0;
 482         int ret, i;
 483
 484         if (!screen)
 485                 return NULL;
 486
 487         pscreen = &screen->base.base;
 488
 489         ret = nouveau_screen_init(&screen->base, dev);
 490         if (ret) {
 491                 nvfx_screen_destroy(pscreen);
 492                 return NULL;
 493         }
 494         chan = screen->base.channel;
 495         screen->cur_ctx = NULL;
 496         chan->user_private = screen;
 497         chan->flush_notify = nvfx_channel_flush_notify;
 498
 499         pscreen->destroy = nvfx_screen_destroy;
 500         pscreen->get_param = nvfx_screen_get_param;
 501         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 502         pscreen->get_paramf = nvfx_screen_get_paramf;
 503         pscreen->get_video_param = nvfx_screen_get_video_param;
 504         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 505         pscreen->is_video_format_supported = vl_video_buffer_is_format_supported;
 506         pscreen->context_create = nvfx_create;
 507
 508         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 4096, &screen->fence);
 509         if (ret) {
 510                 nvfx_screen_destroy(pscreen);
 511                 return NULL;
 512         }
 513
 514         switch (dev->chipset & 0xf0) {
 515         case 0x30:
 516                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 517                         eng3d_class = NV30_3D;
 518                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 519                         eng3d_class = NV34_3D;
 520                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 521                         eng3d_class = NV35_3D;
 522                 break;
 523         case 0x40:
 524                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 525                         eng3d_class = NV40_3D;
 526                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 527                         eng3d_class = NV44_3D;
 528                 screen->is_nv4x = ~0;
 529                 break;
 530         case 0x60:
 531                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 532                         eng3d_class = NV44_3D;
 533                 screen->is_nv4x = ~0;
 534                 break;
 535         }
 536
 537         if (!eng3d_class) {
 538                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 539                 return NULL;
 540         }
 541
 542         screen->advertise_npot = !!screen->is_nv4x;
 543         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 544         screen->use_nv4x = screen->is_nv4x;
 545
 546         if(screen->is_nv4x) {
 547                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 548                         screen->use_nv4x = 0;
 549                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 550                         screen->advertise_npot = 0;
 551                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 552                         screen->advertise_blend_equation_separate = 0;
 553         }
 554
 555         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 556         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 557
 558         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 559         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 560         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 561
 562         /* We don't advertise these by default because filtering and blending doesn't work as
 563          * it should, due to several restrictions.
 564          * The only exception is fp16 on nv40.
 565          */
 566         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 567         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 568
 569         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 570
 571         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 572         if(eng3d_class == NV40_3D)
 573                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 574
 575         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 576                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 577
 578         nvfx_screen_init_resource_functions(pscreen);
 579
 580         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 581         if (ret) {
 582                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 583                 return FALSE;
 584         }
 585
 586         /* 2D engine setup */
 587         nvfx_screen_surface_init(pscreen);
 588
 589         /* Notifier for sync purposes */
 590         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 591         if (ret) {
 592                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 593                 nvfx_screen_destroy(pscreen);
 594                 return NULL;
 595         }
 596
 597         /* Query objects */
 598         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 599         {
 600                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 601                 if(!ret)
 602                         break;
 603         }
 604
 605         if (ret) {
 606                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 607                 nvfx_screen_destroy(pscreen);
 608                 return NULL;
 609         }
 610
 611         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 612         if (ret) {
 613                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 614                 nvfx_screen_destroy(pscreen);
 615                 return NULL;
 616         }
 617
 618         LIST_INITHEAD(&screen->query_list);
 619
 620         /* Vtxprog resources */
 621         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 622             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 623                 nvfx_screen_destroy(pscreen);
 624                 return NULL;
 625         }
 626
 627         BIND_RING(chan, screen->eng3d, 7);
 628
 629         /* Static eng3d initialisation */
 630         /* note that we just started using the channel, so we must have space in the pushbuffer */
 631         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 632         OUT_RING(chan, screen->sync->handle);
 633         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 634         OUT_RING(chan, chan->vram->handle);
 635         OUT_RING(chan, chan->gart->handle);
 636         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 637         OUT_RING(chan, chan->vram->handle);
 638         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 639         OUT_RING(chan, chan->vram->handle);
 640         OUT_RING(chan, chan->vram->handle);
 641         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 642         OUT_RING(chan, chan->vram->handle);
 643         OUT_RING(chan, chan->gart->handle);
 644
 645         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 646         OUT_RING(chan, 0);
 647         OUT_RING(chan, screen->query->handle);
 648
 649         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 650         OUT_RING(chan, chan->vram->handle);
 651         OUT_RING(chan, chan->vram->handle);
 652
 653         if(!screen->is_nv4x)
 654                 nv30_screen_init(screen);
 655         else
 656                 nv40_screen_init(screen);
 657
 658         return pscreen;
 659 }