src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format_s3tc.h"
   4 #include "util/u_simple_screen.h"
   5
   6 #include "nouveau/nouveau_screen.h"
   7 #include "nouveau/nv_object.xml.h"
   8 #include "nvfx_context.h"
   9 #include "nvfx_video_context.h"
  10 #include "nvfx_screen.h"
  11 #include "nvfx_resource.h"
  12 #include "nvfx_tex.h"
  13
  14 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  15 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  16 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  17
  18 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  19 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  20 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  21
  22 static int
  23 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  24 {
  25         struct nvfx_screen *screen = nvfx_screen(pscreen);
  26
  27         switch (param) {
  28         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  29                 return 16;
  30         case PIPE_CAP_NPOT_TEXTURES:
  31                 return screen->advertise_npot;
  32         case PIPE_CAP_TWO_SIDED_STENCIL:
  33                 return 1;
  34         case PIPE_CAP_GLSL:
  35                 return 1;
  36         case PIPE_CAP_ANISOTROPIC_FILTER:
  37                 return 1;
  38         case PIPE_CAP_POINT_SPRITE:
  39                 return 1;
  40         case PIPE_CAP_MAX_RENDER_TARGETS:
  41                 return screen->use_nv4x ? 4 : 1;
  42         case PIPE_CAP_OCCLUSION_QUERY:
  43                 return 1;
  44         case PIPE_CAP_TIMER_QUERY:
  45                 return 0;
  46         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  47                 return 1;
  48         case PIPE_CAP_TEXTURE_SWIZZLE:
  49                 return 1;
  50         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  51                 return 13;
  52         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  53                 return 10;
  54         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  55                 return 13;
  56         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  57                 return !!screen->use_nv4x;
  58         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  59                 return 1;
  60         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  61                 return 0; /* We have 4 on nv40 - but unsupported currently */
  62         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  63                 return screen->advertise_blend_equation_separate;
  64         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  65                 return 16;
  66         case PIPE_CAP_INDEP_BLEND_ENABLE:
  67                 /* TODO: on nv40 we have separate color masks */
  68                 /* TODO: nv40 mrt blending is probably broken */
  69                 return 0;
  70         case PIPE_CAP_INDEP_BLEND_FUNC:
  71                 return 0;
  72         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  73                 return 0;
  74         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  75         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  76         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  77         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  78                 return 1;
  79         case PIPE_CAP_DEPTH_CLAMP:
  80                 return 0; // TODO: implement depth clamp
  81         case PIPE_CAP_PRIMITIVE_RESTART:
  82                 return 0; // TODO: implement primitive restart
  83         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  84                 return 0;
  85         default:
  86                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  87                 return 0;
  88         }
  89 }
  90
  91 static int
  92 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
  93 {
  94         struct nvfx_screen *screen = nvfx_screen(pscreen);
  95
  96         switch(shader) {
  97         case PIPE_SHADER_FRAGMENT:
  98                 switch(param) {
  99                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 100                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 101                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 102                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 103                         return 4096;
 104                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 105                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 106                          value (nv30:0/nv40:4) ? */
 107                         return screen->use_nv4x ? 4 : 0;
 108                 case PIPE_SHADER_CAP_MAX_INPUTS:
 109                         return screen->use_nv4x ? 12 : 10;
 110                 case PIPE_SHADER_CAP_MAX_CONSTS:
 111                         return screen->use_nv4x ? 224 : 32;
 112                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 113                     return 1;
 114                 case PIPE_SHADER_CAP_MAX_TEMPS:
 115                         return 32;
 116                 case PIPE_SHADER_CAP_MAX_ADDRS:
 117                         return screen->use_nv4x ? 1 : 0;
 118                 case PIPE_SHADER_CAP_MAX_PREDS:
 119                         return 0; /* we could expose these, but nothing uses them */
 120                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 121                     return 0;
 122                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 123                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 124                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 125                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 126                         return 0;
 127                 default:
 128                         break;
 129                 }
 130                 break;
 131         case PIPE_SHADER_VERTEX:
 132                 switch(param) {
 133                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 134                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 135                         return screen->use_nv4x ? 512 : 256;
 136                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 137                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 138                         return screen->use_nv4x ? 512 : 0;
 139                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 140                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 141                          value (nv30:1/nv40:4) ? */
 142                         return screen->use_nv4x ? 4 : 1;
 143                 case PIPE_SHADER_CAP_MAX_INPUTS:
 144                         return 16;
 145                 case PIPE_SHADER_CAP_MAX_CONSTS:
 146                         /* - 6 is for clip planes; Gallium should be fixed to put
 147                          * them in the vertex shader itself, so we don't need to reserve these */
 148                         return (screen->use_nv4x ? 468 : 256) - 6;
 149                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 150                             return 1;
 151                 case PIPE_SHADER_CAP_MAX_TEMPS:
 152                         return screen->use_nv4x ? 32 : 13;
 153                 case PIPE_SHADER_CAP_MAX_ADDRS:
 154                         return 2;
 155                 case PIPE_SHADER_CAP_MAX_PREDS:
 156                         return 0; /* we could expose these, but nothing uses them */
 157                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 158                         return 1;
 159                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 160                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 161                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 162                         return 0;
 163                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 164                         return 1;
 165                 default:
 166                         break;
 167                 }
 168                 break;
 169         default:
 170                 break;
 171         }
 172         return 0;
 173 }
 174
 175 static float
 176 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_cap param)
 177 {
 178         struct nvfx_screen *screen = nvfx_screen(pscreen);
 179
 180         switch (param) {
 181         case PIPE_CAP_MAX_LINE_WIDTH:
 182         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 183                 return 10.0;
 184         case PIPE_CAP_MAX_POINT_WIDTH:
 185         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 186                 return 64.0;
 187         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 188                 return screen->use_nv4x ? 16.0 : 8.0;
 189         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 190                 return 15.0;
 191         default:
 192                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 193                 return 0.0;
 194         }
 195 }
 196
 197 static boolean
 198 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 199                                      enum pipe_format format,
 200                                      enum pipe_texture_target target,
 201                                      unsigned sample_count,
 202                                      unsigned bind, unsigned geom_flags)
 203 {
 204         struct nvfx_screen *screen = nvfx_screen(pscreen);
 205
 206          if (sample_count > 1)
 207                 return FALSE;
 208
 209         if (bind & PIPE_BIND_RENDER_TARGET) {
 210                 switch (format) {
 211                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 212                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 213                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 214                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 215                 case PIPE_FORMAT_B5G6R5_UNORM:
 216                         break;
 217                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 218                         if(!screen->advertise_fp16)
 219                                 return FALSE;
 220                         break;
 221                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 222                         if(!screen->advertise_fp32)
 223                                 return FALSE;
 224                         break;
 225                 default:
 226                         return FALSE;
 227                 }
 228         }
 229
 230         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 231                 switch (format) {
 232                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 233                 case PIPE_FORMAT_X8Z24_UNORM:
 234                 case PIPE_FORMAT_Z16_UNORM:
 235                         break;
 236                 default:
 237                         return FALSE;
 238                 }
 239         }
 240
 241         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 242                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 243                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 244                         return FALSE;
 245                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 246                         return FALSE;
 247                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 248                         return FALSE;
 249                 if(screen->use_nv4x)
 250                 {
 251                         if(tf->fmt[4] < 0)
 252                                 return FALSE;
 253                 }
 254                 else
 255                 {
 256                         if(tf->fmt[0] < 0)
 257                                 return FALSE;
 258                 }
 259         }
 260
 261         // note that we do actually support everything through translate
 262         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 263                 unsigned type = nvfx_vertex_formats[format];
 264                 if(!type)
 265                         return FALSE;
 266         }
 267
 268         if (bind & PIPE_BIND_INDEX_BUFFER) {
 269                 // 8-bit indices supported, but not in hardware index buffer
 270                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 271                         return FALSE;
 272         }
 273
 274         if(bind & PIPE_BIND_STREAM_OUTPUT)
 275                 return FALSE;
 276
 277         return TRUE;
 278 }
 279
 280 static void
 281 nvfx_screen_destroy(struct pipe_screen *pscreen)
 282 {
 283         struct nvfx_screen *screen = nvfx_screen(pscreen);
 284
 285         nouveau_resource_destroy(&screen->vp_exec_heap);
 286         nouveau_resource_destroy(&screen->vp_data_heap);
 287         nouveau_resource_destroy(&screen->query_heap);
 288         nouveau_notifier_free(&screen->query);
 289         nouveau_notifier_free(&screen->sync);
 290         nouveau_grobj_free(&screen->eng3d);
 291         nvfx_screen_surface_takedown(pscreen);
 292
 293         nouveau_screen_fini(&screen->base);
 294
 295         FREE(pscreen);
 296 }
 297
 298 static void nv30_screen_init(struct nvfx_screen *screen)
 299 {
 300         struct nouveau_channel *chan = screen->base.channel;
 301         int i;
 302
 303         /* TODO: perhaps we should do some of this on nv40 too? */
 304         for (i=1; i<8; i++) {
 305                 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1));
 306                 OUT_RING(chan, 0);
 307                 OUT_RING(chan, RING_3D(NV30_3D_VIEWPORT_CLIP_VERT(i), 1));
 308                 OUT_RING(chan, 0);
 309         }
 310
 311         OUT_RING(chan, RING_3D(0x220, 1));
 312         OUT_RING(chan, 1);
 313
 314         OUT_RING(chan, RING_3D(0x03b0, 1));
 315         OUT_RING(chan, 0x00100000);
 316         OUT_RING(chan, RING_3D(0x1454, 1));
 317         OUT_RING(chan, 0);
 318         OUT_RING(chan, RING_3D(0x1d80, 1));
 319         OUT_RING(chan, 3);
 320         OUT_RING(chan, RING_3D(0x1450, 1));
 321         OUT_RING(chan, 0x00030004);
 322
 323         /* NEW */
 324         OUT_RING(chan, RING_3D(0x1e98, 1));
 325         OUT_RING(chan, 0);
 326         OUT_RING(chan, RING_3D(0x17e0, 3));
 327         OUT_RING(chan, fui(0.0));
 328         OUT_RING(chan, fui(0.0));
 329         OUT_RING(chan, fui(1.0));
 330         OUT_RING(chan, RING_3D(0x1f80, 16));
 331         for (i=0; i<16; i++) {
 332                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 333         }
 334
 335         OUT_RING(chan, RING_3D(0x120, 3));
 336         OUT_RING(chan, 0);
 337         OUT_RING(chan, 1);
 338         OUT_RING(chan, 2);
 339
 340         OUT_RING(chan, RING_3D(0x1d88, 1));
 341         OUT_RING(chan, 0x00001200);
 342
 343         OUT_RING(chan, RING_3D(NV30_3D_RC_ENABLE, 1));
 344         OUT_RING(chan, 0);
 345
 346         OUT_RING(chan, RING_3D(NV30_3D_DEPTH_RANGE_NEAR, 2));
 347         OUT_RING(chan, fui(0.0));
 348         OUT_RING(chan, fui(1.0));
 349
 350         OUT_RING(chan, RING_3D(NV30_3D_MULTISAMPLE_CONTROL, 1));
 351         OUT_RING(chan, 0xffff0000);
 352
 353         /* enables use of vp rather than fixed-function somehow */
 354         OUT_RING(chan, RING_3D(0x1e94, 1));
 355         OUT_RING(chan, 0x13);
 356 }
 357
 358 static void nv40_screen_init(struct nvfx_screen *screen)
 359 {
 360         struct nouveau_channel *chan = screen->base.channel;
 361
 362         OUT_RING(chan, RING_3D(NV40_3D_DMA_COLOR2, 2));
 363         OUT_RING(chan, screen->base.channel->vram->handle);
 364         OUT_RING(chan, screen->base.channel->vram->handle);
 365
 366         OUT_RING(chan, RING_3D(0x1450, 1));
 367         OUT_RING(chan, 0x00000004);
 368
 369         OUT_RING(chan, RING_3D(0x1ea4, 3));
 370         OUT_RING(chan, 0x00000010);
 371         OUT_RING(chan, 0x01000100);
 372         OUT_RING(chan, 0xff800006);
 373
 374         /* vtxprog output routing */
 375         OUT_RING(chan, RING_3D(0x1fc4, 1));
 376         OUT_RING(chan, 0x06144321);
 377         OUT_RING(chan, RING_3D(0x1fc8, 2));
 378         OUT_RING(chan, 0xedcba987);
 379         OUT_RING(chan, 0x0000006f);
 380         OUT_RING(chan, RING_3D(0x1fd0, 1));
 381         OUT_RING(chan, 0x00171615);
 382         OUT_RING(chan, RING_3D(0x1fd4, 1));
 383         OUT_RING(chan, 0x001b1a19);
 384
 385         OUT_RING(chan, RING_3D(0x1ef8, 1));
 386         OUT_RING(chan, 0x0020ffff);
 387         OUT_RING(chan, RING_3D(0x1d64, 1));
 388         OUT_RING(chan, 0x01d300d4);
 389         OUT_RING(chan, RING_3D(0x1e94, 1));
 390         OUT_RING(chan, 0x00000001);
 391
 392         OUT_RING(chan, RING_3D(NV40_3D_MIPMAP_ROUNDING, 1));
 393         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 394 }
 395
 396 static unsigned
 397 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 398 {
 399         int vram_hack_default = 0;
 400         int vram_hack;
 401         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 402         // It may also depend on the specific card or the AGP/PCIe chipset.
 403         if(screen->base.device->chipset == 0x47 /* G70 */
 404                 || screen->base.device->chipset == 0x49 /* G71 */
 405                 || screen->base.device->chipset == 0x46 /* G72 */
 406                 )
 407                 vram_hack_default = 1;
 408         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 409
 410         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 411 }
 412
 413 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 414 {
 415         struct nvfx_screen* screen = chan->user_private;
 416         struct nvfx_context* nvfx = screen->cur_ctx;
 417         if(nvfx)
 418                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 419 }
 420
 421 struct pipe_screen *
 422 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 423 {
 424         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 425         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 426         struct nouveau_channel *chan;
 427         struct pipe_screen *pscreen;
 428         unsigned eng3d_class = 0;
 429         int ret, i;
 430
 431         if (!screen)
 432                 return NULL;
 433
 434         pscreen = &screen->base.base;
 435
 436         ret = nouveau_screen_init(&screen->base, dev);
 437         if (ret) {
 438                 nvfx_screen_destroy(pscreen);
 439                 return NULL;
 440         }
 441         chan = screen->base.channel;
 442         screen->cur_ctx = NULL;
 443         chan->user_private = screen;
 444         chan->flush_notify = nvfx_channel_flush_notify;
 445
 446         pscreen->winsys = ws;
 447         pscreen->destroy = nvfx_screen_destroy;
 448         pscreen->get_param = nvfx_screen_get_param;
 449         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 450         pscreen->get_paramf = nvfx_screen_get_paramf;
 451         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 452         pscreen->context_create = nvfx_create;
 453         pscreen->video_context_create = nvfx_video_create;
 454
 455         switch (dev->chipset & 0xf0) {
 456         case 0x30:
 457                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 458                         eng3d_class = NV30_3D;
 459                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 460                         eng3d_class = NV34_3D;
 461                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 462                         eng3d_class = NV35_3D;
 463                 break;
 464         case 0x40:
 465                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 466                         eng3d_class = NV40_3D;
 467                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 468                         eng3d_class = NV44_3D;
 469                 screen->is_nv4x = ~0;
 470                 break;
 471         case 0x60:
 472                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 473                         eng3d_class = NV44_3D;
 474                 screen->is_nv4x = ~0;
 475                 break;
 476         }
 477
 478         if (!eng3d_class) {
 479                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 480                 return NULL;
 481         }
 482
 483         screen->advertise_npot = !!screen->is_nv4x;
 484         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 485         screen->use_nv4x = screen->is_nv4x;
 486
 487         if(screen->is_nv4x) {
 488                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 489                         screen->use_nv4x = 0;
 490                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 491                         screen->advertise_npot = 0;
 492                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 493                         screen->advertise_blend_equation_separate = 0;
 494         }
 495
 496         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 497         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 498
 499         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 500         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 501         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 502
 503         /* We don't advertise these by default because filtering and blending doesn't work as
 504          * it should, due to several restrictions.
 505          * The only exception is fp16 on nv40.
 506          */
 507         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 508         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 509
 510         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 511
 512         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 513         if(eng3d_class == NV40_3D)
 514                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 515
 516         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 517                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 518
 519         nvfx_screen_init_resource_functions(pscreen);
 520
 521         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 522         if (ret) {
 523                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 524                 return FALSE;
 525         }
 526
 527         /* 2D engine setup */
 528         nvfx_screen_surface_init(pscreen);
 529
 530         /* Notifier for sync purposes */
 531         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 532         if (ret) {
 533                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 534                 nvfx_screen_destroy(pscreen);
 535                 return NULL;
 536         }
 537
 538         /* Query objects */
 539         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 540         {
 541                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 542                 if(!ret)
 543                         break;
 544         }
 545
 546         if (ret) {
 547                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 548                 nvfx_screen_destroy(pscreen);
 549                 return NULL;
 550         }
 551
 552         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 553         if (ret) {
 554                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 555                 nvfx_screen_destroy(pscreen);
 556                 return NULL;
 557         }
 558
 559         LIST_INITHEAD(&screen->query_list);
 560
 561         /* Vtxprog resources */
 562         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 563             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 564                 nvfx_screen_destroy(pscreen);
 565                 return NULL;
 566         }
 567
 568         BIND_RING(chan, screen->eng3d, 7);
 569
 570         /* Static eng3d initialisation */
 571         /* note that we just started using the channel, so we must have space in the pushbuffer */
 572         OUT_RING(chan, RING_3D(NV30_3D_DMA_NOTIFY, 1));
 573         OUT_RING(chan, screen->sync->handle);
 574         OUT_RING(chan, RING_3D(NV30_3D_DMA_TEXTURE0, 2));
 575         OUT_RING(chan, chan->vram->handle);
 576         OUT_RING(chan, chan->gart->handle);
 577         OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR1, 1));
 578         OUT_RING(chan, chan->vram->handle);
 579         OUT_RING(chan, RING_3D(NV30_3D_DMA_COLOR0, 2));
 580         OUT_RING(chan, chan->vram->handle);
 581         OUT_RING(chan, chan->vram->handle);
 582         OUT_RING(chan, RING_3D(NV30_3D_DMA_VTXBUF0, 2));
 583         OUT_RING(chan, chan->vram->handle);
 584         OUT_RING(chan, chan->gart->handle);
 585
 586         OUT_RING(chan, RING_3D(NV30_3D_DMA_FENCE, 2));
 587         OUT_RING(chan, 0);
 588         OUT_RING(chan, screen->query->handle);
 589
 590         OUT_RING(chan, RING_3D(NV30_3D_DMA_UNK1AC, 2));
 591         OUT_RING(chan, chan->vram->handle);
 592         OUT_RING(chan, chan->vram->handle);
 593
 594         if(!screen->is_nv4x)
 595                 nv30_screen_init(screen);
 596         else
 597                 nv40_screen_init(screen);
 598
 599         return pscreen;
 600 }