src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_format.h"
   4 #include "util/u_format_s3tc.h"
   5 #include "util/u_simple_screen.h"
   6 #include "vl/vl_decoder.h"
   7 #include "vl/vl_video_buffer.h"
   8
   9 #include "nouveau/nouveau_screen.h"
  10 #include "nouveau/nv_object.xml.h"
  11 #include "nvfx_context.h"
  12 #include "nvfx_screen.h"
  13 #include "nvfx_resource.h"
  14 #include "nvfx_tex.h"
  15
  16 #define NV30_3D_CHIPSET_3X_MASK 0x00000003
  17 #define NV34_3D_CHIPSET_3X_MASK 0x00000010
  18 #define NV35_3D_CHIPSET_3X_MASK 0x000001e0
  19
  20 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  21 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  22 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  23
  24 static int
  25 nvfx_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
  26 {
  27         struct nvfx_screen *screen = nvfx_screen(pscreen);
  28
  29         switch (param) {
  30         case PIPE_CAP_NPOT_TEXTURES:
  31                 return screen->advertise_npot;
  32         case PIPE_CAP_TWO_SIDED_STENCIL:
  33                 return 1;
  34         case PIPE_CAP_SM3:
  35                 /* TODO: >= nv4x support Shader Model 3.0 */
  36                 return 0;
  37         case PIPE_CAP_ANISOTROPIC_FILTER:
  38                 return 1;
  39         case PIPE_CAP_POINT_SPRITE:
  40                 return 1;
  41         case PIPE_CAP_MAX_RENDER_TARGETS:
  42                 return screen->use_nv4x ? 4 : 1;
  43         case PIPE_CAP_OCCLUSION_QUERY:
  44                 return 1;
  45         case PIPE_CAP_TIMER_QUERY:
  46                 return 0;
  47         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  48                 return 1;
  49         case PIPE_CAP_TEXTURE_SWIZZLE:
  50                 return 1;
  51         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  52                 return 13;
  53         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  54                 return 10;
  55         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  56                 return 13;
  57         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  58                 return !!screen->use_nv4x;
  59         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  60                 return screen->advertise_blend_equation_separate;
  61         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  62                 return 16;
  63         case PIPE_CAP_INDEP_BLEND_ENABLE:
  64                 /* TODO: on nv40 we have separate color masks */
  65                 /* TODO: nv40 mrt blending is probably broken */
  66                 return 0;
  67         case PIPE_CAP_INDEP_BLEND_FUNC:
  68                 return 0;
  69         case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
  70                 return 0;
  71         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  72         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  73         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  74         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  75                 return 1;
  76         case PIPE_CAP_DEPTH_CLAMP:
  77                 return 0; // TODO: implement depth clamp
  78         case PIPE_CAP_PRIMITIVE_RESTART:
  79                 return 0; // TODO: implement primitive restart
  80         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
  81         case PIPE_CAP_TGSI_INSTANCEID:
  82         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
  83         case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
  84         case PIPE_CAP_SEAMLESS_CUBE_MAP:
  85         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
  86         case PIPE_CAP_SHADER_STENCIL_EXPORT:
  87         case PIPE_CAP_MIN_TEXEL_OFFSET:
  88         case PIPE_CAP_MAX_TEXEL_OFFSET:
  89         case PIPE_CAP_CONDITIONAL_RENDER:
  90         case PIPE_CAP_TEXTURE_BARRIER:
  91                 return 0;
  92         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
  93                 return 0;
  94         default:
  95                 NOUVEAU_ERR("Warning: unknown PIPE_CAP %d\n", param);
  96                 return 0;
  97         }
  98 }
  99
 100 static int
 101 nvfx_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, enum pipe_shader_cap param)
 102 {
 103         struct nvfx_screen *screen = nvfx_screen(pscreen);
 104
 105         switch(shader) {
 106         case PIPE_SHADER_FRAGMENT:
 107                 switch(param) {
 108                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 109                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 110                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 111                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 112                         return 4096;
 113                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 114                         /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
 115                          value (nv30:0/nv40:4) ? */
 116                         return screen->use_nv4x ? 4 : 0;
 117                 case PIPE_SHADER_CAP_MAX_INPUTS:
 118                         return screen->use_nv4x ? 12 : 10;
 119                 case PIPE_SHADER_CAP_MAX_CONSTS:
 120                         return screen->use_nv4x ? 224 : 32;
 121                 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 122                     return 1;
 123                 case PIPE_SHADER_CAP_MAX_TEMPS:
 124                         return 32;
 125                 case PIPE_SHADER_CAP_MAX_ADDRS:
 126                         return screen->use_nv4x ? 1 : 0;
 127                 case PIPE_SHADER_CAP_MAX_PREDS:
 128                         return 0; /* we could expose these, but nothing uses them */
 129                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 130                     return 0;
 131                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 132                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 133                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 134                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 135                         return 0;
 136                 case PIPE_SHADER_CAP_SUBROUTINES:
 137                         return screen->use_nv4x ? 1 : 0;
 138                 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 139                         return 16;
 140                 default:
 141                         break;
 142                 }
 143                 break;
 144         case PIPE_SHADER_VERTEX:
 145                 switch(param) {
 146                 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 147                 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 148                         return screen->use_nv4x ? 512 : 256;
 149                 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 150                 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 151                         return screen->use_nv4x ? 512 : 0;
 152                 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 153                         /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
 154                          value (nv30:1/nv40:4) ? */
 155                         return screen->use_nv4x ? 4 : 1;
 156                 case PIPE_SHADER_CAP_MAX_INPUTS:
 157                         return 16;
 158                 case PIPE_SHADER_CAP_MAX_CONSTS:
 159                         /* - 6 is for clip planes; Gallium should be fixed to put
 160                          * them in the vertex shader itself, so we don't need to reserve these */
 161                         return (screen->use_nv4x ? 468 : 256) - 6;
 162                      case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 163                             return 1;
 164                 case PIPE_SHADER_CAP_MAX_TEMPS:
 165                         return screen->use_nv4x ? 32 : 13;
 166                 case PIPE_SHADER_CAP_MAX_ADDRS:
 167                         return 2;
 168                 case PIPE_SHADER_CAP_MAX_PREDS:
 169                         return 0; /* we could expose these, but nothing uses them */
 170                 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 171                         return 1;
 172                 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 173                 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 174                 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 175                         return 0;
 176                 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 177                         return 1;
 178                 case PIPE_SHADER_CAP_SUBROUTINES:
 179                         return 1;
 180                 case PIPE_SHADER_CAP_INTEGERS:
 181                         return 0;
 182                 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 183                         return 0; /* We have 4 on nv40 - but unsupported currently */
 184                 default:
 185                         break;
 186                 }
 187                 break;
 188         default:
 189                 break;
 190         }
 191         return 0;
 192 }
 193
 194 static float
 195 nvfx_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
 196 {
 197         struct nvfx_screen *screen = nvfx_screen(pscreen);
 198
 199         switch (param) {
 200         case PIPE_CAPF_MAX_LINE_WIDTH:
 201         case PIPE_CAPF_MAX_LINE_WIDTH_AA:
 202                 return 10.0;
 203         case PIPE_CAPF_MAX_POINT_WIDTH:
 204         case PIPE_CAPF_MAX_POINT_WIDTH_AA:
 205                 return 64.0;
 206         case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
 207                 return screen->use_nv4x ? 16.0 : 8.0;
 208         case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
 209                 return 15.0;
 210         default:
 211                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 212                 return 0.0;
 213         }
 214 }
 215
 216 static int
 217 nvfx_screen_get_video_param(struct pipe_screen *screen,
 218                                 enum pipe_video_profile profile,
 219                                 enum pipe_video_cap param)
 220 {
 221         switch (param) {
 222         case PIPE_VIDEO_CAP_SUPPORTED:
 223                 return vl_profile_supported(screen, profile);
 224         case PIPE_VIDEO_CAP_NPOT_TEXTURES:
 225                 return 0;
 226         case PIPE_VIDEO_CAP_MAX_WIDTH:
 227         case PIPE_VIDEO_CAP_MAX_HEIGHT:
 228                 return vl_video_buffer_max_size(screen);
 229         case PIPE_VIDEO_CAP_NUM_BUFFERS_DESIRED:
 230                 return vl_num_buffers_desired(screen, profile);
 231         default:
 232                 return 0;
 233         }
 234 }
 235
 236 static boolean
 237 nvfx_screen_is_format_supported(struct pipe_screen *pscreen,
 238                                      enum pipe_format format,
 239                                      enum pipe_texture_target target,
 240                                      unsigned sample_count,
 241                                      unsigned bind)
 242 {
 243         struct nvfx_screen *screen = nvfx_screen(pscreen);
 244
 245         if (!util_format_is_supported(format, bind))
 246                 return FALSE;
 247
 248          if (sample_count > 1)
 249                 return FALSE;
 250
 251         if (bind & PIPE_BIND_RENDER_TARGET) {
 252                 switch (format) {
 253                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 254                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 255                 case PIPE_FORMAT_R8G8B8A8_UNORM:
 256                 case PIPE_FORMAT_R8G8B8X8_UNORM:
 257                 case PIPE_FORMAT_B5G6R5_UNORM:
 258                         break;
 259                 case PIPE_FORMAT_R16G16B16A16_FLOAT:
 260                         if(!screen->advertise_fp16)
 261                                 return FALSE;
 262                         break;
 263                 case PIPE_FORMAT_R32G32B32A32_FLOAT:
 264                         if(!screen->advertise_fp32)
 265                                 return FALSE;
 266                         break;
 267                 default:
 268                         return FALSE;
 269                 }
 270         }
 271
 272         if (bind & PIPE_BIND_DEPTH_STENCIL) {
 273                 switch (format) {
 274                 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 275                 case PIPE_FORMAT_X8Z24_UNORM:
 276                 case PIPE_FORMAT_Z16_UNORM:
 277                         break;
 278                 default:
 279                         return FALSE;
 280                 }
 281         }
 282
 283         if (bind & PIPE_BIND_SAMPLER_VIEW) {
 284                 struct nvfx_texture_format* tf = &nvfx_texture_formats[format];
 285                 if(util_format_is_s3tc(format) && !util_format_s3tc_enabled)
 286                         return FALSE;
 287                 if(format == PIPE_FORMAT_R16G16B16A16_FLOAT && !screen->advertise_fp16)
 288                         return FALSE;
 289                 if(format == PIPE_FORMAT_R32G32B32A32_FLOAT && !screen->advertise_fp32)
 290                         return FALSE;
 291                 if(screen->use_nv4x)
 292                 {
 293                         if(tf->fmt[4] < 0)
 294                                 return FALSE;
 295                 }
 296                 else
 297                 {
 298                         if(tf->fmt[0] < 0)
 299                                 return FALSE;
 300                 }
 301         }
 302
 303         // note that we do actually support everything through translate
 304         if (bind & PIPE_BIND_VERTEX_BUFFER) {
 305                 unsigned type = nvfx_vertex_formats[format];
 306                 if(!type)
 307                         return FALSE;
 308         }
 309
 310         if (bind & PIPE_BIND_INDEX_BUFFER) {
 311                 // 8-bit indices supported, but not in hardware index buffer
 312                 if(format != PIPE_FORMAT_R16_USCALED && format != PIPE_FORMAT_R32_USCALED)
 313                         return FALSE;
 314         }
 315
 316         if(bind & PIPE_BIND_STREAM_OUTPUT)
 317                 return FALSE;
 318
 319         return TRUE;
 320 }
 321
 322 static void
 323 nvfx_screen_destroy(struct pipe_screen *pscreen)
 324 {
 325         struct nvfx_screen *screen = nvfx_screen(pscreen);
 326
 327         nouveau_resource_destroy(&screen->vp_exec_heap);
 328         nouveau_resource_destroy(&screen->vp_data_heap);
 329         nouveau_resource_destroy(&screen->query_heap);
 330         nouveau_notifier_free(&screen->query);
 331         nouveau_notifier_free(&screen->sync);
 332         nouveau_grobj_free(&screen->eng3d);
 333         nvfx_screen_surface_takedown(pscreen);
 334         nouveau_bo_ref(NULL, &screen->fence);
 335
 336         nouveau_screen_fini(&screen->base);
 337
 338         FREE(pscreen);
 339 }
 340
 341 static void nv30_screen_init(struct nvfx_screen *screen)
 342 {
 343         struct nouveau_channel *chan = screen->base.channel;
 344         struct nouveau_grobj *eng3d = screen->eng3d;
 345         int i;
 346
 347         /* TODO: perhaps we should do some of this on nv40 too? */
 348         for (i=1; i<8; i++) {
 349                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_HORIZ(i), 1);
 350                 OUT_RING(chan, 0);
 351                 BEGIN_RING(chan, eng3d, NV30_3D_VIEWPORT_CLIP_VERT(i), 1);
 352                 OUT_RING(chan, 0);
 353         }
 354
 355         BEGIN_RING(chan, eng3d, 0x220, 1);
 356         OUT_RING(chan, 1);
 357
 358         BEGIN_RING(chan, eng3d, 0x03b0, 1);
 359         OUT_RING(chan, 0x00100000);
 360         BEGIN_RING(chan, eng3d, 0x1454, 1);
 361         OUT_RING(chan, 0);
 362         BEGIN_RING(chan, eng3d, 0x1d80, 1);
 363         OUT_RING(chan, 3);
 364         BEGIN_RING(chan, eng3d, 0x1450, 1);
 365         OUT_RING(chan, 0x00030004);
 366
 367         /* NEW */
 368         BEGIN_RING(chan, eng3d, 0x1e98, 1);
 369         OUT_RING(chan, 0);
 370         BEGIN_RING(chan, eng3d, 0x17e0, 3);
 371         OUT_RING(chan, fui(0.0));
 372         OUT_RING(chan, fui(0.0));
 373         OUT_RING(chan, fui(1.0));
 374         BEGIN_RING(chan, eng3d, 0x1f80, 16);
 375         for (i=0; i<16; i++) {
 376                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 377         }
 378
 379         BEGIN_RING(chan, eng3d, 0x120, 3);
 380         OUT_RING(chan, 0);
 381         OUT_RING(chan, 1);
 382         OUT_RING(chan, 2);
 383
 384         BEGIN_RING(chan, eng3d, 0x1d88, 1);
 385         OUT_RING(chan, 0x00001200);
 386
 387         BEGIN_RING(chan, eng3d, NV30_3D_RC_ENABLE, 1);
 388         OUT_RING(chan, 0);
 389
 390         BEGIN_RING(chan, eng3d, NV30_3D_DEPTH_RANGE_NEAR, 2);
 391         OUT_RING(chan, fui(0.0));
 392         OUT_RING(chan, fui(1.0));
 393
 394         BEGIN_RING(chan, eng3d, NV30_3D_MULTISAMPLE_CONTROL, 1);
 395         OUT_RING(chan, 0xffff0000);
 396
 397         /* enables use of vp rather than fixed-function somehow */
 398         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 399         OUT_RING(chan, 0x13);
 400 }
 401
 402 static void nv40_screen_init(struct nvfx_screen *screen)
 403 {
 404         struct nouveau_channel *chan = screen->base.channel;
 405         struct nouveau_grobj *eng3d = screen->eng3d;
 406
 407         BEGIN_RING(chan, eng3d, NV40_3D_DMA_COLOR2, 2);
 408         OUT_RING(chan, screen->base.channel->vram->handle);
 409         OUT_RING(chan, screen->base.channel->vram->handle);
 410
 411         BEGIN_RING(chan, eng3d, 0x1450, 1);
 412         OUT_RING(chan, 0x00000004);
 413
 414         BEGIN_RING(chan, eng3d, 0x1ea4, 3);
 415         OUT_RING(chan, 0x00000010);
 416         OUT_RING(chan, 0x01000100);
 417         OUT_RING(chan, 0xff800006);
 418
 419         /* vtxprog output routing */
 420         BEGIN_RING(chan, eng3d, 0x1fc4, 1);
 421         OUT_RING(chan, 0x06144321);
 422         BEGIN_RING(chan, eng3d, 0x1fc8, 2);
 423         OUT_RING(chan, 0xedcba987);
 424         OUT_RING(chan, 0x0000006f);
 425         BEGIN_RING(chan, eng3d, 0x1fd0, 1);
 426         OUT_RING(chan, 0x00171615);
 427         BEGIN_RING(chan, eng3d, 0x1fd4, 1);
 428         OUT_RING(chan, 0x001b1a19);
 429
 430         BEGIN_RING(chan, eng3d, 0x1ef8, 1);
 431         OUT_RING(chan, 0x0020ffff);
 432         BEGIN_RING(chan, eng3d, 0x1d64, 1);
 433         OUT_RING(chan, 0x01d300d4);
 434         BEGIN_RING(chan, eng3d, 0x1e94, 1);
 435         OUT_RING(chan, 0x00000001);
 436
 437         BEGIN_RING(chan, eng3d, NV40_3D_MIPMAP_ROUNDING, 1);
 438         OUT_RING(chan, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
 439 }
 440
 441 static unsigned
 442 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
 443 {
 444         int vram_hack_default = 0;
 445         int vram_hack;
 446         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 447         // It may also depend on the specific card or the AGP/PCIe chipset.
 448         if(screen->base.device->chipset == 0x47 /* G70 */
 449                 || screen->base.device->chipset == 0x49 /* G71 */
 450                 || screen->base.device->chipset == 0x46 /* G72 */
 451                 )
 452                 vram_hack_default = 1;
 453         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 454
 455         return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 456 }
 457
 458 static void nvfx_channel_flush_notify(struct nouveau_channel* chan)
 459 {
 460         struct nvfx_screen* screen = chan->user_private;
 461         struct nvfx_context* nvfx = screen->cur_ctx;
 462         if(nvfx)
 463                 nvfx->relocs_needed = NVFX_RELOCATE_ALL;
 464 }
 465
 466 struct pipe_screen *
 467 nvfx_screen_create(struct nouveau_device *dev)
 468 {
 469         static const unsigned query_sizes[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
 470         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 471         struct nouveau_channel *chan;
 472         struct pipe_screen *pscreen;
 473         unsigned eng3d_class = 0;
 474         int ret, i;
 475
 476         if (!screen)
 477                 return NULL;
 478
 479         pscreen = &screen->base.base;
 480
 481         ret = nouveau_screen_init(&screen->base, dev);
 482         if (ret) {
 483                 nvfx_screen_destroy(pscreen);
 484                 return NULL;
 485         }
 486         chan = screen->base.channel;
 487         screen->cur_ctx = NULL;
 488         chan->user_private = screen;
 489         chan->flush_notify = nvfx_channel_flush_notify;
 490
 491         pscreen->destroy = nvfx_screen_destroy;
 492         pscreen->get_param = nvfx_screen_get_param;
 493         pscreen->get_shader_param = nvfx_screen_get_shader_param;
 494         pscreen->get_paramf = nvfx_screen_get_paramf;
 495         pscreen->get_video_param = nvfx_screen_get_video_param;
 496         pscreen->is_format_supported = nvfx_screen_is_format_supported;
 497         pscreen->is_video_format_supported = vl_video_buffer_is_format_supported;
 498         pscreen->context_create = nvfx_create;
 499
 500         ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 0, 4096, &screen->fence);
 501         if (ret) {
 502                 nvfx_screen_destroy(pscreen);
 503                 return NULL;
 504         }
 505
 506         switch (dev->chipset & 0xf0) {
 507         case 0x30:
 508                 if (NV30_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 509                         eng3d_class = NV30_3D;
 510                 else if (NV34_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 511                         eng3d_class = NV34_3D;
 512                 else if (NV35_3D_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 513                         eng3d_class = NV35_3D;
 514                 break;
 515         case 0x40:
 516                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 517                         eng3d_class = NV40_3D;
 518                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 519                         eng3d_class = NV44_3D;
 520                 screen->is_nv4x = ~0;
 521                 break;
 522         case 0x60:
 523                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 524                         eng3d_class = NV44_3D;
 525                 screen->is_nv4x = ~0;
 526                 break;
 527         }
 528
 529         if (!eng3d_class) {
 530                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 531                 return NULL;
 532         }
 533
 534         screen->advertise_npot = !!screen->is_nv4x;
 535         screen->advertise_blend_equation_separate = !!screen->is_nv4x;
 536         screen->use_nv4x = screen->is_nv4x;
 537
 538         if(screen->is_nv4x) {
 539                 if(debug_get_bool_option("NVFX_SIMULATE_NV30", FALSE))
 540                         screen->use_nv4x = 0;
 541                 if(!debug_get_bool_option("NVFX_NPOT", TRUE))
 542                         screen->advertise_npot = 0;
 543                 if(!debug_get_bool_option("NVFX_BLEND_EQ_SEP", TRUE))
 544                         screen->advertise_blend_equation_separate = 0;
 545         }
 546
 547         screen->force_swtnl = debug_get_bool_option("NVFX_SWTNL", FALSE);
 548         screen->trace_draw = debug_get_bool_option("NVFX_TRACE_DRAW", FALSE);
 549
 550         screen->buffer_allocation_cost = debug_get_num_option("NVFX_BUFFER_ALLOCATION_COST", 16384);
 551         screen->inline_cost_per_hardware_cost = atof(debug_get_option("NVFX_INLINE_COST_PER_HARDWARE_COST", "1.0"));
 552         screen->static_reuse_threshold = atof(debug_get_option("NVFX_STATIC_REUSE_THRESHOLD", "2.0"));
 553
 554         /* We don't advertise these by default because filtering and blending doesn't work as
 555          * it should, due to several restrictions.
 556          * The only exception is fp16 on nv40.
 557          */
 558         screen->advertise_fp16 = debug_get_bool_option("NVFX_FP16", !!screen->use_nv4x);
 559         screen->advertise_fp32 = debug_get_bool_option("NVFX_FP32", 0);
 560
 561         screen->vertex_buffer_reloc_flags = nvfx_screen_get_vertex_buffer_flags(screen);
 562
 563         /* surely both nv3x and nv44 support index buffers too: find out how and test that */
 564         if(eng3d_class == NV40_3D)
 565                 screen->index_buffer_reloc_flags = screen->vertex_buffer_reloc_flags;
 566
 567         if(!screen->force_swtnl && screen->vertex_buffer_reloc_flags == screen->index_buffer_reloc_flags)
 568                 screen->base.vertex_buffer_flags = screen->base.index_buffer_flags = screen->vertex_buffer_reloc_flags;
 569
 570         nvfx_screen_init_resource_functions(pscreen);
 571
 572         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 573         if (ret) {
 574                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 575                 return FALSE;
 576         }
 577
 578         /* 2D engine setup */
 579         nvfx_screen_surface_init(pscreen);
 580
 581         /* Notifier for sync purposes */
 582         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 583         if (ret) {
 584                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 585                 nvfx_screen_destroy(pscreen);
 586                 return NULL;
 587         }
 588
 589         /* Query objects */
 590         for(i = 0; i < sizeof(query_sizes) / sizeof(query_sizes[0]); ++i)
 591         {
 592                 ret = nouveau_notifier_alloc(chan, 0xbeef0302, query_sizes[i], &screen->query);
 593                 if(!ret)
 594                         break;
 595         }
 596
 597         if (ret) {
 598                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 599                 nvfx_screen_destroy(pscreen);
 600                 return NULL;
 601         }
 602
 603         ret = nouveau_resource_init(&screen->query_heap, 0, query_sizes[i]);
 604         if (ret) {
 605                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 606                 nvfx_screen_destroy(pscreen);
 607                 return NULL;
 608         }
 609
 610         LIST_INITHEAD(&screen->query_list);
 611
 612         /* Vtxprog resources */
 613         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->use_nv4x ? 512 : 256) ||
 614             nouveau_resource_init(&screen->vp_data_heap, 0, screen->use_nv4x ? 468 : 256)) {
 615                 nvfx_screen_destroy(pscreen);
 616                 return NULL;
 617         }
 618
 619         BIND_RING(chan, screen->eng3d, 7);
 620
 621         /* Static eng3d initialisation */
 622         /* note that we just started using the channel, so we must have space in the pushbuffer */
 623         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_NOTIFY, 1);
 624         OUT_RING(chan, screen->sync->handle);
 625         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_TEXTURE0, 2);
 626         OUT_RING(chan, chan->vram->handle);
 627         OUT_RING(chan, chan->gart->handle);
 628         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR1, 1);
 629         OUT_RING(chan, chan->vram->handle);
 630         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_COLOR0, 2);
 631         OUT_RING(chan, chan->vram->handle);
 632         OUT_RING(chan, chan->vram->handle);
 633         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_VTXBUF0, 2);
 634         OUT_RING(chan, chan->vram->handle);
 635         OUT_RING(chan, chan->gart->handle);
 636
 637         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_FENCE, 2);
 638         OUT_RING(chan, 0);
 639         OUT_RING(chan, screen->query->handle);
 640
 641         BEGIN_RING(chan, screen->eng3d, NV30_3D_DMA_UNK1AC, 2);
 642         OUT_RING(chan, chan->vram->handle);
 643         OUT_RING(chan, chan->vram->handle);
 644
 645         if(!screen->is_nv4x)
 646                 nv30_screen_init(screen);
 647         else
 648                 nv40_screen_init(screen);
 649
 650         return pscreen;
 651 }