1 #include "pipe/p_screen.h"
2 #include "pipe/p_state.h"
3 #include "util/u_format_s3tc.h"
4 #include "util/u_simple_screen.h"
6 #include "nouveau/nouveau_screen.h"
8 #include "nvfx_context.h"
9 #include "nvfx_screen.h"
10 #include "nvfx_resource.h"
12 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
13 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
14 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
16 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
17 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
18 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
19 * with same number of bits everywhere.
21 struct nouveau_winsys
{
22 struct pipe_winsys base
;
24 struct pipe_screen
*pscreen
;
26 struct pipe_surface
*front
;
28 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
29 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
30 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
33 nvfx_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
35 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
38 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
39 /* TODO: check this */
40 return screen
->is_nv4x
? 16 : 8;
41 case PIPE_CAP_NPOT_TEXTURES
:
42 return !!screen
->is_nv4x
;
43 case PIPE_CAP_TWO_SIDED_STENCIL
:
47 case PIPE_CAP_ANISOTROPIC_FILTER
:
49 case PIPE_CAP_POINT_SPRITE
:
51 case PIPE_CAP_MAX_RENDER_TARGETS
:
52 return screen
->is_nv4x
? 4 : 2;
53 case PIPE_CAP_OCCLUSION_QUERY
:
55 case PIPE_CAP_TIMER_QUERY
:
57 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
59 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
61 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
63 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
65 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
66 return !!screen
->is_nv4x
;
67 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
69 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
70 return 0; /* We have 4 on nv40 - but unsupported currently */
71 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
73 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
74 return !!screen
->is_nv4x
;
75 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
77 case PIPE_CAP_INDEP_BLEND_ENABLE
:
78 /* TODO: on nv40 we have separate color masks */
79 /* TODO: nv40 mrt blending is probably broken */
81 case PIPE_CAP_INDEP_BLEND_FUNC
:
83 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE
:
85 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
86 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
88 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
89 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
91 case PIPE_CAP_MAX_FS_INSTRUCTIONS
:
92 case PIPE_CAP_MAX_FS_ALU_INSTRUCTIONS
:
93 case PIPE_CAP_MAX_FS_TEX_INSTRUCTIONS
:
94 case PIPE_CAP_MAX_FS_TEX_INDIRECTIONS
:
96 case PIPE_CAP_MAX_FS_CONTROL_FLOW_DEPTH
:
97 /* FIXME: is it the dynamic (nv30:0/nv40:24) or the static
98 value (nv30:0/nv40:4) ? */
99 return screen
->is_nv4x
? 4 : 0;
100 case PIPE_CAP_MAX_FS_INPUTS
:
102 case PIPE_CAP_MAX_FS_CONSTS
:
103 return screen
->is_nv4x
? 224 : 32;
104 case PIPE_CAP_MAX_FS_TEMPS
:
106 case PIPE_CAP_MAX_FS_ADDRS
:
107 return screen
->is_nv4x
? 1 : 0;
108 case PIPE_CAP_MAX_FS_PREDS
:
109 return screen
->is_nv4x
? 1 : 0;
110 case PIPE_CAP_MAX_VS_INSTRUCTIONS
:
111 case PIPE_CAP_MAX_VS_ALU_INSTRUCTIONS
:
112 return screen
->is_nv4x
? 512 : 256;
113 case PIPE_CAP_MAX_VS_TEX_INSTRUCTIONS
:
114 case PIPE_CAP_MAX_VS_TEX_INDIRECTIONS
:
115 return screen
->is_nv4x
? 512 : 0;
116 case PIPE_CAP_MAX_VS_CONTROL_FLOW_DEPTH
:
117 /* FIXME: is it the dynamic (nv30:24/nv40:24) or the static
118 value (nv30:1/nv40:4) ? */
119 return screen
->is_nv4x
? 4 : 1;
120 case PIPE_CAP_MAX_VS_INPUTS
:
122 case PIPE_CAP_MAX_VS_CONSTS
:
124 case PIPE_CAP_MAX_VS_TEMPS
:
125 return screen
->is_nv4x
? 32 : 13;
126 case PIPE_CAP_MAX_VS_ADDRS
:
128 case PIPE_CAP_MAX_VS_PREDS
:
129 return screen
->is_nv4x
? 1 : 0;
131 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
137 nvfx_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_cap param
)
139 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
142 case PIPE_CAP_MAX_LINE_WIDTH
:
143 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
145 case PIPE_CAP_MAX_POINT_WIDTH
:
146 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
148 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
149 return screen
->is_nv4x
? 16.0 : 8.0;
150 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
151 return screen
->is_nv4x
? 16.0 : 4.0;
153 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
159 nvfx_screen_surface_format_supported(struct pipe_screen
*pscreen
,
160 enum pipe_format format
,
161 enum pipe_texture_target target
,
162 unsigned sample_count
,
163 unsigned tex_usage
, unsigned geom_flags
)
165 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
166 struct pipe_surface
*front
= ((struct nouveau_winsys
*) pscreen
->winsys
)->front
;
168 if (sample_count
> 1)
171 if (tex_usage
& PIPE_BIND_RENDER_TARGET
) {
173 case PIPE_FORMAT_B8G8R8A8_UNORM
:
174 case PIPE_FORMAT_B8G8R8X8_UNORM
:
175 case PIPE_FORMAT_B5G6R5_UNORM
:
181 if (tex_usage
& PIPE_BIND_DEPTH_STENCIL
) {
183 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
184 case PIPE_FORMAT_X8Z24_UNORM
:
186 case PIPE_FORMAT_Z16_UNORM
:
187 /* TODO: this nv30 limitation probably does not exist */
188 if (!screen
->is_nv4x
&& front
)
189 return (front
->format
== PIPE_FORMAT_B5G6R5_UNORM
);
196 if (tex_usage
& PIPE_BIND_SAMPLER_VIEW
) {
198 case PIPE_FORMAT_DXT1_RGB
:
199 case PIPE_FORMAT_DXT1_RGBA
:
200 case PIPE_FORMAT_DXT3_RGBA
:
201 case PIPE_FORMAT_DXT5_RGBA
:
202 return util_format_s3tc_enabled
;
207 case PIPE_FORMAT_B8G8R8A8_UNORM
:
208 case PIPE_FORMAT_B8G8R8X8_UNORM
:
209 case PIPE_FORMAT_B5G5R5A1_UNORM
:
210 case PIPE_FORMAT_B4G4R4A4_UNORM
:
211 case PIPE_FORMAT_B5G6R5_UNORM
:
212 case PIPE_FORMAT_L8_UNORM
:
213 case PIPE_FORMAT_A8_UNORM
:
214 case PIPE_FORMAT_I8_UNORM
:
215 case PIPE_FORMAT_L8A8_UNORM
:
216 case PIPE_FORMAT_Z16_UNORM
:
217 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
219 /* TODO: does nv30 support this? */
220 case PIPE_FORMAT_R16_SNORM
:
221 return !!screen
->is_nv4x
;
232 nvfx_screen_destroy(struct pipe_screen
*pscreen
)
234 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
236 nouveau_resource_destroy(&screen
->vp_exec_heap
);
237 nouveau_resource_destroy(&screen
->vp_data_heap
);
238 nouveau_resource_destroy(&screen
->query_heap
);
239 nouveau_notifier_free(&screen
->query
);
240 nouveau_notifier_free(&screen
->sync
);
241 nouveau_grobj_free(&screen
->eng3d
);
242 nv04_surface_2d_takedown(&screen
->eng2d
);
244 nouveau_screen_fini(&screen
->base
);
249 static void nv30_screen_init(struct nvfx_screen
*screen
)
251 struct nouveau_channel
*chan
= screen
->base
.channel
;
254 /* TODO: perhaps we should do some of this on nv40 too? */
255 for (i
=1; i
<8; i
++) {
256 OUT_RING(chan
, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i
), 1));
258 OUT_RING(chan
, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i
), 1));
262 OUT_RING(chan
, RING_3D(0x220, 1));
265 OUT_RING(chan
, RING_3D(0x03b0, 1));
266 OUT_RING(chan
, 0x00100000);
267 OUT_RING(chan
, RING_3D(0x1454, 1));
269 OUT_RING(chan
, RING_3D(0x1d80, 1));
271 OUT_RING(chan
, RING_3D(0x1450, 1));
272 OUT_RING(chan
, 0x00030004);
275 OUT_RING(chan
, RING_3D(0x1e98, 1));
277 OUT_RING(chan
, RING_3D(0x17e0, 3));
278 OUT_RING(chan
, fui(0.0));
279 OUT_RING(chan
, fui(0.0));
280 OUT_RING(chan
, fui(1.0));
281 OUT_RING(chan
, RING_3D(0x1f80, 16));
282 for (i
=0; i
<16; i
++) {
283 OUT_RING(chan
, (i
==8) ? 0x0000ffff : 0);
286 OUT_RING(chan
, RING_3D(0x120, 3));
291 OUT_RING(chan
, RING_3D(0x1d88, 1));
292 OUT_RING(chan
, 0x00001200);
294 OUT_RING(chan
, RING_3D(NV34TCL_RC_ENABLE
, 1));
297 OUT_RING(chan
, RING_3D(NV34TCL_DEPTH_RANGE_NEAR
, 2));
298 OUT_RING(chan
, fui(0.0));
299 OUT_RING(chan
, fui(1.0));
301 OUT_RING(chan
, RING_3D(NV34TCL_MULTISAMPLE_CONTROL
, 1));
302 OUT_RING(chan
, 0xffff0000);
304 /* enables use of vp rather than fixed-function somehow */
305 OUT_RING(chan
, RING_3D(0x1e94, 1));
306 OUT_RING(chan
, 0x13);
309 static void nv40_screen_init(struct nvfx_screen
*screen
)
311 struct nouveau_channel
*chan
= screen
->base
.channel
;
313 OUT_RING(chan
, RING_3D(NV40TCL_DMA_COLOR2
, 2));
314 OUT_RING(chan
, screen
->base
.channel
->vram
->handle
);
315 OUT_RING(chan
, screen
->base
.channel
->vram
->handle
);
317 OUT_RING(chan
, RING_3D(0x1ea4, 3));
318 OUT_RING(chan
, 0x00000010);
319 OUT_RING(chan
, 0x01000100);
320 OUT_RING(chan
, 0xff800006);
322 /* vtxprog output routing */
323 OUT_RING(chan
, RING_3D(0x1fc4, 1));
324 OUT_RING(chan
, 0x06144321);
325 OUT_RING(chan
, RING_3D(0x1fc8, 2));
326 OUT_RING(chan
, 0xedcba987);
327 OUT_RING(chan
, 0x00000021);
328 OUT_RING(chan
, RING_3D(0x1fd0, 1));
329 OUT_RING(chan
, 0x00171615);
330 OUT_RING(chan
, RING_3D(0x1fd4, 1));
331 OUT_RING(chan
, 0x001b1a19);
333 OUT_RING(chan
, RING_3D(0x1ef8, 1));
334 OUT_RING(chan
, 0x0020ffff);
335 OUT_RING(chan
, RING_3D(0x1d64, 1));
336 OUT_RING(chan
, 0x00d30000);
337 OUT_RING(chan
, RING_3D(0x1e94, 1));
338 OUT_RING(chan
, 0x00000001);
342 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen
* screen
)
344 int vram_hack_default
= 0;
346 // TODO: this is a bit of a guess; also add other cards that may need this hack.
347 // It may also depend on the specific card or the AGP/PCIe chipset.
348 if(screen
->base
.device
->chipset
== 0x47 /* G70 */
349 || screen
->base
.device
->chipset
== 0x49 /* G71 */
350 || screen
->base
.device
->chipset
== 0x46 /* G72 */
352 vram_hack_default
= 1;
353 vram_hack
= debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default
);
358 fprintf(stderr
, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
359 "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
363 fprintf(stderr
, "A performance reducing hack is being used to help avoid graphics corruption.\n"
364 "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
368 return vram_hack
? NOUVEAU_BO_VRAM
: NOUVEAU_BO_GART
;
372 nvfx_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
374 static const unsigned query_sizes
[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
375 struct nvfx_screen
*screen
= CALLOC_STRUCT(nvfx_screen
);
376 struct nouveau_channel
*chan
;
377 struct pipe_screen
*pscreen
;
378 unsigned eng3d_class
= 0;
384 pscreen
= &screen
->base
.base
;
386 ret
= nouveau_screen_init(&screen
->base
, dev
);
388 nvfx_screen_destroy(pscreen
);
391 chan
= screen
->base
.channel
;
393 pscreen
->winsys
= ws
;
394 pscreen
->destroy
= nvfx_screen_destroy
;
395 pscreen
->get_param
= nvfx_screen_get_param
;
396 pscreen
->get_paramf
= nvfx_screen_get_paramf
;
397 pscreen
->is_format_supported
= nvfx_screen_surface_format_supported
;
398 pscreen
->context_create
= nvfx_create
;
400 switch (dev
->chipset
& 0xf0) {
402 if (NV30TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
403 eng3d_class
= 0x0397;
404 else if (NV34TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
405 eng3d_class
= 0x0697;
406 else if (NV35TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
407 eng3d_class
= 0x0497;
410 if (NV4X_GRCLASS4097_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
411 eng3d_class
= NV40TCL
;
412 else if (NV4X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
413 eng3d_class
= NV44TCL
;
414 screen
->is_nv4x
= ~0;
417 if (NV6X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
418 eng3d_class
= NV44TCL
;
419 screen
->is_nv4x
= ~0;
424 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev
->chipset
);
428 screen
->force_swtnl
= debug_get_bool_option("NOUVEAU_SWTNL", FALSE
);
430 screen
->vertex_buffer_reloc_flags
= nvfx_screen_get_vertex_buffer_flags(screen
);
432 /* surely both nv3x and nv44 support index buffers too: find out how and test that */
433 if(eng3d_class
== NV40TCL
)
434 screen
->index_buffer_reloc_flags
= screen
->vertex_buffer_reloc_flags
;
436 if(!screen
->force_swtnl
&& screen
->vertex_buffer_reloc_flags
== screen
->index_buffer_reloc_flags
)
437 screen
->base
.vertex_buffer_flags
= screen
->base
.index_buffer_flags
= screen
->vertex_buffer_reloc_flags
;
439 nvfx_screen_init_resource_functions(pscreen
);
441 ret
= nouveau_grobj_alloc(chan
, 0xbeef3097, eng3d_class
, &screen
->eng3d
);
443 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
447 /* 2D engine setup */
448 screen
->eng2d
= nv04_surface_2d_init(&screen
->base
);
449 screen
->eng2d
->buf
= nvfx_surface_buffer
;
451 /* Notifier for sync purposes */
452 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
454 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
455 nvfx_screen_destroy(pscreen
);
460 for(i
= 0; i
< sizeof(query_sizes
) / sizeof(query_sizes
[0]); ++i
)
462 ret
= nouveau_notifier_alloc(chan
, 0xbeef0302, query_sizes
[i
], &screen
->query
);
468 NOUVEAU_ERR("Error initialising query objects: %d\n", ret
);
469 nvfx_screen_destroy(pscreen
);
473 ret
= nouveau_resource_init(&screen
->query_heap
, 0, query_sizes
[i
]);
475 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret
);
476 nvfx_screen_destroy(pscreen
);
480 LIST_INITHEAD(&screen
->query_list
);
482 /* Vtxprog resources */
483 if (nouveau_resource_init(&screen
->vp_exec_heap
, 0, screen
->is_nv4x
? 512 : 256) ||
484 nouveau_resource_init(&screen
->vp_data_heap
, 0, 256)) {
485 nvfx_screen_destroy(pscreen
);
489 BIND_RING(chan
, screen
->eng3d
, 7);
491 /* Static eng3d initialisation */
492 /* note that we just started using the channel, so we must have space in the pushbuffer */
493 OUT_RING(chan
, RING_3D(NV34TCL_DMA_NOTIFY
, 1));
494 OUT_RING(chan
, screen
->sync
->handle
);
495 OUT_RING(chan
, RING_3D(NV34TCL_DMA_TEXTURE0
, 2));
496 OUT_RING(chan
, chan
->vram
->handle
);
497 OUT_RING(chan
, chan
->gart
->handle
);
498 OUT_RING(chan
, RING_3D(NV34TCL_DMA_COLOR1
, 1));
499 OUT_RING(chan
, chan
->vram
->handle
);
500 OUT_RING(chan
, RING_3D(NV34TCL_DMA_COLOR0
, 2));
501 OUT_RING(chan
, chan
->vram
->handle
);
502 OUT_RING(chan
, chan
->vram
->handle
);
503 OUT_RING(chan
, RING_3D(NV34TCL_DMA_VTXBUF0
, 2));
504 OUT_RING(chan
, chan
->vram
->handle
);
505 OUT_RING(chan
, chan
->gart
->handle
);
507 OUT_RING(chan
, RING_3D(NV34TCL_DMA_FENCE
, 2));
509 OUT_RING(chan
, screen
->query
->handle
);
511 OUT_RING(chan
, RING_3D(NV34TCL_DMA_IN_MEMORY7
, 2));
512 OUT_RING(chan
, chan
->vram
->handle
);
513 OUT_RING(chan
, chan
->vram
->handle
);
516 nv30_screen_init(screen
);
518 nv40_screen_init(screen
);