1 #include "pipe/p_screen.h"
2 #include "pipe/p_state.h"
3 #include "util/u_simple_screen.h"
5 #include "nouveau/nouveau_screen.h"
7 #include "nvfx_context.h"
8 #include "nvfx_screen.h"
9 #include "nvfx_resource.h"
11 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
12 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
13 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
15 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
16 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
17 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
18 * with same number of bits everywhere.
20 struct nouveau_winsys
{
21 struct pipe_winsys base
;
23 struct pipe_screen
*pscreen
;
25 struct pipe_surface
*front
;
27 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
28 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
29 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
32 nvfx_screen_get_param(struct pipe_screen
*pscreen
, int param
)
34 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
37 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
38 /* TODO: check this */
39 return screen
->is_nv4x
? 16 : 8;
40 case PIPE_CAP_NPOT_TEXTURES
:
41 return !!screen
->is_nv4x
;
42 case PIPE_CAP_TWO_SIDED_STENCIL
:
46 case PIPE_CAP_ANISOTROPIC_FILTER
:
48 case PIPE_CAP_POINT_SPRITE
:
50 case PIPE_CAP_MAX_RENDER_TARGETS
:
51 return screen
->is_nv4x
? 4 : 2;
52 case PIPE_CAP_OCCLUSION_QUERY
:
54 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
56 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
58 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
60 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
62 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
63 return !!screen
->is_nv4x
;
64 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
66 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
67 return 0; /* We have 4 on nv40 - but unsupported currently */
68 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
70 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
71 return !!screen
->is_nv4x
;
72 case NOUVEAU_CAP_HW_VTXBUF
:
73 return !screen
->force_swtnl
;
74 case NOUVEAU_CAP_HW_IDXBUF
:
75 return !screen
->force_swtnl
&& screen
->eng3d
->grclass
== NV40TCL
;
76 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
78 case PIPE_CAP_INDEP_BLEND_ENABLE
:
79 /* TODO: on nv40 we have separate color masks */
80 /* TODO: nv40 mrt blending is probably broken */
82 case PIPE_CAP_INDEP_BLEND_FUNC
:
84 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
85 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
87 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
88 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
91 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
97 nvfx_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
99 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
102 case PIPE_CAP_MAX_LINE_WIDTH
:
103 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
105 case PIPE_CAP_MAX_POINT_WIDTH
:
106 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
108 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
109 return screen
->is_nv4x
? 16.0 : 8.0;
110 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
111 return screen
->is_nv4x
? 16.0 : 4.0;
113 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
119 nvfx_screen_surface_format_supported(struct pipe_screen
*pscreen
,
120 enum pipe_format format
,
121 enum pipe_texture_target target
,
122 unsigned tex_usage
, unsigned geom_flags
)
124 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
125 struct pipe_surface
*front
= ((struct nouveau_winsys
*) pscreen
->winsys
)->front
;
127 if (tex_usage
& PIPE_BIND_RENDER_TARGET
) {
129 case PIPE_FORMAT_B8G8R8A8_UNORM
:
130 case PIPE_FORMAT_B8G8R8X8_UNORM
:
131 case PIPE_FORMAT_B5G6R5_UNORM
:
137 if (tex_usage
& PIPE_BIND_DEPTH_STENCIL
) {
139 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
140 case PIPE_FORMAT_X8Z24_UNORM
:
142 case PIPE_FORMAT_Z16_UNORM
:
143 /* TODO: this nv30 limitation probably does not exist */
144 if (!screen
->is_nv4x
&& front
)
145 return (front
->format
== PIPE_FORMAT_B5G6R5_UNORM
);
152 case PIPE_FORMAT_B8G8R8A8_UNORM
:
153 case PIPE_FORMAT_B8G8R8X8_UNORM
:
154 case PIPE_FORMAT_B5G5R5A1_UNORM
:
155 case PIPE_FORMAT_B4G4R4A4_UNORM
:
156 case PIPE_FORMAT_B5G6R5_UNORM
:
157 case PIPE_FORMAT_L8_UNORM
:
158 case PIPE_FORMAT_A8_UNORM
:
159 case PIPE_FORMAT_I8_UNORM
:
160 case PIPE_FORMAT_L8A8_UNORM
:
161 case PIPE_FORMAT_Z16_UNORM
:
162 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
163 case PIPE_FORMAT_DXT1_RGB
:
164 case PIPE_FORMAT_DXT1_RGBA
:
165 case PIPE_FORMAT_DXT3_RGBA
:
166 case PIPE_FORMAT_DXT5_RGBA
:
168 /* TODO: does nv30 support this? */
169 case PIPE_FORMAT_R16_SNORM
:
170 return !!screen
->is_nv4x
;
181 nvfx_screen_destroy(struct pipe_screen
*pscreen
)
183 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
185 nouveau_resource_destroy(&screen
->vp_exec_heap
);
186 nouveau_resource_destroy(&screen
->vp_data_heap
);
187 nouveau_resource_destroy(&screen
->query_heap
);
188 nouveau_notifier_free(&screen
->query
);
189 nouveau_notifier_free(&screen
->sync
);
190 nouveau_grobj_free(&screen
->eng3d
);
191 nv04_surface_2d_takedown(&screen
->eng2d
);
193 nouveau_screen_fini(&screen
->base
);
198 static void nv30_screen_init(struct nvfx_screen
*screen
)
200 struct nouveau_channel
*chan
= screen
->base
.channel
;
203 /* TODO: perhaps we should do some of this on nv40 too? */
204 for (i
=1; i
<8; i
++) {
205 OUT_RING(chan
, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i
), 1));
207 OUT_RING(chan
, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i
), 1));
211 OUT_RING(chan
, RING_3D(0x220, 1));
214 OUT_RING(chan
, RING_3D(0x03b0, 1));
215 OUT_RING(chan
, 0x00100000);
216 OUT_RING(chan
, RING_3D(0x1454, 1));
218 OUT_RING(chan
, RING_3D(0x1d80, 1));
220 OUT_RING(chan
, RING_3D(0x1450, 1));
221 OUT_RING(chan
, 0x00030004);
224 OUT_RING(chan
, RING_3D(0x1e98, 1));
226 OUT_RING(chan
, RING_3D(0x17e0, 3));
227 OUT_RING(chan
, fui(0.0));
228 OUT_RING(chan
, fui(0.0));
229 OUT_RING(chan
, fui(1.0));
230 OUT_RING(chan
, RING_3D(0x1f80, 16));
231 for (i
=0; i
<16; i
++) {
232 OUT_RING(chan
, (i
==8) ? 0x0000ffff : 0);
235 OUT_RING(chan
, RING_3D(0x120, 3));
240 OUT_RING(chan
, RING_3D(0x1d88, 1));
241 OUT_RING(chan
, 0x00001200);
243 OUT_RING(chan
, RING_3D(NV34TCL_RC_ENABLE
, 1));
246 OUT_RING(chan
, RING_3D(NV34TCL_DEPTH_RANGE_NEAR
, 2));
247 OUT_RING(chan
, fui(0.0));
248 OUT_RING(chan
, fui(1.0));
250 OUT_RING(chan
, RING_3D(NV34TCL_MULTISAMPLE_CONTROL
, 1));
251 OUT_RING(chan
, 0xffff0000);
253 /* enables use of vp rather than fixed-function somehow */
254 OUT_RING(chan
, RING_3D(0x1e94, 1));
255 OUT_RING(chan
, 0x13);
258 static void nv40_screen_init(struct nvfx_screen
*screen
)
260 struct nouveau_channel
*chan
= screen
->base
.channel
;
262 OUT_RING(chan
, RING_3D(NV40TCL_DMA_COLOR2
, 2));
263 OUT_RING(chan
, screen
->base
.channel
->vram
->handle
);
264 OUT_RING(chan
, screen
->base
.channel
->vram
->handle
);
266 OUT_RING(chan
, RING_3D(0x1ea4, 3));
267 OUT_RING(chan
, 0x00000010);
268 OUT_RING(chan
, 0x01000100);
269 OUT_RING(chan
, 0xff800006);
271 /* vtxprog output routing */
272 OUT_RING(chan
, RING_3D(0x1fc4, 1));
273 OUT_RING(chan
, 0x06144321);
274 OUT_RING(chan
, RING_3D(0x1fc8, 2));
275 OUT_RING(chan
, 0xedcba987);
276 OUT_RING(chan
, 0x00000021);
277 OUT_RING(chan
, RING_3D(0x1fd0, 1));
278 OUT_RING(chan
, 0x00171615);
279 OUT_RING(chan
, RING_3D(0x1fd4, 1));
280 OUT_RING(chan
, 0x001b1a19);
282 OUT_RING(chan
, RING_3D(0x1ef8, 1));
283 OUT_RING(chan
, 0x0020ffff);
284 OUT_RING(chan
, RING_3D(0x1d64, 1));
285 OUT_RING(chan
, 0x00d30000);
286 OUT_RING(chan
, RING_3D(0x1e94, 1));
287 OUT_RING(chan
, 0x00000001);
291 nvfx_screen_init_buffer_functions(struct nvfx_screen
* screen
)
293 int vram_hack_default
= 0;
295 // TODO: this is a bit of a guess; also add other cards that may need this hack.
296 // It may also depend on the specific card or the AGP/PCIe chipset.
297 if(screen
->base
.device
->chipset
== 0x47 /* G70 */
298 || screen
->base
.device
->chipset
== 0x49 /* G71 */
299 || screen
->base
.device
->chipset
== 0x46 /* G72 */
301 vram_hack_default
= 1;
302 vram_hack
= debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default
);
307 fprintf(stderr
, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
308 "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
312 fprintf(stderr
, "A performance reducing hack is being used to help avoid graphics corruption.\n"
313 "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
317 screen
->vertex_buffer_flags
= vram_hack
? NOUVEAU_BO_VRAM
: NOUVEAU_BO_GART
;
321 nvfx_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
323 struct nvfx_screen
*screen
= CALLOC_STRUCT(nvfx_screen
);
324 struct nouveau_channel
*chan
;
325 struct pipe_screen
*pscreen
;
326 unsigned eng3d_class
= 0;
332 pscreen
= &screen
->base
.base
;
334 ret
= nouveau_screen_init(&screen
->base
, dev
);
336 nvfx_screen_destroy(pscreen
);
339 chan
= screen
->base
.channel
;
341 pscreen
->winsys
= ws
;
342 pscreen
->destroy
= nvfx_screen_destroy
;
343 pscreen
->get_param
= nvfx_screen_get_param
;
344 pscreen
->get_paramf
= nvfx_screen_get_paramf
;
345 pscreen
->is_format_supported
= nvfx_screen_surface_format_supported
;
346 pscreen
->context_create
= nvfx_create
;
348 switch (dev
->chipset
& 0xf0) {
350 if (NV30TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
351 eng3d_class
= 0x0397;
352 else if (NV34TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
353 eng3d_class
= 0x0697;
354 else if (NV35TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
355 eng3d_class
= 0x0497;
358 if (NV4X_GRCLASS4097_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
359 eng3d_class
= NV40TCL
;
360 else if (NV4X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
361 eng3d_class
= NV44TCL
;
362 screen
->is_nv4x
= ~0;
365 if (NV6X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
366 eng3d_class
= NV44TCL
;
367 screen
->is_nv4x
= ~0;
372 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev
->chipset
);
376 screen
->force_swtnl
= debug_get_bool_option("NOUVEAU_SWTNL", FALSE
);
378 nvfx_screen_init_resource_functions(pscreen
);
379 nvfx_screen_init_buffer_functions(screen
);
381 ret
= nouveau_grobj_alloc(chan
, 0xbeef3097, eng3d_class
, &screen
->eng3d
);
383 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
387 /* 2D engine setup */
388 screen
->eng2d
= nv04_surface_2d_init(&screen
->base
);
389 screen
->eng2d
->buf
= nvfx_surface_buffer
;
391 /* Notifier for sync purposes */
392 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
394 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
395 nvfx_screen_destroy(pscreen
);
400 unsigned query_sizes
[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
401 for(i
= 0; i
< sizeof(query_sizes
) / sizeof(query_sizes
[0]); ++i
)
403 ret
= nouveau_notifier_alloc(chan
, 0xbeef0302, query_sizes
[i
], &screen
->query
);
409 NOUVEAU_ERR("Error initialising query objects: %d\n", ret
);
410 nvfx_screen_destroy(pscreen
);
414 ret
= nouveau_resource_init(&screen
->query_heap
, 0, query_sizes
[i
]);
416 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret
);
417 nvfx_screen_destroy(pscreen
);
421 LIST_INITHEAD(&screen
->query_list
);
423 /* Vtxprog resources */
424 if (nouveau_resource_init(&screen
->vp_exec_heap
, 0, screen
->is_nv4x
? 512 : 256) ||
425 nouveau_resource_init(&screen
->vp_data_heap
, 0, 256)) {
426 nvfx_screen_destroy(pscreen
);
430 BIND_RING(chan
, screen
->eng3d
, 7);
432 /* Static eng3d initialisation */
433 /* note that we just started using the channel, so we must have space in the pushbuffer */
434 OUT_RING(chan
, RING_3D(NV34TCL_DMA_NOTIFY
, 1));
435 OUT_RING(chan
, screen
->sync
->handle
);
436 OUT_RING(chan
, RING_3D(NV34TCL_DMA_TEXTURE0
, 2));
437 OUT_RING(chan
, chan
->vram
->handle
);
438 OUT_RING(chan
, chan
->gart
->handle
);
439 OUT_RING(chan
, RING_3D(NV34TCL_DMA_COLOR1
, 1));
440 OUT_RING(chan
, chan
->vram
->handle
);
441 OUT_RING(chan
, RING_3D(NV34TCL_DMA_COLOR0
, 2));
442 OUT_RING(chan
, chan
->vram
->handle
);
443 OUT_RING(chan
, chan
->vram
->handle
);
444 OUT_RING(chan
, RING_3D(NV34TCL_DMA_VTXBUF0
, 2));
445 OUT_RING(chan
, chan
->vram
->handle
);
446 OUT_RING(chan
, chan
->gart
->handle
);
448 OUT_RING(chan
, RING_3D(NV34TCL_DMA_FENCE
, 2));
450 OUT_RING(chan
, screen
->query
->handle
);
452 OUT_RING(chan
, RING_3D(NV34TCL_DMA_IN_MEMORY7
, 2));
453 OUT_RING(chan
, chan
->vram
->handle
);
454 OUT_RING(chan
, chan
->vram
->handle
);
457 nv30_screen_init(screen
);
459 nv40_screen_init(screen
);