src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3
   4 #include "nouveau/nouveau_screen.h"
   5
   6 #include "nvfx_context.h"
   7 #include "nvfx_screen.h"
   8
   9 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
  10 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
  11 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
  12
  13 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
  14 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
  15 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
  16 * with same number of bits everywhere.
  17 */
  18 struct nouveau_winsys {
  19         struct pipe_winsys base;
  20
  21         struct pipe_screen *pscreen;
  22
  23         struct pipe_surface *front;
  24 };
  25 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  26 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  27 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  28
  29 static int
  30 nvfx_screen_get_param(struct pipe_screen *pscreen, int param)
  31 {
  32         struct nvfx_screen *screen = nvfx_screen(pscreen);
  33
  34         switch (param) {
  35         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  36                 /* TODO: check this */
  37                 return screen->is_nv4x ? 16 : 8;
  38         case PIPE_CAP_NPOT_TEXTURES:
  39                 return !!screen->is_nv4x;
  40         case PIPE_CAP_TWO_SIDED_STENCIL:
  41                 return 1;
  42         case PIPE_CAP_GLSL:
  43                 return 0;
  44         case PIPE_CAP_ANISOTROPIC_FILTER:
  45                 return 1;
  46         case PIPE_CAP_POINT_SPRITE:
  47                 return 1;
  48         case PIPE_CAP_MAX_RENDER_TARGETS:
  49                 return screen->is_nv4x ? 4 : 2;
  50         case PIPE_CAP_OCCLUSION_QUERY:
  51                 return 1;
  52         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  53                 return 1;
  54         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  55                 return 13;
  56         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  57                 return 10;
  58         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  59                 return 13;
  60         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  61                 return !!screen->is_nv4x;
  62         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  63                 return 1;
  64         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  65                 return 0; /* We have 4 on nv40 - but unsupported currently */
  66         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  67                 return 0;
  68         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  69                 return !!screen->is_nv4x;
  70         case NOUVEAU_CAP_HW_VTXBUF:
  71                 /* TODO: this is almost surely wrong */
  72                 return !!screen->is_nv4x;
  73         case NOUVEAU_CAP_HW_IDXBUF:
  74                 /* TODO: this is also almost surely wrong */
  75                 return screen->is_nv4x && screen->eng3d->grclass == NV40TCL;
  76         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  77                 return 16;
  78         case PIPE_CAP_INDEP_BLEND_ENABLE:
  79                 /* TODO: on nv40 we have separate color masks */
  80                 /* TODO: nv40 mrt blending is probably broken */
  81                 return 0;
  82         case PIPE_CAP_INDEP_BLEND_FUNC:
  83                 return 0;
  84         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  85         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  86                 return 1;
  87         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  88         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  89                 return 0;
  90         default:
  91                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  92                 return 0;
  93         }
  94 }
  95
  96 static float
  97 nvfx_screen_get_paramf(struct pipe_screen *pscreen, int param)
  98 {
  99         struct nvfx_screen *screen = nvfx_screen(pscreen);
 100
 101         switch (param) {
 102         case PIPE_CAP_MAX_LINE_WIDTH:
 103         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 104                 return 10.0;
 105         case PIPE_CAP_MAX_POINT_WIDTH:
 106         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 107                 return 64.0;
 108         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 109                 return screen->is_nv4x ? 16.0 : 8.0;
 110         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 111                 return screen->is_nv4x ? 16.0 : 4.0;
 112         default:
 113                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 114                 return 0.0;
 115         }
 116 }
 117
 118 static boolean
 119 nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 120                                      enum pipe_format format,
 121                                      enum pipe_texture_target target,
 122                                      unsigned tex_usage, unsigned geom_flags)
 123 {
 124         struct nvfx_screen *screen = nvfx_screen(pscreen);
 125         struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
 126
 127         if (tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET) {
 128                 switch (format) {
 129                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 130                 case PIPE_FORMAT_B5G6R5_UNORM:
 131                         return TRUE;
 132                 default:
 133                         break;
 134                 }
 135         } else
 136         if (tex_usage & PIPE_TEXTURE_USAGE_DEPTH_STENCIL) {
 137                 switch (format) {
 138                 case PIPE_FORMAT_S8Z24_UNORM:
 139                 case PIPE_FORMAT_X8Z24_UNORM:
 140                         return TRUE;
 141                 case PIPE_FORMAT_Z16_UNORM:
 142                         /* TODO: this nv30 limitation probably does not exist */
 143                         if (!screen->is_nv4x && front)
 144                                 return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
 145                         return TRUE;
 146                 default:
 147                         break;
 148                 }
 149         } else {
 150                 switch (format) {
 151                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 152                 case PIPE_FORMAT_B5G5R5A1_UNORM:
 153                 case PIPE_FORMAT_B4G4R4A4_UNORM:
 154                 case PIPE_FORMAT_B5G6R5_UNORM:
 155                 case PIPE_FORMAT_L8_UNORM:
 156                 case PIPE_FORMAT_A8_UNORM:
 157                 case PIPE_FORMAT_I8_UNORM:
 158                 case PIPE_FORMAT_L8A8_UNORM:
 159                 case PIPE_FORMAT_Z16_UNORM:
 160                 case PIPE_FORMAT_S8Z24_UNORM:
 161                 case PIPE_FORMAT_DXT1_RGB:
 162                 case PIPE_FORMAT_DXT1_RGBA:
 163                 case PIPE_FORMAT_DXT3_RGBA:
 164                 case PIPE_FORMAT_DXT5_RGBA:
 165                         return TRUE;
 166                 /* TODO: does nv30 support this? */
 167                 case PIPE_FORMAT_R16_SNORM:
 168                         return !!screen->is_nv4x;
 169                 default:
 170                         break;
 171                 }
 172         }
 173
 174         return FALSE;
 175 }
 176
 177 static struct pipe_buffer *
 178 nvfx_surface_buffer(struct pipe_surface *surf)
 179 {
 180         struct nvfx_miptree *mt = (struct nvfx_miptree *)surf->texture;
 181
 182         return mt->buffer;
 183 }
 184
 185 static void
 186 nvfx_screen_destroy(struct pipe_screen *pscreen)
 187 {
 188         struct nvfx_screen *screen = nvfx_screen(pscreen);
 189         unsigned i;
 190
 191         for (i = 0; i < NVFX_STATE_MAX; i++) {
 192                 if (screen->state[i])
 193                         so_ref(NULL, &screen->state[i]);
 194         }
 195
 196         nouveau_resource_destroy(&screen->vp_exec_heap);
 197         nouveau_resource_destroy(&screen->vp_data_heap);
 198         nouveau_resource_destroy(&screen->query_heap);
 199         nouveau_notifier_free(&screen->query);
 200         nouveau_notifier_free(&screen->sync);
 201         nouveau_grobj_free(&screen->eng3d);
 202         nv04_surface_2d_takedown(&screen->eng2d);
 203
 204         nouveau_screen_fini(&screen->base);
 205
 206         FREE(pscreen);
 207 }
 208
 209 static void nv30_screen_init(struct nvfx_screen *screen, struct nouveau_stateobj* so)
 210 {
 211         screen->base.base.context_create = nv30_create;
 212         int i;
 213
 214         /* TODO: perhaps we should do some of this on nv40 too? */
 215         for (i=1; i<8; i++) {
 216                 so_method(so, screen->eng3d, NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1);
 217                 so_data  (so, 0);
 218                 so_method(so, screen->eng3d, NV34TCL_VIEWPORT_CLIP_VERT(i), 1);
 219                 so_data  (so, 0);
 220         }
 221
 222         so_method(so, screen->eng3d, 0x220, 1);
 223         so_data  (so, 1);
 224
 225         so_method(so, screen->eng3d, 0x03b0, 1);
 226         so_data  (so, 0x00100000);
 227         so_method(so, screen->eng3d, 0x1454, 1);
 228         so_data  (so, 0);
 229         so_method(so, screen->eng3d, 0x1d80, 1);
 230         so_data  (so, 3);
 231         so_method(so, screen->eng3d, 0x1450, 1);
 232         so_data  (so, 0x00030004);
 233
 234         /* NEW */
 235         so_method(so, screen->eng3d, 0x1e98, 1);
 236         so_data  (so, 0);
 237         so_method(so, screen->eng3d, 0x17e0, 3);
 238         so_data  (so, fui(0.0));
 239         so_data  (so, fui(0.0));
 240         so_data  (so, fui(1.0));
 241         so_method(so, screen->eng3d, 0x1f80, 16);
 242         for (i=0; i<16; i++) {
 243                 so_data  (so, (i==8) ? 0x0000ffff : 0);
 244         }
 245
 246         so_method(so, screen->eng3d, 0x120, 3);
 247         so_data  (so, 0);
 248         so_data  (so, 1);
 249         so_data  (so, 2);
 250
 251         so_method(so, screen->eng3d, 0x1d88, 1);
 252         so_data  (so, 0x00001200);
 253
 254         so_method(so, screen->eng3d, NV34TCL_RC_ENABLE, 1);
 255         so_data  (so, 0);
 256
 257         so_method(so, screen->eng3d, NV34TCL_DEPTH_RANGE_NEAR, 2);
 258         so_data  (so, fui(0.0));
 259         so_data  (so, fui(1.0));
 260
 261         so_method(so, screen->eng3d, NV34TCL_MULTISAMPLE_CONTROL, 1);
 262         so_data  (so, 0xffff0000);
 263
 264         /* enables use of vp rather than fixed-function somehow */
 265         so_method(so, screen->eng3d, 0x1e94, 1);
 266         so_data  (so, 0x13);
 267 }
 268
 269 static void nv40_screen_init(struct nvfx_screen *screen, struct nouveau_stateobj* so)
 270 {
 271         screen->base.base.context_create = nv40_create;
 272
 273         so_method(so, screen->eng3d, NV40TCL_DMA_COLOR2, 2);
 274         so_data  (so, screen->base.channel->vram->handle);
 275         so_data  (so, screen->base.channel->vram->handle);
 276
 277         so_method(so, screen->eng3d, 0x1ea4, 3);
 278         so_data  (so, 0x00000010);
 279         so_data  (so, 0x01000100);
 280         so_data  (so, 0xff800006);
 281
 282         /* vtxprog output routing */
 283         so_method(so, screen->eng3d, 0x1fc4, 1);
 284         so_data  (so, 0x06144321);
 285         so_method(so, screen->eng3d, 0x1fc8, 2);
 286         so_data  (so, 0xedcba987);
 287         so_data  (so, 0x00000021);
 288         so_method(so, screen->eng3d, 0x1fd0, 1);
 289         so_data  (so, 0x00171615);
 290         so_method(so, screen->eng3d, 0x1fd4, 1);
 291         so_data  (so, 0x001b1a19);
 292
 293         so_method(so, screen->eng3d, 0x1ef8, 1);
 294         so_data  (so, 0x0020ffff);
 295         so_method(so, screen->eng3d, 0x1d64, 1);
 296         so_data  (so, 0x00d30000);
 297         so_method(so, screen->eng3d, 0x1e94, 1);
 298         so_data  (so, 0x00000001);
 299 }
 300
 301 struct pipe_screen *
 302 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 303 {
 304         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 305         struct nouveau_channel *chan;
 306         struct pipe_screen *pscreen;
 307         struct nouveau_stateobj *so;
 308         unsigned eng3d_class = 0;
 309         int ret;
 310
 311         if (!screen)
 312                 return NULL;
 313
 314         pscreen = &screen->base.base;
 315
 316         ret = nouveau_screen_init(&screen->base, dev);
 317         if (ret) {
 318                 nvfx_screen_destroy(pscreen);
 319                 return NULL;
 320         }
 321         chan = screen->base.channel;
 322
 323         pscreen->winsys = ws;
 324         pscreen->destroy = nvfx_screen_destroy;
 325         pscreen->get_param = nvfx_screen_get_param;
 326         pscreen->get_paramf = nvfx_screen_get_paramf;
 327         pscreen->is_format_supported = nvfx_screen_surface_format_supported;
 328
 329         switch (dev->chipset & 0xf0) {
 330         case 0x30:
 331                 if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 332                         eng3d_class = 0x0397;
 333                 else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 334                         eng3d_class = 0x0697;
 335                 else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 336                         eng3d_class = 0x0497;
 337                 break;
 338         case 0x40:
 339                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 340                         eng3d_class = NV40TCL;
 341                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 342                         eng3d_class = NV44TCL;
 343                 screen->is_nv4x = ~0;
 344                 break;
 345         case 0x60:
 346                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 347                         eng3d_class = NV44TCL;
 348                 screen->is_nv4x = ~0;
 349                 break;
 350         }
 351
 352         if (!eng3d_class) {
 353                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 354                 return NULL;
 355         }
 356
 357         nvfx_screen_init_miptree_functions(pscreen);
 358
 359         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 360         if (ret) {
 361                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 362                 return FALSE;
 363         }
 364
 365         /* 2D engine setup */
 366         screen->eng2d = nv04_surface_2d_init(&screen->base);
 367         screen->eng2d->buf = nvfx_surface_buffer;
 368
 369         /* Notifier for sync purposes */
 370         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 371         if (ret) {
 372                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 373                 nvfx_screen_destroy(pscreen);
 374                 return NULL;
 375         }
 376
 377         /* Query objects */
 378         ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
 379         if (ret) {
 380                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 381                 nvfx_screen_destroy(pscreen);
 382                 return NULL;
 383         }
 384
 385         ret = nouveau_resource_init(&screen->query_heap, 0, 32);
 386         if (ret) {
 387                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 388                 nvfx_screen_destroy(pscreen);
 389                 return NULL;
 390         }
 391
 392         /* Vtxprog resources */
 393         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
 394             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 395                 nvfx_screen_destroy(pscreen);
 396                 return NULL;
 397         }
 398
 399         /* Static eng3d initialisation */
 400         /* make the so big and don't worry about exact values
 401            since we it will be thrown away immediately after use */
 402         so = so_new(256, 256, 0);
 403         so_method(so, screen->eng3d, NV34TCL_DMA_NOTIFY, 1);
 404         so_data  (so, screen->sync->handle);
 405         so_method(so, screen->eng3d, NV34TCL_DMA_TEXTURE0, 2);
 406         so_data  (so, chan->vram->handle);
 407         so_data  (so, chan->gart->handle);
 408         so_method(so, screen->eng3d, NV34TCL_DMA_COLOR1, 1);
 409         so_data  (so, chan->vram->handle);
 410         so_method(so, screen->eng3d, NV34TCL_DMA_COLOR0, 2);
 411         so_data  (so, chan->vram->handle);
 412         so_data  (so, chan->vram->handle);
 413         so_method(so, screen->eng3d, NV34TCL_DMA_VTXBUF0, 2);
 414         so_data  (so, chan->vram->handle);
 415         so_data  (so, chan->gart->handle);
 416
 417         so_method(so, screen->eng3d, NV34TCL_DMA_FENCE, 2);
 418         so_data  (so, 0);
 419         so_data  (so, screen->query->handle);
 420
 421         so_method(so, screen->eng3d, NV34TCL_DMA_IN_MEMORY7, 2);
 422         so_data  (so, chan->vram->handle);
 423         so_data  (so, chan->vram->handle);
 424
 425         if(!screen->is_nv4x)
 426                 nv30_screen_init(screen, so);
 427         else
 428                 nv40_screen_init(screen, so);
 429
 430         so_emit(chan, so);
 431         so_ref(NULL, &so);
 432         nouveau_pushbuf_flush(chan, 0);
 433
 434         return pscreen;
 435 }