src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_simple_screen.h"
   4
   5 #include "nouveau/nouveau_screen.h"
   6
   7 #include "nvfx_context.h"
   8 #include "nvfx_screen.h"
   9 #include "nvfx_resource.h"
  10
  11 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
  12 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
  13 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
  14
  15 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
  16 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
  17 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
  18 * with same number of bits everywhere.
  19 */
  20 struct nouveau_winsys {
  21         struct pipe_winsys base;
  22
  23         struct pipe_screen *pscreen;
  24
  25         struct pipe_surface *front;
  26 };
  27 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  28 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  29 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  30
  31 static int
  32 nvfx_screen_get_param(struct pipe_screen *pscreen, int param)
  33 {
  34         struct nvfx_screen *screen = nvfx_screen(pscreen);
  35
  36         switch (param) {
  37         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  38                 /* TODO: check this */
  39                 return screen->is_nv4x ? 16 : 8;
  40         case PIPE_CAP_NPOT_TEXTURES:
  41                 return !!screen->is_nv4x;
  42         case PIPE_CAP_TWO_SIDED_STENCIL:
  43                 return 1;
  44         case PIPE_CAP_GLSL:
  45                 return 0;
  46         case PIPE_CAP_ANISOTROPIC_FILTER:
  47                 return 1;
  48         case PIPE_CAP_POINT_SPRITE:
  49                 return 1;
  50         case PIPE_CAP_MAX_RENDER_TARGETS:
  51                 return screen->is_nv4x ? 4 : 2;
  52         case PIPE_CAP_OCCLUSION_QUERY:
  53                 return 1;
  54         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  55                 return 1;
  56         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  57                 return 13;
  58         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  59                 return 10;
  60         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  61                 return 13;
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  63                 return !!screen->is_nv4x;
  64         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  65                 return 1;
  66         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  67                 return 0; /* We have 4 on nv40 - but unsupported currently */
  68         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  69                 return 0;
  70         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  71                 return !!screen->is_nv4x;
  72         case NOUVEAU_CAP_HW_VTXBUF:
  73                 return 0;
  74         case NOUVEAU_CAP_HW_IDXBUF:
  75                 return 0;
  76         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  77                 return 16;
  78         case PIPE_CAP_INDEP_BLEND_ENABLE:
  79                 /* TODO: on nv40 we have separate color masks */
  80                 /* TODO: nv40 mrt blending is probably broken */
  81                 return 0;
  82         case PIPE_CAP_INDEP_BLEND_FUNC:
  83                 return 0;
  84         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  85         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  86                 return 1;
  87         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  88         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  89                 return 0;
  90         default:
  91                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  92                 return 0;
  93         }
  94 }
  95
  96 static float
  97 nvfx_screen_get_paramf(struct pipe_screen *pscreen, int param)
  98 {
  99         struct nvfx_screen *screen = nvfx_screen(pscreen);
 100
 101         switch (param) {
 102         case PIPE_CAP_MAX_LINE_WIDTH:
 103         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 104                 return 10.0;
 105         case PIPE_CAP_MAX_POINT_WIDTH:
 106         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 107                 return 64.0;
 108         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 109                 return screen->is_nv4x ? 16.0 : 8.0;
 110         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 111                 return screen->is_nv4x ? 16.0 : 4.0;
 112         default:
 113                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 114                 return 0.0;
 115         }
 116 }
 117
 118 static boolean
 119 nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 120                                      enum pipe_format format,
 121                                      enum pipe_texture_target target,
 122                                      unsigned tex_usage, unsigned geom_flags)
 123 {
 124         struct nvfx_screen *screen = nvfx_screen(pscreen);
 125         struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
 126
 127         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
 128                 switch (format) {
 129                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 130                 case PIPE_FORMAT_B5G6R5_UNORM:
 131                         return TRUE;
 132                 default:
 133                         break;
 134                 }
 135         } else
 136         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
 137                 switch (format) {
 138                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 139                 case PIPE_FORMAT_X8Z24_UNORM:
 140                         return TRUE;
 141                 case PIPE_FORMAT_Z16_UNORM:
 142                         /* TODO: this nv30 limitation probably does not exist */
 143                         if (!screen->is_nv4x && front)
 144                                 return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
 145                         return TRUE;
 146                 default:
 147                         break;
 148                 }
 149         } else {
 150                 switch (format) {
 151                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 152                 case PIPE_FORMAT_B5G5R5A1_UNORM:
 153                 case PIPE_FORMAT_B4G4R4A4_UNORM:
 154                 case PIPE_FORMAT_B5G6R5_UNORM:
 155                 case PIPE_FORMAT_L8_UNORM:
 156                 case PIPE_FORMAT_A8_UNORM:
 157                 case PIPE_FORMAT_I8_UNORM:
 158                 case PIPE_FORMAT_L8A8_UNORM:
 159                 case PIPE_FORMAT_Z16_UNORM:
 160                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 161                 case PIPE_FORMAT_DXT1_RGB:
 162                 case PIPE_FORMAT_DXT1_RGBA:
 163                 case PIPE_FORMAT_DXT3_RGBA:
 164                 case PIPE_FORMAT_DXT5_RGBA:
 165                         return TRUE;
 166                 /* TODO: does nv30 support this? */
 167                 case PIPE_FORMAT_R16_SNORM:
 168                         return !!screen->is_nv4x;
 169                 default:
 170                         break;
 171                 }
 172         }
 173
 174         return FALSE;
 175 }
 176
 177
 178 static void
 179 nvfx_screen_destroy(struct pipe_screen *pscreen)
 180 {
 181         struct nvfx_screen *screen = nvfx_screen(pscreen);
 182         unsigned i;
 183
 184         for (i = 0; i < NVFX_STATE_MAX; i++) {
 185                 if (screen->state[i])
 186                         so_ref(NULL, &screen->state[i]);
 187         }
 188
 189         nouveau_resource_destroy(&screen->vp_exec_heap);
 190         nouveau_resource_destroy(&screen->vp_data_heap);
 191         nouveau_resource_destroy(&screen->query_heap);
 192         nouveau_notifier_free(&screen->query);
 193         nouveau_notifier_free(&screen->sync);
 194         nouveau_grobj_free(&screen->eng3d);
 195         nv04_surface_2d_takedown(&screen->eng2d);
 196
 197         nouveau_screen_fini(&screen->base);
 198
 199         FREE(pscreen);
 200 }
 201
 202 static void nv30_screen_init(struct nvfx_screen *screen)
 203 {
 204         struct nouveau_channel *chan = screen->base.channel;
 205         int i;
 206
 207         /* TODO: perhaps we should do some of this on nv40 too? */
 208         for (i=1; i<8; i++) {
 209                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1));
 210                 OUT_RING(chan, 0);
 211                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i), 1));
 212                 OUT_RING(chan, 0);
 213         }
 214
 215         OUT_RING(chan, RING_3D(0x220, 1));
 216         OUT_RING(chan, 1);
 217
 218         OUT_RING(chan, RING_3D(0x03b0, 1));
 219         OUT_RING(chan, 0x00100000);
 220         OUT_RING(chan, RING_3D(0x1454, 1));
 221         OUT_RING(chan, 0);
 222         OUT_RING(chan, RING_3D(0x1d80, 1));
 223         OUT_RING(chan, 3);
 224         OUT_RING(chan, RING_3D(0x1450, 1));
 225         OUT_RING(chan, 0x00030004);
 226
 227         /* NEW */
 228         OUT_RING(chan, RING_3D(0x1e98, 1));
 229         OUT_RING(chan, 0);
 230         OUT_RING(chan, RING_3D(0x17e0, 3));
 231         OUT_RING(chan, fui(0.0));
 232         OUT_RING(chan, fui(0.0));
 233         OUT_RING(chan, fui(1.0));
 234         OUT_RING(chan, RING_3D(0x1f80, 16));
 235         for (i=0; i<16; i++) {
 236                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 237         }
 238
 239         OUT_RING(chan, RING_3D(0x120, 3));
 240         OUT_RING(chan, 0);
 241         OUT_RING(chan, 1);
 242         OUT_RING(chan, 2);
 243
 244         OUT_RING(chan, RING_3D(0x1d88, 1));
 245         OUT_RING(chan, 0x00001200);
 246
 247         OUT_RING(chan, RING_3D(NV34TCL_RC_ENABLE, 1));
 248         OUT_RING(chan, 0);
 249
 250         OUT_RING(chan, RING_3D(NV34TCL_DEPTH_RANGE_NEAR, 2));
 251         OUT_RING(chan, fui(0.0));
 252         OUT_RING(chan, fui(1.0));
 253
 254         OUT_RING(chan, RING_3D(NV34TCL_MULTISAMPLE_CONTROL, 1));
 255         OUT_RING(chan, 0xffff0000);
 256
 257         /* enables use of vp rather than fixed-function somehow */
 258         OUT_RING(chan, RING_3D(0x1e94, 1));
 259         OUT_RING(chan, 0x13);
 260 }
 261
 262 static void nv40_screen_init(struct nvfx_screen *screen)
 263 {
 264         struct nouveau_channel *chan = screen->base.channel;
 265
 266         OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 2));
 267         OUT_RING(chan, screen->base.channel->vram->handle);
 268         OUT_RING(chan, screen->base.channel->vram->handle);
 269
 270         OUT_RING(chan, RING_3D(0x1ea4, 3));
 271         OUT_RING(chan, 0x00000010);
 272         OUT_RING(chan, 0x01000100);
 273         OUT_RING(chan, 0xff800006);
 274
 275         /* vtxprog output routing */
 276         OUT_RING(chan, RING_3D(0x1fc4, 1));
 277         OUT_RING(chan, 0x06144321);
 278         OUT_RING(chan, RING_3D(0x1fc8, 2));
 279         OUT_RING(chan, 0xedcba987);
 280         OUT_RING(chan, 0x00000021);
 281         OUT_RING(chan, RING_3D(0x1fd0, 1));
 282         OUT_RING(chan, 0x00171615);
 283         OUT_RING(chan, RING_3D(0x1fd4, 1));
 284         OUT_RING(chan, 0x001b1a19);
 285
 286         OUT_RING(chan, RING_3D(0x1ef8, 1));
 287         OUT_RING(chan, 0x0020ffff);
 288         OUT_RING(chan, RING_3D(0x1d64, 1));
 289         OUT_RING(chan, 0x00d30000);
 290         OUT_RING(chan, RING_3D(0x1e94, 1));
 291         OUT_RING(chan, 0x00000001);
 292 }
 293
 294 static void
 295 nvfx_screen_init_buffer_functions(struct nvfx_screen* screen)
 296 {
 297         int vram_hack_default = 0;
 298         int vram_hack;
 299         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 300         // It may also depend on the specific card or the AGP/PCIe chipset.
 301         if(screen->base.device->chipset == 0x47 /* G70 */
 302                 || screen->base.device->chipset == 0x49 /* G71 */
 303                 || screen->base.device->chipset == 0x46 /* G72 */
 304                 )
 305                 vram_hack_default = 1;
 306         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 307
 308 #ifdef DEBUG
 309         if(!vram_hack)
 310         {
 311                 fprintf(stderr, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
 312                         "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
 313         }
 314         else
 315         {
 316                 fprintf(stderr, "A performance reducing hack is being used to help avoid graphics corruption.\n"
 317                         "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
 318         }
 319 #endif
 320
 321         screen->vertex_buffer_flags = vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 322 }
 323
 324 struct pipe_screen *
 325 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 326 {
 327         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 328         struct nouveau_channel *chan;
 329         struct pipe_screen *pscreen;
 330         unsigned eng3d_class = 0;
 331         int ret;
 332
 333         if (!screen)
 334                 return NULL;
 335
 336         pscreen = &screen->base.base;
 337
 338         ret = nouveau_screen_init(&screen->base, dev);
 339         if (ret) {
 340                 nvfx_screen_destroy(pscreen);
 341                 return NULL;
 342         }
 343         chan = screen->base.channel;
 344
 345         pscreen->winsys = ws;
 346         pscreen->destroy = nvfx_screen_destroy;
 347         pscreen->get_param = nvfx_screen_get_param;
 348         pscreen->get_paramf = nvfx_screen_get_paramf;
 349         pscreen->is_format_supported = nvfx_screen_surface_format_supported;
 350         pscreen->context_create = nvfx_create;
 351
 352         switch (dev->chipset & 0xf0) {
 353         case 0x30:
 354                 if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 355                         eng3d_class = 0x0397;
 356                 else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 357                         eng3d_class = 0x0697;
 358                 else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 359                         eng3d_class = 0x0497;
 360                 break;
 361         case 0x40:
 362                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 363                         eng3d_class = NV40TCL;
 364                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 365                         eng3d_class = NV44TCL;
 366                 screen->is_nv4x = ~0;
 367                 break;
 368         case 0x60:
 369                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 370                         eng3d_class = NV44TCL;
 371                 screen->is_nv4x = ~0;
 372                 break;
 373         }
 374
 375         if (!eng3d_class) {
 376                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 377                 return NULL;
 378         }
 379
 380         nvfx_screen_init_resource_functions(pscreen);
 381         nvfx_screen_init_buffer_functions(screen);
 382
 383         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 384         if (ret) {
 385                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 386                 return FALSE;
 387         }
 388
 389         /* 2D engine setup */
 390         screen->eng2d = nv04_surface_2d_init(&screen->base);
 391         screen->eng2d->buf = nvfx_surface_buffer;
 392
 393         /* Notifier for sync purposes */
 394         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 395         if (ret) {
 396                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 397                 nvfx_screen_destroy(pscreen);
 398                 return NULL;
 399         }
 400
 401         /* Query objects */
 402         ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
 403         if (ret) {
 404                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 405                 nvfx_screen_destroy(pscreen);
 406                 return NULL;
 407         }
 408
 409         ret = nouveau_resource_init(&screen->query_heap, 0, 32);
 410         if (ret) {
 411                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 412                 nvfx_screen_destroy(pscreen);
 413                 return NULL;
 414         }
 415
 416         /* Vtxprog resources */
 417         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
 418             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 419                 nvfx_screen_destroy(pscreen);
 420                 return NULL;
 421         }
 422
 423         BIND_RING(chan, screen->eng3d, 7);
 424
 425         /* Static eng3d initialisation */
 426         /* note that we just started using the channel, so we must have space in the pushbuffer */
 427         OUT_RING(chan, RING_3D(NV34TCL_DMA_NOTIFY, 1));
 428         OUT_RING(chan, screen->sync->handle);
 429         OUT_RING(chan, RING_3D(NV34TCL_DMA_TEXTURE0, 2));
 430         OUT_RING(chan, chan->vram->handle);
 431         OUT_RING(chan, chan->gart->handle);
 432         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1));
 433         OUT_RING(chan, chan->vram->handle);
 434         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 2));
 435         OUT_RING(chan, chan->vram->handle);
 436         OUT_RING(chan, chan->vram->handle);
 437         OUT_RING(chan, RING_3D(NV34TCL_DMA_VTXBUF0, 2));
 438         OUT_RING(chan, chan->vram->handle);
 439         OUT_RING(chan, chan->gart->handle);
 440
 441         OUT_RING(chan, RING_3D(NV34TCL_DMA_FENCE, 2));
 442         OUT_RING(chan, 0);
 443         OUT_RING(chan, screen->query->handle);
 444
 445         OUT_RING(chan, RING_3D(NV34TCL_DMA_IN_MEMORY7, 2));
 446         OUT_RING(chan, chan->vram->handle);
 447         OUT_RING(chan, chan->vram->handle);
 448
 449         if(!screen->is_nv4x)
 450                 nv30_screen_init(screen);
 451         else
 452                 nv40_screen_init(screen);
 453
 454         return pscreen;
 455 }