1 #include "pipe/p_screen.h"
2 #include "pipe/p_state.h"
4 #include "nouveau/nouveau_screen.h"
6 #include "nvfx_context.h"
7 #include "nvfx_screen.h"
9 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
10 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
11 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
13 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
14 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
15 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
16 * with same number of bits everywhere.
18 struct nouveau_winsys
{
19 struct pipe_winsys base
;
21 struct pipe_screen
*pscreen
;
23 struct pipe_surface
*front
;
25 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
26 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
27 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
30 nvfx_screen_get_param(struct pipe_screen
*pscreen
, int param
)
32 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
35 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
36 /* TODO: check this */
37 return screen
->is_nv4x
? 16 : 8;
38 case PIPE_CAP_NPOT_TEXTURES
:
39 return !!screen
->is_nv4x
;
40 case PIPE_CAP_TWO_SIDED_STENCIL
:
44 case PIPE_CAP_ANISOTROPIC_FILTER
:
46 case PIPE_CAP_POINT_SPRITE
:
48 case PIPE_CAP_MAX_RENDER_TARGETS
:
49 return screen
->is_nv4x
? 4 : 2;
50 case PIPE_CAP_OCCLUSION_QUERY
:
52 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
54 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
56 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
58 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
60 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
61 return !!screen
->is_nv4x
;
62 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
64 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
65 return 0; /* We have 4 on nv40 - but unsupported currently */
66 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
68 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
69 return !!screen
->is_nv4x
;
70 case NOUVEAU_CAP_HW_VTXBUF
:
72 case NOUVEAU_CAP_HW_IDXBUF
:
74 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
76 case PIPE_CAP_INDEP_BLEND_ENABLE
:
77 /* TODO: on nv40 we have separate color masks */
78 /* TODO: nv40 mrt blending is probably broken */
80 case PIPE_CAP_INDEP_BLEND_FUNC
:
82 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
83 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
85 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
86 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
89 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
95 nvfx_screen_get_paramf(struct pipe_screen
*pscreen
, int param
)
97 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
100 case PIPE_CAP_MAX_LINE_WIDTH
:
101 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
103 case PIPE_CAP_MAX_POINT_WIDTH
:
104 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
106 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
107 return screen
->is_nv4x
? 16.0 : 8.0;
108 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
109 return screen
->is_nv4x
? 16.0 : 4.0;
111 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
117 nvfx_screen_surface_format_supported(struct pipe_screen
*pscreen
,
118 enum pipe_format format
,
119 enum pipe_texture_target target
,
120 unsigned tex_usage
, unsigned geom_flags
)
122 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
123 struct pipe_surface
*front
= ((struct nouveau_winsys
*) pscreen
->winsys
)->front
;
125 if (tex_usage
& PIPE_TEXTURE_USAGE_RENDER_TARGET
) {
127 case PIPE_FORMAT_B8G8R8A8_UNORM
:
128 case PIPE_FORMAT_B5G6R5_UNORM
:
134 if (tex_usage
& PIPE_TEXTURE_USAGE_DEPTH_STENCIL
) {
136 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
137 case PIPE_FORMAT_X8Z24_UNORM
:
139 case PIPE_FORMAT_Z16_UNORM
:
140 /* TODO: this nv30 limitation probably does not exist */
141 if (!screen
->is_nv4x
&& front
)
142 return (front
->format
== PIPE_FORMAT_B5G6R5_UNORM
);
149 case PIPE_FORMAT_B8G8R8A8_UNORM
:
150 case PIPE_FORMAT_B5G5R5A1_UNORM
:
151 case PIPE_FORMAT_B4G4R4A4_UNORM
:
152 case PIPE_FORMAT_B5G6R5_UNORM
:
153 case PIPE_FORMAT_L8_UNORM
:
154 case PIPE_FORMAT_A8_UNORM
:
155 case PIPE_FORMAT_I8_UNORM
:
156 case PIPE_FORMAT_L8A8_UNORM
:
157 case PIPE_FORMAT_Z16_UNORM
:
158 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
159 case PIPE_FORMAT_DXT1_RGB
:
160 case PIPE_FORMAT_DXT1_RGBA
:
161 case PIPE_FORMAT_DXT3_RGBA
:
162 case PIPE_FORMAT_DXT5_RGBA
:
164 /* TODO: does nv30 support this? */
165 case PIPE_FORMAT_R16_SNORM
:
166 return !!screen
->is_nv4x
;
175 static struct pipe_buffer
*
176 nvfx_surface_buffer(struct pipe_surface
*surf
)
178 struct nvfx_miptree
*mt
= (struct nvfx_miptree
*)surf
->texture
;
184 nvfx_screen_destroy(struct pipe_screen
*pscreen
)
186 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
189 for (i
= 0; i
< NVFX_STATE_MAX
; i
++) {
190 if (screen
->state
[i
])
191 so_ref(NULL
, &screen
->state
[i
]);
194 nouveau_resource_destroy(&screen
->vp_exec_heap
);
195 nouveau_resource_destroy(&screen
->vp_data_heap
);
196 nouveau_resource_destroy(&screen
->query_heap
);
197 nouveau_notifier_free(&screen
->query
);
198 nouveau_notifier_free(&screen
->sync
);
199 nouveau_grobj_free(&screen
->eng3d
);
200 nv04_surface_2d_takedown(&screen
->eng2d
);
202 nouveau_screen_fini(&screen
->base
);
207 static void nv30_screen_init(struct nvfx_screen
*screen
, struct nouveau_stateobj
* so
)
211 /* TODO: perhaps we should do some of this on nv40 too? */
212 for (i
=1; i
<8; i
++) {
213 so_method(so
, screen
->eng3d
, NV34TCL_VIEWPORT_CLIP_HORIZ(i
), 1);
215 so_method(so
, screen
->eng3d
, NV34TCL_VIEWPORT_CLIP_VERT(i
), 1);
219 so_method(so
, screen
->eng3d
, 0x220, 1);
222 so_method(so
, screen
->eng3d
, 0x03b0, 1);
223 so_data (so
, 0x00100000);
224 so_method(so
, screen
->eng3d
, 0x1454, 1);
226 so_method(so
, screen
->eng3d
, 0x1d80, 1);
228 so_method(so
, screen
->eng3d
, 0x1450, 1);
229 so_data (so
, 0x00030004);
232 so_method(so
, screen
->eng3d
, 0x1e98, 1);
234 so_method(so
, screen
->eng3d
, 0x17e0, 3);
235 so_data (so
, fui(0.0));
236 so_data (so
, fui(0.0));
237 so_data (so
, fui(1.0));
238 so_method(so
, screen
->eng3d
, 0x1f80, 16);
239 for (i
=0; i
<16; i
++) {
240 so_data (so
, (i
==8) ? 0x0000ffff : 0);
243 so_method(so
, screen
->eng3d
, 0x120, 3);
248 so_method(so
, screen
->eng3d
, 0x1d88, 1);
249 so_data (so
, 0x00001200);
251 so_method(so
, screen
->eng3d
, NV34TCL_RC_ENABLE
, 1);
254 so_method(so
, screen
->eng3d
, NV34TCL_DEPTH_RANGE_NEAR
, 2);
255 so_data (so
, fui(0.0));
256 so_data (so
, fui(1.0));
258 so_method(so
, screen
->eng3d
, NV34TCL_MULTISAMPLE_CONTROL
, 1);
259 so_data (so
, 0xffff0000);
261 /* enables use of vp rather than fixed-function somehow */
262 so_method(so
, screen
->eng3d
, 0x1e94, 1);
266 static void nv40_screen_init(struct nvfx_screen
*screen
, struct nouveau_stateobj
* so
)
268 so_method(so
, screen
->eng3d
, NV40TCL_DMA_COLOR2
, 2);
269 so_data (so
, screen
->base
.channel
->vram
->handle
);
270 so_data (so
, screen
->base
.channel
->vram
->handle
);
272 so_method(so
, screen
->eng3d
, 0x1ea4, 3);
273 so_data (so
, 0x00000010);
274 so_data (so
, 0x01000100);
275 so_data (so
, 0xff800006);
277 /* vtxprog output routing */
278 so_method(so
, screen
->eng3d
, 0x1fc4, 1);
279 so_data (so
, 0x06144321);
280 so_method(so
, screen
->eng3d
, 0x1fc8, 2);
281 so_data (so
, 0xedcba987);
282 so_data (so
, 0x00000021);
283 so_method(so
, screen
->eng3d
, 0x1fd0, 1);
284 so_data (so
, 0x00171615);
285 so_method(so
, screen
->eng3d
, 0x1fd4, 1);
286 so_data (so
, 0x001b1a19);
288 so_method(so
, screen
->eng3d
, 0x1ef8, 1);
289 so_data (so
, 0x0020ffff);
290 so_method(so
, screen
->eng3d
, 0x1d64, 1);
291 so_data (so
, 0x00d30000);
292 so_method(so
, screen
->eng3d
, 0x1e94, 1);
293 so_data (so
, 0x00000001);
297 nvfx_screen_init_buffer_functions(struct nvfx_screen
* screen
)
299 int vram_hack_default
= 0;
301 // TODO: this is a bit of a guess; also add other cards that may need this hack.
302 // It may also depend on the specific card or the AGP/PCIe chipset.
303 if(screen
->base
.device
->chipset
== 0x47 /* G70 */
304 || screen
->base
.device
->chipset
== 0x49 /* G71 */
305 || screen
->base
.device
->chipset
== 0x46 /* G72 */
307 vram_hack_default
= 1;
308 vram_hack
= debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default
);
313 fprintf(stderr
, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
314 "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
318 fprintf(stderr
, "A performance reducing hack is being used to help avoid graphics corruption.\n"
319 "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
323 screen
->vertex_buffer_flags
= vram_hack
? NOUVEAU_BO_VRAM
: NOUVEAU_BO_GART
;
327 nvfx_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
329 struct nvfx_screen
*screen
= CALLOC_STRUCT(nvfx_screen
);
330 struct nouveau_channel
*chan
;
331 struct pipe_screen
*pscreen
;
332 struct nouveau_stateobj
*so
;
333 unsigned eng3d_class
= 0;
339 pscreen
= &screen
->base
.base
;
341 ret
= nouveau_screen_init(&screen
->base
, dev
);
343 nvfx_screen_destroy(pscreen
);
346 chan
= screen
->base
.channel
;
348 pscreen
->winsys
= ws
;
349 pscreen
->destroy
= nvfx_screen_destroy
;
350 pscreen
->get_param
= nvfx_screen_get_param
;
351 pscreen
->get_paramf
= nvfx_screen_get_paramf
;
352 pscreen
->is_format_supported
= nvfx_screen_surface_format_supported
;
353 pscreen
->context_create
= nvfx_create
;
355 switch (dev
->chipset
& 0xf0) {
357 if (NV30TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
358 eng3d_class
= 0x0397;
359 else if (NV34TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
360 eng3d_class
= 0x0697;
361 else if (NV35TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
362 eng3d_class
= 0x0497;
365 if (NV4X_GRCLASS4097_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
366 eng3d_class
= NV40TCL
;
367 else if (NV4X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
368 eng3d_class
= NV44TCL
;
369 screen
->is_nv4x
= ~0;
372 if (NV6X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
373 eng3d_class
= NV44TCL
;
374 screen
->is_nv4x
= ~0;
379 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev
->chipset
);
383 nvfx_screen_init_buffer_functions(screen
);
384 nvfx_screen_init_miptree_functions(pscreen
);
386 ret
= nouveau_grobj_alloc(chan
, 0xbeef3097, eng3d_class
, &screen
->eng3d
);
388 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
392 /* 2D engine setup */
393 screen
->eng2d
= nv04_surface_2d_init(&screen
->base
);
394 screen
->eng2d
->buf
= nvfx_surface_buffer
;
396 /* Notifier for sync purposes */
397 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
399 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
400 nvfx_screen_destroy(pscreen
);
405 ret
= nouveau_notifier_alloc(chan
, 0xbeef0302, 32, &screen
->query
);
407 NOUVEAU_ERR("Error initialising query objects: %d\n", ret
);
408 nvfx_screen_destroy(pscreen
);
412 ret
= nouveau_resource_init(&screen
->query_heap
, 0, 32);
414 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret
);
415 nvfx_screen_destroy(pscreen
);
419 /* Vtxprog resources */
420 if (nouveau_resource_init(&screen
->vp_exec_heap
, 0, screen
->is_nv4x
? 512 : 256) ||
421 nouveau_resource_init(&screen
->vp_data_heap
, 0, 256)) {
422 nvfx_screen_destroy(pscreen
);
426 /* Static eng3d initialisation */
427 /* make the so big and don't worry about exact values
428 since we it will be thrown away immediately after use */
429 so
= so_new(256, 256, 0);
430 so_method(so
, screen
->eng3d
, NV34TCL_DMA_NOTIFY
, 1);
431 so_data (so
, screen
->sync
->handle
);
432 so_method(so
, screen
->eng3d
, NV34TCL_DMA_TEXTURE0
, 2);
433 so_data (so
, chan
->vram
->handle
);
434 so_data (so
, chan
->gart
->handle
);
435 so_method(so
, screen
->eng3d
, NV34TCL_DMA_COLOR1
, 1);
436 so_data (so
, chan
->vram
->handle
);
437 so_method(so
, screen
->eng3d
, NV34TCL_DMA_COLOR0
, 2);
438 so_data (so
, chan
->vram
->handle
);
439 so_data (so
, chan
->vram
->handle
);
440 so_method(so
, screen
->eng3d
, NV34TCL_DMA_VTXBUF0
, 2);
441 so_data (so
, chan
->vram
->handle
);
442 so_data (so
, chan
->gart
->handle
);
444 so_method(so
, screen
->eng3d
, NV34TCL_DMA_FENCE
, 2);
446 so_data (so
, screen
->query
->handle
);
448 so_method(so
, screen
->eng3d
, NV34TCL_DMA_IN_MEMORY7
, 2);
449 so_data (so
, chan
->vram
->handle
);
450 so_data (so
, chan
->vram
->handle
);
453 nv30_screen_init(screen
, so
);
455 nv40_screen_init(screen
, so
);
459 nouveau_pushbuf_flush(chan
, 0);