1 #include "pipe/p_screen.h"
2 #include "pipe/p_state.h"
3 #include "util/u_format_s3tc.h"
4 #include "util/u_simple_screen.h"
6 #include "nouveau/nouveau_screen.h"
8 #include "nvfx_context.h"
9 #include "nvfx_screen.h"
10 #include "nvfx_resource.h"
12 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
13 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
14 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
16 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
17 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
18 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
19 * with same number of bits everywhere.
21 struct nouveau_winsys
{
22 struct pipe_winsys base
;
24 struct pipe_screen
*pscreen
;
26 struct pipe_surface
*front
;
28 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
29 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
30 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
33 nvfx_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
35 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
38 case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS
:
39 /* TODO: check this */
40 return screen
->is_nv4x
? 16 : 8;
41 case PIPE_CAP_NPOT_TEXTURES
:
42 return !!screen
->is_nv4x
;
43 case PIPE_CAP_TWO_SIDED_STENCIL
:
47 case PIPE_CAP_ANISOTROPIC_FILTER
:
49 case PIPE_CAP_POINT_SPRITE
:
51 case PIPE_CAP_MAX_RENDER_TARGETS
:
52 return screen
->is_nv4x
? 4 : 2;
53 case PIPE_CAP_OCCLUSION_QUERY
:
55 case PIPE_CAP_TEXTURE_SHADOW_MAP
:
57 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS
:
59 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
61 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
63 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
64 return !!screen
->is_nv4x
;
65 case PIPE_CAP_TEXTURE_MIRROR_REPEAT
:
67 case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS
:
68 return 0; /* We have 4 on nv40 - but unsupported currently */
69 case PIPE_CAP_TGSI_CONT_SUPPORTED
:
71 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
72 return !!screen
->is_nv4x
;
73 case PIPE_CAP_MAX_COMBINED_SAMPLERS
:
75 case PIPE_CAP_INDEP_BLEND_ENABLE
:
76 /* TODO: on nv40 we have separate color masks */
77 /* TODO: nv40 mrt blending is probably broken */
79 case PIPE_CAP_INDEP_BLEND_FUNC
:
81 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
82 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
84 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
85 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
88 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
94 nvfx_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_cap param
)
96 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
99 case PIPE_CAP_MAX_LINE_WIDTH
:
100 case PIPE_CAP_MAX_LINE_WIDTH_AA
:
102 case PIPE_CAP_MAX_POINT_WIDTH
:
103 case PIPE_CAP_MAX_POINT_WIDTH_AA
:
105 case PIPE_CAP_MAX_TEXTURE_ANISOTROPY
:
106 return screen
->is_nv4x
? 16.0 : 8.0;
107 case PIPE_CAP_MAX_TEXTURE_LOD_BIAS
:
108 return screen
->is_nv4x
? 16.0 : 4.0;
110 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param
);
116 nvfx_screen_surface_format_supported(struct pipe_screen
*pscreen
,
117 enum pipe_format format
,
118 enum pipe_texture_target target
,
119 unsigned tex_usage
, unsigned geom_flags
)
121 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
122 struct pipe_surface
*front
= ((struct nouveau_winsys
*) pscreen
->winsys
)->front
;
124 if (tex_usage
& PIPE_BIND_RENDER_TARGET
) {
126 case PIPE_FORMAT_B8G8R8A8_UNORM
:
127 case PIPE_FORMAT_B8G8R8X8_UNORM
:
128 case PIPE_FORMAT_B5G6R5_UNORM
:
134 if (tex_usage
& PIPE_BIND_DEPTH_STENCIL
) {
136 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
137 case PIPE_FORMAT_X8Z24_UNORM
:
139 case PIPE_FORMAT_Z16_UNORM
:
140 /* TODO: this nv30 limitation probably does not exist */
141 if (!screen
->is_nv4x
&& front
)
142 return (front
->format
== PIPE_FORMAT_B5G6R5_UNORM
);
149 if (tex_usage
& PIPE_BIND_SAMPLER_VIEW
) {
151 case PIPE_FORMAT_DXT1_RGB
:
152 case PIPE_FORMAT_DXT1_RGBA
:
153 case PIPE_FORMAT_DXT3_RGBA
:
154 case PIPE_FORMAT_DXT5_RGBA
:
155 return util_format_s3tc_enabled
;
160 case PIPE_FORMAT_B8G8R8A8_UNORM
:
161 case PIPE_FORMAT_B8G8R8X8_UNORM
:
162 case PIPE_FORMAT_B5G5R5A1_UNORM
:
163 case PIPE_FORMAT_B4G4R4A4_UNORM
:
164 case PIPE_FORMAT_B5G6R5_UNORM
:
165 case PIPE_FORMAT_L8_UNORM
:
166 case PIPE_FORMAT_A8_UNORM
:
167 case PIPE_FORMAT_I8_UNORM
:
168 case PIPE_FORMAT_L8A8_UNORM
:
169 case PIPE_FORMAT_Z16_UNORM
:
170 case PIPE_FORMAT_S8_USCALED_Z24_UNORM
:
172 /* TODO: does nv30 support this? */
173 case PIPE_FORMAT_R16_SNORM
:
174 return !!screen
->is_nv4x
;
185 nvfx_screen_destroy(struct pipe_screen
*pscreen
)
187 struct nvfx_screen
*screen
= nvfx_screen(pscreen
);
189 nouveau_resource_destroy(&screen
->vp_exec_heap
);
190 nouveau_resource_destroy(&screen
->vp_data_heap
);
191 nouveau_resource_destroy(&screen
->query_heap
);
192 nouveau_notifier_free(&screen
->query
);
193 nouveau_notifier_free(&screen
->sync
);
194 nouveau_grobj_free(&screen
->eng3d
);
195 nv04_surface_2d_takedown(&screen
->eng2d
);
197 nouveau_screen_fini(&screen
->base
);
202 static void nv30_screen_init(struct nvfx_screen
*screen
)
204 struct nouveau_channel
*chan
= screen
->base
.channel
;
207 /* TODO: perhaps we should do some of this on nv40 too? */
208 for (i
=1; i
<8; i
++) {
209 OUT_RING(chan
, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i
), 1));
211 OUT_RING(chan
, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i
), 1));
215 OUT_RING(chan
, RING_3D(0x220, 1));
218 OUT_RING(chan
, RING_3D(0x03b0, 1));
219 OUT_RING(chan
, 0x00100000);
220 OUT_RING(chan
, RING_3D(0x1454, 1));
222 OUT_RING(chan
, RING_3D(0x1d80, 1));
224 OUT_RING(chan
, RING_3D(0x1450, 1));
225 OUT_RING(chan
, 0x00030004);
228 OUT_RING(chan
, RING_3D(0x1e98, 1));
230 OUT_RING(chan
, RING_3D(0x17e0, 3));
231 OUT_RING(chan
, fui(0.0));
232 OUT_RING(chan
, fui(0.0));
233 OUT_RING(chan
, fui(1.0));
234 OUT_RING(chan
, RING_3D(0x1f80, 16));
235 for (i
=0; i
<16; i
++) {
236 OUT_RING(chan
, (i
==8) ? 0x0000ffff : 0);
239 OUT_RING(chan
, RING_3D(0x120, 3));
244 OUT_RING(chan
, RING_3D(0x1d88, 1));
245 OUT_RING(chan
, 0x00001200);
247 OUT_RING(chan
, RING_3D(NV34TCL_RC_ENABLE
, 1));
250 OUT_RING(chan
, RING_3D(NV34TCL_DEPTH_RANGE_NEAR
, 2));
251 OUT_RING(chan
, fui(0.0));
252 OUT_RING(chan
, fui(1.0));
254 OUT_RING(chan
, RING_3D(NV34TCL_MULTISAMPLE_CONTROL
, 1));
255 OUT_RING(chan
, 0xffff0000);
257 /* enables use of vp rather than fixed-function somehow */
258 OUT_RING(chan
, RING_3D(0x1e94, 1));
259 OUT_RING(chan
, 0x13);
262 static void nv40_screen_init(struct nvfx_screen
*screen
)
264 struct nouveau_channel
*chan
= screen
->base
.channel
;
266 OUT_RING(chan
, RING_3D(NV40TCL_DMA_COLOR2
, 2));
267 OUT_RING(chan
, screen
->base
.channel
->vram
->handle
);
268 OUT_RING(chan
, screen
->base
.channel
->vram
->handle
);
270 OUT_RING(chan
, RING_3D(0x1ea4, 3));
271 OUT_RING(chan
, 0x00000010);
272 OUT_RING(chan
, 0x01000100);
273 OUT_RING(chan
, 0xff800006);
275 /* vtxprog output routing */
276 OUT_RING(chan
, RING_3D(0x1fc4, 1));
277 OUT_RING(chan
, 0x06144321);
278 OUT_RING(chan
, RING_3D(0x1fc8, 2));
279 OUT_RING(chan
, 0xedcba987);
280 OUT_RING(chan
, 0x00000021);
281 OUT_RING(chan
, RING_3D(0x1fd0, 1));
282 OUT_RING(chan
, 0x00171615);
283 OUT_RING(chan
, RING_3D(0x1fd4, 1));
284 OUT_RING(chan
, 0x001b1a19);
286 OUT_RING(chan
, RING_3D(0x1ef8, 1));
287 OUT_RING(chan
, 0x0020ffff);
288 OUT_RING(chan
, RING_3D(0x1d64, 1));
289 OUT_RING(chan
, 0x00d30000);
290 OUT_RING(chan
, RING_3D(0x1e94, 1));
291 OUT_RING(chan
, 0x00000001);
295 nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen
* screen
)
297 int vram_hack_default
= 0;
299 // TODO: this is a bit of a guess; also add other cards that may need this hack.
300 // It may also depend on the specific card or the AGP/PCIe chipset.
301 if(screen
->base
.device
->chipset
== 0x47 /* G70 */
302 || screen
->base
.device
->chipset
== 0x49 /* G71 */
303 || screen
->base
.device
->chipset
== 0x46 /* G72 */
305 vram_hack_default
= 1;
306 vram_hack
= debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default
);
311 fprintf(stderr
, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
312 "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
316 fprintf(stderr
, "A performance reducing hack is being used to help avoid graphics corruption.\n"
317 "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
321 return vram_hack
? NOUVEAU_BO_VRAM
: NOUVEAU_BO_GART
;
325 nvfx_screen_create(struct pipe_winsys
*ws
, struct nouveau_device
*dev
)
327 static const unsigned query_sizes
[] = {(4096 - 4 * 32) / 32, 3 * 1024 / 32, 2 * 1024 / 32, 1024 / 32};
328 struct nvfx_screen
*screen
= CALLOC_STRUCT(nvfx_screen
);
329 struct nouveau_channel
*chan
;
330 struct pipe_screen
*pscreen
;
331 unsigned eng3d_class
= 0;
337 pscreen
= &screen
->base
.base
;
339 ret
= nouveau_screen_init(&screen
->base
, dev
);
341 nvfx_screen_destroy(pscreen
);
344 chan
= screen
->base
.channel
;
346 pscreen
->winsys
= ws
;
347 pscreen
->destroy
= nvfx_screen_destroy
;
348 pscreen
->get_param
= nvfx_screen_get_param
;
349 pscreen
->get_paramf
= nvfx_screen_get_paramf
;
350 pscreen
->is_format_supported
= nvfx_screen_surface_format_supported
;
351 pscreen
->context_create
= nvfx_create
;
353 switch (dev
->chipset
& 0xf0) {
355 if (NV30TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
356 eng3d_class
= 0x0397;
357 else if (NV34TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
358 eng3d_class
= 0x0697;
359 else if (NV35TCL_CHIPSET_3X_MASK
& (1 << (dev
->chipset
& 0x0f)))
360 eng3d_class
= 0x0497;
363 if (NV4X_GRCLASS4097_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
364 eng3d_class
= NV40TCL
;
365 else if (NV4X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
366 eng3d_class
= NV44TCL
;
367 screen
->is_nv4x
= ~0;
370 if (NV6X_GRCLASS4497_CHIPSETS
& (1 << (dev
->chipset
& 0x0f)))
371 eng3d_class
= NV44TCL
;
372 screen
->is_nv4x
= ~0;
377 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev
->chipset
);
381 screen
->force_swtnl
= debug_get_bool_option("NOUVEAU_SWTNL", FALSE
);
383 screen
->vertex_buffer_reloc_flags
= nvfx_screen_get_vertex_buffer_flags(screen
);
385 /* surely both nv3x and nv44 support index buffers too: find out how and test that */
386 if(eng3d_class
== NV40TCL
)
387 screen
->index_buffer_reloc_flags
= screen
->vertex_buffer_reloc_flags
;
389 if(!screen
->force_swtnl
&& screen
->vertex_buffer_reloc_flags
== screen
->index_buffer_reloc_flags
)
390 screen
->base
.vertex_buffer_flags
= screen
->base
.index_buffer_flags
= screen
->vertex_buffer_reloc_flags
;
392 nvfx_screen_init_resource_functions(pscreen
);
394 ret
= nouveau_grobj_alloc(chan
, 0xbeef3097, eng3d_class
, &screen
->eng3d
);
396 NOUVEAU_ERR("Error creating 3D object: %d\n", ret
);
400 /* 2D engine setup */
401 screen
->eng2d
= nv04_surface_2d_init(&screen
->base
);
402 screen
->eng2d
->buf
= nvfx_surface_buffer
;
404 /* Notifier for sync purposes */
405 ret
= nouveau_notifier_alloc(chan
, 0xbeef0301, 1, &screen
->sync
);
407 NOUVEAU_ERR("Error creating notifier object: %d\n", ret
);
408 nvfx_screen_destroy(pscreen
);
413 for(i
= 0; i
< sizeof(query_sizes
) / sizeof(query_sizes
[0]); ++i
)
415 ret
= nouveau_notifier_alloc(chan
, 0xbeef0302, query_sizes
[i
], &screen
->query
);
421 NOUVEAU_ERR("Error initialising query objects: %d\n", ret
);
422 nvfx_screen_destroy(pscreen
);
426 ret
= nouveau_resource_init(&screen
->query_heap
, 0, query_sizes
[i
]);
428 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret
);
429 nvfx_screen_destroy(pscreen
);
433 LIST_INITHEAD(&screen
->query_list
);
435 /* Vtxprog resources */
436 if (nouveau_resource_init(&screen
->vp_exec_heap
, 0, screen
->is_nv4x
? 512 : 256) ||
437 nouveau_resource_init(&screen
->vp_data_heap
, 0, 256)) {
438 nvfx_screen_destroy(pscreen
);
442 BIND_RING(chan
, screen
->eng3d
, 7);
444 /* Static eng3d initialisation */
445 /* note that we just started using the channel, so we must have space in the pushbuffer */
446 OUT_RING(chan
, RING_3D(NV34TCL_DMA_NOTIFY
, 1));
447 OUT_RING(chan
, screen
->sync
->handle
);
448 OUT_RING(chan
, RING_3D(NV34TCL_DMA_TEXTURE0
, 2));
449 OUT_RING(chan
, chan
->vram
->handle
);
450 OUT_RING(chan
, chan
->gart
->handle
);
451 OUT_RING(chan
, RING_3D(NV34TCL_DMA_COLOR1
, 1));
452 OUT_RING(chan
, chan
->vram
->handle
);
453 OUT_RING(chan
, RING_3D(NV34TCL_DMA_COLOR0
, 2));
454 OUT_RING(chan
, chan
->vram
->handle
);
455 OUT_RING(chan
, chan
->vram
->handle
);
456 OUT_RING(chan
, RING_3D(NV34TCL_DMA_VTXBUF0
, 2));
457 OUT_RING(chan
, chan
->vram
->handle
);
458 OUT_RING(chan
, chan
->gart
->handle
);
460 OUT_RING(chan
, RING_3D(NV34TCL_DMA_FENCE
, 2));
462 OUT_RING(chan
, screen
->query
->handle
);
464 OUT_RING(chan
, RING_3D(NV34TCL_DMA_IN_MEMORY7
, 2));
465 OUT_RING(chan
, chan
->vram
->handle
);
466 OUT_RING(chan
, chan
->vram
->handle
);
469 nv30_screen_init(screen
);
471 nv40_screen_init(screen
);