src/gallium/drivers/nvfx/nvfx_screen.c

   1 #include "pipe/p_screen.h"
   2 #include "pipe/p_state.h"
   3 #include "util/u_simple_screen.h"
   4
   5 #include "nouveau/nouveau_screen.h"
   6
   7 #include "nvfx_context.h"
   8 #include "nvfx_screen.h"
   9 #include "nvfx_resource.h"
  10
  11 #define NV30TCL_CHIPSET_3X_MASK 0x00000003
  12 #define NV34TCL_CHIPSET_3X_MASK 0x00000010
  13 #define NV35TCL_CHIPSET_3X_MASK 0x000001e0
  14
  15 /* FIXME: It seems I should not include directly ../../winsys/drm/nouveau/drm/nouveau_drm_api.h
  16 * to get the pointer to the context front buffer, so I copied nouveau_winsys here.
  17 * nv30_screen_surface_format_supported() can then use it to enforce creating fbo
  18 * with same number of bits everywhere.
  19 */
  20 struct nouveau_winsys {
  21         struct pipe_winsys base;
  22
  23         struct pipe_screen *pscreen;
  24
  25         struct pipe_surface *front;
  26 };
  27 #define NV4X_GRCLASS4097_CHIPSETS 0x00000baf
  28 #define NV4X_GRCLASS4497_CHIPSETS 0x00005450
  29 #define NV6X_GRCLASS4497_CHIPSETS 0x00000088
  30
  31 static int
  32 nvfx_screen_get_param(struct pipe_screen *pscreen, int param)
  33 {
  34         struct nvfx_screen *screen = nvfx_screen(pscreen);
  35
  36         switch (param) {
  37         case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
  38                 /* TODO: check this */
  39                 return screen->is_nv4x ? 16 : 8;
  40         case PIPE_CAP_NPOT_TEXTURES:
  41                 return !!screen->is_nv4x;
  42         case PIPE_CAP_TWO_SIDED_STENCIL:
  43                 return 1;
  44         case PIPE_CAP_GLSL:
  45                 return 0;
  46         case PIPE_CAP_ANISOTROPIC_FILTER:
  47                 return 1;
  48         case PIPE_CAP_POINT_SPRITE:
  49                 return 1;
  50         case PIPE_CAP_MAX_RENDER_TARGETS:
  51                 return screen->is_nv4x ? 4 : 2;
  52         case PIPE_CAP_OCCLUSION_QUERY:
  53                 return 1;
  54         case PIPE_CAP_TEXTURE_SHADOW_MAP:
  55                 return 1;
  56         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
  57                 return 13;
  58         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
  59                 return 10;
  60         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
  61                 return 13;
  62         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
  63                 return !!screen->is_nv4x;
  64         case PIPE_CAP_TEXTURE_MIRROR_REPEAT:
  65                 return 1;
  66         case PIPE_CAP_MAX_VERTEX_TEXTURE_UNITS:
  67                 return 0; /* We have 4 on nv40 - but unsupported currently */
  68         case PIPE_CAP_TGSI_CONT_SUPPORTED:
  69                 return 0;
  70         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
  71                 return !!screen->is_nv4x;
  72         case NOUVEAU_CAP_HW_VTXBUF:
  73         case NOUVEAU_CAP_HW_IDXBUF:
  74                 return !screen->force_swtnl;
  75         case PIPE_CAP_MAX_COMBINED_SAMPLERS:
  76                 return 16;
  77         case PIPE_CAP_INDEP_BLEND_ENABLE:
  78                 /* TODO: on nv40 we have separate color masks */
  79                 /* TODO: nv40 mrt blending is probably broken */
  80                 return 0;
  81         case PIPE_CAP_INDEP_BLEND_FUNC:
  82                 return 0;
  83         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
  84         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
  85                 return 1;
  86         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
  87         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
  88                 return 0;
  89         default:
  90                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
  91                 return 0;
  92         }
  93 }
  94
  95 static float
  96 nvfx_screen_get_paramf(struct pipe_screen *pscreen, int param)
  97 {
  98         struct nvfx_screen *screen = nvfx_screen(pscreen);
  99
 100         switch (param) {
 101         case PIPE_CAP_MAX_LINE_WIDTH:
 102         case PIPE_CAP_MAX_LINE_WIDTH_AA:
 103                 return 10.0;
 104         case PIPE_CAP_MAX_POINT_WIDTH:
 105         case PIPE_CAP_MAX_POINT_WIDTH_AA:
 106                 return 64.0;
 107         case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
 108                 return screen->is_nv4x ? 16.0 : 8.0;
 109         case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
 110                 return screen->is_nv4x ? 16.0 : 4.0;
 111         default:
 112                 NOUVEAU_ERR("Unknown PIPE_CAP %d\n", param);
 113                 return 0.0;
 114         }
 115 }
 116
 117 static boolean
 118 nvfx_screen_surface_format_supported(struct pipe_screen *pscreen,
 119                                      enum pipe_format format,
 120                                      enum pipe_texture_target target,
 121                                      unsigned tex_usage, unsigned geom_flags)
 122 {
 123         struct nvfx_screen *screen = nvfx_screen(pscreen);
 124         struct pipe_surface *front = ((struct nouveau_winsys *) pscreen->winsys)->front;
 125
 126         if (tex_usage & PIPE_BIND_RENDER_TARGET) {
 127                 switch (format) {
 128                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 129                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 130                 case PIPE_FORMAT_B5G6R5_UNORM:
 131                         return TRUE;
 132                 default:
 133                         break;
 134                 }
 135         } else
 136         if (tex_usage & PIPE_BIND_DEPTH_STENCIL) {
 137                 switch (format) {
 138                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 139                 case PIPE_FORMAT_X8Z24_UNORM:
 140                         return TRUE;
 141                 case PIPE_FORMAT_Z16_UNORM:
 142                         /* TODO: this nv30 limitation probably does not exist */
 143                         if (!screen->is_nv4x && front)
 144                                 return (front->format == PIPE_FORMAT_B5G6R5_UNORM);
 145                         return TRUE;
 146                 default:
 147                         break;
 148                 }
 149         } else {
 150                 switch (format) {
 151                 case PIPE_FORMAT_B8G8R8A8_UNORM:
 152                 case PIPE_FORMAT_B8G8R8X8_UNORM:
 153                 case PIPE_FORMAT_B5G5R5A1_UNORM:
 154                 case PIPE_FORMAT_B4G4R4A4_UNORM:
 155                 case PIPE_FORMAT_B5G6R5_UNORM:
 156                 case PIPE_FORMAT_L8_UNORM:
 157                 case PIPE_FORMAT_A8_UNORM:
 158                 case PIPE_FORMAT_I8_UNORM:
 159                 case PIPE_FORMAT_L8A8_UNORM:
 160                 case PIPE_FORMAT_Z16_UNORM:
 161                 case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 162                 case PIPE_FORMAT_DXT1_RGB:
 163                 case PIPE_FORMAT_DXT1_RGBA:
 164                 case PIPE_FORMAT_DXT3_RGBA:
 165                 case PIPE_FORMAT_DXT5_RGBA:
 166                         return TRUE;
 167                 /* TODO: does nv30 support this? */
 168                 case PIPE_FORMAT_R16_SNORM:
 169                         return !!screen->is_nv4x;
 170                 default:
 171                         break;
 172                 }
 173         }
 174
 175         return FALSE;
 176 }
 177
 178
 179 static void
 180 nvfx_screen_destroy(struct pipe_screen *pscreen)
 181 {
 182         struct nvfx_screen *screen = nvfx_screen(pscreen);
 183
 184         nouveau_resource_destroy(&screen->vp_exec_heap);
 185         nouveau_resource_destroy(&screen->vp_data_heap);
 186         nouveau_resource_destroy(&screen->query_heap);
 187         nouveau_notifier_free(&screen->query);
 188         nouveau_notifier_free(&screen->sync);
 189         nouveau_grobj_free(&screen->eng3d);
 190         nv04_surface_2d_takedown(&screen->eng2d);
 191
 192         nouveau_screen_fini(&screen->base);
 193
 194         FREE(pscreen);
 195 }
 196
 197 static void nv30_screen_init(struct nvfx_screen *screen)
 198 {
 199         struct nouveau_channel *chan = screen->base.channel;
 200         int i;
 201
 202         /* TODO: perhaps we should do some of this on nv40 too? */
 203         for (i=1; i<8; i++) {
 204                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_HORIZ(i), 1));
 205                 OUT_RING(chan, 0);
 206                 OUT_RING(chan, RING_3D(NV34TCL_VIEWPORT_CLIP_VERT(i), 1));
 207                 OUT_RING(chan, 0);
 208         }
 209
 210         OUT_RING(chan, RING_3D(0x220, 1));
 211         OUT_RING(chan, 1);
 212
 213         OUT_RING(chan, RING_3D(0x03b0, 1));
 214         OUT_RING(chan, 0x00100000);
 215         OUT_RING(chan, RING_3D(0x1454, 1));
 216         OUT_RING(chan, 0);
 217         OUT_RING(chan, RING_3D(0x1d80, 1));
 218         OUT_RING(chan, 3);
 219         OUT_RING(chan, RING_3D(0x1450, 1));
 220         OUT_RING(chan, 0x00030004);
 221
 222         /* NEW */
 223         OUT_RING(chan, RING_3D(0x1e98, 1));
 224         OUT_RING(chan, 0);
 225         OUT_RING(chan, RING_3D(0x17e0, 3));
 226         OUT_RING(chan, fui(0.0));
 227         OUT_RING(chan, fui(0.0));
 228         OUT_RING(chan, fui(1.0));
 229         OUT_RING(chan, RING_3D(0x1f80, 16));
 230         for (i=0; i<16; i++) {
 231                 OUT_RING(chan, (i==8) ? 0x0000ffff : 0);
 232         }
 233
 234         OUT_RING(chan, RING_3D(0x120, 3));
 235         OUT_RING(chan, 0);
 236         OUT_RING(chan, 1);
 237         OUT_RING(chan, 2);
 238
 239         OUT_RING(chan, RING_3D(0x1d88, 1));
 240         OUT_RING(chan, 0x00001200);
 241
 242         OUT_RING(chan, RING_3D(NV34TCL_RC_ENABLE, 1));
 243         OUT_RING(chan, 0);
 244
 245         OUT_RING(chan, RING_3D(NV34TCL_DEPTH_RANGE_NEAR, 2));
 246         OUT_RING(chan, fui(0.0));
 247         OUT_RING(chan, fui(1.0));
 248
 249         OUT_RING(chan, RING_3D(NV34TCL_MULTISAMPLE_CONTROL, 1));
 250         OUT_RING(chan, 0xffff0000);
 251
 252         /* enables use of vp rather than fixed-function somehow */
 253         OUT_RING(chan, RING_3D(0x1e94, 1));
 254         OUT_RING(chan, 0x13);
 255 }
 256
 257 static void nv40_screen_init(struct nvfx_screen *screen)
 258 {
 259         struct nouveau_channel *chan = screen->base.channel;
 260
 261         OUT_RING(chan, RING_3D(NV40TCL_DMA_COLOR2, 2));
 262         OUT_RING(chan, screen->base.channel->vram->handle);
 263         OUT_RING(chan, screen->base.channel->vram->handle);
 264
 265         OUT_RING(chan, RING_3D(0x1ea4, 3));
 266         OUT_RING(chan, 0x00000010);
 267         OUT_RING(chan, 0x01000100);
 268         OUT_RING(chan, 0xff800006);
 269
 270         /* vtxprog output routing */
 271         OUT_RING(chan, RING_3D(0x1fc4, 1));
 272         OUT_RING(chan, 0x06144321);
 273         OUT_RING(chan, RING_3D(0x1fc8, 2));
 274         OUT_RING(chan, 0xedcba987);
 275         OUT_RING(chan, 0x00000021);
 276         OUT_RING(chan, RING_3D(0x1fd0, 1));
 277         OUT_RING(chan, 0x00171615);
 278         OUT_RING(chan, RING_3D(0x1fd4, 1));
 279         OUT_RING(chan, 0x001b1a19);
 280
 281         OUT_RING(chan, RING_3D(0x1ef8, 1));
 282         OUT_RING(chan, 0x0020ffff);
 283         OUT_RING(chan, RING_3D(0x1d64, 1));
 284         OUT_RING(chan, 0x00d30000);
 285         OUT_RING(chan, RING_3D(0x1e94, 1));
 286         OUT_RING(chan, 0x00000001);
 287 }
 288
 289 static void
 290 nvfx_screen_init_buffer_functions(struct nvfx_screen* screen)
 291 {
 292         int vram_hack_default = 0;
 293         int vram_hack;
 294         // TODO: this is a bit of a guess; also add other cards that may need this hack.
 295         // It may also depend on the specific card or the AGP/PCIe chipset.
 296         if(screen->base.device->chipset == 0x47 /* G70 */
 297                 || screen->base.device->chipset == 0x49 /* G71 */
 298                 || screen->base.device->chipset == 0x46 /* G72 */
 299                 )
 300                 vram_hack_default = 1;
 301         vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
 302
 303 #ifdef DEBUG
 304         if(!vram_hack)
 305         {
 306                 fprintf(stderr, "Some systems may experience graphics corruption due to randomly misplaced vertices.\n"
 307                         "If this is happening, export NOUVEAU_VTXIDX_IN_VRAM=1 may reduce or eliminate the problem\n");
 308         }
 309         else
 310         {
 311                 fprintf(stderr, "A performance reducing hack is being used to help avoid graphics corruption.\n"
 312                         "You can try export NOUVEAU_VTXIDX_IN_VRAM=0 to disable it.\n");
 313         }
 314 #endif
 315
 316         screen->vertex_buffer_flags = vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
 317 }
 318
 319 struct pipe_screen *
 320 nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *dev)
 321 {
 322         struct nvfx_screen *screen = CALLOC_STRUCT(nvfx_screen);
 323         struct nouveau_channel *chan;
 324         struct pipe_screen *pscreen;
 325         unsigned eng3d_class = 0;
 326         int ret;
 327
 328         if (!screen)
 329                 return NULL;
 330
 331         pscreen = &screen->base.base;
 332
 333         ret = nouveau_screen_init(&screen->base, dev);
 334         if (ret) {
 335                 nvfx_screen_destroy(pscreen);
 336                 return NULL;
 337         }
 338         chan = screen->base.channel;
 339
 340         pscreen->winsys = ws;
 341         pscreen->destroy = nvfx_screen_destroy;
 342         pscreen->get_param = nvfx_screen_get_param;
 343         pscreen->get_paramf = nvfx_screen_get_paramf;
 344         pscreen->is_format_supported = nvfx_screen_surface_format_supported;
 345         pscreen->context_create = nvfx_create;
 346
 347         switch (dev->chipset & 0xf0) {
 348         case 0x30:
 349                 if (NV30TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 350                         eng3d_class = 0x0397;
 351                 else if (NV34TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 352                         eng3d_class = 0x0697;
 353                 else if (NV35TCL_CHIPSET_3X_MASK & (1 << (dev->chipset & 0x0f)))
 354                         eng3d_class = 0x0497;
 355                 break;
 356         case 0x40:
 357                 if (NV4X_GRCLASS4097_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 358                         eng3d_class = NV40TCL;
 359                 else if (NV4X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 360                         eng3d_class = NV44TCL;
 361                 screen->is_nv4x = ~0;
 362                 break;
 363         case 0x60:
 364                 if (NV6X_GRCLASS4497_CHIPSETS & (1 << (dev->chipset & 0x0f)))
 365                         eng3d_class = NV44TCL;
 366                 screen->is_nv4x = ~0;
 367                 break;
 368         }
 369
 370         if (!eng3d_class) {
 371                 NOUVEAU_ERR("Unknown nv3x/nv4x chipset: nv%02x\n", dev->chipset);
 372                 return NULL;
 373         }
 374
 375         screen->force_swtnl = debug_get_bool_option("NOUVEAU_SWTNL", FALSE);
 376
 377         nvfx_screen_init_resource_functions(pscreen);
 378         nvfx_screen_init_buffer_functions(screen);
 379
 380         ret = nouveau_grobj_alloc(chan, 0xbeef3097, eng3d_class, &screen->eng3d);
 381         if (ret) {
 382                 NOUVEAU_ERR("Error creating 3D object: %d\n", ret);
 383                 return FALSE;
 384         }
 385
 386         /* 2D engine setup */
 387         screen->eng2d = nv04_surface_2d_init(&screen->base);
 388         screen->eng2d->buf = nvfx_surface_buffer;
 389
 390         /* Notifier for sync purposes */
 391         ret = nouveau_notifier_alloc(chan, 0xbeef0301, 1, &screen->sync);
 392         if (ret) {
 393                 NOUVEAU_ERR("Error creating notifier object: %d\n", ret);
 394                 nvfx_screen_destroy(pscreen);
 395                 return NULL;
 396         }
 397
 398         /* Query objects */
 399         ret = nouveau_notifier_alloc(chan, 0xbeef0302, 32, &screen->query);
 400         if (ret) {
 401                 NOUVEAU_ERR("Error initialising query objects: %d\n", ret);
 402                 nvfx_screen_destroy(pscreen);
 403                 return NULL;
 404         }
 405
 406         ret = nouveau_resource_init(&screen->query_heap, 0, 32);
 407         if (ret) {
 408                 NOUVEAU_ERR("Error initialising query object heap: %d\n", ret);
 409                 nvfx_screen_destroy(pscreen);
 410                 return NULL;
 411         }
 412
 413         /* Vtxprog resources */
 414         if (nouveau_resource_init(&screen->vp_exec_heap, 0, screen->is_nv4x ? 512 : 256) ||
 415             nouveau_resource_init(&screen->vp_data_heap, 0, 256)) {
 416                 nvfx_screen_destroy(pscreen);
 417                 return NULL;
 418         }
 419
 420         BIND_RING(chan, screen->eng3d, 7);
 421
 422         /* Static eng3d initialisation */
 423         /* note that we just started using the channel, so we must have space in the pushbuffer */
 424         OUT_RING(chan, RING_3D(NV34TCL_DMA_NOTIFY, 1));
 425         OUT_RING(chan, screen->sync->handle);
 426         OUT_RING(chan, RING_3D(NV34TCL_DMA_TEXTURE0, 2));
 427         OUT_RING(chan, chan->vram->handle);
 428         OUT_RING(chan, chan->gart->handle);
 429         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR1, 1));
 430         OUT_RING(chan, chan->vram->handle);
 431         OUT_RING(chan, RING_3D(NV34TCL_DMA_COLOR0, 2));
 432         OUT_RING(chan, chan->vram->handle);
 433         OUT_RING(chan, chan->vram->handle);
 434         OUT_RING(chan, RING_3D(NV34TCL_DMA_VTXBUF0, 2));
 435         OUT_RING(chan, chan->vram->handle);
 436         OUT_RING(chan, chan->gart->handle);
 437
 438         OUT_RING(chan, RING_3D(NV34TCL_DMA_FENCE, 2));
 439         OUT_RING(chan, 0);
 440         OUT_RING(chan, screen->query->handle);
 441
 442         OUT_RING(chan, RING_3D(NV34TCL_DMA_IN_MEMORY7, 2));
 443         OUT_RING(chan, chan->vram->handle);
 444         OUT_RING(chan, chan->vram->handle);
 445
 446         if(!screen->is_nv4x)
 447                 nv30_screen_init(screen);
 448         else
 449                 nv40_screen_init(screen);
 450
 451         return pscreen;
 452 }