src/gallium/drivers/nvfx/nvfx_shader.h

   1 #ifndef __NVFX_SHADER_H__
   2 #define __NVFX_SHADER_H__
   3
   4 #define NVFX_SWZ_IDENTITY ((3 << 6) | (2 << 4) | (1 << 2) | (0 << 0))
   5
   6 /* this will resolve to either the NV30 or the NV40 version
   7  * depending on the current hardware */
   8 /* unusual, but very fast and compact method */
   9 #define NVFX_VP(c) ((NV30_VP_##c) + (nvfx->is_nv4x & ((NV40_VP_##c) - (NV30_VP_##c))))
  10
  11 #define NVFX_VP_INST_SLOT_VEC 0
  12 #define NVFX_VP_INST_SLOT_SCA 1
  13
  14 #define NVFX_VP_INST_IN_POS  0    /* These seem to match the bindings specified in */
  15 #define NVFX_VP_INST_IN_WEIGHT  1    /* the ARB_v_p spec (2.14.3.1) */
  16 #define NVFX_VP_INST_IN_NORMAL  2
  17 #define NVFX_VP_INST_IN_COL0  3    /* Should probably confirm them all though */
  18 #define NVFX_VP_INST_IN_COL1  4
  19 #define NVFX_VP_INST_IN_FOGC  5
  20 #define NVFX_VP_INST_IN_TC0  8
  21 #define NVFX_VP_INST_IN_TC(n)  (8+n)
  22
  23 #define NVFX_VP_INST_SCA_OP_NOP 0x00
  24 #define NVFX_VP_INST_SCA_OP_MOV 0x01
  25 #define NVFX_VP_INST_SCA_OP_RCP 0x02
  26 #define NVFX_VP_INST_SCA_OP_RCC 0x03
  27 #define NVFX_VP_INST_SCA_OP_RSQ 0x04
  28 #define NVFX_VP_INST_SCA_OP_EXP 0x05
  29 #define NVFX_VP_INST_SCA_OP_LOG 0x06
  30 #define NVFX_VP_INST_SCA_OP_LIT 0x07
  31 #define NVFX_VP_INST_SCA_OP_BRA 0x09
  32 #define NVFX_VP_INST_SCA_OP_CAL 0x0B
  33 #define NVFX_VP_INST_SCA_OP_RET 0x0C
  34 #define NVFX_VP_INST_SCA_OP_LG2 0x0D
  35 #define NVFX_VP_INST_SCA_OP_EX2 0x0E
  36 #define NVFX_VP_INST_SCA_OP_SIN 0x0F
  37 #define NVFX_VP_INST_SCA_OP_COS 0x10
  38
  39 #define NV40_VP_INST_SCA_OP_PUSHA 0x13
  40 #define NV40_VP_INST_SCA_OP_POPA 0x14
  41
  42 #define NVFX_VP_INST_VEC_OP_NOP 0x00
  43 #define NVFX_VP_INST_VEC_OP_MOV 0x01
  44 #define NVFX_VP_INST_VEC_OP_MUL 0x02
  45 #define NVFX_VP_INST_VEC_OP_ADD 0x03
  46 #define NVFX_VP_INST_VEC_OP_MAD 0x04
  47 #define NVFX_VP_INST_VEC_OP_DP3 0x05
  48 #define NVFX_VP_INST_VEC_OP_DPH 0x06
  49 #define NVFX_VP_INST_VEC_OP_DP4 0x07
  50 #define NVFX_VP_INST_VEC_OP_DST 0x08
  51 #define NVFX_VP_INST_VEC_OP_MIN 0x09
  52 #define NVFX_VP_INST_VEC_OP_MAX 0x0A
  53 #define NVFX_VP_INST_VEC_OP_SLT 0x0B
  54 #define NVFX_VP_INST_VEC_OP_SGE 0x0C
  55 #define NVFX_VP_INST_VEC_OP_ARL 0x0D
  56 #define NVFX_VP_INST_VEC_OP_FRC 0x0E
  57 #define NVFX_VP_INST_VEC_OP_FLR 0x0F
  58 #define NVFX_VP_INST_VEC_OP_SEQ 0x10
  59 #define NVFX_VP_INST_VEC_OP_SFL 0x11
  60 #define NVFX_VP_INST_VEC_OP_SGT 0x12
  61 #define NVFX_VP_INST_VEC_OP_SLE 0x13
  62 #define NVFX_VP_INST_VEC_OP_SNE 0x14
  63 #define NVFX_VP_INST_VEC_OP_STR 0x15
  64 #define NVFX_VP_INST_VEC_OP_SSG 0x16
  65 #define NVFX_VP_INST_VEC_OP_ARR 0x17
  66 #define NVFX_VP_INST_VEC_OP_ARA 0x18
  67
  68 #define NV40_VP_INST_VEC_OP_TXL 0x19
  69
  70 /* DWORD 3 */
  71 #define NVFX_VP_INST_LAST                           (1 << 0)
  72
  73 /*
  74  * Each fragment program opcode appears to be comprised of 4 32-bit values.
  75  *
  76  * 0: OPDEST
  77  *      0: program end
  78  *      1-6: destination register
  79  *      7: destination register is fp16?? (use for outputs)
  80  *      8: set condition code
  81  *      9: writemask x
  82  *      10: writemask y
  83  *      11: writemask z
  84  *      12: writemask w
  85  *      13-16: source attribute register number (e.g. COL0)
  86  *      17-20: texture unit number
  87  *      21: expand value on texture operation (x -> 2x - 1)
  88  *      22-23: precision 0 = fp32, 1 = fp16, 2 = s1.10 fixed, 3 = s0.8 fixed (nv40-only))
  89  *      24-29: opcode
  90  *      30: no destination
  91  *      31: saturate
  92  * 1 - SRC0
  93  *      0-17: see common source fields
  94  *      18: execute if condition code less
  95  *      19: execute if condition code equal
  96  *      20: execute if condition code greater
  97  *      21-22: condition code swizzle x source component
  98  *      23-24: condition code swizzle y source component
  99  *      25-26: condition code swizzle z source component
 100  *      27-28: condition code swizzle w source component
 101  *      29: source 0 absolute
 102  *      30: always 0 in renouveau tests
 103  *      31: always 0 in renouveau tests
 104  * 2 - SRC1
 105  *      0-17: see common source fields
 106  *      18: source 1 absolute
 107  *      19-20: input precision 0 = fp32, 1 = fp16, 2 = s1.10 fixed, 3 = ???
 108  *      21-27: always 0 in renouveau tests
 109  *      28-30: scale (0 = 1x, 1 = 2x, 2 = 4x, 3 = 8x, 4 = ???, 5, = 1/2, 6 = 1/4, 7 = 1/8)
 110  *      31: opcode is branch
 111  * 3 - SRC2
 112  *      0-17: see common source fields
 113  *      18: source 2 absolute
 114  *      19-29: address register displacement
 115  *      30: use index register
 116  *      31: disable perspective-correct interpolation?
 117  *
 118 * Common fields of 0, 1, 2 - SRC
 119  *      0-1: source register type (0 = temp, 1 = input, 2 = immediate, 3 = ???)
 120  *      2-7: source temp register index
 121  *      8: source register is fp16??
 122  *      9-10: source swizzle x source component
 123  *      11-12: source swizzle y source component
 124  *      13-14: source swizzle z source component
 125  *      15-16: source swizzle w source component
 126  *      17: negate
 127
 128  * There appears to be no special difference between result regs and temp regs.
 129  *     result.color == R0.xyzw
 130  *     result.depth == R1.z
 131  * When the fragprog contains instructions to write depth, NV30_TCL_PRIMITIVE_3D_UNK1D78=0
 132  * otherwise it is set to 1.
 133  *
 134  * Constants are inserted directly after the instruction that uses them.
 135  *
 136  * It appears that it's not possible to use two input registers in one
 137  * instruction as the input sourcing is done in the instruction dword
 138  * and not the source selection dwords.  As such instructions such as:
 139  *
 140  *     ADD result.color, fragment.color, fragment.texcoord[0];
 141  *
 142  * must be split into two MOV's and then an ADD (nvidia does this) but
 143  * I'm not sure why it's not just one MOV and then source the second input
 144  * in the ADD instruction..
 145  *
 146  * Negation of the full source is done with NV30_FP_REG_NEGATE, arbitrary
 147  * negation requires multiplication with a const.
 148  *
 149  * Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO/SWIZZLE_ONE
 150  * The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as SWIZZLE_ZERO
 151  * is implemented simply by not writing to the relevant components of the destination.
 152  *
 153  * Conditional execution
 154  *   TODO
 155  *
 156  * Non-native instructions:
 157  *   LIT
 158  *   LRP - MAD+MAD
 159  *   SUB - ADD, negate second source
 160  *   RSQ - LG2 + EX2
 161  *   POW - LG2 + MUL + EX2
 162  *   SCS - COS + SIN
 163  *   XPD
 164  *
 165  * NV40 Looping
 166  *   Loops appear to be fairly expensive on NV40 at least, the proprietary
 167  *   driver goes to a lot of effort to avoid using the native looping
 168  *   instructions.  If the total number of *executed* instructions between
 169  *   REP/ENDREP or LOOP/ENDLOOP is <=500, the driver will unroll the loop.
 170  *   The maximum loop count is 255.
 171  *
 172  */
 173
 174 //== Opcode / Destination selection ==
 175 #define NVFX_FP_OP_PROGRAM_END          (1 << 0)
 176 #define NVFX_FP_OP_OUT_REG_SHIFT        1
 177 #define NV30_FP_OP_OUT_REG_MASK          (31 << 1)  /* uncertain */
 178 #define NV40_FP_OP_OUT_REG_MASK          (63 << 1)
 179 /* Needs to be set when writing outputs to get expected result.. */
 180 #define NVFX_FP_OP_OUT_REG_HALF          (1 << 7)
 181 #define NVFX_FP_OP_COND_WRITE_ENABLE        (1 << 8)
 182 #define NVFX_FP_OP_OUTMASK_SHIFT        9
 183 #define NVFX_FP_OP_OUTMASK_MASK          (0xF << 9)
 184 #  define NVFX_FP_OP_OUT_X  (1<<9)
 185 #  define NVFX_FP_OP_OUT_Y  (1<<10)
 186 #  define NVFX_FP_OP_OUT_Z  (1<<11)
 187 #  define NVFX_FP_OP_OUT_W  (1<<12)
 188 /* Uncertain about these, especially the input_src values.. it's possible that
 189  * they can be dynamically changed.
 190  */
 191 #define NVFX_FP_OP_INPUT_SRC_SHIFT        13
 192 #define NVFX_FP_OP_INPUT_SRC_MASK        (15 << 13)
 193 #  define NVFX_FP_OP_INPUT_SRC_POSITION  0x0
 194 #  define NVFX_FP_OP_INPUT_SRC_COL0  0x1
 195 #  define NVFX_FP_OP_INPUT_SRC_COL1  0x2
 196 #  define NVFX_FP_OP_INPUT_SRC_FOGC  0x3
 197 #  define NVFX_FP_OP_INPUT_SRC_TC0    0x4
 198 #  define NVFX_FP_OP_INPUT_SRC_TC(n)  (0x4 + n)
 199 #  define NV40_FP_OP_INPUT_SRC_FACING  0xE
 200 #define NVFX_FP_OP_TEX_UNIT_SHIFT        17
 201 #define NVFX_FP_OP_TEX_UNIT_MASK        (0xF << 17) /* guess */
 202 #define NVFX_FP_OP_PRECISION_SHIFT        22
 203 #define NVFX_FP_OP_PRECISION_MASK        (3 << 22)
 204 #   define NVFX_FP_PRECISION_FP32  0
 205 #   define NVFX_FP_PRECISION_FP16  1
 206 #   define NVFX_FP_PRECISION_FX12  2
 207 #define NVFX_FP_OP_OPCODE_SHIFT          24
 208 #define NVFX_FP_OP_OPCODE_MASK          (0x3F << 24)
 209 /* NV30/NV40 fragment program opcodes */
 210 #define NVFX_FP_OP_OPCODE_NOP 0x00
 211 #define NVFX_FP_OP_OPCODE_MOV 0x01
 212 #define NVFX_FP_OP_OPCODE_MUL 0x02
 213 #define NVFX_FP_OP_OPCODE_ADD 0x03
 214 #define NVFX_FP_OP_OPCODE_MAD 0x04
 215 #define NVFX_FP_OP_OPCODE_DP3 0x05
 216 #define NVFX_FP_OP_OPCODE_DP4 0x06
 217 #define NVFX_FP_OP_OPCODE_DST 0x07
 218 #define NVFX_FP_OP_OPCODE_MIN 0x08
 219 #define NVFX_FP_OP_OPCODE_MAX 0x09
 220 #define NVFX_FP_OP_OPCODE_SLT 0x0A
 221 #define NVFX_FP_OP_OPCODE_SGE 0x0B
 222 #define NVFX_FP_OP_OPCODE_SLE 0x0C
 223 #define NVFX_FP_OP_OPCODE_SGT 0x0D
 224 #define NVFX_FP_OP_OPCODE_SNE 0x0E
 225 #define NVFX_FP_OP_OPCODE_SEQ 0x0F
 226 #define NVFX_FP_OP_OPCODE_FRC 0x10
 227 #define NVFX_FP_OP_OPCODE_FLR 0x11
 228 #define NVFX_FP_OP_OPCODE_KIL 0x12
 229 #define NVFX_FP_OP_OPCODE_PK4B 0x13
 230 #define NVFX_FP_OP_OPCODE_UP4B 0x14
 231 #define NVFX_FP_OP_OPCODE_DDX 0x15 /* can only write XY */
 232 #define NVFX_FP_OP_OPCODE_DDY 0x16 /* can only write XY */
 233 #define NVFX_FP_OP_OPCODE_TEX 0x17
 234 #define NVFX_FP_OP_OPCODE_TXP 0x18
 235 #define NVFX_FP_OP_OPCODE_TXD 0x19
 236 #define NVFX_FP_OP_OPCODE_RCP 0x1A
 237 #define NVFX_FP_OP_OPCODE_EX2 0x1C
 238 #define NVFX_FP_OP_OPCODE_LG2 0x1D
 239 #define NVFX_FP_OP_OPCODE_STR 0x20
 240 #define NVFX_FP_OP_OPCODE_SFL 0x21
 241 #define NVFX_FP_OP_OPCODE_COS 0x22
 242 #define NVFX_FP_OP_OPCODE_SIN 0x23
 243 #define NVFX_FP_OP_OPCODE_PK2H 0x24
 244 #define NVFX_FP_OP_OPCODE_UP2H 0x25
 245 #define NVFX_FP_OP_OPCODE_PK4UB 0x27
 246 #define NVFX_FP_OP_OPCODE_UP4UB 0x28
 247 #define NVFX_FP_OP_OPCODE_PK2US 0x29
 248 #define NVFX_FP_OP_OPCODE_UP2US 0x2A
 249 #define NVFX_FP_OP_OPCODE_DP2A 0x2E
 250 #define NVFX_FP_OP_OPCODE_TXB 0x31
 251 #define NVFX_FP_OP_OPCODE_DIV 0x3A
 252
 253 /* NV30 only fragment program opcodes */
 254 #define NVFX_FP_OP_OPCODE_RSQ_NV30 0x1B
 255 #define NVFX_FP_OP_OPCODE_LIT_NV30 0x1E
 256 #define NVFX_FP_OP_OPCODE_LRP_NV30 0x1F
 257 #define NVFX_FP_OP_OPCODE_POW_NV30 0x26
 258 #define NVFX_FP_OP_OPCODE_RFL_NV30 0x36
 259
 260 /* NV40 only fragment program opcodes */
 261 #define NVFX_FP_OP_OPCODE_TXL_NV40 0x2F
 262
 263 /* The use of these instructions appears to be indicated by bit 31 of DWORD 2.*/
 264 #define NV40_FP_OP_BRA_OPCODE_BRK                                    0x0
 265 #define NV40_FP_OP_BRA_OPCODE_CAL                                    0x1
 266 #define NV40_FP_OP_BRA_OPCODE_IF                                     0x2
 267 #define NV40_FP_OP_BRA_OPCODE_LOOP                                   0x3
 268 #define NV40_FP_OP_BRA_OPCODE_REP                                    0x4
 269 #define NV40_FP_OP_BRA_OPCODE_RET                                    0x5
 270
 271 #define NV40_FP_OP_OUT_NONE         (1 << 30)
 272 #define NVFX_FP_OP_OUT_SAT          (1 << 31)
 273
 274 /* high order bits of SRC0 */
 275 #define NVFX_FP_OP_SRC0_ABS          (1 << 29)
 276 #define NVFX_FP_OP_COND_SWZ_W_SHIFT        27
 277 #define NVFX_FP_OP_COND_SWZ_W_MASK        (3 << 27)
 278 #define NVFX_FP_OP_COND_SWZ_Z_SHIFT        25
 279 #define NVFX_FP_OP_COND_SWZ_Z_MASK        (3 << 25)
 280 #define NVFX_FP_OP_COND_SWZ_Y_SHIFT        23
 281 #define NVFX_FP_OP_COND_SWZ_Y_MASK        (3 << 23)
 282 #define NVFX_FP_OP_COND_SWZ_X_SHIFT        21
 283 #define NVFX_FP_OP_COND_SWZ_X_MASK        (3 << 21)
 284 #define NVFX_FP_OP_COND_SWZ_ALL_SHIFT        21
 285 #define NVFX_FP_OP_COND_SWZ_ALL_MASK        (0xFF << 21)
 286 #define NVFX_FP_OP_COND_SHIFT          18
 287 #define NVFX_FP_OP_COND_MASK          (0x07 << 18)
 288 #  define NVFX_FP_OP_COND_FL  0
 289 #  define NVFX_FP_OP_COND_LT  1
 290 #  define NVFX_FP_OP_COND_EQ  2
 291 #  define NVFX_FP_OP_COND_LE  3
 292 #  define NVFX_FP_OP_COND_GT  4
 293 #  define NVFX_FP_OP_COND_NE  5
 294 #  define NVFX_FP_OP_COND_GE  6
 295 #  define NVFX_FP_OP_COND_TR  7
 296
 297 /* high order bits of SRC1 */
 298 #define NV40_FP_OP_OPCODE_IS_BRANCH                                      (1<<31)
 299 #define NVFX_FP_OP_DST_SCALE_SHIFT        28
 300 #define NVFX_FP_OP_DST_SCALE_MASK        (3 << 28)
 301 #define NVFX_FP_OP_DST_SCALE_1X                                                0
 302 #define NVFX_FP_OP_DST_SCALE_2X                                                1
 303 #define NVFX_FP_OP_DST_SCALE_4X                                                2
 304 #define NVFX_FP_OP_DST_SCALE_8X                                                3
 305 #define NVFX_FP_OP_DST_SCALE_INV_2X                                            5
 306 #define NVFX_FP_OP_DST_SCALE_INV_4X                                            6
 307 #define NVFX_FP_OP_DST_SCALE_INV_8X                                            7
 308 #define NVFX_FP_OP_SRC1_ABS          (1 << 18)
 309
 310 /* SRC1 LOOP */
 311 #define NV40_FP_OP_LOOP_INCR_SHIFT                                            19
 312 #define NV40_FP_OP_LOOP_INCR_MASK                                   (0xFF << 19)
 313 #define NV40_FP_OP_LOOP_INDEX_SHIFT                                           10
 314 #define NV40_FP_OP_LOOP_INDEX_MASK                                  (0xFF << 10)
 315 #define NV40_FP_OP_LOOP_COUNT_SHIFT                                            2
 316 #define NV40_FP_OP_LOOP_COUNT_MASK                                   (0xFF << 2)
 317
 318 /* SRC1 IF: absolute offset in dwords */
 319 #define NV40_FP_OP_ELSE_OFFSET_SHIFT                                           0
 320 #define NV40_FP_OP_ELSE_OFFSET_MASK                             (0x7FFFFFFF << 0)
 321
 322 /* SRC1 CAL */
 323 #define NV40_FP_OP_SUB_OFFSET_SHIFT                                                 0
 324 #define NV40_FP_OP_SUB_OFFSET_MASK                                   (0x7FFFFFFF << 0)
 325
 326 /* SRC1 REP
 327  *   I have no idea why there are 3 count values here..  but they
 328  *   have always been filled with the same value in my tests so
 329  *   far..
 330  */
 331 #define NV40_FP_OP_REP_COUNT1_SHIFT                                            2
 332 #define NV40_FP_OP_REP_COUNT1_MASK                                   (0xFF << 2)
 333 #define NV40_FP_OP_REP_COUNT2_SHIFT                                           10
 334 #define NV40_FP_OP_REP_COUNT2_MASK                                  (0xFF << 10)
 335 #define NV40_FP_OP_REP_COUNT3_SHIFT                                           19
 336 #define NV40_FP_OP_REP_COUNT3_MASK                                  (0xFF << 19)
 337
 338 /* SRC2 REP/IF: absolute offset in dwords */
 339 #define NV40_FP_OP_END_OFFSET_SHIFT                                            0
 340 #define NV40_FP_OP_END_OFFSET_MASK                              (0x7FFFFFFF << 0)
 341
 342 /* high order bits of SRC2 */
 343 #define NVFX_FP_OP_INDEX_INPUT          (1 << 30)
 344 #define NV40_FP_OP_ADDR_INDEX_SHIFT        19
 345 #define NV40_FP_OP_ADDR_INDEX_MASK        (0xF << 19)
 346
 347 //== Register selection ==
 348 #define NVFX_FP_REG_TYPE_SHIFT           0
 349 #define NVFX_FP_REG_TYPE_MASK           (3 << 0)
 350 #  define NVFX_FP_REG_TYPE_TEMP   0
 351 #  define NVFX_FP_REG_TYPE_INPUT  1
 352 #  define NVFX_FP_REG_TYPE_CONST  2
 353 #define NVFX_FP_REG_SRC_SHIFT            2
 354 #define NV30_FP_REG_SRC_MASK              (31 << 2)
 355 #define NV40_FP_REG_SRC_MASK              (63 << 2)
 356 #define NVFX_FP_REG_SRC_HALF            (1 << 8)
 357 #define NVFX_FP_REG_SWZ_ALL_SHIFT        9
 358 #define NVFX_FP_REG_SWZ_ALL_MASK        (255 << 9)
 359 #define NVFX_FP_REG_SWZ_X_SHIFT          9
 360 #define NVFX_FP_REG_SWZ_X_MASK          (3 << 9)
 361 #define NVFX_FP_REG_SWZ_Y_SHIFT          11
 362 #define NVFX_FP_REG_SWZ_Y_MASK          (3 << 11)
 363 #define NVFX_FP_REG_SWZ_Z_SHIFT          13
 364 #define NVFX_FP_REG_SWZ_Z_MASK          (3 << 13)
 365 #define NVFX_FP_REG_SWZ_W_SHIFT          15
 366 #define NVFX_FP_REG_SWZ_W_MASK          (3 << 15)
 367 #  define NVFX_FP_SWIZZLE_X  0
 368 #  define NVFX_FP_SWIZZLE_Y  1
 369 #  define NVFX_FP_SWIZZLE_Z  2
 370 #  define NVFX_FP_SWIZZLE_W  3
 371 #define NVFX_FP_REG_NEGATE          (1 << 17)
 372
 373 #define NVFXSR_NONE     0
 374 #define NVFXSR_OUTPUT   1
 375 #define NVFXSR_INPUT    2
 376 #define NVFXSR_TEMP     3
 377 #define NVFXSR_CONST    4
 378 #define NVFXSR_RELOCATED        5
 379
 380 #define NVFX_COND_FL  0
 381 #define NVFX_COND_LT  1
 382 #define NVFX_COND_EQ  2
 383 #define NVFX_COND_LE  3
 384 #define NVFX_COND_GT  4
 385 #define NVFX_COND_NE  5
 386 #define NVFX_COND_GE  6
 387 #define NVFX_COND_TR  7
 388
 389 /* Yes, this are ordered differently... */
 390
 391 #define NVFX_VP_MASK_X 8
 392 #define NVFX_VP_MASK_Y 4
 393 #define NVFX_VP_MASK_Z 2
 394 #define NVFX_VP_MASK_W 1
 395 #define NVFX_VP_MASK_ALL 0xf
 396
 397 #define NVFX_FP_MASK_X 1
 398 #define NVFX_FP_MASK_Y 2
 399 #define NVFX_FP_MASK_Z 4
 400 #define NVFX_FP_MASK_W 8
 401 #define NVFX_FP_MASK_ALL 0xf
 402
 403 #define NVFX_SWZ_X 0
 404 #define NVFX_SWZ_Y 1
 405 #define NVFX_SWZ_Z 2
 406 #define NVFX_SWZ_W 3
 407
 408 #define swz(s,x,y,z,w) nvfx_src_swz((s), NVFX_SWZ_##x, NVFX_SWZ_##y, NVFX_SWZ_##z, NVFX_SWZ_##w)
 409 #define neg(s) nvfx_src_neg((s))
 410 #define abs(s) nvfx_src_abs((s))
 411
 412 struct nvfx_reg {
 413         uint8_t type;
 414         uint32_t index;
 415 };
 416
 417 struct nvfx_src {
 418         struct nvfx_reg reg;
 419
 420         /* src only */
 421         uint8_t negate : 1;
 422         uint8_t abs : 1;
 423         uint8_t swz[4];
 424 };
 425
 426 struct nvfx_insn
 427 {
 428         uint8_t op;
 429         char scale;
 430         int8_t unit;
 431         uint8_t mask;
 432         uint8_t cc_swz[4];
 433
 434         uint8_t sat : 1;
 435         uint8_t cc_update : 1;
 436         uint8_t cc_update_reg : 1;
 437         uint8_t cc_test : 3;
 438         uint8_t cc_test_reg : 1;
 439
 440         struct nvfx_reg dst;
 441         struct nvfx_src src[3];
 442 };
 443
 444 static INLINE struct nvfx_insn
 445 nvfx_insn(boolean sat, unsigned op, int unit, struct nvfx_reg dst, unsigned mask, struct nvfx_src s0, struct nvfx_src s1, struct nvfx_src s2)
 446 {
 447         struct nvfx_insn insn = {
 448                 .op = op,
 449                 .scale = 0,
 450                 .unit = unit,
 451                 .sat = sat,
 452                 .mask = mask,
 453                 .cc_update = 0,
 454                 .cc_update_reg = 0,
 455                 .cc_test = NVFX_COND_TR,
 456                 .cc_test_reg = 0,
 457                 .cc_swz = { 0, 1, 2, 3 },
 458                 .dst = dst,
 459                 .src = {s0, s1, s2}
 460         };
 461         return insn;
 462 }
 463
 464 static INLINE struct nvfx_reg
 465 nvfx_reg(int type, int index)
 466 {
 467         struct nvfx_reg temp = {
 468                 .type = type,
 469                 .index = index,
 470         };
 471         return temp;
 472 }
 473
 474 static INLINE struct nvfx_src
 475 nvfx_src(struct nvfx_reg reg)
 476 {
 477         struct nvfx_src temp = {
 478                 .reg = reg,
 479                 .abs = 0,
 480                 .negate = 0,
 481                 .swz = { 0, 1, 2, 3 },
 482         };
 483         return temp;
 484 }
 485
 486 static INLINE struct nvfx_src
 487 nvfx_src_swz(struct nvfx_src src, int x, int y, int z, int w)
 488 {
 489         struct nvfx_src dst = src;
 490
 491         dst.swz[NVFX_SWZ_X] = src.swz[x];
 492         dst.swz[NVFX_SWZ_Y] = src.swz[y];
 493         dst.swz[NVFX_SWZ_Z] = src.swz[z];
 494         dst.swz[NVFX_SWZ_W] = src.swz[w];
 495         return dst;
 496 }
 497
 498 static INLINE struct nvfx_src
 499 nvfx_src_neg(struct nvfx_src src)
 500 {
 501         src.negate = !src.negate;
 502         return src;
 503 }
 504
 505 static INLINE struct nvfx_src
 506 nvfx_src_abs(struct nvfx_src src)
 507 {
 508         src.abs = 1;
 509         return src;
 510 }
 511
 512 #endif