nouveau: rework and simplify nv04/nv05 driver a bit
[mesa.git] / src / gallium / drivers / nvfx / nvfx_surface.c
1
2 /**************************************************************************
3 *
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
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12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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27 **************************************************************************/
28
29 #include "pipe/p_context.h"
30 #include "pipe/p_format.h"
31 #include "util/u_format.h"
32 #include "util/u_math.h"
33 #include "util/u_memory.h"
34 #include "util/u_pack_color.h"
35 #include "util/u_blitter.h"
36 #include "util/u_surface.h"
37
38 #include "nouveau/nouveau_winsys.h"
39 #include "nouveau/nouveau_screen.h"
40 #include "nvfx_context.h"
41 #include "nvfx_screen.h"
42 #include "nvfx_resource.h"
43 #include "nv04_2d.h"
44
45 #include <nouveau/nouveau_bo.h>
46
47 static INLINE void
48 nvfx_region_set_format(struct nv04_region* rgn, enum pipe_format format)
49 {
50 unsigned bits = util_format_get_blocksizebits(format);
51 unsigned shift = 0;
52 rgn->one_bits = 0;
53
54 switch(bits)
55 {
56 case 8:
57 rgn->bpps = 0;
58 break;
59 case 16:
60 rgn->bpps = 1;
61 if(format == PIPE_FORMAT_B5G5R5X1_UNORM)
62 rgn->one_bits = 1;
63 break;
64 case 32:
65 rgn->bpps = 2;
66 if(format == PIPE_FORMAT_R8G8B8X8_UNORM || format == PIPE_FORMAT_B8G8R8X8_UNORM)
67 rgn->one_bits = 8;
68 break;
69 case 64:
70 rgn->bpps = 2;
71 shift = 1;
72 break;
73 case 128:
74 rgn->bpps = 2;
75 shift = 2;
76 break;
77 }
78
79 if(shift) {
80 rgn->x = util_format_get_nblocksx(format, rgn->x) << shift;
81 rgn->y = util_format_get_nblocksy(format, rgn->y);
82 rgn->w <<= shift;
83 }
84 }
85
86 static INLINE void
87 nvfx_region_init_for_surface(struct nv04_region* rgn, struct nvfx_surface* surf, unsigned x, unsigned y, boolean for_write)
88 {
89 rgn->x = x;
90 rgn->y = y;
91 rgn->z = 0;
92
93 rgn->bo = ((struct nvfx_resource*)surf->base.texture)->bo;
94 rgn->offset = surf->offset;
95
96 if(surf->base.texture->flags & NOUVEAU_RESOURCE_FLAG_LINEAR)
97 rgn->pitch = surf->pitch;
98 else {
99 rgn->pitch = 0;
100 rgn->z = surf->base.u.tex.first_layer;
101 rgn->w = surf->base.width;
102 rgn->h = surf->base.height;
103 rgn->d = u_minify(surf->base.texture->depth0, surf->base.u.tex.level);
104 }
105
106 nvfx_region_set_format(rgn, surf->base.format);
107 if(!rgn->pitch)
108 nv04_region_try_to_linearize(rgn);
109 }
110
111 static INLINE void
112 nvfx_region_init_for_subresource(struct nv04_region* rgn, struct pipe_resource* pt, unsigned level, unsigned x, unsigned y, unsigned z, boolean for_write)
113 {
114 if(pt->target != PIPE_BUFFER)
115 {
116 struct nvfx_surface* ns = (struct nvfx_surface*)util_surfaces_peek(&((struct nvfx_miptree*)pt)->surfaces, pt, level, z);
117 if(ns)
118 {
119 nvfx_region_init_for_surface(rgn, ns, x, y, for_write);
120 return;
121 }
122 }
123
124 rgn->bo = ((struct nvfx_resource*)pt)->bo;
125 rgn->offset = nvfx_subresource_offset(pt, z, level, z);
126 rgn->x = x;
127 rgn->y = y;
128
129 if(pt->flags & NOUVEAU_RESOURCE_FLAG_LINEAR)
130 {
131 rgn->pitch = nvfx_subresource_pitch(pt, level);
132 rgn->z = 0;
133 }
134 else
135 {
136 rgn->pitch = 0;
137 rgn->z = z;
138 rgn->w = u_minify(pt->width0, level);
139 rgn->h = u_minify(pt->height0, level);
140 rgn->d = u_minify(pt->depth0, level);
141 }
142
143 nvfx_region_set_format(rgn, pt->format);
144 if(!rgn->pitch)
145 nv04_region_try_to_linearize(rgn);
146 }
147
148 // don't save index buffer because blitter doesn't setit
149 static struct blitter_context*
150 nvfx_get_blitter(struct pipe_context* pipe, int copy)
151 {
152 struct nvfx_context* nvfx = nvfx_context(pipe);
153 struct blitter_context** pblitter;
154 struct blitter_context* blitter;
155
156 assert(nvfx->blitters_in_use < Elements(nvfx->blitter));
157
158 if(nvfx->query && !nvfx->blitters_in_use)
159 {
160 struct nouveau_channel* chan = nvfx->screen->base.channel;
161 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
162 BEGIN_RING(chan, eng3d, NV30_3D_QUERY_ENABLE, 1);
163 OUT_RING(chan, 0);
164 }
165
166 pblitter = &nvfx->blitter[nvfx->blitters_in_use++];
167 if(!*pblitter)
168 *pblitter = util_blitter_create(pipe);
169 blitter = *pblitter;
170
171 util_blitter_save_blend(blitter, nvfx->blend);
172 util_blitter_save_depth_stencil_alpha(blitter, nvfx->zsa);
173 util_blitter_save_stencil_ref(blitter, &nvfx->stencil_ref);
174 util_blitter_save_rasterizer(blitter, nvfx->rasterizer);
175 util_blitter_save_fragment_shader(blitter, nvfx->fragprog);
176 util_blitter_save_vertex_shader(blitter, nvfx->vertprog);
177 util_blitter_save_viewport(blitter, &nvfx->viewport);
178 util_blitter_save_framebuffer(blitter, &nvfx->framebuffer);
179 util_blitter_save_vertex_elements(blitter, nvfx->vtxelt);
180 util_blitter_save_vertex_buffers(blitter, nvfx->vtxbuf_nr, nvfx->vtxbuf);
181
182 if(copy)
183 {
184 util_blitter_save_fragment_sampler_states(blitter, nvfx->nr_samplers, (void**)nvfx->tex_sampler);
185 util_blitter_save_fragment_sampler_views(blitter, nvfx->nr_textures, nvfx->fragment_sampler_views);
186 }
187
188 return blitter;
189 }
190
191 static inline void
192 nvfx_put_blitter(struct pipe_context* pipe, struct blitter_context* blitter)
193 {
194 struct nvfx_context* nvfx = nvfx_context(pipe);
195 --nvfx->blitters_in_use;
196 assert(nvfx->blitters_in_use >= 0);
197
198 if(nvfx->query && !nvfx->blitters_in_use)
199 {
200 struct nouveau_channel* chan = nvfx->screen->base.channel;
201 struct nouveau_grobj *eng3d = nvfx->screen->eng3d;
202 BEGIN_RING(chan, eng3d, NV30_3D_QUERY_ENABLE, 1);
203 OUT_RING(chan, 1);
204 }
205 }
206
207 static unsigned
208 nvfx_region_clone(struct nv04_2d_context* ctx, struct nv04_region* rgn, unsigned w, unsigned h, boolean for_read)
209 {
210 unsigned begin = nv04_region_begin(rgn, w, h);
211 unsigned end = nv04_region_end(rgn, w, h);
212 unsigned size = end - begin;
213 struct nouveau_bo* bo = 0;
214 nouveau_bo_new(rgn->bo->device, NOUVEAU_BO_MAP | NOUVEAU_BO_GART, 256, size, &bo);
215
216 if(for_read || (size > ((w * h) << rgn->bpps)))
217 nv04_memcpy(ctx, bo, 0, rgn->bo, rgn->offset + begin, size);
218
219 rgn->bo = bo;
220 rgn->offset = -begin;
221 return begin;
222 }
223
224 static void
225 nvfx_resource_copy_region(struct pipe_context *pipe,
226 struct pipe_resource *dstr, unsigned dst_level,
227 unsigned dstx, unsigned dsty, unsigned dstz,
228 struct pipe_resource *srcr, unsigned src_level,
229 const struct pipe_box *src_box)
230 {
231 static int copy_threshold = -1;
232 struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d;
233 struct nv04_region dst, src;
234 int dst_to_gpu;
235 int src_on_gpu;
236 boolean small;
237 int ret;
238 unsigned w = src_box->width;
239 unsigned h = src_box->height;
240
241 if(!w || !h)
242 return;
243
244 /* Fallback for buffers. */
245 if (dstr->target == PIPE_BUFFER && srcr->target == PIPE_BUFFER) {
246 util_resource_copy_region(pipe, dstr, dst_level, dstx, dsty, dstz,
247 srcr, src_level, src_box);
248 return;
249 }
250
251 if(copy_threshold < 0)
252 copy_threshold = debug_get_num_option("NOUVEAU_COPY_THRESHOLD", 4);
253
254 dst_to_gpu = dstr->usage != PIPE_USAGE_DYNAMIC && dstr->usage != PIPE_USAGE_STAGING;
255 src_on_gpu = nvfx_resource_on_gpu(srcr);
256
257 nvfx_region_init_for_subresource(&dst, dstr, dst_level, dstx, dsty, dstz, TRUE);
258 nvfx_region_init_for_subresource(&src, srcr, src_level, src_box->x, src_box->y, src_box->z, FALSE);
259 w = util_format_get_stride(dstr->format, w) >> dst.bpps;
260 h = util_format_get_nblocksy(dstr->format, h);
261
262 small = (w * h <= copy_threshold);
263 if((!dst_to_gpu || !src_on_gpu) && small)
264 ret = -1; /* use the CPU */
265 else
266 ret = nv04_region_copy_2d(ctx, &dst, &src, w, h, dst_to_gpu, src_on_gpu);
267 if(!ret)
268 {}
269 else if(ret > 0
270 && dstr->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL)
271 && srcr->bind & PIPE_BIND_SAMPLER_VIEW)
272 {
273 /* this currently works because we hack the bind flags on resource creation to be
274 * the maximum set that the resource type actually supports
275 *
276 * TODO: perhaps support reinterpreting the formats
277 */
278 struct blitter_context* blitter = nvfx_get_blitter(pipe, 1);
279 util_blitter_copy_texture(blitter, dstr, dst_level, dstx, dsty, dstz, srcr, src_level, src_box, TRUE);
280 nvfx_put_blitter(pipe, blitter);
281 }
282 else
283 {
284 struct nv04_region dstt = dst;
285 struct nv04_region srct = src;
286 unsigned dstbegin = 0;
287
288 if(!small)
289 {
290 if(src_on_gpu)
291 nvfx_region_clone(ctx, &srct, w, h, TRUE);
292
293 if(dst_to_gpu)
294 dstbegin = nvfx_region_clone(ctx, &dstt, w, h, FALSE);
295 }
296
297 nv04_region_copy_cpu(&dstt, &srct, w, h);
298
299 if(srct.bo != src.bo)
300 nouveau_screen_bo_release(pipe->screen, srct.bo);
301
302 if(dstt.bo != dst.bo)
303 {
304 nv04_memcpy(ctx, dst.bo, dst.offset + dstbegin, dstt.bo, 0, dstt.bo->size);
305 nouveau_screen_bo_release(pipe->screen, dstt.bo);
306 }
307 }
308 }
309
310 static int
311 nvfx_surface_fill(struct pipe_context* pipe, struct pipe_surface *dsts,
312 unsigned dx, unsigned dy, unsigned w, unsigned h, unsigned value)
313 {
314 struct nv04_2d_context *ctx = nvfx_screen(pipe->screen)->eng2d;
315 struct nv04_region dst;
316 int ret;
317 /* Always try to use the GPU right now, if possible
318 * If the user wanted the surface data on the CPU, he would have cleared with memset (hopefully) */
319
320 // we don't care about interior pixel order since we set all them to the same value
321 nvfx_region_init_for_surface(&dst, (struct nvfx_surface*)dsts, dx, dy, TRUE);
322
323 w = util_format_get_stride(dsts->format, w) >> dst.bpps;
324 h = util_format_get_nblocksy(dsts->format, h);
325
326 ret = nv04_region_fill_2d(ctx, &dst, w, h, value);
327 if(ret > 0 && dsts->texture->bind & PIPE_BIND_RENDER_TARGET)
328 return 1;
329 else if(ret)
330 {
331 struct nv04_region dstt = dst;
332 unsigned dstbegin = 0;
333
334 if(nvfx_resource_on_gpu(dsts->texture))
335 dstbegin = nvfx_region_clone(ctx, &dstt, w, h, FALSE);
336
337 nv04_region_fill_cpu(&dstt, w, h, value);
338
339 if(dstt.bo != dst.bo)
340 {
341 nv04_memcpy(ctx, dst.bo, dst.offset + dstbegin, dstt.bo, 0, dstt.bo->size);
342 nouveau_screen_bo_release(pipe->screen, dstt.bo);
343 }
344 }
345
346 return 0;
347 }
348
349
350 void
351 nvfx_screen_surface_takedown(struct pipe_screen *pscreen)
352 {
353 nv04_2d_context_takedown(nvfx_screen(pscreen)->eng2d);
354 nvfx_screen(pscreen)->eng2d = 0;
355 }
356
357 int
358 nvfx_screen_surface_init(struct pipe_screen *pscreen)
359 {
360 struct nv04_2d_context* ctx = nv04_2d_context_init(nouveau_screen(pscreen)->channel);
361 if(!ctx)
362 return -1;
363 nvfx_screen(pscreen)->eng2d = ctx;
364 return 0;
365 }
366
367 static void
368 nvfx_clear_render_target(struct pipe_context *pipe,
369 struct pipe_surface *dst,
370 const union pipe_color_union *color,
371 unsigned dstx, unsigned dsty,
372 unsigned width, unsigned height)
373 {
374 union util_color uc;
375 util_pack_color(color->f, dst->format, &uc);
376
377 if(util_format_get_blocksizebits(dst->format) > 32
378 || nvfx_surface_fill(pipe, dst, dstx, dsty, width, height, uc.ui))
379 {
380 // TODO: probably should use hardware clear here instead if possible
381 struct blitter_context* blitter = nvfx_get_blitter(pipe, 0);
382 util_blitter_clear_render_target(blitter, dst, color, dstx, dsty, width, height);
383 nvfx_put_blitter(pipe, blitter);
384 }
385 }
386
387 static void
388 nvfx_clear_depth_stencil(struct pipe_context *pipe,
389 struct pipe_surface *dst,
390 unsigned clear_flags,
391 double depth,
392 unsigned stencil,
393 unsigned dstx, unsigned dsty,
394 unsigned width, unsigned height)
395 {
396 if(util_format_get_blocksizebits(dst->format) > 32
397 || nvfx_surface_fill(pipe, dst, dstx, dsty, width, height, util_pack_z_stencil(dst->format, depth, stencil)))
398 {
399 // TODO: probably should use hardware clear here instead if possible
400 struct blitter_context* blitter = nvfx_get_blitter(pipe, 0);
401 util_blitter_clear_depth_stencil(blitter, dst, clear_flags, depth, stencil, dstx, dsty, width, height);
402 nvfx_put_blitter(pipe, blitter);
403 }
404 }
405
406
407 void
408 nvfx_init_surface_functions(struct nvfx_context *nvfx)
409 {
410 nvfx->pipe.resource_copy_region = nvfx_resource_copy_region;
411 nvfx->pipe.clear_render_target = nvfx_clear_render_target;
412 nvfx->pipe.clear_depth_stencil = nvfx_clear_depth_stencil;
413 }