1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_linkage.h"
5 #include "util/u_debug.h"
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_dump.h"
10 #include "tgsi/tgsi_util.h"
12 #include "nvfx_context.h"
13 #include "nvfx_state.h"
14 #include "nvfx_resource.h"
16 /* TODO (at least...):
17 * 1. Indexed consts + ARL
18 * 3. NV_vp11, NV_vp2, NV_vp3 features
19 * - extra arith opcodes
27 #include "nv30_vertprog.h"
28 #include "nv40_vertprog.h"
30 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
33 struct nvfx_context
* nvfx
;
34 struct nvfx_vertex_program
*vp
;
36 struct nvfx_vertex_program_exec
*vpi
;
39 unsigned r_temps_discard
;
40 struct nvfx_reg r_result
[PIPE_MAX_SHADER_OUTPUTS
];
41 struct nvfx_reg
*r_address
;
42 struct nvfx_reg
*r_temp
;
50 static struct nvfx_reg
51 temp(struct nvfx_vpc
*vpc
)
53 int idx
= ffs(~vpc
->r_temps
) - 1;
56 NOUVEAU_ERR("out of temps!!\n");
58 return nvfx_reg(NVFXSR_TEMP
, 0);
61 vpc
->r_temps
|= (1 << idx
);
62 vpc
->r_temps_discard
|= (1 << idx
);
63 return nvfx_reg(NVFXSR_TEMP
, idx
);
67 release_temps(struct nvfx_vpc
*vpc
)
69 vpc
->r_temps
&= ~vpc
->r_temps_discard
;
70 vpc
->r_temps_discard
= 0;
73 static struct nvfx_reg
74 constant(struct nvfx_vpc
*vpc
, int pipe
, float x
, float y
, float z
, float w
)
76 struct nvfx_vertex_program
*vp
= vpc
->vp
;
77 struct nvfx_vertex_program_data
*vpd
;
81 for (idx
= 0; idx
< vp
->nr_consts
; idx
++) {
82 if (vp
->consts
[idx
].index
== pipe
)
83 return nvfx_reg(NVFXSR_CONST
, idx
);
87 idx
= vp
->nr_consts
++;
88 vp
->consts
= realloc(vp
->consts
, sizeof(*vpd
) * vp
->nr_consts
);
89 vpd
= &vp
->consts
[idx
];
96 return nvfx_reg(NVFXSR_CONST
, idx
);
99 #define arith(s,o,d,m,s0,s1,s2) \
100 nvfx_insn(0, (NVFX_VP_INST_SLOT_##s << 7) | NVFX_VP_INST_##s##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
103 emit_src(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
, uint32_t *hw
, int pos
, struct nvfx_src src
)
105 struct nvfx_vertex_program
*vp
= vpc
->vp
;
108 switch (src
.reg
.type
) {
110 sr
|= (NVFX_VP(SRC_REG_TYPE_TEMP
) << NVFX_VP(SRC_REG_TYPE_SHIFT
));
111 sr
|= (src
.reg
.index
<< NVFX_VP(SRC_TEMP_SRC_SHIFT
));
114 sr
|= (NVFX_VP(SRC_REG_TYPE_INPUT
) <<
115 NVFX_VP(SRC_REG_TYPE_SHIFT
));
116 vp
->ir
|= (1 << src
.reg
.index
);
117 hw
[1] |= (src
.reg
.index
<< NVFX_VP(INST_INPUT_SRC_SHIFT
));
120 sr
|= (NVFX_VP(SRC_REG_TYPE_CONST
) <<
121 NVFX_VP(SRC_REG_TYPE_SHIFT
));
122 assert(vpc
->vpi
->const_index
== -1 ||
123 vpc
->vpi
->const_index
== src
.reg
.index
);
124 vpc
->vpi
->const_index
= src
.reg
.index
;
127 sr
|= (NVFX_VP(SRC_REG_TYPE_INPUT
) <<
128 NVFX_VP(SRC_REG_TYPE_SHIFT
));
135 sr
|= NVFX_VP(SRC_NEGATE
);
138 hw
[0] |= (1 << (21 + pos
));
140 sr
|= ((src
.swz
[0] << NVFX_VP(SRC_SWZ_X_SHIFT
)) |
141 (src
.swz
[1] << NVFX_VP(SRC_SWZ_Y_SHIFT
)) |
142 (src
.swz
[2] << NVFX_VP(SRC_SWZ_Z_SHIFT
)) |
143 (src
.swz
[3] << NVFX_VP(SRC_SWZ_W_SHIFT
)));
147 hw
[1] |= ((sr
& NVFX_VP(SRC0_HIGH_MASK
)) >>
148 NVFX_VP(SRC0_HIGH_SHIFT
)) << NVFX_VP(INST_SRC0H_SHIFT
);
149 hw
[2] |= (sr
& NVFX_VP(SRC0_LOW_MASK
)) <<
150 NVFX_VP(INST_SRC0L_SHIFT
);
153 hw
[2] |= sr
<< NVFX_VP(INST_SRC1_SHIFT
);
156 hw
[2] |= ((sr
& NVFX_VP(SRC2_HIGH_MASK
)) >>
157 NVFX_VP(SRC2_HIGH_SHIFT
)) << NVFX_VP(INST_SRC2H_SHIFT
);
158 hw
[3] |= (sr
& NVFX_VP(SRC2_LOW_MASK
)) <<
159 NVFX_VP(INST_SRC2L_SHIFT
);
167 emit_dst(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
, uint32_t *hw
, int slot
, struct nvfx_reg dst
)
169 struct nvfx_vertex_program
*vp
= vpc
->vp
;
174 hw
[0] |= (dst
.index
<< NV30_VP_INST_DEST_TEMP_ID_SHIFT
);
176 hw
[3] |= NV40_VP_INST_DEST_MASK
;
178 hw
[0] |= (dst
.index
<< NV40_VP_INST_VEC_DEST_TEMP_SHIFT
);
180 hw
[3] |= (dst
.index
<< NV40_VP_INST_SCA_DEST_TEMP_SHIFT
);
184 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
186 case NVFX_VP_INST_DEST_CLIP(0):
188 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0
;
189 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
191 case NVFX_VP_INST_DEST_CLIP(1):
193 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1
;
194 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
196 case NVFX_VP_INST_DEST_CLIP(2):
198 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2
;
199 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
201 case NVFX_VP_INST_DEST_CLIP(3):
203 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3
;
204 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
206 case NVFX_VP_INST_DEST_CLIP(4):
208 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4
;
209 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
211 case NVFX_VP_INST_DEST_CLIP(5):
213 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5
;
214 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
219 case NV30_VP_INST_DEST_COL0
: vp
->or |= (1 << 0); break;
220 case NV30_VP_INST_DEST_COL1
: vp
->or |= (1 << 1); break;
221 case NV30_VP_INST_DEST_BFC0
: vp
->or |= (1 << 2); break;
222 case NV30_VP_INST_DEST_BFC1
: vp
->or |= (1 << 3); break;
223 case NV30_VP_INST_DEST_FOGC
: vp
->or |= (1 << 4); break;
224 case NV30_VP_INST_DEST_PSZ
: vp
->or |= (1 << 5); break;
225 case NV30_VP_INST_DEST_TC(0): vp
->or |= (1 << 14); break;
226 case NV30_VP_INST_DEST_TC(1): vp
->or |= (1 << 15); break;
227 case NV30_VP_INST_DEST_TC(2): vp
->or |= (1 << 16); break;
228 case NV30_VP_INST_DEST_TC(3): vp
->or |= (1 << 17); break;
229 case NV30_VP_INST_DEST_TC(4): vp
->or |= (1 << 18); break;
230 case NV30_VP_INST_DEST_TC(5): vp
->or |= (1 << 19); break;
231 case NV30_VP_INST_DEST_TC(6): vp
->or |= (1 << 20); break;
232 case NV30_VP_INST_DEST_TC(7): vp
->or |= (1 << 21); break;
236 case NV40_VP_INST_DEST_COL0
: vp
->or |= (1 << 0); break;
237 case NV40_VP_INST_DEST_COL1
: vp
->or |= (1 << 1); break;
238 case NV40_VP_INST_DEST_BFC0
: vp
->or |= (1 << 2); break;
239 case NV40_VP_INST_DEST_BFC1
: vp
->or |= (1 << 3); break;
240 case NV40_VP_INST_DEST_FOGC
: vp
->or |= (1 << 4); break;
241 case NV40_VP_INST_DEST_PSZ
: vp
->or |= (1 << 5); break;
242 case NV40_VP_INST_DEST_TC(0): vp
->or |= (1 << 14); break;
243 case NV40_VP_INST_DEST_TC(1): vp
->or |= (1 << 15); break;
244 case NV40_VP_INST_DEST_TC(2): vp
->or |= (1 << 16); break;
245 case NV40_VP_INST_DEST_TC(3): vp
->or |= (1 << 17); break;
246 case NV40_VP_INST_DEST_TC(4): vp
->or |= (1 << 18); break;
247 case NV40_VP_INST_DEST_TC(5): vp
->or |= (1 << 19); break;
248 case NV40_VP_INST_DEST_TC(6): vp
->or |= (1 << 20); break;
249 case NV40_VP_INST_DEST_TC(7): vp
->or |= (1 << 21); break;
256 hw
[3] |= (dst
.index
<< NV30_VP_INST_DEST_SHIFT
);
257 hw
[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK
| (1<<20);
259 /*XXX: no way this is entirely correct, someone needs to
260 * figure out what exactly it is.
264 hw
[3] |= (dst
.index
<< NV40_VP_INST_DEST_SHIFT
);
266 hw
[0] |= NV40_VP_INST_VEC_RESULT
;
267 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
| (1<<20);
269 hw
[3] |= NV40_VP_INST_SCA_RESULT
;
270 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
280 nvfx_vp_emit(struct nvfx_vpc
*vpc
, struct nvfx_insn insn
)
282 struct nvfx_context
* nvfx
= vpc
->nvfx
;
283 struct nvfx_vertex_program
*vp
= vpc
->vp
;
284 unsigned slot
= insn
.op
>> 7;
285 unsigned op
= insn
.op
& 0x7f;
288 vp
->insns
= realloc(vp
->insns
, ++vp
->nr_insns
* sizeof(*vpc
->vpi
));
289 vpc
->vpi
= &vp
->insns
[vp
->nr_insns
- 1];
290 memset(vpc
->vpi
, 0, sizeof(*vpc
->vpi
));
291 vpc
->vpi
->const_index
= -1;
295 hw
[0] |= (NVFX_COND_TR
<< NVFX_VP(INST_COND_SHIFT
));
296 hw
[0] |= ((0 << NVFX_VP(INST_COND_SWZ_X_SHIFT
)) |
297 (1 << NVFX_VP(INST_COND_SWZ_Y_SHIFT
)) |
298 (2 << NVFX_VP(INST_COND_SWZ_Z_SHIFT
)) |
299 (3 << NVFX_VP(INST_COND_SWZ_W_SHIFT
)));
303 hw
[1] |= (op
<< NV30_VP_INST_VEC_OPCODE_SHIFT
);
306 hw
[0] |= ((op
>> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT
);
307 hw
[1] |= ((op
& 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT
);
309 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
310 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
312 if (insn
.dst
.type
== NVFXSR_OUTPUT
) {
314 hw
[3] |= (insn
.mask
<< NV30_VP_INST_SDEST_WRITEMASK_SHIFT
);
316 hw
[3] |= (insn
.mask
<< NV30_VP_INST_VDEST_WRITEMASK_SHIFT
);
319 hw
[3] |= (insn
.mask
<< NV30_VP_INST_STEMP_WRITEMASK_SHIFT
);
321 hw
[3] |= (insn
.mask
<< NV30_VP_INST_VTEMP_WRITEMASK_SHIFT
);
325 hw
[1] |= (op
<< NV40_VP_INST_VEC_OPCODE_SHIFT
);
326 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
327 hw
[3] |= (insn
.mask
<< NV40_VP_INST_VEC_WRITEMASK_SHIFT
);
329 hw
[1] |= (op
<< NV40_VP_INST_SCA_OPCODE_SHIFT
);
330 hw
[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK
| (1 << 20));
331 hw
[3] |= (insn
.mask
<< NV40_VP_INST_SCA_WRITEMASK_SHIFT
);
335 emit_dst(nvfx
, vpc
, hw
, slot
, insn
.dst
);
336 emit_src(nvfx
, vpc
, hw
, 0, insn
.src
[0]);
337 emit_src(nvfx
, vpc
, hw
, 1, insn
.src
[1]);
338 emit_src(nvfx
, vpc
, hw
, 2, insn
.src
[2]);
341 static inline struct nvfx_src
342 tgsi_src(struct nvfx_vpc
*vpc
, const struct tgsi_full_src_register
*fsrc
) {
345 switch (fsrc
->Register
.File
) {
346 case TGSI_FILE_INPUT
:
347 src
.reg
= nvfx_reg(NVFXSR_INPUT
, fsrc
->Register
.Index
);
349 case TGSI_FILE_CONSTANT
:
350 src
.reg
= constant(vpc
, fsrc
->Register
.Index
, 0, 0, 0, 0);
352 case TGSI_FILE_IMMEDIATE
:
353 src
.reg
= vpc
->imm
[fsrc
->Register
.Index
];
355 case TGSI_FILE_TEMPORARY
:
356 src
.reg
= vpc
->r_temp
[fsrc
->Register
.Index
];
359 NOUVEAU_ERR("bad src file\n");
363 src
.abs
= fsrc
->Register
.Absolute
;
364 src
.negate
= fsrc
->Register
.Negate
;
365 src
.swz
[0] = fsrc
->Register
.SwizzleX
;
366 src
.swz
[1] = fsrc
->Register
.SwizzleY
;
367 src
.swz
[2] = fsrc
->Register
.SwizzleZ
;
368 src
.swz
[3] = fsrc
->Register
.SwizzleW
;
372 static INLINE
struct nvfx_reg
373 tgsi_dst(struct nvfx_vpc
*vpc
, const struct tgsi_full_dst_register
*fdst
) {
376 switch (fdst
->Register
.File
) {
377 case TGSI_FILE_OUTPUT
:
378 dst
= vpc
->r_result
[fdst
->Register
.Index
];
380 case TGSI_FILE_TEMPORARY
:
381 dst
= vpc
->r_temp
[fdst
->Register
.Index
];
383 case TGSI_FILE_ADDRESS
:
384 dst
= vpc
->r_address
[fdst
->Register
.Index
];
387 NOUVEAU_ERR("bad dst file %i\n", fdst
->Register
.File
);
399 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= NVFX_VP_MASK_X
;
400 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= NVFX_VP_MASK_Y
;
401 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= NVFX_VP_MASK_Z
;
402 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= NVFX_VP_MASK_W
;
407 nvfx_vertprog_parse_instruction(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
,
408 const struct tgsi_full_instruction
*finst
)
410 struct nvfx_src src
[3], tmp
;
412 struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
414 int ai
= -1, ci
= -1, ii
= -1;
417 if (finst
->Instruction
.Opcode
== TGSI_OPCODE_END
)
420 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
421 const struct tgsi_full_src_register
*fsrc
;
423 fsrc
= &finst
->Src
[i
];
424 if (fsrc
->Register
.File
== TGSI_FILE_TEMPORARY
) {
425 src
[i
] = tgsi_src(vpc
, fsrc
);
429 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
430 const struct tgsi_full_src_register
*fsrc
;
432 fsrc
= &finst
->Src
[i
];
434 switch (fsrc
->Register
.File
) {
435 case TGSI_FILE_INPUT
:
436 if (ai
== -1 || ai
== fsrc
->Register
.Index
) {
437 ai
= fsrc
->Register
.Index
;
438 src
[i
] = tgsi_src(vpc
, fsrc
);
440 src
[i
] = nvfx_src(temp(vpc
));
441 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
, tgsi_src(vpc
, fsrc
), none
, none
));
444 case TGSI_FILE_CONSTANT
:
445 if ((ci
== -1 && ii
== -1) ||
446 ci
== fsrc
->Register
.Index
) {
447 ci
= fsrc
->Register
.Index
;
448 src
[i
] = tgsi_src(vpc
, fsrc
);
450 src
[i
] = nvfx_src(temp(vpc
));
451 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
, tgsi_src(vpc
, fsrc
), none
, none
));
454 case TGSI_FILE_IMMEDIATE
:
455 if ((ci
== -1 && ii
== -1) ||
456 ii
== fsrc
->Register
.Index
) {
457 ii
= fsrc
->Register
.Index
;
458 src
[i
] = tgsi_src(vpc
, fsrc
);
460 src
[i
] = nvfx_src(temp(vpc
));
461 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
, tgsi_src(vpc
, fsrc
), none
, none
));
464 case TGSI_FILE_TEMPORARY
:
468 NOUVEAU_ERR("bad src file\n");
473 dst
= tgsi_dst(vpc
, &finst
->Dst
[0]);
474 mask
= tgsi_mask(finst
->Dst
[0].Register
.WriteMask
);
476 switch (finst
->Instruction
.Opcode
) {
477 case TGSI_OPCODE_ABS
:
478 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, dst
, mask
, abs(src
[0]), none
, none
));
480 case TGSI_OPCODE_ADD
:
481 nvfx_vp_emit(vpc
, arith(VEC
, ADD
, dst
, mask
, src
[0], none
, src
[1]));
483 case TGSI_OPCODE_ARL
:
484 nvfx_vp_emit(vpc
, arith(VEC
, ARL
, dst
, mask
, src
[0], none
, none
));
486 case TGSI_OPCODE_COS
:
487 nvfx_vp_emit(vpc
, arith(SCA
, COS
, dst
, mask
, none
, none
, src
[0]));
489 case TGSI_OPCODE_DP3
:
490 nvfx_vp_emit(vpc
, arith(VEC
, DP3
, dst
, mask
, src
[0], src
[1], none
));
492 case TGSI_OPCODE_DP4
:
493 nvfx_vp_emit(vpc
, arith(VEC
, DP4
, dst
, mask
, src
[0], src
[1], none
));
495 case TGSI_OPCODE_DPH
:
496 nvfx_vp_emit(vpc
, arith(VEC
, DPH
, dst
, mask
, src
[0], src
[1], none
));
498 case TGSI_OPCODE_DST
:
499 nvfx_vp_emit(vpc
, arith(VEC
, DST
, dst
, mask
, src
[0], src
[1], none
));
501 case TGSI_OPCODE_EX2
:
502 nvfx_vp_emit(vpc
, arith(SCA
, EX2
, dst
, mask
, none
, none
, src
[0]));
504 case TGSI_OPCODE_EXP
:
505 nvfx_vp_emit(vpc
, arith(SCA
, EXP
, dst
, mask
, none
, none
, src
[0]));
507 case TGSI_OPCODE_FLR
:
508 nvfx_vp_emit(vpc
, arith(VEC
, FLR
, dst
, mask
, src
[0], none
, none
));
510 case TGSI_OPCODE_FRC
:
511 nvfx_vp_emit(vpc
, arith(VEC
, FRC
, dst
, mask
, src
[0], none
, none
));
513 case TGSI_OPCODE_LG2
:
514 nvfx_vp_emit(vpc
, arith(SCA
, LG2
, dst
, mask
, none
, none
, src
[0]));
516 case TGSI_OPCODE_LIT
:
517 nvfx_vp_emit(vpc
, arith(SCA
, LIT
, dst
, mask
, none
, none
, src
[0]));
519 case TGSI_OPCODE_LOG
:
520 nvfx_vp_emit(vpc
, arith(SCA
, LOG
, dst
, mask
, none
, none
, src
[0]));
522 case TGSI_OPCODE_LRP
:
523 tmp
= nvfx_src(temp(vpc
));
524 nvfx_vp_emit(vpc
, arith(VEC
, MAD
, tmp
.reg
, mask
, neg(src
[0]), src
[2], src
[2]));
525 nvfx_vp_emit(vpc
, arith(VEC
, MAD
, dst
, mask
, src
[0], src
[1], tmp
));
527 case TGSI_OPCODE_MAD
:
528 nvfx_vp_emit(vpc
, arith(VEC
, MAD
, dst
, mask
, src
[0], src
[1], src
[2]));
530 case TGSI_OPCODE_MAX
:
531 nvfx_vp_emit(vpc
, arith(VEC
, MAX
, dst
, mask
, src
[0], src
[1], none
));
533 case TGSI_OPCODE_MIN
:
534 nvfx_vp_emit(vpc
, arith(VEC
, MIN
, dst
, mask
, src
[0], src
[1], none
));
536 case TGSI_OPCODE_MOV
:
537 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, dst
, mask
, src
[0], none
, none
));
539 case TGSI_OPCODE_MUL
:
540 nvfx_vp_emit(vpc
, arith(VEC
, MUL
, dst
, mask
, src
[0], src
[1], none
));
542 case TGSI_OPCODE_POW
:
543 tmp
= nvfx_src(temp(vpc
));
544 nvfx_vp_emit(vpc
, arith(SCA
, LG2
, tmp
.reg
, NVFX_VP_MASK_X
, none
, none
, swz(src
[0], X
, X
, X
, X
)));
545 nvfx_vp_emit(vpc
, arith(VEC
, MUL
, tmp
.reg
, NVFX_VP_MASK_X
, swz(tmp
, X
, X
, X
, X
), swz(src
[1], X
, X
, X
, X
), none
));
546 nvfx_vp_emit(vpc
, arith(SCA
, EX2
, dst
, mask
, none
, none
, swz(tmp
, X
, X
, X
, X
)));
548 case TGSI_OPCODE_RCP
:
549 nvfx_vp_emit(vpc
, arith(SCA
, RCP
, dst
, mask
, none
, none
, src
[0]));
551 case TGSI_OPCODE_RET
:
553 case TGSI_OPCODE_RSQ
:
554 nvfx_vp_emit(vpc
, arith(SCA
, RSQ
, dst
, mask
, none
, none
, abs(src
[0])));
556 case TGSI_OPCODE_SEQ
:
557 nvfx_vp_emit(vpc
, arith(VEC
, SEQ
, dst
, mask
, src
[0], src
[1], none
));
559 case TGSI_OPCODE_SFL
:
560 nvfx_vp_emit(vpc
, arith(VEC
, SFL
, dst
, mask
, src
[0], src
[1], none
));
562 case TGSI_OPCODE_SGE
:
563 nvfx_vp_emit(vpc
, arith(VEC
, SGE
, dst
, mask
, src
[0], src
[1], none
));
565 case TGSI_OPCODE_SGT
:
566 nvfx_vp_emit(vpc
, arith(VEC
, SGT
, dst
, mask
, src
[0], src
[1], none
));
568 case TGSI_OPCODE_SIN
:
569 nvfx_vp_emit(vpc
, arith(SCA
, SIN
, dst
, mask
, none
, none
, src
[0]));
571 case TGSI_OPCODE_SLE
:
572 nvfx_vp_emit(vpc
, arith(VEC
, SLE
, dst
, mask
, src
[0], src
[1], none
));
574 case TGSI_OPCODE_SLT
:
575 nvfx_vp_emit(vpc
, arith(VEC
, SLT
, dst
, mask
, src
[0], src
[1], none
));
577 case TGSI_OPCODE_SNE
:
578 nvfx_vp_emit(vpc
, arith(VEC
, SNE
, dst
, mask
, src
[0], src
[1], none
));
580 case TGSI_OPCODE_SSG
:
581 nvfx_vp_emit(vpc
, arith(VEC
, SSG
, dst
, mask
, src
[0], src
[1], none
));
583 case TGSI_OPCODE_STR
:
584 nvfx_vp_emit(vpc
, arith(VEC
, STR
, dst
, mask
, src
[0], src
[1], none
));
586 case TGSI_OPCODE_SUB
:
587 nvfx_vp_emit(vpc
, arith(VEC
, ADD
, dst
, mask
, src
[0], none
, neg(src
[1])));
589 case TGSI_OPCODE_XPD
:
590 tmp
= nvfx_src(temp(vpc
));
591 nvfx_vp_emit(vpc
, arith(VEC
, MUL
, tmp
.reg
, mask
, swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
));
592 nvfx_vp_emit(vpc
, arith(VEC
, MAD
, dst
, (mask
& ~NVFX_VP_MASK_W
), swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
), neg(tmp
)));
595 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
604 nvfx_vertprog_parse_decl_output(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
,
605 const struct tgsi_full_declaration
*fdec
)
607 unsigned idx
= fdec
->Range
.First
;
610 switch (fdec
->Semantic
.Name
) {
611 case TGSI_SEMANTIC_POSITION
:
612 hw
= NVFX_VP(INST_DEST_POS
);
615 case TGSI_SEMANTIC_COLOR
:
616 if (fdec
->Semantic
.Index
== 0) {
617 hw
= NVFX_VP(INST_DEST_COL0
);
619 if (fdec
->Semantic
.Index
== 1) {
620 hw
= NVFX_VP(INST_DEST_COL1
);
622 NOUVEAU_ERR("bad colour semantic index\n");
626 case TGSI_SEMANTIC_BCOLOR
:
627 if (fdec
->Semantic
.Index
== 0) {
628 hw
= NVFX_VP(INST_DEST_BFC0
);
630 if (fdec
->Semantic
.Index
== 1) {
631 hw
= NVFX_VP(INST_DEST_BFC1
);
633 NOUVEAU_ERR("bad bcolour semantic index\n");
637 case TGSI_SEMANTIC_FOG
:
638 hw
= NVFX_VP(INST_DEST_FOGC
);
640 case TGSI_SEMANTIC_PSIZE
:
641 hw
= NVFX_VP(INST_DEST_PSZ
);
643 case TGSI_SEMANTIC_GENERIC
:
644 hw
= (vpc
->vp
->generic_to_fp_input
[fdec
->Semantic
.Index
] & 0xf)
645 + NVFX_VP(INST_DEST_TC(0)) - NVFX_FP_OP_INPUT_SRC_TC(0);
647 case TGSI_SEMANTIC_EDGEFLAG
:
648 /* not really an error just a fallback */
649 NOUVEAU_ERR("cannot handle edgeflag output\n");
652 NOUVEAU_ERR("bad output semantic\n");
656 vpc
->r_result
[idx
] = nvfx_reg(NVFXSR_OUTPUT
, hw
);
661 nvfx_vertprog_prepare(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
)
663 struct tgsi_parse_context p
;
664 int high_temp
= -1, high_addr
= -1, nr_imm
= 0, i
;
665 struct util_semantic_set set
;
666 unsigned char sem_layout
[8];
667 unsigned sem_layout_size
;
668 unsigned num_outputs
;
670 num_outputs
= util_semantic_set_from_program_file(&set
, vpc
->vp
->pipe
.tokens
, TGSI_FILE_OUTPUT
);
672 if(num_outputs
> 8) {
673 NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs
);
676 util_semantic_layout_from_set(sem_layout
, &set
, 8, 8);
678 /* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */
679 memset(vpc
->vp
->generic_to_fp_input
, 0x0f, sizeof(vpc
->vp
->generic_to_fp_input
));
680 vpc
->vp
->texcoord_ouput_mask
= 0;
681 for(int i
= 0; i
< 8; ++i
) {
682 if(sem_layout
[i
] == 0xff)
684 vpc
->vp
->texcoord_ouput_mask
|= (1 << i
);
685 //printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i);
686 vpc
->vp
->generic_to_fp_input
[sem_layout
[i
]] = 0xf0 | (NVFX_FP_OP_INPUT_SRC_TC(0) + i
);
689 tgsi_parse_init(&p
, vpc
->vp
->pipe
.tokens
);
690 while (!tgsi_parse_end_of_tokens(&p
)) {
691 const union tgsi_full_token
*tok
= &p
.FullToken
;
693 tgsi_parse_token(&p
);
694 switch(tok
->Token
.Type
) {
695 case TGSI_TOKEN_TYPE_IMMEDIATE
:
698 case TGSI_TOKEN_TYPE_DECLARATION
:
700 const struct tgsi_full_declaration
*fdec
;
702 fdec
= &p
.FullToken
.FullDeclaration
;
703 switch (fdec
->Declaration
.File
) {
704 case TGSI_FILE_TEMPORARY
:
705 if (fdec
->Range
.Last
> high_temp
) {
710 #if 0 /* this would be nice.. except gallium doesn't track it */
711 case TGSI_FILE_ADDRESS
:
712 if (fdec
->Range
.Last
> high_addr
) {
718 case TGSI_FILE_OUTPUT
:
719 if (!nvfx_vertprog_parse_decl_output(nvfx
, vpc
, fdec
))
727 #if 1 /* yay, parse instructions looking for address regs instead */
728 case TGSI_TOKEN_TYPE_INSTRUCTION
:
730 const struct tgsi_full_instruction
*finst
;
731 const struct tgsi_full_dst_register
*fdst
;
733 finst
= &p
.FullToken
.FullInstruction
;
734 fdst
= &finst
->Dst
[0];
736 if (fdst
->Register
.File
== TGSI_FILE_ADDRESS
) {
737 if (fdst
->Register
.Index
> high_addr
)
738 high_addr
= fdst
->Register
.Index
;
751 vpc
->imm
= CALLOC(nr_imm
, sizeof(struct nvfx_reg
));
756 vpc
->r_temp
= CALLOC(high_temp
, sizeof(struct nvfx_reg
));
757 for (i
= 0; i
< high_temp
; i
++)
758 vpc
->r_temp
[i
] = temp(vpc
);
762 vpc
->r_address
= CALLOC(high_addr
, sizeof(struct nvfx_reg
));
763 for (i
= 0; i
< high_addr
; i
++)
764 vpc
->r_address
[i
] = temp(vpc
);
767 vpc
->r_temps_discard
= 0;
771 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp
, "NVFX_DUMP_VP", FALSE
)
774 nvfx_vertprog_translate(struct nvfx_context
*nvfx
,
775 struct nvfx_vertex_program
*vp
)
777 struct tgsi_parse_context parse
;
778 struct nvfx_vpc
*vpc
= NULL
;
779 struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
782 vpc
= CALLOC(1, sizeof(struct nvfx_vpc
));
788 if (!nvfx_vertprog_prepare(nvfx
, vpc
)) {
793 /* Redirect post-transform vertex position to a temp if user clip
794 * planes are enabled. We need to append code to the vtxprog
795 * to handle clip planes later.
798 vpc
->r_result
[vpc
->hpos_idx
] = temp(vpc
);
799 vpc
->r_temps_discard
= 0;
802 tgsi_parse_init(&parse
, vp
->pipe
.tokens
);
804 while (!tgsi_parse_end_of_tokens(&parse
)) {
805 tgsi_parse_token(&parse
);
807 switch (parse
.FullToken
.Token
.Type
) {
808 case TGSI_TOKEN_TYPE_IMMEDIATE
:
810 const struct tgsi_full_immediate
*imm
;
812 imm
= &parse
.FullToken
.FullImmediate
;
813 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
814 assert(imm
->Immediate
.NrTokens
== 4 + 1);
815 vpc
->imm
[vpc
->nr_imm
++] =
823 case TGSI_TOKEN_TYPE_INSTRUCTION
:
825 const struct tgsi_full_instruction
*finst
;
826 finst
= &parse
.FullToken
.FullInstruction
;
827 if (!nvfx_vertprog_parse_instruction(nvfx
, vpc
, finst
))
836 /* Write out HPOS if it was redirected to a temp earlier */
837 if (vpc
->r_result
[vpc
->hpos_idx
].type
!= NVFXSR_OUTPUT
) {
838 struct nvfx_reg hpos
= nvfx_reg(NVFXSR_OUTPUT
,
839 NVFX_VP(INST_DEST_POS
));
840 struct nvfx_src htmp
= nvfx_src(vpc
->r_result
[vpc
->hpos_idx
]);
842 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, hpos
, NVFX_VP_MASK_ALL
, htmp
, none
, none
));
845 /* Insert code to handle user clip planes */
846 for (i
= 0; i
< vp
->ucp
.nr
; i
++) {
847 struct nvfx_reg cdst
= nvfx_reg(NVFXSR_OUTPUT
,
848 NVFX_VP_INST_DEST_CLIP(i
));
849 struct nvfx_src ceqn
= nvfx_src(constant(vpc
, -1,
850 nvfx
->clip
.ucp
[i
][0],
851 nvfx
->clip
.ucp
[i
][1],
852 nvfx
->clip
.ucp
[i
][2],
853 nvfx
->clip
.ucp
[i
][3]));
854 struct nvfx_src htmp
= nvfx_src(vpc
->r_result
[vpc
->hpos_idx
]);
858 case 0: case 3: mask
= NVFX_VP_MASK_Y
; break;
859 case 1: case 4: mask
= NVFX_VP_MASK_Z
; break;
860 case 2: case 5: mask
= NVFX_VP_MASK_W
; break;
862 NOUVEAU_ERR("invalid clip dist #%d\n", i
);
866 nvfx_vp_emit(vpc
, arith(VEC
, DP4
, cdst
, mask
, htmp
, ceqn
, none
));
869 vp
->insns
[vp
->nr_insns
- 1].data
[3] |= NVFX_VP_INST_LAST
;
871 if(debug_get_option_nvfx_dump_vp())
874 tgsi_dump(vp
->pipe
.tokens
, 0);
876 debug_printf("\n%s vertex program:\n", nvfx
->is_nv4x
? "nv4x" : "nv3x");
877 for (i
= 0; i
< vp
->nr_insns
; i
++)
878 debug_printf("%3u: %08x %08x %08x %08x\n", i
, vp
->insns
[i
].data
[0], vp
->insns
[i
].data
[1], vp
->insns
[i
].data
[2], vp
->insns
[i
].data
[3]);
882 vp
->translated
= TRUE
;
884 tgsi_parse_free(&parse
);
888 FREE(vpc
->r_address
);
895 nvfx_vertprog_validate(struct nvfx_context
*nvfx
)
897 struct pipe_context
*pipe
= &nvfx
->pipe
;
898 struct nvfx_screen
*screen
= nvfx
->screen
;
899 struct nouveau_channel
*chan
= screen
->base
.channel
;
900 struct nouveau_grobj
*eng3d
= screen
->eng3d
;
901 struct nvfx_vertex_program
*vp
;
902 struct pipe_resource
*constbuf
;
903 boolean upload_code
= FALSE
, upload_data
= FALSE
;
906 if (nvfx
->render_mode
== HW
) {
908 constbuf
= nvfx
->constbuf
[PIPE_SHADER_VERTEX
];
910 // TODO: ouch! can't we just use constant slots for these?!
911 if ((nvfx
->dirty
& NVFX_NEW_UCP
) ||
912 memcmp(&nvfx
->clip
, &vp
->ucp
, sizeof(vp
->ucp
))) {
913 nvfx_vertprog_destroy(nvfx
, vp
);
914 memcpy(&vp
->ucp
, &nvfx
->clip
, sizeof(vp
->ucp
));
917 vp
= nvfx
->swtnl
.vertprog
;
921 /* Translate TGSI shader into hw bytecode */
924 nvfx
->fallback_swtnl
&= ~NVFX_NEW_VERTPROG
;
925 nvfx_vertprog_translate(nvfx
, vp
);
926 if (!vp
->translated
) {
927 nvfx
->fallback_swtnl
|= NVFX_NEW_VERTPROG
;
932 /* Allocate hw vtxprog exec slots */
934 struct nouveau_resource
*heap
= nvfx
->screen
->vp_exec_heap
;
935 uint vplen
= vp
->nr_insns
;
937 if (nouveau_resource_alloc(heap
, vplen
, vp
, &vp
->exec
)) {
938 while (heap
->next
&& heap
->size
< vplen
) {
939 struct nvfx_vertex_program
*evict
;
941 evict
= heap
->next
->priv
;
942 nouveau_resource_free(&evict
->exec
);
945 if (nouveau_resource_alloc(heap
, vplen
, vp
, &vp
->exec
))
952 /* Allocate hw vtxprog const slots */
953 if (vp
->nr_consts
&& !vp
->data
) {
954 struct nouveau_resource
*heap
= nvfx
->screen
->vp_data_heap
;
956 if (nouveau_resource_alloc(heap
, vp
->nr_consts
, vp
, &vp
->data
)) {
957 while (heap
->next
&& heap
->size
< vp
->nr_consts
) {
958 struct nvfx_vertex_program
*evict
;
960 evict
= heap
->next
->priv
;
961 nouveau_resource_free(&evict
->data
);
964 if (nouveau_resource_alloc(heap
, vp
->nr_consts
, vp
, &vp
->data
))
968 /*XXX: handle this some day */
969 assert(vp
->data
->start
>= vp
->data_start_min
);
972 if (vp
->data_start
!= vp
->data
->start
)
976 /* If exec or data segments moved we need to patch the program to
977 * fixup offsets and register IDs.
979 if (vp
->exec_start
!= vp
->exec
->start
) {
980 for (i
= 0; i
< vp
->nr_insns
; i
++) {
981 struct nvfx_vertex_program_exec
*vpi
= &vp
->insns
[i
];
983 if (vpi
->has_branch_offset
) {
988 vp
->exec_start
= vp
->exec
->start
;
991 if (vp
->nr_consts
&& vp
->data_start
!= vp
->data
->start
) {
992 for (i
= 0; i
< vp
->nr_insns
; i
++) {
993 struct nvfx_vertex_program_exec
*vpi
= &vp
->insns
[i
];
995 if (vpi
->const_index
>= 0) {
996 vpi
->data
[1] &= ~NVFX_VP(INST_CONST_SRC_MASK
);
998 (vpi
->const_index
+ vp
->data
->start
) <<
999 NVFX_VP(INST_CONST_SRC_SHIFT
);
1004 vp
->data_start
= vp
->data
->start
;
1007 /* Update + Upload constant values */
1008 if (vp
->nr_consts
) {
1012 map
= nvfx_buffer(constbuf
)->data
;
1014 for (i
= 0; i
< vp
->nr_consts
; i
++) {
1015 struct nvfx_vertex_program_data
*vpd
= &vp
->consts
[i
];
1017 if (vpd
->index
>= 0) {
1019 !memcmp(vpd
->value
, &map
[vpd
->index
* 4],
1022 memcpy(vpd
->value
, &map
[vpd
->index
* 4],
1026 BEGIN_RING(chan
, eng3d
, NV34TCL_VP_UPLOAD_CONST_ID
, 5);
1027 OUT_RING (chan
, i
+ vp
->data
->start
);
1028 OUT_RINGp (chan
, (uint32_t *)vpd
->value
, 4);
1032 /* Upload vtxprog */
1034 BEGIN_RING(chan
, eng3d
, NV34TCL_VP_UPLOAD_FROM_ID
, 1);
1035 OUT_RING (chan
, vp
->exec
->start
);
1036 for (i
= 0; i
< vp
->nr_insns
; i
++) {
1037 BEGIN_RING(chan
, eng3d
, NV34TCL_VP_UPLOAD_INST(0), 4);
1038 OUT_RINGp (chan
, vp
->insns
[i
].data
, 4);
1042 if(nvfx
->dirty
& (NVFX_NEW_VERTPROG
| NVFX_NEW_UCP
))
1045 OUT_RING(chan
, RING_3D(NV34TCL_VP_START_FROM_ID
, 1));
1046 OUT_RING(chan
, vp
->exec
->start
);
1048 OUT_RING(chan
, RING_3D(NV40TCL_VP_ATTRIB_EN
, 2));
1049 OUT_RING(chan
, vp
->ir
);
1050 OUT_RING(chan
, vp
->or);
1052 OUT_RING(chan
, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE
, 1));
1053 OUT_RING(chan
, vp
->clip_ctrl
);
1060 nvfx_vertprog_destroy(struct nvfx_context
*nvfx
, struct nvfx_vertex_program
*vp
)
1062 vp
->translated
= FALSE
;
1070 if (vp
->nr_consts
) {
1076 nouveau_resource_free(&vp
->exec
);
1078 nouveau_resource_free(&vp
->data
);
1080 vp
->data_start_min
= 0;
1082 vp
->ir
= vp
->or = vp
->clip_ctrl
= 0;