projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
nvfx: implement DP2 in vp and fp
[mesa.git] / src / gallium / drivers / nvfx / nvfx_vertprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_linkage.h"
5 #include "util/u_debug.h"
6
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_dump.h"
10 #include "tgsi/tgsi_util.h"
11
12 #include "nvfx_context.h"
13 #include "nvfx_state.h"
14 #include "nvfx_resource.h"
15
16 /* TODO (at least...):
17 * 1. Indexed consts + ARL
18 * 3. NV_vp11, NV_vp2, NV_vp3 features
19 * - extra arith opcodes
20 * - branching
21 * - texture sampling
22 * - indexed attribs
23 * - indexed results
24 * 4. bugs
25 */
26
27 #include "nv30_vertprog.h"
28 #include "nv40_vertprog.h"
29
30 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
31
32 struct nvfx_loop_entry
33 {
34 unsigned brk_target;
35 unsigned cont_target;
36 };
37
38 struct nvfx_vpc {
39 struct nvfx_context* nvfx;
40 struct nvfx_vertex_program *vp;
41
42 struct nvfx_vertex_program_exec *vpi;
43
44 unsigned r_temps;
45 unsigned r_temps_discard;
46 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
47 struct nvfx_reg *r_address;
48 struct nvfx_reg *r_temp;
49
50 struct nvfx_reg *imm;
51 unsigned nr_imm;
52
53 unsigned hpos_idx;
54
55 struct util_dynarray label_relocs;
56 struct util_dynarray loop_stack;
57 };
58
59 static struct nvfx_reg
60 temp(struct nvfx_vpc *vpc)
61 {
62 int idx = ffs(~vpc->r_temps) - 1;
63
64 if (idx < 0) {
65 NOUVEAU_ERR("out of temps!!\n");
66 assert(0);
67 return nvfx_reg(NVFXSR_TEMP, 0);
68 }
69
70 vpc->r_temps |= (1 << idx);
71 vpc->r_temps_discard |= (1 << idx);
72 return nvfx_reg(NVFXSR_TEMP, idx);
73 }
74
75 static inline void
76 release_temps(struct nvfx_vpc *vpc)
77 {
78 vpc->r_temps &= ~vpc->r_temps_discard;
79 vpc->r_temps_discard = 0;
80 }
81
82 static struct nvfx_reg
83 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
84 {
85 struct nvfx_vertex_program *vp = vpc->vp;
86 struct nvfx_vertex_program_data *vpd;
87 int idx;
88
89 if (pipe >= 0) {
90 for (idx = 0; idx < vp->nr_consts; idx++) {
91 if (vp->consts[idx].index == pipe)
92 return nvfx_reg(NVFXSR_CONST, idx);
93 }
94 }
95
96 idx = vp->nr_consts++;
97 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
98 vpd = &vp->consts[idx];
99
100 vpd->index = pipe;
101 vpd->value[0] = x;
102 vpd->value[1] = y;
103 vpd->value[2] = z;
104 vpd->value[3] = w;
105 return nvfx_reg(NVFXSR_CONST, idx);
106 }
107
108 #define arith(s,o,d,m,s0,s1,s2) \
109 nvfx_insn(0, (NVFX_VP_INST_SLOT_##s << 7) | NVFX_VP_INST_##s##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
110
111 static void
112 emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_src src)
113 {
114 struct nvfx_vertex_program *vp = vpc->vp;
115 uint32_t sr = 0;
116
117 switch (src.reg.type) {
118 case NVFXSR_TEMP:
119 sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
120 sr |= (src.reg.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
121 break;
122 case NVFXSR_INPUT:
123 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
124 NVFX_VP(SRC_REG_TYPE_SHIFT));
125 vp->ir |= (1 << src.reg.index);
126 hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
127 break;
128 case NVFXSR_CONST:
129 sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
130 NVFX_VP(SRC_REG_TYPE_SHIFT));
131 assert(vpc->vpi->const_index == -1 ||
132 vpc->vpi->const_index == src.reg.index);
133 vpc->vpi->const_index = src.reg.index;
134 break;
135 case NVFXSR_NONE:
136 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
137 NVFX_VP(SRC_REG_TYPE_SHIFT));
138 break;
139 default:
140 assert(0);
141 }
142
143 if (src.negate)
144 sr |= NVFX_VP(SRC_NEGATE);
145
146 if (src.abs)
147 hw[0] |= (1 << (21 + pos));
148
149 sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
150 (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
151 (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
152 (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
153
154 switch (pos) {
155 case 0:
156 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
157 NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
158 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
159 NVFX_VP(INST_SRC0L_SHIFT);
160 break;
161 case 1:
162 hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
163 break;
164 case 2:
165 hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
166 NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
167 hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
168 NVFX_VP(INST_SRC2L_SHIFT);
169 break;
170 default:
171 assert(0);
172 }
173 }
174
175 static void
176 emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_reg dst)
177 {
178 struct nvfx_vertex_program *vp = vpc->vp;
179
180 switch (dst.type) {
181 case NVFXSR_NONE:
182 if(!nvfx->is_nv4x)
183 hw[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK;
184 else {
185 hw[3] |= NV40_VP_INST_DEST_MASK;
186 if (slot == 0)
187 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
188 else
189 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
190 }
191 break;
192 case NVFXSR_TEMP:
193 if(!nvfx->is_nv4x)
194 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
195 else {
196 hw[3] |= NV40_VP_INST_DEST_MASK;
197 if (slot == 0)
198 hw[0] |= (dst.index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
199 else
200 hw[3] |= (dst.index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
201 }
202 break;
203 case NVFXSR_OUTPUT:
204 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
205 switch (dst.index) {
206 case NVFX_VP_INST_DEST_CLIP(0):
207 vp->or |= (1 << 6);
208 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0;
209 dst.index = NVFX_VP(INST_DEST_FOGC);
210 break;
211 case NVFX_VP_INST_DEST_CLIP(1):
212 vp->or |= (1 << 7);
213 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1;
214 dst.index = NVFX_VP(INST_DEST_FOGC);
215 break;
216 case NVFX_VP_INST_DEST_CLIP(2):
217 vp->or |= (1 << 8);
218 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2;
219 dst.index = NVFX_VP(INST_DEST_FOGC);
220 break;
221 case NVFX_VP_INST_DEST_CLIP(3):
222 vp->or |= (1 << 9);
223 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3;
224 dst.index = NVFX_VP(INST_DEST_PSZ);
225 break;
226 case NVFX_VP_INST_DEST_CLIP(4):
227 vp->or |= (1 << 10);
228 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4;
229 dst.index = NVFX_VP(INST_DEST_PSZ);
230 break;
231 case NVFX_VP_INST_DEST_CLIP(5):
232 vp->or |= (1 << 11);
233 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5;
234 dst.index = NVFX_VP(INST_DEST_PSZ);
235 break;
236 default:
237 if(!nvfx->is_nv4x) {
238 switch (dst.index) {
239 case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
240 case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
241 case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
242 case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
243 case NV30_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
244 case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
245 case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
246 case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
247 case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
248 case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
249 case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
250 case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
251 case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
252 case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
253 }
254 } else {
255 switch (dst.index) {
256 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
257 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
258 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
259 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
260 case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
261 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
262 case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
263 case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
264 case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
265 case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
266 case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
267 case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
268 case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
269 case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
270 }
271 }
272 break;
273 }
274
275 if(!nvfx->is_nv4x) {
276 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
277 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK;
278
279 /*XXX: no way this is entirely correct, someone needs to
280 * figure out what exactly it is.
281 */
282 hw[3] |= 0x800;
283 } else {
284 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
285 if (slot == 0) {
286 hw[0] |= NV40_VP_INST_VEC_RESULT;
287 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
288 } else {
289 hw[3] |= NV40_VP_INST_SCA_RESULT;
290 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
291 }
292 }
293 break;
294 default:
295 assert(0);
296 }
297 }
298
299 static void
300 nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
301 {
302 struct nvfx_context* nvfx = vpc->nvfx;
303 struct nvfx_vertex_program *vp = vpc->vp;
304 unsigned slot = insn.op >> 7;
305 unsigned op = insn.op & 0x7f;
306 uint32_t *hw;
307
308 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
309 vpc->vpi = &vp->insns[vp->nr_insns - 1];
310 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
311 vpc->vpi->const_index = -1;
312
313 hw = vpc->vpi->data;
314
315 hw[0] |= (insn.cc_test << NVFX_VP(INST_COND_SHIFT));
316 hw[0] |= ((insn.cc_swz[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
317 (insn.cc_swz[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
318 (insn.cc_swz[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
319 (insn.cc_swz[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
320 if(insn.cc_update)
321 hw[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE);
322
323 if(!nvfx->is_nv4x) {
324 if(slot == 0)
325 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
326 else
327 {
328 hw[0] |= ((op >> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT);
329 hw[1] |= ((op & 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT);
330 }
331 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
332 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
333
334 if (insn.dst.type == NVFXSR_OUTPUT) {
335 if (slot)
336 hw[3] |= (insn.mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
337 else
338 hw[3] |= (insn.mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
339 } else {
340 if (slot)
341 hw[3] |= (insn.mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
342 else
343 hw[3] |= (insn.mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
344 }
345 } else {
346 if (slot == 0) {
347 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
348 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
349 hw[3] |= (insn.mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
350 } else {
351 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
352 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK ;
353 hw[3] |= (insn.mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
354 }
355 }
356
357 emit_dst(nvfx, vpc, hw, slot, insn.dst);
358 emit_src(nvfx, vpc, hw, 0, insn.src[0]);
359 emit_src(nvfx, vpc, hw, 1, insn.src[1]);
360 emit_src(nvfx, vpc, hw, 2, insn.src[2]);
361 }
362
363 static inline struct nvfx_src
364 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
365 struct nvfx_src src;
366
367 switch (fsrc->Register.File) {
368 case TGSI_FILE_INPUT:
369 src.reg = nvfx_reg(NVFXSR_INPUT, fsrc->Register.Index);
370 break;
371 case TGSI_FILE_CONSTANT:
372 src.reg = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
373 break;
374 case TGSI_FILE_IMMEDIATE:
375 src.reg = vpc->imm[fsrc->Register.Index];
376 break;
377 case TGSI_FILE_TEMPORARY:
378 src.reg = vpc->r_temp[fsrc->Register.Index];
379 break;
380 default:
381 NOUVEAU_ERR("bad src file\n");
382 break;
383 }
384
385 src.abs = fsrc->Register.Absolute;
386 src.negate = fsrc->Register.Negate;
387 src.swz[0] = fsrc->Register.SwizzleX;
388 src.swz[1] = fsrc->Register.SwizzleY;
389 src.swz[2] = fsrc->Register.SwizzleZ;
390 src.swz[3] = fsrc->Register.SwizzleW;
391 return src;
392 }
393
394 static INLINE struct nvfx_reg
395 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
396 struct nvfx_reg dst;
397
398 switch (fdst->Register.File) {
399 case TGSI_FILE_NULL:
400 dst = nvfx_reg(NVFXSR_NONE, 0);
401 break;
402 case TGSI_FILE_OUTPUT:
403 dst = vpc->r_result[fdst->Register.Index];
404 break;
405 case TGSI_FILE_TEMPORARY:
406 dst = vpc->r_temp[fdst->Register.Index];
407 break;
408 case TGSI_FILE_ADDRESS:
409 dst = vpc->r_address[fdst->Register.Index];
410 break;
411 default:
412 NOUVEAU_ERR("bad dst file %i\n", fdst->Register.File);
413 break;
414 }
415
416 return dst;
417 }
418
419 static inline int
420 tgsi_mask(uint tgsi)
421 {
422 int mask = 0;
423
424 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
425 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
426 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
427 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
428 return mask;
429 }
430
431 static boolean
432 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
433 unsigned idx, const struct tgsi_full_instruction *finst)
434 {
435 struct nvfx_src src[3], tmp;
436 struct nvfx_reg dst;
437 struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
438 struct nvfx_insn insn;
439 struct nvfx_label_relocation reloc;
440 struct nvfx_loop_entry loop;
441 int mask;
442 int ai = -1, ci = -1, ii = -1;
443 int i;
444
445 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
446 return TRUE;
447
448 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
449 const struct tgsi_full_src_register *fsrc;
450
451 fsrc = &finst->Src[i];
452 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
453 src[i] = tgsi_src(vpc, fsrc);
454 }
455 }
456
457 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
458 const struct tgsi_full_src_register *fsrc;
459
460 fsrc = &finst->Src[i];
461
462 switch (fsrc->Register.File) {
463 case TGSI_FILE_INPUT:
464 if (ai == -1 || ai == fsrc->Register.Index) {
465 ai = fsrc->Register.Index;
466 src[i] = tgsi_src(vpc, fsrc);
467 } else {
468 src[i] = nvfx_src(temp(vpc));
469 nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
470 }
471 break;
472 case TGSI_FILE_CONSTANT:
473 if ((ci == -1 && ii == -1) ||
474 ci == fsrc->Register.Index) {
475 ci = fsrc->Register.Index;
476 src[i] = tgsi_src(vpc, fsrc);
477 } else {
478 src[i] = nvfx_src(temp(vpc));
479 nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
480 }
481 break;
482 case TGSI_FILE_IMMEDIATE:
483 if ((ci == -1 && ii == -1) ||
484 ii == fsrc->Register.Index) {
485 ii = fsrc->Register.Index;
486 src[i] = tgsi_src(vpc, fsrc);
487 } else {
488 src[i] = nvfx_src(temp(vpc));
489 nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
490 }
491 break;
492 case TGSI_FILE_TEMPORARY:
493 /* handled above */
494 break;
495 default:
496 NOUVEAU_ERR("bad src file\n");
497 return FALSE;
498 }
499 }
500
501 dst = tgsi_dst(vpc, &finst->Dst[0]);
502 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
503
504 switch (finst->Instruction.Opcode) {
505 case TGSI_OPCODE_ABS:
506 nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, abs(src[0]), none, none));
507 break;
508 case TGSI_OPCODE_ADD:
509 nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, src[1]));
510 break;
511 case TGSI_OPCODE_ARL:
512 nvfx_vp_emit(vpc, arith(VEC, ARL, dst, mask, src[0], none, none));
513 break;
514 case TGSI_OPCODE_COS:
515 nvfx_vp_emit(vpc, arith(SCA, COS, dst, mask, none, none, src[0]));
516 break;
517 case TGSI_OPCODE_DP2:
518 tmp = nvfx_src(temp(vpc));
519 nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X | NVFX_VP_MASK_Y, src[0], src[1], none));
520 nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, swz(tmp, X, X, X, X), swz(tmp, Y, Y, Y, Y), none));
521 break;
522 case TGSI_OPCODE_DP3:
523 nvfx_vp_emit(vpc, arith(VEC, DP3, dst, mask, src[0], src[1], none));
524 break;
525 case TGSI_OPCODE_DP4:
526 nvfx_vp_emit(vpc, arith(VEC, DP4, dst, mask, src[0], src[1], none));
527 break;
528 case TGSI_OPCODE_DPH:
529 nvfx_vp_emit(vpc, arith(VEC, DPH, dst, mask, src[0], src[1], none));
530 break;
531 case TGSI_OPCODE_DST:
532 nvfx_vp_emit(vpc, arith(VEC, DST, dst, mask, src[0], src[1], none));
533 break;
534 case TGSI_OPCODE_EX2:
535 nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, src[0]));
536 break;
537 case TGSI_OPCODE_EXP:
538 nvfx_vp_emit(vpc, arith(SCA, EXP, dst, mask, none, none, src[0]));
539 break;
540 case TGSI_OPCODE_FLR:
541 nvfx_vp_emit(vpc, arith(VEC, FLR, dst, mask, src[0], none, none));
542 break;
543 case TGSI_OPCODE_FRC:
544 nvfx_vp_emit(vpc, arith(VEC, FRC, dst, mask, src[0], none, none));
545 break;
546 case TGSI_OPCODE_LG2:
547 nvfx_vp_emit(vpc, arith(SCA, LG2, dst, mask, none, none, src[0]));
548 break;
549 case TGSI_OPCODE_LIT:
550 nvfx_vp_emit(vpc, arith(SCA, LIT, dst, mask, none, none, src[0]));
551 break;
552 case TGSI_OPCODE_LOG:
553 nvfx_vp_emit(vpc, arith(SCA, LOG, dst, mask, none, none, src[0]));
554 break;
555 case TGSI_OPCODE_LRP:
556 tmp = nvfx_src(temp(vpc));
557 nvfx_vp_emit(vpc, arith(VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
558 nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], tmp));
559 break;
560 case TGSI_OPCODE_MAD:
561 nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], src[2]));
562 break;
563 case TGSI_OPCODE_MAX:
564 nvfx_vp_emit(vpc, arith(VEC, MAX, dst, mask, src[0], src[1], none));
565 break;
566 case TGSI_OPCODE_MIN:
567 nvfx_vp_emit(vpc, arith(VEC, MIN, dst, mask, src[0], src[1], none));
568 break;
569 case TGSI_OPCODE_MOV:
570 nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, src[0], none, none));
571 break;
572 case TGSI_OPCODE_MUL:
573 nvfx_vp_emit(vpc, arith(VEC, MUL, dst, mask, src[0], src[1], none));
574 break;
575 case TGSI_OPCODE_NOP:
576 break;
577 case TGSI_OPCODE_POW:
578 tmp = nvfx_src(temp(vpc));
579 nvfx_vp_emit(vpc, arith(SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X)));
580 nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
581 nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X)));
582 break;
583 case TGSI_OPCODE_RCP:
584 nvfx_vp_emit(vpc, arith(SCA, RCP, dst, mask, none, none, src[0]));
585 break;
586 case TGSI_OPCODE_RSQ:
587 nvfx_vp_emit(vpc, arith(SCA, RSQ, dst, mask, none, none, abs(src[0])));
588 break;
589 case TGSI_OPCODE_SEQ:
590 nvfx_vp_emit(vpc, arith(VEC, SEQ, dst, mask, src[0], src[1], none));
591 break;
592 case TGSI_OPCODE_SFL:
593 nvfx_vp_emit(vpc, arith(VEC, SFL, dst, mask, src[0], src[1], none));
594 break;
595 case TGSI_OPCODE_SGE:
596 nvfx_vp_emit(vpc, arith(VEC, SGE, dst, mask, src[0], src[1], none));
597 break;
598 case TGSI_OPCODE_SGT:
599 nvfx_vp_emit(vpc, arith(VEC, SGT, dst, mask, src[0], src[1], none));
600 break;
601 case TGSI_OPCODE_SIN:
602 nvfx_vp_emit(vpc, arith(SCA, SIN, dst, mask, none, none, src[0]));
603 break;
604 case TGSI_OPCODE_SLE:
605 nvfx_vp_emit(vpc, arith(VEC, SLE, dst, mask, src[0], src[1], none));
606 break;
607 case TGSI_OPCODE_SLT:
608 nvfx_vp_emit(vpc, arith(VEC, SLT, dst, mask, src[0], src[1], none));
609 break;
610 case TGSI_OPCODE_SNE:
611 nvfx_vp_emit(vpc, arith(VEC, SNE, dst, mask, src[0], src[1], none));
612 break;
613 case TGSI_OPCODE_SSG:
614 nvfx_vp_emit(vpc, arith(VEC, SSG, dst, mask, src[0], src[1], none));
615 break;
616 case TGSI_OPCODE_STR:
617 nvfx_vp_emit(vpc, arith(VEC, STR, dst, mask, src[0], src[1], none));
618 break;
619 case TGSI_OPCODE_SUB:
620 nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, neg(src[1])));
621 break;
622 case TGSI_OPCODE_TRUNC:
623 tmp = nvfx_src(temp(vpc));
624 insn = arith(VEC, MOV, none.reg, mask, src[0], none, none);
625 insn.cc_update = 1;
626 nvfx_vp_emit(vpc, insn);
627
628 nvfx_vp_emit(vpc, arith(VEC, FLR, tmp.reg, mask, abs(src[0]), none, none));
629 nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, tmp, none, none));
630
631 insn = arith(VEC, MOV, dst, mask, neg(tmp), none, none);
632 insn.cc_test = NVFX_COND_LT;
633 nvfx_vp_emit(vpc, insn);
634 break;
635 case TGSI_OPCODE_XPD:
636 tmp = nvfx_src(temp(vpc));
637 nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
638 nvfx_vp_emit(vpc, arith(VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
639 break;
640
641 case TGSI_OPCODE_IF:
642 insn = arith(VEC, MOV, none.reg, NVFX_VP_MASK_X, src[0], none, none);
643 insn.cc_update = 1;
644 nvfx_vp_emit(vpc, insn);
645
646 reloc.location = vpc->vp->nr_insns;
647 reloc.target = finst->Label.Label + 1;
648 util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
649
650 insn = arith(SCA, BRA, none.reg, 0, none, none, none);
651 insn.cc_test = NVFX_COND_EQ;
652 insn.cc_swz[0] = insn.cc_swz[1] = insn.cc_swz[2] = insn.cc_swz[3] = 0;
653 nvfx_vp_emit(vpc, insn);
654 break;
655
656 case TGSI_OPCODE_ELSE:
657 case TGSI_OPCODE_BRA:
658 case TGSI_OPCODE_CAL:
659 reloc.location = vpc->vp->nr_insns;
660 reloc.target = finst->Label.Label;
661 util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
662
663 if(finst->Instruction.Opcode == TGSI_OPCODE_CAL)
664 insn = arith(SCA, CAL, none.reg, 0, none, none, none);
665 else
666 insn = arith(SCA, BRA, none.reg, 0, none, none, none);
667 nvfx_vp_emit(vpc, insn);
668 break;
669
670 case TGSI_OPCODE_RET:
671 tmp = none;
672 tmp.swz[0] = tmp.swz[1] = tmp.swz[2] = tmp.swz[3] = 0;
673 nvfx_vp_emit(vpc, arith(SCA, RET, none.reg, 0, none, none, tmp));
674 break;
675
676 case TGSI_OPCODE_BGNSUB:
677 case TGSI_OPCODE_ENDSUB:
678 case TGSI_OPCODE_ENDIF:
679 /* nothing to do here */
680 break;
681
682 case TGSI_OPCODE_BGNLOOP:
683 loop.cont_target = idx;
684 loop.brk_target = finst->Label.Label + 1;
685 util_dynarray_append(&vpc->loop_stack, struct nvfx_loop_entry, loop);
686 break;
687
688 case TGSI_OPCODE_ENDLOOP:
689 loop = util_dynarray_pop(&vpc->loop_stack, struct nvfx_loop_entry);
690
691 reloc.location = vpc->vp->nr_insns;
692 reloc.target = loop.cont_target;
693 util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
694
695 nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none));
696 break;
697
698 case TGSI_OPCODE_CONT:
699 loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
700
701 reloc.location = vpc->vp->nr_insns;
702 reloc.target = loop.cont_target;
703 util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
704
705 nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none));
706 break;
707
708 case TGSI_OPCODE_BRK:
709 loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
710
711 reloc.location = vpc->vp->nr_insns;
712 reloc.target = loop.brk_target;
713 util_dynarray_append(&vpc->label_relocs, struct nvfx_label_relocation, reloc);
714
715 nvfx_vp_emit(vpc, arith(SCA, BRA, none.reg, 0, none, none, none));
716 break;
717
718 default:
719 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
720 return FALSE;
721 }
722
723 release_temps(vpc);
724 return TRUE;
725 }
726
727 static boolean
728 nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
729 const struct tgsi_full_declaration *fdec)
730 {
731 unsigned idx = fdec->Range.First;
732 int hw;
733
734 switch (fdec->Semantic.Name) {
735 case TGSI_SEMANTIC_POSITION:
736 hw = NVFX_VP(INST_DEST_POS);
737 vpc->hpos_idx = idx;
738 break;
739 case TGSI_SEMANTIC_COLOR:
740 if (fdec->Semantic.Index == 0) {
741 hw = NVFX_VP(INST_DEST_COL0);
742 } else
743 if (fdec->Semantic.Index == 1) {
744 hw = NVFX_VP(INST_DEST_COL1);
745 } else {
746 NOUVEAU_ERR("bad colour semantic index\n");
747 return FALSE;
748 }
749 break;
750 case TGSI_SEMANTIC_BCOLOR:
751 if (fdec->Semantic.Index == 0) {
752 hw = NVFX_VP(INST_DEST_BFC0);
753 } else
754 if (fdec->Semantic.Index == 1) {
755 hw = NVFX_VP(INST_DEST_BFC1);
756 } else {
757 NOUVEAU_ERR("bad bcolour semantic index\n");
758 return FALSE;
759 }
760 break;
761 case TGSI_SEMANTIC_FOG:
762 hw = NVFX_VP(INST_DEST_FOGC);
763 break;
764 case TGSI_SEMANTIC_PSIZE:
765 hw = NVFX_VP(INST_DEST_PSZ);
766 break;
767 case TGSI_SEMANTIC_GENERIC:
768 hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf)
769 + NVFX_VP(INST_DEST_TC(0)) - NVFX_FP_OP_INPUT_SRC_TC(0);
770 break;
771 case TGSI_SEMANTIC_EDGEFLAG:
772 /* not really an error just a fallback */
773 NOUVEAU_ERR("cannot handle edgeflag output\n");
774 return FALSE;
775 default:
776 NOUVEAU_ERR("bad output semantic\n");
777 return FALSE;
778 }
779
780 vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
781 return TRUE;
782 }
783
784 static boolean
785 nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
786 {
787 struct tgsi_parse_context p;
788 int high_temp = -1, high_addr = -1, nr_imm = 0, i;
789 struct util_semantic_set set;
790 unsigned char sem_layout[8];
791 unsigned sem_layout_size;
792 unsigned num_outputs;
793
794 num_outputs = util_semantic_set_from_program_file(&set, vpc->vp->pipe.tokens, TGSI_FILE_OUTPUT);
795
796 if(num_outputs > 8) {
797 NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs);
798 return FALSE;
799 }
800 util_semantic_layout_from_set(sem_layout, &set, 8, 8);
801
802 /* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */
803 memset(vpc->vp->generic_to_fp_input, 0x0f, sizeof(vpc->vp->generic_to_fp_input));
804 vpc->vp->texcoord_ouput_mask = 0;
805 for(int i = 0; i < 8; ++i) {
806 if(sem_layout[i] == 0xff)
807 continue;
808 vpc->vp->texcoord_ouput_mask |= (1 << i);
809 //printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i);
810 vpc->vp->generic_to_fp_input[sem_layout[i]] = 0xf0 | (NVFX_FP_OP_INPUT_SRC_TC(0) + i);
811 }
812
813 tgsi_parse_init(&p, vpc->vp->pipe.tokens);
814 while (!tgsi_parse_end_of_tokens(&p)) {
815 const union tgsi_full_token *tok = &p.FullToken;
816
817 tgsi_parse_token(&p);
818 switch(tok->Token.Type) {
819 case TGSI_TOKEN_TYPE_IMMEDIATE:
820 nr_imm++;
821 break;
822 case TGSI_TOKEN_TYPE_DECLARATION:
823 {
824 const struct tgsi_full_declaration *fdec;
825
826 fdec = &p.FullToken.FullDeclaration;
827 switch (fdec->Declaration.File) {
828 case TGSI_FILE_TEMPORARY:
829 if (fdec->Range.Last > high_temp) {
830 high_temp =
831 fdec->Range.Last;
832 }
833 break;
834 #if 0 /* this would be nice.. except gallium doesn't track it */
835 case TGSI_FILE_ADDRESS:
836 if (fdec->Range.Last > high_addr) {
837 high_addr =
838 fdec->Range.Last;
839 }
840 break;
841 #endif
842 case TGSI_FILE_OUTPUT:
843 if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec))
844 return FALSE;
845 break;
846 default:
847 break;
848 }
849 }
850 break;
851 #if 1 /* yay, parse instructions looking for address regs instead */
852 case TGSI_TOKEN_TYPE_INSTRUCTION:
853 {
854 const struct tgsi_full_instruction *finst;
855 const struct tgsi_full_dst_register *fdst;
856
857 finst = &p.FullToken.FullInstruction;
858 fdst = &finst->Dst[0];
859
860 if (fdst->Register.File == TGSI_FILE_ADDRESS) {
861 if (fdst->Register.Index > high_addr)
862 high_addr = fdst->Register.Index;
863 }
864
865 }
866 break;
867 #endif
868 default:
869 break;
870 }
871 }
872 tgsi_parse_free(&p);
873
874 if (nr_imm) {
875 vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_reg));
876 assert(vpc->imm);
877 }
878
879 if (++high_temp) {
880 vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
881 for (i = 0; i < high_temp; i++)
882 vpc->r_temp[i] = temp(vpc);
883 }
884
885 if (++high_addr) {
886 vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_reg));
887 for (i = 0; i < high_addr; i++)
888 vpc->r_address[i] = temp(vpc);
889 }
890
891 vpc->r_temps_discard = 0;
892 return TRUE;
893 }
894
895 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", FALSE)
896
897 static void
898 nvfx_vertprog_translate(struct nvfx_context *nvfx,
899 struct nvfx_vertex_program *vp)
900 {
901 struct tgsi_parse_context parse;
902 struct nvfx_vpc *vpc = NULL;
903 struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
904 struct util_dynarray insns;
905 int i;
906
907 vpc = CALLOC(1, sizeof(struct nvfx_vpc));
908 if (!vpc)
909 return;
910 vpc->nvfx = nvfx;
911 vpc->vp = vp;
912
913 if (!nvfx_vertprog_prepare(nvfx, vpc)) {
914 FREE(vpc);
915 return;
916 }
917
918 /* Redirect post-transform vertex position to a temp if user clip
919 * planes are enabled. We need to append code to the vtxprog
920 * to handle clip planes later.
921 */
922 if (vp->ucp.nr) {
923 vpc->r_result[vpc->hpos_idx] = temp(vpc);
924 vpc->r_temps_discard = 0;
925 }
926
927 tgsi_parse_init(&parse, vp->pipe.tokens);
928
929 util_dynarray_init(&insns);
930 while (!tgsi_parse_end_of_tokens(&parse)) {
931 tgsi_parse_token(&parse);
932
933 switch (parse.FullToken.Token.Type) {
934 case TGSI_TOKEN_TYPE_IMMEDIATE:
935 {
936 const struct tgsi_full_immediate *imm;
937
938 imm = &parse.FullToken.FullImmediate;
939 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
940 assert(imm->Immediate.NrTokens == 4 + 1);
941 vpc->imm[vpc->nr_imm++] =
942 constant(vpc, -1,
943 imm->u[0].Float,
944 imm->u[1].Float,
945 imm->u[2].Float,
946 imm->u[3].Float);
947 }
948 break;
949 case TGSI_TOKEN_TYPE_INSTRUCTION:
950 {
951 const struct tgsi_full_instruction *finst;
952 unsigned idx = insns.size >> 2;
953 util_dynarray_append(&insns, unsigned, vp->nr_insns);
954 finst = &parse.FullToken.FullInstruction;
955 if (!nvfx_vertprog_parse_instruction(nvfx, vpc, idx, finst))
956 goto out_err;
957 }
958 break;
959 default:
960 break;
961 }
962 }
963
964 util_dynarray_append(&insns, unsigned, vp->nr_insns);
965
966 for(unsigned i = 0; i < vpc->label_relocs.size; i += sizeof(struct nvfx_label_relocation))
967 {
968 struct nvfx_label_relocation* label_reloc = (struct nvfx_label_relocation*)((char*)vpc->label_relocs.data + i);
969 struct nvfx_label_relocation hw_reloc;
970
971 hw_reloc.location = label_reloc->location;
972 hw_reloc.target = ((unsigned*)insns.data)[label_reloc->target];
973
974 //debug_printf("hw %u -> tgsi %u = hw %u\n", hw_reloc.location, label_reloc->target, hw_reloc.target);
975
976 util_dynarray_append(&vp->branch_relocs, struct nvfx_label_relocation, hw_reloc);
977 }
978 util_dynarray_fini(&insns);
979 util_dynarray_trim(&vp->branch_relocs);
980
981 /* XXX: what if we add a RET before?! make sure we jump here...*/
982
983 /* Write out HPOS if it was redirected to a temp earlier */
984 if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
985 struct nvfx_reg hpos = nvfx_reg(NVFXSR_OUTPUT,
986 NVFX_VP(INST_DEST_POS));
987 struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
988
989 nvfx_vp_emit(vpc, arith(VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none));
990 }
991
992 /* Insert code to handle user clip planes */
993 for (i = 0; i < vp->ucp.nr; i++) {
994 struct nvfx_reg cdst = nvfx_reg(NVFXSR_OUTPUT,
995 NVFX_VP_INST_DEST_CLIP(i));
996 struct nvfx_src ceqn = nvfx_src(constant(vpc, -1,
997 nvfx->clip.ucp[i][0],
998 nvfx->clip.ucp[i][1],
999 nvfx->clip.ucp[i][2],
1000 nvfx->clip.ucp[i][3]));
1001 struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
1002 unsigned mask;
1003
1004 switch (i) {
1005 case 0: case 3: mask = NVFX_VP_MASK_Y; break;
1006 case 1: case 4: mask = NVFX_VP_MASK_Z; break;
1007 case 2: case 5: mask = NVFX_VP_MASK_W; break;
1008 default:
1009 NOUVEAU_ERR("invalid clip dist #%d\n", i);
1010 goto out_err;
1011 }
1012
1013 nvfx_vp_emit(vpc, arith(VEC, DP4, cdst, mask, htmp, ceqn, none));
1014 }
1015
1016 //vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
1017
1018 /* Append NOP + END instruction for branches to the end of the program */
1019 nvfx_vp_emit(vpc, arith(VEC, NOP, none.reg, 0, none, none, none));
1020 vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST | 0x1000;
1021
1022 if(debug_get_option_nvfx_dump_vp())
1023 {
1024 debug_printf("\n");
1025 tgsi_dump(vp->pipe.tokens, 0);
1026
1027 debug_printf("\n%s vertex program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
1028 for (i = 0; i < vp->nr_insns; i++)
1029 debug_printf("%3u: %08x %08x %08x %08x\n", i, vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]);
1030 debug_printf("\n");
1031 }
1032
1033 vp->exec_start = -1;
1034 vp->translated = TRUE;
1035 out_err:
1036 tgsi_parse_free(&parse);
1037 util_dynarray_fini(&vpc->label_relocs);
1038 util_dynarray_fini(&vpc->loop_stack);
1039 if (vpc->r_temp)
1040 FREE(vpc->r_temp);
1041 if (vpc->r_address)
1042 FREE(vpc->r_address);
1043 if (vpc->imm)
1044 FREE(vpc->imm);
1045 FREE(vpc);
1046 }
1047
1048 boolean
1049 nvfx_vertprog_validate(struct nvfx_context *nvfx)
1050 {
1051 struct pipe_context *pipe = &nvfx->pipe;
1052 struct nvfx_screen *screen = nvfx->screen;
1053 struct nouveau_channel *chan = screen->base.channel;
1054 struct nouveau_grobj *eng3d = screen->eng3d;
1055 struct nvfx_vertex_program *vp;
1056 struct pipe_resource *constbuf;
1057 boolean upload_code = FALSE, upload_data = FALSE;
1058 int i;
1059
1060 if (nvfx->render_mode == HW) {
1061 vp = nvfx->vertprog;
1062 constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
1063
1064 // TODO: ouch! can't we just use constant slots for these?!
1065 if ((nvfx->dirty & NVFX_NEW_UCP) ||
1066 memcmp(&nvfx->clip, &vp->ucp, sizeof(vp->ucp))) {
1067 nvfx_vertprog_destroy(nvfx, vp);
1068 memcpy(&vp->ucp, &nvfx->clip, sizeof(vp->ucp));
1069 }
1070 } else {
1071 vp = nvfx->swtnl.vertprog;
1072 constbuf = NULL;
1073 }
1074
1075 /* Translate TGSI shader into hw bytecode */
1076 if (!vp->translated)
1077 {
1078 nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG;
1079 nvfx_vertprog_translate(nvfx, vp);
1080 if (!vp->translated) {
1081 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
1082 return FALSE;
1083 }
1084 }
1085
1086 /* Allocate hw vtxprog exec slots */
1087 if (!vp->exec) {
1088 struct nouveau_resource *heap = nvfx->screen->vp_exec_heap;
1089 uint vplen = vp->nr_insns;
1090
1091 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
1092 while (heap->next && heap->size < vplen) {
1093 struct nvfx_vertex_program *evict;
1094
1095 evict = heap->next->priv;
1096 nouveau_resource_free(&evict->exec);
1097 }
1098
1099 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
1100 assert(0);
1101 }
1102
1103 upload_code = TRUE;
1104 }
1105
1106 /* Allocate hw vtxprog const slots */
1107 if (vp->nr_consts && !vp->data) {
1108 struct nouveau_resource *heap = nvfx->screen->vp_data_heap;
1109
1110 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
1111 while (heap->next && heap->size < vp->nr_consts) {
1112 struct nvfx_vertex_program *evict;
1113
1114 evict = heap->next->priv;
1115 nouveau_resource_free(&evict->data);
1116 }
1117
1118 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
1119 assert(0);
1120 }
1121
1122 /*XXX: handle this some day */
1123 assert(vp->data->start >= vp->data_start_min);
1124
1125 upload_data = TRUE;
1126 if (vp->data_start != vp->data->start)
1127 upload_code = TRUE;
1128 }
1129
1130 /* If exec or data segments moved we need to patch the program to
1131 * fixup offsets and register IDs.
1132 */
1133 if (vp->exec_start != vp->exec->start) {
1134 //printf("vp_relocs %u -> %u\n", vp->exec_start, vp->exec->start);
1135 for(unsigned i = 0; i < vp->branch_relocs.size; i += sizeof(struct nvfx_label_relocation))
1136 {
1137 struct nvfx_label_relocation* reloc = (struct nvfx_label_relocation*)((char*)vp->branch_relocs.data + i);
1138 uint32_t* hw = vp->insns[reloc->location].data;
1139 unsigned target = vp->exec->start + reloc->target;
1140
1141 //debug_printf("vp_reloc hw %u -> hw %u\n", reloc->location, target);
1142
1143 if(!nvfx->is_nv4x)
1144 {
1145 hw[2] &=~ NV30_VP_INST_IADDR_MASK;
1146 hw[2] |= (target & 0x1ff) << NV30_VP_INST_IADDR_SHIFT;
1147 }
1148 else
1149 {
1150 hw[3] &=~ NV40_VP_INST_IADDRL_MASK;
1151 hw[3] |= (target & 7) << NV40_VP_INST_IADDRL_SHIFT;
1152
1153 hw[2] &=~ NV40_VP_INST_IADDRH_MASK;
1154 hw[2] |= ((target >> 3) & 0x3f) << NV40_VP_INST_IADDRH_SHIFT;
1155 }
1156 }
1157
1158 vp->exec_start = vp->exec->start;
1159 }
1160
1161 if (vp->nr_consts && vp->data_start != vp->data->start) {
1162 for (i = 0; i < vp->nr_insns; i++) {
1163 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
1164
1165 if (vpi->const_index >= 0) {
1166 vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
1167 vpi->data[1] |=
1168 (vpi->const_index + vp->data->start) <<
1169 NVFX_VP(INST_CONST_SRC_SHIFT);
1170
1171 }
1172 }
1173
1174 vp->data_start = vp->data->start;
1175 }
1176
1177 /* Update + Upload constant values */
1178 if (vp->nr_consts) {
1179 float *map = NULL;
1180
1181 if (constbuf)
1182 map = nvfx_buffer(constbuf)->data;
1183
1184 for (i = 0; i < vp->nr_consts; i++) {
1185 struct nvfx_vertex_program_data *vpd = &vp->consts[i];
1186
1187 if (vpd->index >= 0) {
1188 if (!upload_data &&
1189 !memcmp(vpd->value, &map[vpd->index * 4],
1190 4 * sizeof(float)))
1191 continue;
1192 memcpy(vpd->value, &map[vpd->index * 4],
1193 4 * sizeof(float));
1194 }
1195
1196 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5);
1197 OUT_RING (chan, i + vp->data->start);
1198 OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
1199 }
1200 }
1201
1202 /* Upload vtxprog */
1203 if (upload_code) {
1204 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
1205 OUT_RING (chan, vp->exec->start);
1206 for (i = 0; i < vp->nr_insns; i++) {
1207 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
1208 OUT_RINGp (chan, vp->insns[i].data, 4);
1209 }
1210 }
1211
1212 if(nvfx->dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP))
1213 {
1214 WAIT_RING(chan, 7);
1215 OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1));
1216 OUT_RING(chan, vp->exec->start);
1217 if(nvfx->is_nv4x) {
1218 OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 2));
1219 OUT_RING(chan, vp->ir);
1220 OUT_RING(chan, vp->or);
1221 }
1222 OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
1223 OUT_RING(chan, vp->clip_ctrl);
1224 }
1225
1226 return TRUE;
1227 }
1228
1229 void
1230 nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
1231 {
1232 vp->translated = FALSE;
1233
1234 if (vp->nr_insns) {
1235 FREE(vp->insns);
1236 vp->insns = NULL;
1237 vp->nr_insns = 0;
1238 }
1239
1240 if (vp->nr_consts) {
1241 FREE(vp->consts);
1242 vp->consts = NULL;
1243 vp->nr_consts = 0;
1244 }
1245
1246 nouveau_resource_free(&vp->exec);
1247 vp->exec_start = 0;
1248 nouveau_resource_free(&vp->data);
1249 vp->data_start = 0;
1250 vp->data_start_min = 0;
1251
1252 vp->ir = vp->or = vp->clip_ctrl = 0;
1253 }