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nvfx: support nv30 simulation on nv40
[mesa.git] / src / gallium / drivers / nvfx / nvfx_vertprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_linkage.h"
5 #include "util/u_debug.h"
6
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_dump.h"
10 #include "tgsi/tgsi_util.h"
11 #include "tgsi/tgsi_ureg.h"
12
13 #include "draw/draw_context.h"
14
15 #include "nvfx_context.h"
16 #include "nvfx_state.h"
17 #include "nvfx_resource.h"
18
19 /* TODO (at least...):
20 * 1. Indexed consts + ARL
21 * 3. NV_vp11, NV_vp2, NV_vp3 features
22 * - extra arith opcodes
23 * - branching
24 * - texture sampling
25 * - indexed attribs
26 * - indexed results
27 * 4. bugs
28 */
29
30 #include "nv30_vertprog.h"
31 #include "nv40_vertprog.h"
32
33 struct nvfx_loop_entry
34 {
35 unsigned brk_target;
36 unsigned cont_target;
37 };
38
39 struct nvfx_vpc {
40 struct nvfx_context* nvfx;
41 struct pipe_shader_state pipe;
42 struct nvfx_vertex_program *vp;
43
44 struct nvfx_vertex_program_exec *vpi;
45
46 unsigned r_temps;
47 unsigned r_temps_discard;
48 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
49 struct nvfx_reg *r_address;
50 struct nvfx_reg *r_temp;
51 struct nvfx_reg *r_const;
52 struct nvfx_reg r_0_1;
53
54 struct nvfx_reg *imm;
55 unsigned nr_imm;
56
57 unsigned hpos_idx;
58
59 struct util_dynarray label_relocs;
60 struct util_dynarray loop_stack;
61 };
62
63 static struct nvfx_reg
64 temp(struct nvfx_vpc *vpc)
65 {
66 int idx = ffs(~vpc->r_temps) - 1;
67
68 if (idx < 0) {
69 NOUVEAU_ERR("out of temps!!\n");
70 assert(0);
71 return nvfx_reg(NVFXSR_TEMP, 0);
72 }
73
74 vpc->r_temps |= (1 << idx);
75 vpc->r_temps_discard |= (1 << idx);
76 return nvfx_reg(NVFXSR_TEMP, idx);
77 }
78
79 static inline void
80 release_temps(struct nvfx_vpc *vpc)
81 {
82 vpc->r_temps &= ~vpc->r_temps_discard;
83 vpc->r_temps_discard = 0;
84 }
85
86 static struct nvfx_reg
87 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
88 {
89 struct nvfx_vertex_program *vp = vpc->vp;
90 struct nvfx_vertex_program_data *vpd;
91 int idx;
92
93 if (pipe >= 0) {
94 for (idx = 0; idx < vp->nr_consts; idx++) {
95 if (vp->consts[idx].index == pipe)
96 return nvfx_reg(NVFXSR_CONST, idx);
97 }
98 }
99
100 idx = vp->nr_consts++;
101 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
102 vpd = &vp->consts[idx];
103
104 vpd->index = pipe;
105 vpd->value[0] = x;
106 vpd->value[1] = y;
107 vpd->value[2] = z;
108 vpd->value[3] = w;
109 return nvfx_reg(NVFXSR_CONST, idx);
110 }
111
112 #define arith(s,t,o,d,m,s0,s1,s2) \
113 nvfx_insn((s), (NVFX_VP_INST_SLOT_##t << 7) | NVFX_VP_INST_##t##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
114
115 static void
116 emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_src src)
117 {
118 struct nvfx_vertex_program *vp = vpc->vp;
119 uint32_t sr = 0;
120 struct nvfx_relocation reloc;
121
122 switch (src.reg.type) {
123 case NVFXSR_TEMP:
124 sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
125 sr |= (src.reg.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
126 break;
127 case NVFXSR_INPUT:
128 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
129 NVFX_VP(SRC_REG_TYPE_SHIFT));
130 vp->ir |= (1 << src.reg.index);
131 hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
132 break;
133 case NVFXSR_CONST:
134 sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
135 NVFX_VP(SRC_REG_TYPE_SHIFT));
136 reloc.location = vp->nr_insns - 1;
137 reloc.target = src.reg.index;
138 util_dynarray_append(&vp->const_relocs, struct nvfx_relocation, reloc);
139 break;
140 case NVFXSR_NONE:
141 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
142 NVFX_VP(SRC_REG_TYPE_SHIFT));
143 break;
144 default:
145 assert(0);
146 }
147
148 if (src.negate)
149 sr |= NVFX_VP(SRC_NEGATE);
150
151 if (src.abs)
152 hw[0] |= (1 << (21 + pos));
153
154 sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
155 (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
156 (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
157 (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
158
159 if(src.indirect) {
160 if(src.reg.type == NVFXSR_CONST)
161 hw[3] |= NVFX_VP(INST_INDEX_CONST);
162 else if(src.reg.type == NVFXSR_INPUT)
163 hw[0] |= NVFX_VP(INST_INDEX_INPUT);
164 else
165 assert(0);
166 if(src.indirect_reg)
167 hw[0] |= NVFX_VP(INST_ADDR_REG_SELECT_1);
168 hw[0] |= src.indirect_swz << NVFX_VP(INST_ADDR_SWZ_SHIFT);
169 }
170
171 switch (pos) {
172 case 0:
173 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
174 NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
175 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
176 NVFX_VP(INST_SRC0L_SHIFT);
177 break;
178 case 1:
179 hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
180 break;
181 case 2:
182 hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
183 NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
184 hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
185 NVFX_VP(INST_SRC2L_SHIFT);
186 break;
187 default:
188 assert(0);
189 }
190 }
191
192 static void
193 emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_reg dst)
194 {
195 struct nvfx_vertex_program *vp = vpc->vp;
196
197 switch (dst.type) {
198 case NVFXSR_NONE:
199 if(!nvfx->is_nv4x)
200 hw[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK;
201 else {
202 hw[3] |= NV40_VP_INST_DEST_MASK;
203 if (slot == 0)
204 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
205 else
206 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
207 }
208 break;
209 case NVFXSR_TEMP:
210 if(!nvfx->is_nv4x)
211 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
212 else {
213 hw[3] |= NV40_VP_INST_DEST_MASK;
214 if (slot == 0)
215 hw[0] |= (dst.index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
216 else
217 hw[3] |= (dst.index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
218 }
219 break;
220 case NVFXSR_OUTPUT:
221 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
222 if(nvfx->is_nv4x) {
223 switch (dst.index) {
224 case NV30_VP_INST_DEST_CLP(0):
225 dst.index = NVFX_VP(INST_DEST_FOGC);
226 break;
227 case NV30_VP_INST_DEST_CLP(1):
228 dst.index = NVFX_VP(INST_DEST_FOGC);
229 break;
230 case NV30_VP_INST_DEST_CLP(2):
231 dst.index = NVFX_VP(INST_DEST_FOGC);
232 break;
233 case NV30_VP_INST_DEST_CLP(3):
234 dst.index = NVFX_VP(INST_DEST_PSZ);
235 break;
236 case NV30_VP_INST_DEST_CLP(4):
237 dst.index = NVFX_VP(INST_DEST_PSZ);
238 break;
239 case NV30_VP_INST_DEST_CLP(5):
240 dst.index = NVFX_VP(INST_DEST_PSZ);
241 break;
242 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
243 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
244 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
245 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
246 case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
247 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
248 }
249 }
250
251 if(!nvfx->is_nv4x) {
252 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
253 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK;
254
255 /*XXX: no way this is entirely correct, someone needs to
256 * figure out what exactly it is.
257 */
258 hw[3] |= 0x800;
259 } else {
260 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
261 if (slot == 0) {
262 hw[0] |= NV40_VP_INST_VEC_RESULT;
263 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK;
264 } else {
265 hw[3] |= NV40_VP_INST_SCA_RESULT;
266 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
267 }
268 }
269 break;
270 default:
271 assert(0);
272 }
273 }
274
275 static void
276 nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
277 {
278 struct nvfx_context* nvfx = vpc->nvfx;
279 struct nvfx_vertex_program *vp = vpc->vp;
280 unsigned slot = insn.op >> 7;
281 unsigned op = insn.op & 0x7f;
282 uint32_t *hw;
283
284 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
285 vpc->vpi = &vp->insns[vp->nr_insns - 1];
286 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
287
288 hw = vpc->vpi->data;
289
290 hw[0] |= (insn.cc_test << NVFX_VP(INST_COND_SHIFT));
291 hw[0] |= ((insn.cc_swz[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
292 (insn.cc_swz[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
293 (insn.cc_swz[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
294 (insn.cc_swz[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
295 if(insn.cc_update)
296 hw[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE);
297
298 if(insn.sat)
299 {
300 assert(nvfx->use_nv4x);
301 if(nvfx->use_nv4x)
302 hw[0] |= NV40_VP_INST_SATURATE;
303 }
304
305 if(!nvfx->is_nv4x) {
306 if(slot == 0)
307 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
308 else
309 {
310 hw[0] |= ((op >> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT);
311 hw[1] |= ((op & 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT);
312 }
313 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
314 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
315
316 if (insn.dst.type == NVFXSR_OUTPUT) {
317 if (slot)
318 hw[3] |= (insn.mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
319 else
320 hw[3] |= (insn.mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
321 } else {
322 if (slot)
323 hw[3] |= (insn.mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
324 else
325 hw[3] |= (insn.mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
326 }
327 } else {
328 if (slot == 0) {
329 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
330 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
331 hw[3] |= (insn.mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
332 } else {
333 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
334 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK ;
335 hw[3] |= (insn.mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
336 }
337 }
338
339 emit_dst(nvfx, vpc, hw, slot, insn.dst);
340 emit_src(nvfx, vpc, hw, 0, insn.src[0]);
341 emit_src(nvfx, vpc, hw, 1, insn.src[1]);
342 emit_src(nvfx, vpc, hw, 2, insn.src[2]);
343
344 // if(insn.src[0].indirect || op == NVFX_VP_INST_VEC_OP_ARL)
345 // hw[3] |= NV40_VP_INST_SCA_RESULT;
346 }
347
348 static inline struct nvfx_src
349 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
350 struct nvfx_src src;
351
352 switch (fsrc->Register.File) {
353 case TGSI_FILE_INPUT:
354 src.reg = nvfx_reg(NVFXSR_INPUT, fsrc->Register.Index);
355 break;
356 case TGSI_FILE_CONSTANT:
357 src.reg = vpc->r_const[fsrc->Register.Index];
358 break;
359 case TGSI_FILE_IMMEDIATE:
360 src.reg = vpc->imm[fsrc->Register.Index];
361 break;
362 case TGSI_FILE_TEMPORARY:
363 src.reg = vpc->r_temp[fsrc->Register.Index];
364 break;
365 default:
366 NOUVEAU_ERR("bad src file\n");
367 src.reg.index = 0;
368 src.reg.type = -1;
369 break;
370 }
371
372 src.abs = fsrc->Register.Absolute;
373 src.negate = fsrc->Register.Negate;
374 src.swz[0] = fsrc->Register.SwizzleX;
375 src.swz[1] = fsrc->Register.SwizzleY;
376 src.swz[2] = fsrc->Register.SwizzleZ;
377 src.swz[3] = fsrc->Register.SwizzleW;
378 src.indirect = 0;
379
380 if(fsrc->Register.Indirect) {
381 if(fsrc->Indirect.File == TGSI_FILE_ADDRESS &&
382 (fsrc->Register.File == TGSI_FILE_CONSTANT || fsrc->Register.File == TGSI_FILE_INPUT))
383 {
384 src.indirect = 1;
385 src.indirect_reg = fsrc->Indirect.Index;
386 src.indirect_swz = fsrc->Indirect.SwizzleX;
387 }
388 else
389 {
390 src.reg.index = 0;
391 src.reg.type = -1;
392 }
393 }
394 return src;
395 }
396
397 static INLINE struct nvfx_reg
398 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
399 struct nvfx_reg dst;
400
401 switch (fdst->Register.File) {
402 case TGSI_FILE_NULL:
403 dst = nvfx_reg(NVFXSR_NONE, 0);
404 break;
405 case TGSI_FILE_OUTPUT:
406 dst = vpc->r_result[fdst->Register.Index];
407 break;
408 case TGSI_FILE_TEMPORARY:
409 dst = vpc->r_temp[fdst->Register.Index];
410 break;
411 case TGSI_FILE_ADDRESS:
412 dst = vpc->r_address[fdst->Register.Index];
413 break;
414 default:
415 NOUVEAU_ERR("bad dst file %i\n", fdst->Register.File);
416 dst.index = 0;
417 dst.type = 0;
418 break;
419 }
420
421 return dst;
422 }
423
424 static inline int
425 tgsi_mask(uint tgsi)
426 {
427 int mask = 0;
428
429 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
430 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
431 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
432 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
433 return mask;
434 }
435
436 static boolean
437 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
438 unsigned idx, const struct tgsi_full_instruction *finst)
439 {
440 struct nvfx_src src[3], tmp;
441 struct nvfx_reg dst;
442 struct nvfx_reg final_dst;
443 struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
444 struct nvfx_insn insn;
445 struct nvfx_relocation reloc;
446 struct nvfx_loop_entry loop;
447 boolean sat = FALSE;
448 int mask;
449 int ai = -1, ci = -1, ii = -1;
450 int i;
451
452 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
453 return TRUE;
454
455 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
456 const struct tgsi_full_src_register *fsrc;
457
458 fsrc = &finst->Src[i];
459 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
460 src[i] = tgsi_src(vpc, fsrc);
461 }
462 }
463
464 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
465 const struct tgsi_full_src_register *fsrc;
466
467 fsrc = &finst->Src[i];
468
469 switch (fsrc->Register.File) {
470 case TGSI_FILE_INPUT:
471 if (ai == -1 || ai == fsrc->Register.Index) {
472 ai = fsrc->Register.Index;
473 src[i] = tgsi_src(vpc, fsrc);
474 } else {
475 src[i] = nvfx_src(temp(vpc));
476 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
477 }
478 break;
479 case TGSI_FILE_CONSTANT:
480 if ((ci == -1 && ii == -1) ||
481 ci == fsrc->Register.Index) {
482 ci = fsrc->Register.Index;
483 src[i] = tgsi_src(vpc, fsrc);
484 } else {
485 src[i] = nvfx_src(temp(vpc));
486 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
487 }
488 break;
489 case TGSI_FILE_IMMEDIATE:
490 if ((ci == -1 && ii == -1) ||
491 ii == fsrc->Register.Index) {
492 ii = fsrc->Register.Index;
493 src[i] = tgsi_src(vpc, fsrc);
494 } else {
495 src[i] = nvfx_src(temp(vpc));
496 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
497 }
498 break;
499 case TGSI_FILE_TEMPORARY:
500 /* handled above */
501 break;
502 default:
503 NOUVEAU_ERR("bad src file\n");
504 return FALSE;
505 }
506 }
507
508 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
509 if(src[i].reg.type < 0)
510 return FALSE;
511 }
512
513 if(finst->Dst[0].Register.File == TGSI_FILE_ADDRESS &&
514 finst->Instruction.Opcode != TGSI_OPCODE_ARL)
515 return FALSE;
516
517 final_dst = dst = tgsi_dst(vpc, &finst->Dst[0]);
518 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
519 if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
520 {
521 assert(finst->Instruction.Opcode != TGSI_OPCODE_ARL);
522 if(nvfx->use_nv4x)
523 sat = TRUE;
524 else if(dst.type != NVFXSR_TEMP)
525 dst = temp(vpc);
526 }
527
528 switch (finst->Instruction.Opcode) {
529 case TGSI_OPCODE_ABS:
530 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, abs(src[0]), none, none));
531 break;
532 case TGSI_OPCODE_ADD:
533 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1]));
534 break;
535 case TGSI_OPCODE_ARL:
536 nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none));
537 break;
538 case TGSI_OPCODE_CMP:
539 insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none);
540 insn.cc_update = 1;
541 nvfx_vp_emit(vpc, insn);
542
543 insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none);
544 insn.cc_test = NVFX_COND_GE;
545 nvfx_vp_emit(vpc, insn);
546
547 insn = arith(sat, VEC, MOV, dst, mask, src[1], none, none);
548 insn.cc_test = NVFX_COND_LT;
549 nvfx_vp_emit(vpc, insn);
550 break;
551 case TGSI_OPCODE_COS:
552 nvfx_vp_emit(vpc, arith(sat, SCA, COS, dst, mask, none, none, src[0]));
553 break;
554 case TGSI_OPCODE_DP2:
555 tmp = nvfx_src(temp(vpc));
556 nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X | NVFX_VP_MASK_Y, src[0], src[1], none));
557 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, swz(tmp, X, X, X, X), none, swz(tmp, Y, Y, Y, Y)));
558 break;
559 case TGSI_OPCODE_DP3:
560 nvfx_vp_emit(vpc, arith(sat, VEC, DP3, dst, mask, src[0], src[1], none));
561 break;
562 case TGSI_OPCODE_DP4:
563 nvfx_vp_emit(vpc, arith(sat, VEC, DP4, dst, mask, src[0], src[1], none));
564 break;
565 case TGSI_OPCODE_DPH:
566 nvfx_vp_emit(vpc, arith(sat, VEC, DPH, dst, mask, src[0], src[1], none));
567 break;
568 case TGSI_OPCODE_DST:
569 nvfx_vp_emit(vpc, arith(sat, VEC, DST, dst, mask, src[0], src[1], none));
570 break;
571 case TGSI_OPCODE_EX2:
572 nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, src[0]));
573 break;
574 case TGSI_OPCODE_EXP:
575 nvfx_vp_emit(vpc, arith(sat, SCA, EXP, dst, mask, none, none, src[0]));
576 break;
577 case TGSI_OPCODE_FLR:
578 nvfx_vp_emit(vpc, arith(sat, VEC, FLR, dst, mask, src[0], none, none));
579 break;
580 case TGSI_OPCODE_FRC:
581 nvfx_vp_emit(vpc, arith(sat, VEC, FRC, dst, mask, src[0], none, none));
582 break;
583 case TGSI_OPCODE_LG2:
584 nvfx_vp_emit(vpc, arith(sat, SCA, LG2, dst, mask, none, none, src[0]));
585 break;
586 case TGSI_OPCODE_LIT:
587 nvfx_vp_emit(vpc, arith(sat, SCA, LIT, dst, mask, none, none, src[0]));
588 break;
589 case TGSI_OPCODE_LOG:
590 nvfx_vp_emit(vpc, arith(sat, SCA, LOG, dst, mask, none, none, src[0]));
591 break;
592 case TGSI_OPCODE_LRP:
593 tmp = nvfx_src(temp(vpc));
594 nvfx_vp_emit(vpc, arith(0, VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
595 nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], tmp));
596 break;
597 case TGSI_OPCODE_MAD:
598 nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, mask, src[0], src[1], src[2]));
599 break;
600 case TGSI_OPCODE_MAX:
601 nvfx_vp_emit(vpc, arith(sat, VEC, MAX, dst, mask, src[0], src[1], none));
602 break;
603 case TGSI_OPCODE_MIN:
604 nvfx_vp_emit(vpc, arith(sat, VEC, MIN, dst, mask, src[0], src[1], none));
605 break;
606 case TGSI_OPCODE_MOV:
607 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, src[0], none, none));
608 break;
609 case TGSI_OPCODE_MUL:
610 nvfx_vp_emit(vpc, arith(sat, VEC, MUL, dst, mask, src[0], src[1], none));
611 break;
612 case TGSI_OPCODE_NOP:
613 break;
614 case TGSI_OPCODE_POW:
615 tmp = nvfx_src(temp(vpc));
616 nvfx_vp_emit(vpc, arith(0, SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X)));
617 nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
618 nvfx_vp_emit(vpc, arith(sat, SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X)));
619 break;
620 case TGSI_OPCODE_RCP:
621 nvfx_vp_emit(vpc, arith(sat, SCA, RCP, dst, mask, none, none, src[0]));
622 break;
623 case TGSI_OPCODE_RSQ:
624 nvfx_vp_emit(vpc, arith(sat, SCA, RSQ, dst, mask, none, none, abs(src[0])));
625 break;
626 case TGSI_OPCODE_SEQ:
627 nvfx_vp_emit(vpc, arith(sat, VEC, SEQ, dst, mask, src[0], src[1], none));
628 break;
629 case TGSI_OPCODE_SFL:
630 nvfx_vp_emit(vpc, arith(sat, VEC, SFL, dst, mask, src[0], src[1], none));
631 break;
632 case TGSI_OPCODE_SGE:
633 nvfx_vp_emit(vpc, arith(sat, VEC, SGE, dst, mask, src[0], src[1], none));
634 break;
635 case TGSI_OPCODE_SGT:
636 nvfx_vp_emit(vpc, arith(sat, VEC, SGT, dst, mask, src[0], src[1], none));
637 break;
638 case TGSI_OPCODE_SIN:
639 nvfx_vp_emit(vpc, arith(sat, SCA, SIN, dst, mask, none, none, src[0]));
640 break;
641 case TGSI_OPCODE_SLE:
642 nvfx_vp_emit(vpc, arith(sat, VEC, SLE, dst, mask, src[0], src[1], none));
643 break;
644 case TGSI_OPCODE_SLT:
645 nvfx_vp_emit(vpc, arith(sat, VEC, SLT, dst, mask, src[0], src[1], none));
646 break;
647 case TGSI_OPCODE_SNE:
648 nvfx_vp_emit(vpc, arith(sat, VEC, SNE, dst, mask, src[0], src[1], none));
649 break;
650 case TGSI_OPCODE_SSG:
651 nvfx_vp_emit(vpc, arith(sat, VEC, SSG, dst, mask, src[0], src[1], none));
652 break;
653 case TGSI_OPCODE_STR:
654 nvfx_vp_emit(vpc, arith(sat, VEC, STR, dst, mask, src[0], src[1], none));
655 break;
656 case TGSI_OPCODE_SUB:
657 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, neg(src[1])));
658 break;
659 case TGSI_OPCODE_TRUNC:
660 tmp = nvfx_src(temp(vpc));
661 insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none);
662 insn.cc_update = 1;
663 nvfx_vp_emit(vpc, insn);
664
665 nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, abs(src[0]), none, none));
666 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, tmp, none, none));
667
668 insn = arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none);
669 insn.cc_test = NVFX_COND_LT;
670 nvfx_vp_emit(vpc, insn);
671 break;
672 case TGSI_OPCODE_XPD:
673 tmp = nvfx_src(temp(vpc));
674 nvfx_vp_emit(vpc, arith(0, VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
675 nvfx_vp_emit(vpc, arith(sat, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
676 break;
677
678 case TGSI_OPCODE_IF:
679 insn = arith(0, VEC, MOV, none.reg, NVFX_VP_MASK_X, src[0], none, none);
680 insn.cc_update = 1;
681 nvfx_vp_emit(vpc, insn);
682
683 reloc.location = vpc->vp->nr_insns;
684 reloc.target = finst->Label.Label + 1;
685 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
686
687 insn = arith(0, SCA, BRA, none.reg, 0, none, none, none);
688 insn.cc_test = NVFX_COND_EQ;
689 insn.cc_swz[0] = insn.cc_swz[1] = insn.cc_swz[2] = insn.cc_swz[3] = 0;
690 nvfx_vp_emit(vpc, insn);
691 break;
692
693 case TGSI_OPCODE_ELSE:
694 case TGSI_OPCODE_BRA:
695 case TGSI_OPCODE_CAL:
696 reloc.location = vpc->vp->nr_insns;
697 reloc.target = finst->Label.Label;
698 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
699
700 if(finst->Instruction.Opcode == TGSI_OPCODE_CAL)
701 insn = arith(0, SCA, CAL, none.reg, 0, none, none, none);
702 else
703 insn = arith(0, SCA, BRA, none.reg, 0, none, none, none);
704 nvfx_vp_emit(vpc, insn);
705 break;
706
707 case TGSI_OPCODE_RET:
708 tmp = none;
709 tmp.swz[0] = tmp.swz[1] = tmp.swz[2] = tmp.swz[3] = 0;
710 nvfx_vp_emit(vpc, arith(0, SCA, RET, none.reg, 0, none, none, tmp));
711 break;
712
713 case TGSI_OPCODE_BGNSUB:
714 case TGSI_OPCODE_ENDSUB:
715 case TGSI_OPCODE_ENDIF:
716 /* nothing to do here */
717 break;
718
719 case TGSI_OPCODE_BGNLOOP:
720 loop.cont_target = idx;
721 loop.brk_target = finst->Label.Label + 1;
722 util_dynarray_append(&vpc->loop_stack, struct nvfx_loop_entry, loop);
723 break;
724
725 case TGSI_OPCODE_ENDLOOP:
726 loop = util_dynarray_pop(&vpc->loop_stack, struct nvfx_loop_entry);
727
728 reloc.location = vpc->vp->nr_insns;
729 reloc.target = loop.cont_target;
730 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
731
732 nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
733 break;
734
735 case TGSI_OPCODE_CONT:
736 loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
737
738 reloc.location = vpc->vp->nr_insns;
739 reloc.target = loop.cont_target;
740 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
741
742 nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
743 break;
744
745 case TGSI_OPCODE_BRK:
746 loop = util_dynarray_top(&vpc->loop_stack, struct nvfx_loop_entry);
747
748 reloc.location = vpc->vp->nr_insns;
749 reloc.target = loop.brk_target;
750 util_dynarray_append(&vpc->label_relocs, struct nvfx_relocation, reloc);
751
752 nvfx_vp_emit(vpc, arith(0, SCA, BRA, none.reg, 0, none, none, none));
753 break;
754
755 default:
756 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
757 return FALSE;
758 }
759
760 if(finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE && !nvfx->use_nv4x)
761 {
762 if(!vpc->r_0_1.type)
763 vpc->r_0_1 = constant(vpc, -1, 0, 1, 0, 0);
764 nvfx_vp_emit(vpc, arith(0, VEC, MAX, dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), X, X, X, X), none));
765 nvfx_vp_emit(vpc, arith(0, VEC, MIN, final_dst, mask, nvfx_src(dst), swz(nvfx_src(vpc->r_0_1), Y, Y, Y, Y), none));
766 }
767
768 release_temps(vpc);
769 return TRUE;
770 }
771
772 static boolean
773 nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
774 const struct tgsi_full_declaration *fdec)
775 {
776 unsigned idx = fdec->Range.First;
777 int hw;
778
779 switch (fdec->Semantic.Name) {
780 case TGSI_SEMANTIC_POSITION:
781 hw = NVFX_VP(INST_DEST_POS);
782 vpc->hpos_idx = idx;
783 break;
784 case TGSI_SEMANTIC_COLOR:
785 if (fdec->Semantic.Index == 0) {
786 hw = NVFX_VP(INST_DEST_COL0);
787 } else
788 if (fdec->Semantic.Index == 1) {
789 hw = NVFX_VP(INST_DEST_COL1);
790 } else {
791 NOUVEAU_ERR("bad colour semantic index\n");
792 return FALSE;
793 }
794 break;
795 case TGSI_SEMANTIC_BCOLOR:
796 if (fdec->Semantic.Index == 0) {
797 hw = NVFX_VP(INST_DEST_BFC0);
798 } else
799 if (fdec->Semantic.Index == 1) {
800 hw = NVFX_VP(INST_DEST_BFC1);
801 } else {
802 NOUVEAU_ERR("bad bcolour semantic index\n");
803 return FALSE;
804 }
805 break;
806 case TGSI_SEMANTIC_FOG:
807 hw = NVFX_VP(INST_DEST_FOGC);
808 break;
809 case TGSI_SEMANTIC_PSIZE:
810 hw = NVFX_VP(INST_DEST_PSZ);
811 break;
812 case TGSI_SEMANTIC_GENERIC:
813 hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf) - NVFX_FP_OP_INPUT_SRC_TC(0);
814 if(hw <= 8)
815 hw = NVFX_VP(INST_DEST_TC(hw));
816 else if(hw == 9) /* TODO: this is correct, but how does this overlapping work exactly? */
817 hw = NV40_VP_INST_DEST_PSZ;
818 else
819 assert(0);
820 break;
821 case TGSI_SEMANTIC_EDGEFLAG:
822 /* not really an error just a fallback */
823 NOUVEAU_ERR("cannot handle edgeflag output\n");
824 return FALSE;
825 default:
826 NOUVEAU_ERR("bad output semantic\n");
827 return FALSE;
828 }
829
830 vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
831 return TRUE;
832 }
833
834 static boolean
835 nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
836 {
837 struct tgsi_parse_context p;
838 int high_const = -1, high_temp = -1, high_addr = -1, nr_imm = 0, i;
839 struct util_semantic_set set;
840 unsigned char sem_layout[10];
841 unsigned num_outputs;
842 unsigned num_texcoords = nvfx->is_nv4x ? 10 : 8;
843
844 num_outputs = util_semantic_set_from_program_file(&set, vpc->pipe.tokens, TGSI_FILE_OUTPUT);
845
846 if(num_outputs > num_texcoords) {
847 NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs);
848 return FALSE;
849 }
850 util_semantic_layout_from_set(sem_layout, &set, num_texcoords, num_texcoords);
851
852 /* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */
853 memset(vpc->vp->generic_to_fp_input, 0x0f, sizeof(vpc->vp->generic_to_fp_input));
854 for(int i = 0; i < 10; ++i) {
855 if(sem_layout[i] == 0xff)
856 continue;
857 //printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i);
858 vpc->vp->generic_to_fp_input[sem_layout[i]] = 0xf0 | NVFX_FP_OP_INPUT_SRC_TC(i);
859 }
860
861 vpc->vp->sprite_fp_input = -1;
862 for(int i = 0; i < 10; ++i)
863 {
864 if(sem_layout[i] == 0xff)
865 {
866 vpc->vp->sprite_fp_input = NVFX_FP_OP_INPUT_SRC_TC(i);
867 break;
868 }
869 }
870
871 tgsi_parse_init(&p, vpc->pipe.tokens);
872 while (!tgsi_parse_end_of_tokens(&p)) {
873 const union tgsi_full_token *tok = &p.FullToken;
874
875 tgsi_parse_token(&p);
876 switch(tok->Token.Type) {
877 case TGSI_TOKEN_TYPE_IMMEDIATE:
878 nr_imm++;
879 break;
880 case TGSI_TOKEN_TYPE_DECLARATION:
881 {
882 const struct tgsi_full_declaration *fdec;
883
884 fdec = &p.FullToken.FullDeclaration;
885 switch (fdec->Declaration.File) {
886 case TGSI_FILE_TEMPORARY:
887 if (fdec->Range.Last > high_temp) {
888 high_temp =
889 fdec->Range.Last;
890 }
891 break;
892 case TGSI_FILE_ADDRESS:
893 if (fdec->Range.Last > high_addr) {
894 high_addr =
895 fdec->Range.Last;
896 }
897 break;
898 case TGSI_FILE_CONSTANT:
899 if (fdec->Range.Last > high_const) {
900 high_const =
901 fdec->Range.Last;
902 }
903 break;
904 case TGSI_FILE_OUTPUT:
905 if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec))
906 return FALSE;
907 break;
908 default:
909 break;
910 }
911 }
912 break;
913 default:
914 break;
915 }
916 }
917 tgsi_parse_free(&p);
918
919 if (nr_imm) {
920 vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_reg));
921 assert(vpc->imm);
922 }
923
924 if (++high_temp) {
925 vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
926 for (i = 0; i < high_temp; i++)
927 vpc->r_temp[i] = temp(vpc);
928 }
929
930 if (++high_addr) {
931 vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_reg));
932 for (i = 0; i < high_addr; i++)
933 vpc->r_address[i] = nvfx_reg(NVFXSR_TEMP, i);
934 }
935
936 if(++high_const) {
937 vpc->r_const = CALLOC(high_const, sizeof(struct nvfx_reg));
938 for (i = 0; i < high_const; i++)
939 vpc->r_const[i] = constant(vpc, i, 0, 0, 0, 0);
940 }
941
942 vpc->r_temps_discard = 0;
943 return TRUE;
944 }
945
946 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", FALSE)
947
948 static struct nvfx_vertex_program*
949 nvfx_vertprog_translate(struct nvfx_context *nvfx, const struct pipe_shader_state* vps)
950 {
951 struct tgsi_parse_context parse;
952 struct nvfx_vertex_program* vp = NULL;
953 struct nvfx_vpc *vpc = NULL;
954 struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
955 struct util_dynarray insns;
956 int i;
957
958 tgsi_parse_init(&parse, vps->tokens);
959
960 vp = CALLOC_STRUCT(nvfx_vertex_program);
961 if(!vp)
962 goto out_err;
963
964 vpc = CALLOC_STRUCT(nvfx_vpc);
965 if (!vpc)
966 goto out_err;
967
968 vpc->nvfx = nvfx;
969 vpc->vp = vp;
970 vpc->pipe = *vps;
971
972 {
973 // TODO: use a 64-bit atomic here!
974 static unsigned long long id = 0;
975 vp->id = ++id;
976 }
977
978 /* reserve space for ucps */
979 if(nvfx->use_vp_clipping)
980 {
981 for(i = 0; i < 6; ++i)
982 constant(vpc, -1, 0, 0, 0, 0);
983 }
984
985 if (!nvfx_vertprog_prepare(nvfx, vpc)) {
986 FREE(vpc);
987 return NULL;
988 }
989
990 /* Redirect post-transform vertex position to a temp if user clip
991 * planes are enabled. We need to append code to the vtxprog
992 * to handle clip planes later.
993 */
994 /* TODO: maybe support patching this depending on whether there are ucps: not sure if it is really matters much */
995 if (nvfx->use_vp_clipping) {
996 vpc->r_result[vpc->hpos_idx] = temp(vpc);
997 vpc->r_temps_discard = 0;
998 }
999
1000 util_dynarray_init(&insns);
1001 while (!tgsi_parse_end_of_tokens(&parse)) {
1002 tgsi_parse_token(&parse);
1003
1004 switch (parse.FullToken.Token.Type) {
1005 case TGSI_TOKEN_TYPE_IMMEDIATE:
1006 {
1007 const struct tgsi_full_immediate *imm;
1008
1009 imm = &parse.FullToken.FullImmediate;
1010 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
1011 assert(imm->Immediate.NrTokens == 4 + 1);
1012 vpc->imm[vpc->nr_imm++] =
1013 constant(vpc, -1,
1014 imm->u[0].Float,
1015 imm->u[1].Float,
1016 imm->u[2].Float,
1017 imm->u[3].Float);
1018 }
1019 break;
1020 case TGSI_TOKEN_TYPE_INSTRUCTION:
1021 {
1022 const struct tgsi_full_instruction *finst;
1023 unsigned idx = insns.size >> 2;
1024 util_dynarray_append(&insns, unsigned, vp->nr_insns);
1025 finst = &parse.FullToken.FullInstruction;
1026 if (!nvfx_vertprog_parse_instruction(nvfx, vpc, idx, finst))
1027 goto out_err;
1028 }
1029 break;
1030 default:
1031 break;
1032 }
1033 }
1034
1035 util_dynarray_append(&insns, unsigned, vp->nr_insns);
1036
1037 for(unsigned i = 0; i < vpc->label_relocs.size; i += sizeof(struct nvfx_relocation))
1038 {
1039 struct nvfx_relocation* label_reloc = (struct nvfx_relocation*)((char*)vpc->label_relocs.data + i);
1040 struct nvfx_relocation hw_reloc;
1041
1042 hw_reloc.location = label_reloc->location;
1043 hw_reloc.target = ((unsigned*)insns.data)[label_reloc->target];
1044
1045 //debug_printf("hw %u -> tgsi %u = hw %u\n", hw_reloc.location, label_reloc->target, hw_reloc.target);
1046
1047 util_dynarray_append(&vp->branch_relocs, struct nvfx_relocation, hw_reloc);
1048 }
1049 util_dynarray_fini(&insns);
1050 util_dynarray_trim(&vp->branch_relocs);
1051
1052 /* XXX: what if we add a RET before?! make sure we jump here...*/
1053
1054 /* Write out HPOS if it was redirected to a temp earlier */
1055 if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
1056 struct nvfx_reg hpos = nvfx_reg(NVFXSR_OUTPUT,
1057 NVFX_VP(INST_DEST_POS));
1058 struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
1059
1060 nvfx_vp_emit(vpc, arith(0, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none));
1061 }
1062
1063 /* Insert code to handle user clip planes */
1064 if(nvfx->use_vp_clipping)
1065 {
1066 for (i = 0; i < 6; i++) {
1067 struct nvfx_reg cdst = nvfx_reg(NVFXSR_OUTPUT, NV30_VP_INST_DEST_CLP(i));
1068 struct nvfx_src ceqn = nvfx_src(nvfx_reg(NVFXSR_CONST, i));
1069 struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
1070 unsigned mask;
1071
1072 if(nvfx->is_nv4x)
1073 {
1074 switch (i) {
1075 case 0: case 3: mask = NVFX_VP_MASK_Y; break;
1076 case 1: case 4: mask = NVFX_VP_MASK_Z; break;
1077 case 2: case 5: mask = NVFX_VP_MASK_W; break;
1078 default:
1079 NOUVEAU_ERR("invalid clip dist #%d\n", i);
1080 goto out_err;
1081 }
1082 }
1083 else
1084 mask = NVFX_VP_MASK_X;
1085
1086 nvfx_vp_emit(vpc, arith(0, VEC, DP4, cdst, mask, htmp, ceqn, none));
1087 }
1088 }
1089 else
1090 {
1091 if(vp->nr_insns)
1092 vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
1093
1094 nvfx_vp_emit(vpc, arith(0, VEC, NOP, none.reg, 0, none, none, none));
1095 vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
1096 }
1097
1098 if(debug_get_option_nvfx_dump_vp())
1099 {
1100 debug_printf("\n");
1101 tgsi_dump(vpc->pipe.tokens, 0);
1102
1103 debug_printf("\n%s vertex program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
1104 for (i = 0; i < vp->nr_insns; i++)
1105 debug_printf("%3u: %08x %08x %08x %08x\n", i, vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]);
1106 debug_printf("\n");
1107 }
1108
1109 vp->clip_nr = -1;
1110 vp->exec_start = -1;
1111
1112 out:
1113 tgsi_parse_free(&parse);
1114 if(vpc) {
1115 util_dynarray_fini(&vpc->label_relocs);
1116 util_dynarray_fini(&vpc->loop_stack);
1117 FREE(vpc->r_temp);
1118 FREE(vpc->r_address);
1119 FREE(vpc->r_const);
1120 FREE(vpc->imm);
1121 FREE(vpc);
1122 }
1123 return vp;
1124
1125 out_err:
1126 FREE(vp);
1127 vp = NULL;
1128 goto out;
1129 }
1130
1131 static struct nvfx_vertex_program*
1132 nvfx_vertprog_translate_draw_vp(struct nvfx_context *nvfx, struct nvfx_pipe_vertex_program* pvp)
1133 {
1134 struct nvfx_vertex_program* vp = NULL;
1135 struct pipe_shader_state vps;
1136 struct ureg_program *ureg = NULL;
1137 unsigned num_outputs = MIN2(pvp->info.num_outputs, 16);
1138
1139 ureg = ureg_create( TGSI_PROCESSOR_VERTEX );
1140 if(ureg == NULL)
1141 return 0;
1142
1143 for (unsigned i = 0; i < num_outputs; i++)
1144 ureg_MOV(ureg, ureg_DECL_output(ureg, pvp->info.output_semantic_name[i], pvp->info.output_semantic_index[i]), ureg_DECL_vs_input(ureg, i));
1145
1146 ureg_END( ureg );
1147
1148 vps.tokens = ureg_get_tokens(ureg, 0);
1149 vp = nvfx_vertprog_translate(nvfx, &vps);
1150 ureg_free_tokens(vps.tokens);
1151 ureg_destroy(ureg);
1152
1153 return vp;
1154 }
1155
1156 boolean
1157 nvfx_vertprog_validate(struct nvfx_context *nvfx)
1158 {
1159 struct nvfx_screen *screen = nvfx->screen;
1160 struct nouveau_channel *chan = screen->base.channel;
1161 struct nvfx_pipe_vertex_program *pvp = nvfx->vertprog;
1162 struct nvfx_vertex_program* vp;
1163 struct pipe_resource *constbuf;
1164 boolean upload_code = FALSE, upload_data = FALSE;
1165 int i;
1166
1167 if (nvfx->render_mode == HW) {
1168 nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG;
1169 vp = pvp->vp;
1170
1171 if(!vp) {
1172 vp = nvfx_vertprog_translate(nvfx, &pvp->pipe);
1173 if(!vp)
1174 vp = NVFX_VP_FAILED;
1175 pvp->vp = vp;
1176 }
1177
1178 if(vp == NVFX_VP_FAILED) {
1179 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
1180 return FALSE;
1181 }
1182
1183 constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
1184 } else {
1185 vp = pvp->draw_vp;
1186 if(!vp)
1187 {
1188 pvp->draw_vp = vp = nvfx_vertprog_translate_draw_vp(nvfx, pvp);
1189 if(!vp) {
1190 _debug_printf("Error: unable to create a swtnl passthrough vertex shader: aborting.");
1191 abort();
1192 }
1193 }
1194 constbuf = NULL;
1195 }
1196
1197 nvfx->hw_vertprog = vp;
1198
1199 /* Allocate hw vtxprog exec slots */
1200 if (!vp->exec) {
1201 struct nouveau_resource *heap = nvfx->screen->vp_exec_heap;
1202 uint vplen = vp->nr_insns;
1203
1204 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
1205 while (heap->next && heap->size < vplen) {
1206 struct nvfx_vertex_program *evict;
1207
1208 evict = heap->next->priv;
1209 nouveau_resource_free(&evict->exec);
1210 }
1211
1212 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
1213 {
1214 debug_printf("Vertex shader too long: %u instructions\n", vplen);
1215 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
1216 return FALSE;
1217 }
1218 }
1219
1220 upload_code = TRUE;
1221 }
1222
1223 /* Allocate hw vtxprog const slots */
1224 if (vp->nr_consts && !vp->data) {
1225 struct nouveau_resource *heap = nvfx->screen->vp_data_heap;
1226
1227 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
1228 while (heap->next && heap->size < vp->nr_consts) {
1229 struct nvfx_vertex_program *evict;
1230
1231 evict = heap->next->priv;
1232 nouveau_resource_free(&evict->data);
1233 }
1234
1235 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
1236 {
1237 debug_printf("Vertex shader uses too many constants: %u constants\n", vp->nr_consts);
1238 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
1239 return FALSE;
1240 }
1241 }
1242
1243 //printf("start at %u nc %u\n", vp->data->start, vp->nr_consts);
1244
1245 /*XXX: handle this some day */
1246 assert(vp->data->start >= vp->data_start_min);
1247
1248 upload_data = TRUE;
1249 if (vp->data_start != vp->data->start)
1250 upload_code = TRUE;
1251 }
1252
1253 /* If exec or data segments moved we need to patch the program to
1254 * fixup offsets and register IDs.
1255 */
1256 if (vp->exec_start != vp->exec->start) {
1257 //printf("vp_relocs %u -> %u\n", vp->exec_start, vp->exec->start);
1258 for(unsigned i = 0; i < vp->branch_relocs.size; i += sizeof(struct nvfx_relocation))
1259 {
1260 struct nvfx_relocation* reloc = (struct nvfx_relocation*)((char*)vp->branch_relocs.data + i);
1261 uint32_t* hw = vp->insns[reloc->location].data;
1262 unsigned target = vp->exec->start + reloc->target;
1263
1264 //debug_printf("vp_reloc hw %u -> hw %u\n", reloc->location, target);
1265
1266 if(!nvfx->is_nv4x)
1267 {
1268 hw[2] &=~ NV30_VP_INST_IADDR_MASK;
1269 hw[2] |= (target & 0x1ff) << NV30_VP_INST_IADDR_SHIFT;
1270 }
1271 else
1272 {
1273 hw[3] &=~ NV40_VP_INST_IADDRL_MASK;
1274 hw[3] |= (target & 7) << NV40_VP_INST_IADDRL_SHIFT;
1275
1276 hw[2] &=~ NV40_VP_INST_IADDRH_MASK;
1277 hw[2] |= ((target >> 3) & 0x3f) << NV40_VP_INST_IADDRH_SHIFT;
1278 }
1279 }
1280
1281 vp->exec_start = vp->exec->start;
1282 }
1283
1284 if (vp->data_start != vp->data->start) {
1285 for(unsigned i = 0; i < vp->const_relocs.size; i += sizeof(struct nvfx_relocation))
1286 {
1287 struct nvfx_relocation* reloc = (struct nvfx_relocation*)((char*)vp->const_relocs.data + i);
1288 struct nvfx_vertex_program_exec *vpi = &vp->insns[reloc->location];
1289
1290 //printf("reloc %i to %i + %i\n", reloc->location, vp->data->start, reloc->target);
1291
1292 vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
1293 vpi->data[1] |=
1294 (reloc->target + vp->data->start) <<
1295 NVFX_VP(INST_CONST_SRC_SHIFT);
1296 }
1297
1298 vp->data_start = vp->data->start;
1299 upload_code = TRUE;
1300 }
1301
1302 /* Update + Upload constant values */
1303 if (vp->nr_consts) {
1304 float *map = NULL;
1305
1306 if (constbuf)
1307 map = (float*)nvfx_buffer(constbuf)->data;
1308
1309 /*
1310 * WAIT_RING(chan, 512 * 6);
1311 for (i = 0; i < 512; i++) {
1312 float v[4] = {0.1, 0,2, 0.3, 0.4};
1313 OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5));
1314 OUT_RING(chan, i);
1315 OUT_RINGp(chan, (uint32_t *)v, 4);
1316 printf("frob %i\n", i);
1317 }
1318 */
1319
1320 WAIT_RING(chan, 6 * vp->nr_consts);
1321 for (i = nvfx->use_vp_clipping ? 6 : 0; i < vp->nr_consts; i++) {
1322 struct nvfx_vertex_program_data *vpd = &vp->consts[i];
1323
1324 if (vpd->index >= 0) {
1325 if (!upload_data &&
1326 !memcmp(vpd->value, &map[vpd->index * 4],
1327 4 * sizeof(float)))
1328 continue;
1329 memcpy(vpd->value, &map[vpd->index * 4],
1330 4 * sizeof(float));
1331 }
1332
1333 //printf("upload into %i + %i: %f %f %f %f\n", vp->data->start, i, vpd->value[0], vpd->value[1], vpd->value[2], vpd->value[3]);
1334
1335 OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_CONST_ID, 5));
1336 OUT_RING(chan, i + vp->data->start);
1337 OUT_RINGp(chan, (uint32_t *)vpd->value, 4);
1338 }
1339 }
1340
1341 /* Upload vtxprog */
1342 if (upload_code) {
1343 WAIT_RING(chan, 2 + 5 * vp->nr_insns);
1344 OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_FROM_ID, 1));
1345 OUT_RING(chan, vp->exec->start);
1346 for (i = 0; i < vp->nr_insns; i++) {
1347 OUT_RING(chan, RING_3D(NV30_3D_VP_UPLOAD_INST(0), 4));
1348 //printf("%08x %08x %08x %08x\n", vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]);
1349 OUT_RINGp(chan, vp->insns[i].data, 4);
1350 }
1351 vp->clip_nr = -1;
1352 }
1353
1354 if(nvfx->dirty & (NVFX_NEW_VERTPROG))
1355 {
1356 WAIT_RING(chan, 6);
1357 OUT_RING(chan, RING_3D(NV30_3D_VP_START_FROM_ID, 1));
1358 OUT_RING(chan, vp->exec->start);
1359 if(nvfx->is_nv4x) {
1360 OUT_RING(chan, RING_3D(NV40_3D_VP_ATTRIB_EN, 1));
1361 OUT_RING(chan, vp->ir);
1362 }
1363 }
1364
1365 return TRUE;
1366 }
1367
1368 void
1369 nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
1370 {
1371 if (vp->nr_insns)
1372 FREE(vp->insns);
1373
1374 if (vp->nr_consts)
1375 FREE(vp->consts);
1376
1377 nouveau_resource_free(&vp->exec);
1378 nouveau_resource_free(&vp->data);
1379
1380 util_dynarray_fini(&vp->branch_relocs);
1381 util_dynarray_fini(&vp->const_relocs);
1382 FREE(vp);
1383 }
1384
1385 static void *
1386 nvfx_vp_state_create(struct pipe_context *pipe, const struct pipe_shader_state *cso)
1387 {
1388 struct nvfx_context *nvfx = nvfx_context(pipe);
1389 struct nvfx_pipe_vertex_program *pvp;
1390
1391 pvp = CALLOC(1, sizeof(struct nvfx_pipe_vertex_program));
1392 pvp->pipe.tokens = tgsi_dup_tokens(cso->tokens);
1393 tgsi_scan_shader(pvp->pipe.tokens, &pvp->info);
1394 pvp->draw_elements = MAX2(1, MIN2(pvp->info.num_outputs, 16));
1395 pvp->draw_no_elements = pvp->info.num_outputs == 0;
1396
1397 return (void *)pvp;
1398 }
1399
1400 static void
1401 nvfx_vp_state_bind(struct pipe_context *pipe, void *hwcso)
1402 {
1403 struct nvfx_context *nvfx = nvfx_context(pipe);
1404
1405 nvfx->vertprog = hwcso;
1406 nvfx->dirty |= NVFX_NEW_VERTPROG;
1407 nvfx->draw_dirty |= NVFX_NEW_VERTPROG;
1408 }
1409
1410 static void
1411 nvfx_vp_state_delete(struct pipe_context *pipe, void *hwcso)
1412 {
1413 struct nvfx_context *nvfx = nvfx_context(pipe);
1414 struct nvfx_pipe_vertex_program *pvp = hwcso;
1415
1416 if(pvp->draw_vs)
1417 draw_delete_vertex_shader(nvfx->draw, pvp->draw_vs);
1418 if(pvp->vp && pvp->vp != NVFX_VP_FAILED)
1419 nvfx_vertprog_destroy(nvfx, pvp->vp);
1420 if(pvp->draw_vp)
1421 nvfx_vertprog_destroy(nvfx, pvp->draw_vp);
1422 FREE((void*)pvp->pipe.tokens);
1423 FREE(pvp);
1424 }
1425
1426 void
1427 nvfx_init_vertprog_functions(struct nvfx_context *nvfx)
1428 {
1429 nvfx->pipe.create_vs_state = nvfx_vp_state_create;
1430 nvfx->pipe.bind_vs_state = nvfx_vp_state_bind;
1431 nvfx->pipe.delete_vs_state = nvfx_vp_state_delete;
1432 }