1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_linkage.h"
5 #include "util/u_debug.h"
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_dump.h"
10 #include "tgsi/tgsi_util.h"
12 #include "nvfx_context.h"
13 #include "nvfx_state.h"
14 #include "nvfx_resource.h"
16 /* TODO (at least...):
17 * 1. Indexed consts + ARL
18 * 3. NV_vp11, NV_vp2, NV_vp3 features
19 * - extra arith opcodes
27 #include "nv30_vertprog.h"
28 #include "nv40_vertprog.h"
30 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
32 struct nvfx_loop_entry
39 struct nvfx_context
* nvfx
;
40 struct nvfx_vertex_program
*vp
;
42 struct nvfx_vertex_program_exec
*vpi
;
45 unsigned r_temps_discard
;
46 struct nvfx_reg r_result
[PIPE_MAX_SHADER_OUTPUTS
];
47 struct nvfx_reg
*r_address
;
48 struct nvfx_reg
*r_temp
;
55 struct util_dynarray label_relocs
;
56 struct util_dynarray loop_stack
;
59 static struct nvfx_reg
60 temp(struct nvfx_vpc
*vpc
)
62 int idx
= ffs(~vpc
->r_temps
) - 1;
65 NOUVEAU_ERR("out of temps!!\n");
67 return nvfx_reg(NVFXSR_TEMP
, 0);
70 vpc
->r_temps
|= (1 << idx
);
71 vpc
->r_temps_discard
|= (1 << idx
);
72 return nvfx_reg(NVFXSR_TEMP
, idx
);
76 release_temps(struct nvfx_vpc
*vpc
)
78 vpc
->r_temps
&= ~vpc
->r_temps_discard
;
79 vpc
->r_temps_discard
= 0;
82 static struct nvfx_reg
83 constant(struct nvfx_vpc
*vpc
, int pipe
, float x
, float y
, float z
, float w
)
85 struct nvfx_vertex_program
*vp
= vpc
->vp
;
86 struct nvfx_vertex_program_data
*vpd
;
90 for (idx
= 0; idx
< vp
->nr_consts
; idx
++) {
91 if (vp
->consts
[idx
].index
== pipe
)
92 return nvfx_reg(NVFXSR_CONST
, idx
);
96 idx
= vp
->nr_consts
++;
97 vp
->consts
= realloc(vp
->consts
, sizeof(*vpd
) * vp
->nr_consts
);
98 vpd
= &vp
->consts
[idx
];
105 return nvfx_reg(NVFXSR_CONST
, idx
);
108 #define arith(s,o,d,m,s0,s1,s2) \
109 nvfx_insn(0, (NVFX_VP_INST_SLOT_##s << 7) | NVFX_VP_INST_##s##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
112 emit_src(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
, uint32_t *hw
, int pos
, struct nvfx_src src
)
114 struct nvfx_vertex_program
*vp
= vpc
->vp
;
117 switch (src
.reg
.type
) {
119 sr
|= (NVFX_VP(SRC_REG_TYPE_TEMP
) << NVFX_VP(SRC_REG_TYPE_SHIFT
));
120 sr
|= (src
.reg
.index
<< NVFX_VP(SRC_TEMP_SRC_SHIFT
));
123 sr
|= (NVFX_VP(SRC_REG_TYPE_INPUT
) <<
124 NVFX_VP(SRC_REG_TYPE_SHIFT
));
125 vp
->ir
|= (1 << src
.reg
.index
);
126 hw
[1] |= (src
.reg
.index
<< NVFX_VP(INST_INPUT_SRC_SHIFT
));
129 sr
|= (NVFX_VP(SRC_REG_TYPE_CONST
) <<
130 NVFX_VP(SRC_REG_TYPE_SHIFT
));
131 assert(vpc
->vpi
->const_index
== -1 ||
132 vpc
->vpi
->const_index
== src
.reg
.index
);
133 vpc
->vpi
->const_index
= src
.reg
.index
;
136 sr
|= (NVFX_VP(SRC_REG_TYPE_INPUT
) <<
137 NVFX_VP(SRC_REG_TYPE_SHIFT
));
144 sr
|= NVFX_VP(SRC_NEGATE
);
147 hw
[0] |= (1 << (21 + pos
));
149 sr
|= ((src
.swz
[0] << NVFX_VP(SRC_SWZ_X_SHIFT
)) |
150 (src
.swz
[1] << NVFX_VP(SRC_SWZ_Y_SHIFT
)) |
151 (src
.swz
[2] << NVFX_VP(SRC_SWZ_Z_SHIFT
)) |
152 (src
.swz
[3] << NVFX_VP(SRC_SWZ_W_SHIFT
)));
156 hw
[1] |= ((sr
& NVFX_VP(SRC0_HIGH_MASK
)) >>
157 NVFX_VP(SRC0_HIGH_SHIFT
)) << NVFX_VP(INST_SRC0H_SHIFT
);
158 hw
[2] |= (sr
& NVFX_VP(SRC0_LOW_MASK
)) <<
159 NVFX_VP(INST_SRC0L_SHIFT
);
162 hw
[2] |= sr
<< NVFX_VP(INST_SRC1_SHIFT
);
165 hw
[2] |= ((sr
& NVFX_VP(SRC2_HIGH_MASK
)) >>
166 NVFX_VP(SRC2_HIGH_SHIFT
)) << NVFX_VP(INST_SRC2H_SHIFT
);
167 hw
[3] |= (sr
& NVFX_VP(SRC2_LOW_MASK
)) <<
168 NVFX_VP(INST_SRC2L_SHIFT
);
176 emit_dst(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
, uint32_t *hw
, int slot
, struct nvfx_reg dst
)
178 struct nvfx_vertex_program
*vp
= vpc
->vp
;
183 hw
[0] |= NV30_VP_INST_DEST_TEMP_ID_MASK
;
185 hw
[3] |= NV40_VP_INST_DEST_MASK
;
187 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
;
189 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
194 hw
[0] |= (dst
.index
<< NV30_VP_INST_DEST_TEMP_ID_SHIFT
);
196 hw
[3] |= NV40_VP_INST_DEST_MASK
;
198 hw
[0] |= (dst
.index
<< NV40_VP_INST_VEC_DEST_TEMP_SHIFT
);
200 hw
[3] |= (dst
.index
<< NV40_VP_INST_SCA_DEST_TEMP_SHIFT
);
204 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
206 case NVFX_VP_INST_DEST_CLIP(0):
208 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0
;
209 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
211 case NVFX_VP_INST_DEST_CLIP(1):
213 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1
;
214 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
216 case NVFX_VP_INST_DEST_CLIP(2):
218 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2
;
219 dst
.index
= NVFX_VP(INST_DEST_FOGC
);
221 case NVFX_VP_INST_DEST_CLIP(3):
223 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3
;
224 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
226 case NVFX_VP_INST_DEST_CLIP(4):
228 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4
;
229 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
231 case NVFX_VP_INST_DEST_CLIP(5):
233 vp
->clip_ctrl
|= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5
;
234 dst
.index
= NVFX_VP(INST_DEST_PSZ
);
239 case NV30_VP_INST_DEST_COL0
: vp
->or |= (1 << 0); break;
240 case NV30_VP_INST_DEST_COL1
: vp
->or |= (1 << 1); break;
241 case NV30_VP_INST_DEST_BFC0
: vp
->or |= (1 << 2); break;
242 case NV30_VP_INST_DEST_BFC1
: vp
->or |= (1 << 3); break;
243 case NV30_VP_INST_DEST_FOGC
: vp
->or |= (1 << 4); break;
244 case NV30_VP_INST_DEST_PSZ
: vp
->or |= (1 << 5); break;
245 case NV30_VP_INST_DEST_TC(0): vp
->or |= (1 << 14); break;
246 case NV30_VP_INST_DEST_TC(1): vp
->or |= (1 << 15); break;
247 case NV30_VP_INST_DEST_TC(2): vp
->or |= (1 << 16); break;
248 case NV30_VP_INST_DEST_TC(3): vp
->or |= (1 << 17); break;
249 case NV30_VP_INST_DEST_TC(4): vp
->or |= (1 << 18); break;
250 case NV30_VP_INST_DEST_TC(5): vp
->or |= (1 << 19); break;
251 case NV30_VP_INST_DEST_TC(6): vp
->or |= (1 << 20); break;
252 case NV30_VP_INST_DEST_TC(7): vp
->or |= (1 << 21); break;
256 case NV40_VP_INST_DEST_COL0
: vp
->or |= (1 << 0); break;
257 case NV40_VP_INST_DEST_COL1
: vp
->or |= (1 << 1); break;
258 case NV40_VP_INST_DEST_BFC0
: vp
->or |= (1 << 2); break;
259 case NV40_VP_INST_DEST_BFC1
: vp
->or |= (1 << 3); break;
260 case NV40_VP_INST_DEST_FOGC
: vp
->or |= (1 << 4); break;
261 case NV40_VP_INST_DEST_PSZ
: vp
->or |= (1 << 5); break;
262 case NV40_VP_INST_DEST_TC(0): vp
->or |= (1 << 14); break;
263 case NV40_VP_INST_DEST_TC(1): vp
->or |= (1 << 15); break;
264 case NV40_VP_INST_DEST_TC(2): vp
->or |= (1 << 16); break;
265 case NV40_VP_INST_DEST_TC(3): vp
->or |= (1 << 17); break;
266 case NV40_VP_INST_DEST_TC(4): vp
->or |= (1 << 18); break;
267 case NV40_VP_INST_DEST_TC(5): vp
->or |= (1 << 19); break;
268 case NV40_VP_INST_DEST_TC(6): vp
->or |= (1 << 20); break;
269 case NV40_VP_INST_DEST_TC(7): vp
->or |= (1 << 21); break;
276 hw
[3] |= (dst
.index
<< NV30_VP_INST_DEST_SHIFT
);
277 hw
[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK
;
279 /*XXX: no way this is entirely correct, someone needs to
280 * figure out what exactly it is.
284 hw
[3] |= (dst
.index
<< NV40_VP_INST_DEST_SHIFT
);
286 hw
[0] |= NV40_VP_INST_VEC_RESULT
;
287 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
;
289 hw
[3] |= NV40_VP_INST_SCA_RESULT
;
290 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
300 nvfx_vp_emit(struct nvfx_vpc
*vpc
, struct nvfx_insn insn
)
302 struct nvfx_context
* nvfx
= vpc
->nvfx
;
303 struct nvfx_vertex_program
*vp
= vpc
->vp
;
304 unsigned slot
= insn
.op
>> 7;
305 unsigned op
= insn
.op
& 0x7f;
308 vp
->insns
= realloc(vp
->insns
, ++vp
->nr_insns
* sizeof(*vpc
->vpi
));
309 vpc
->vpi
= &vp
->insns
[vp
->nr_insns
- 1];
310 memset(vpc
->vpi
, 0, sizeof(*vpc
->vpi
));
311 vpc
->vpi
->const_index
= -1;
315 hw
[0] |= (insn
.cc_test
<< NVFX_VP(INST_COND_SHIFT
));
316 hw
[0] |= ((insn
.cc_swz
[0] << NVFX_VP(INST_COND_SWZ_X_SHIFT
)) |
317 (insn
.cc_swz
[1] << NVFX_VP(INST_COND_SWZ_Y_SHIFT
)) |
318 (insn
.cc_swz
[2] << NVFX_VP(INST_COND_SWZ_Z_SHIFT
)) |
319 (insn
.cc_swz
[3] << NVFX_VP(INST_COND_SWZ_W_SHIFT
)));
321 hw
[0] |= NVFX_VP(INST_COND_UPDATE_ENABLE
);
325 hw
[1] |= (op
<< NV30_VP_INST_VEC_OPCODE_SHIFT
);
328 hw
[0] |= ((op
>> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT
);
329 hw
[1] |= ((op
& 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT
);
331 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
332 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
334 if (insn
.dst
.type
== NVFXSR_OUTPUT
) {
336 hw
[3] |= (insn
.mask
<< NV30_VP_INST_SDEST_WRITEMASK_SHIFT
);
338 hw
[3] |= (insn
.mask
<< NV30_VP_INST_VDEST_WRITEMASK_SHIFT
);
341 hw
[3] |= (insn
.mask
<< NV30_VP_INST_STEMP_WRITEMASK_SHIFT
);
343 hw
[3] |= (insn
.mask
<< NV30_VP_INST_VTEMP_WRITEMASK_SHIFT
);
347 hw
[1] |= (op
<< NV40_VP_INST_VEC_OPCODE_SHIFT
);
348 hw
[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK
;
349 hw
[3] |= (insn
.mask
<< NV40_VP_INST_VEC_WRITEMASK_SHIFT
);
351 hw
[1] |= (op
<< NV40_VP_INST_SCA_OPCODE_SHIFT
);
352 hw
[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK
;
353 hw
[3] |= (insn
.mask
<< NV40_VP_INST_SCA_WRITEMASK_SHIFT
);
357 emit_dst(nvfx
, vpc
, hw
, slot
, insn
.dst
);
358 emit_src(nvfx
, vpc
, hw
, 0, insn
.src
[0]);
359 emit_src(nvfx
, vpc
, hw
, 1, insn
.src
[1]);
360 emit_src(nvfx
, vpc
, hw
, 2, insn
.src
[2]);
363 static inline struct nvfx_src
364 tgsi_src(struct nvfx_vpc
*vpc
, const struct tgsi_full_src_register
*fsrc
) {
367 switch (fsrc
->Register
.File
) {
368 case TGSI_FILE_INPUT
:
369 src
.reg
= nvfx_reg(NVFXSR_INPUT
, fsrc
->Register
.Index
);
371 case TGSI_FILE_CONSTANT
:
372 src
.reg
= constant(vpc
, fsrc
->Register
.Index
, 0, 0, 0, 0);
374 case TGSI_FILE_IMMEDIATE
:
375 src
.reg
= vpc
->imm
[fsrc
->Register
.Index
];
377 case TGSI_FILE_TEMPORARY
:
378 src
.reg
= vpc
->r_temp
[fsrc
->Register
.Index
];
381 NOUVEAU_ERR("bad src file\n");
385 src
.abs
= fsrc
->Register
.Absolute
;
386 src
.negate
= fsrc
->Register
.Negate
;
387 src
.swz
[0] = fsrc
->Register
.SwizzleX
;
388 src
.swz
[1] = fsrc
->Register
.SwizzleY
;
389 src
.swz
[2] = fsrc
->Register
.SwizzleZ
;
390 src
.swz
[3] = fsrc
->Register
.SwizzleW
;
394 static INLINE
struct nvfx_reg
395 tgsi_dst(struct nvfx_vpc
*vpc
, const struct tgsi_full_dst_register
*fdst
) {
398 switch (fdst
->Register
.File
) {
400 dst
= nvfx_reg(NVFXSR_NONE
, 0);
402 case TGSI_FILE_OUTPUT
:
403 dst
= vpc
->r_result
[fdst
->Register
.Index
];
405 case TGSI_FILE_TEMPORARY
:
406 dst
= vpc
->r_temp
[fdst
->Register
.Index
];
408 case TGSI_FILE_ADDRESS
:
409 dst
= vpc
->r_address
[fdst
->Register
.Index
];
412 NOUVEAU_ERR("bad dst file %i\n", fdst
->Register
.File
);
424 if (tgsi
& TGSI_WRITEMASK_X
) mask
|= NVFX_VP_MASK_X
;
425 if (tgsi
& TGSI_WRITEMASK_Y
) mask
|= NVFX_VP_MASK_Y
;
426 if (tgsi
& TGSI_WRITEMASK_Z
) mask
|= NVFX_VP_MASK_Z
;
427 if (tgsi
& TGSI_WRITEMASK_W
) mask
|= NVFX_VP_MASK_W
;
432 nvfx_vertprog_parse_instruction(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
,
433 unsigned idx
, const struct tgsi_full_instruction
*finst
)
435 struct nvfx_src src
[3], tmp
;
437 struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
438 struct nvfx_insn insn
;
439 struct nvfx_label_relocation reloc
;
440 struct nvfx_loop_entry loop
;
442 int ai
= -1, ci
= -1, ii
= -1;
445 if (finst
->Instruction
.Opcode
== TGSI_OPCODE_END
)
448 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
449 const struct tgsi_full_src_register
*fsrc
;
451 fsrc
= &finst
->Src
[i
];
452 if (fsrc
->Register
.File
== TGSI_FILE_TEMPORARY
) {
453 src
[i
] = tgsi_src(vpc
, fsrc
);
457 for (i
= 0; i
< finst
->Instruction
.NumSrcRegs
; i
++) {
458 const struct tgsi_full_src_register
*fsrc
;
460 fsrc
= &finst
->Src
[i
];
462 switch (fsrc
->Register
.File
) {
463 case TGSI_FILE_INPUT
:
464 if (ai
== -1 || ai
== fsrc
->Register
.Index
) {
465 ai
= fsrc
->Register
.Index
;
466 src
[i
] = tgsi_src(vpc
, fsrc
);
468 src
[i
] = nvfx_src(temp(vpc
));
469 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
, tgsi_src(vpc
, fsrc
), none
, none
));
472 case TGSI_FILE_CONSTANT
:
473 if ((ci
== -1 && ii
== -1) ||
474 ci
== fsrc
->Register
.Index
) {
475 ci
= fsrc
->Register
.Index
;
476 src
[i
] = tgsi_src(vpc
, fsrc
);
478 src
[i
] = nvfx_src(temp(vpc
));
479 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
, tgsi_src(vpc
, fsrc
), none
, none
));
482 case TGSI_FILE_IMMEDIATE
:
483 if ((ci
== -1 && ii
== -1) ||
484 ii
== fsrc
->Register
.Index
) {
485 ii
= fsrc
->Register
.Index
;
486 src
[i
] = tgsi_src(vpc
, fsrc
);
488 src
[i
] = nvfx_src(temp(vpc
));
489 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, src
[i
].reg
, NVFX_VP_MASK_ALL
, tgsi_src(vpc
, fsrc
), none
, none
));
492 case TGSI_FILE_TEMPORARY
:
496 NOUVEAU_ERR("bad src file\n");
501 dst
= tgsi_dst(vpc
, &finst
->Dst
[0]);
502 mask
= tgsi_mask(finst
->Dst
[0].Register
.WriteMask
);
504 switch (finst
->Instruction
.Opcode
) {
505 case TGSI_OPCODE_ABS
:
506 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, dst
, mask
, abs(src
[0]), none
, none
));
508 case TGSI_OPCODE_ADD
:
509 nvfx_vp_emit(vpc
, arith(VEC
, ADD
, dst
, mask
, src
[0], none
, src
[1]));
511 case TGSI_OPCODE_ARL
:
512 nvfx_vp_emit(vpc
, arith(VEC
, ARL
, dst
, mask
, src
[0], none
, none
));
514 case TGSI_OPCODE_CMP
:
515 insn
= arith(VEC
, MOV
, none
.reg
, mask
, src
[0], none
, none
);
517 nvfx_vp_emit(vpc
, insn
);
519 insn
= arith(VEC
, MOV
, dst
, mask
, src
[2], none
, none
);
520 insn
.cc_test
= NVFX_COND_GE
;
521 nvfx_vp_emit(vpc
, insn
);
523 insn
= arith(VEC
, MOV
, dst
, mask
, src
[1], none
, none
);
524 insn
.cc_test
= NVFX_COND_LT
;
525 nvfx_vp_emit(vpc
, insn
);
527 case TGSI_OPCODE_COS
:
528 nvfx_vp_emit(vpc
, arith(SCA
, COS
, dst
, mask
, none
, none
, src
[0]));
530 case TGSI_OPCODE_DP2
:
531 tmp
= nvfx_src(temp(vpc
));
532 nvfx_vp_emit(vpc
, arith(VEC
, MUL
, tmp
.reg
, NVFX_VP_MASK_X
| NVFX_VP_MASK_Y
, src
[0], src
[1], none
));
533 nvfx_vp_emit(vpc
, arith(VEC
, ADD
, dst
, mask
, swz(tmp
, X
, X
, X
, X
), swz(tmp
, Y
, Y
, Y
, Y
), none
));
535 case TGSI_OPCODE_DP3
:
536 nvfx_vp_emit(vpc
, arith(VEC
, DP3
, dst
, mask
, src
[0], src
[1], none
));
538 case TGSI_OPCODE_DP4
:
539 nvfx_vp_emit(vpc
, arith(VEC
, DP4
, dst
, mask
, src
[0], src
[1], none
));
541 case TGSI_OPCODE_DPH
:
542 nvfx_vp_emit(vpc
, arith(VEC
, DPH
, dst
, mask
, src
[0], src
[1], none
));
544 case TGSI_OPCODE_DST
:
545 nvfx_vp_emit(vpc
, arith(VEC
, DST
, dst
, mask
, src
[0], src
[1], none
));
547 case TGSI_OPCODE_EX2
:
548 nvfx_vp_emit(vpc
, arith(SCA
, EX2
, dst
, mask
, none
, none
, src
[0]));
550 case TGSI_OPCODE_EXP
:
551 nvfx_vp_emit(vpc
, arith(SCA
, EXP
, dst
, mask
, none
, none
, src
[0]));
553 case TGSI_OPCODE_FLR
:
554 nvfx_vp_emit(vpc
, arith(VEC
, FLR
, dst
, mask
, src
[0], none
, none
));
556 case TGSI_OPCODE_FRC
:
557 nvfx_vp_emit(vpc
, arith(VEC
, FRC
, dst
, mask
, src
[0], none
, none
));
559 case TGSI_OPCODE_LG2
:
560 nvfx_vp_emit(vpc
, arith(SCA
, LG2
, dst
, mask
, none
, none
, src
[0]));
562 case TGSI_OPCODE_LIT
:
563 nvfx_vp_emit(vpc
, arith(SCA
, LIT
, dst
, mask
, none
, none
, src
[0]));
565 case TGSI_OPCODE_LOG
:
566 nvfx_vp_emit(vpc
, arith(SCA
, LOG
, dst
, mask
, none
, none
, src
[0]));
568 case TGSI_OPCODE_LRP
:
569 tmp
= nvfx_src(temp(vpc
));
570 nvfx_vp_emit(vpc
, arith(VEC
, MAD
, tmp
.reg
, mask
, neg(src
[0]), src
[2], src
[2]));
571 nvfx_vp_emit(vpc
, arith(VEC
, MAD
, dst
, mask
, src
[0], src
[1], tmp
));
573 case TGSI_OPCODE_MAD
:
574 nvfx_vp_emit(vpc
, arith(VEC
, MAD
, dst
, mask
, src
[0], src
[1], src
[2]));
576 case TGSI_OPCODE_MAX
:
577 nvfx_vp_emit(vpc
, arith(VEC
, MAX
, dst
, mask
, src
[0], src
[1], none
));
579 case TGSI_OPCODE_MIN
:
580 nvfx_vp_emit(vpc
, arith(VEC
, MIN
, dst
, mask
, src
[0], src
[1], none
));
582 case TGSI_OPCODE_MOV
:
583 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, dst
, mask
, src
[0], none
, none
));
585 case TGSI_OPCODE_MUL
:
586 nvfx_vp_emit(vpc
, arith(VEC
, MUL
, dst
, mask
, src
[0], src
[1], none
));
588 case TGSI_OPCODE_NOP
:
590 case TGSI_OPCODE_POW
:
591 tmp
= nvfx_src(temp(vpc
));
592 nvfx_vp_emit(vpc
, arith(SCA
, LG2
, tmp
.reg
, NVFX_VP_MASK_X
, none
, none
, swz(src
[0], X
, X
, X
, X
)));
593 nvfx_vp_emit(vpc
, arith(VEC
, MUL
, tmp
.reg
, NVFX_VP_MASK_X
, swz(tmp
, X
, X
, X
, X
), swz(src
[1], X
, X
, X
, X
), none
));
594 nvfx_vp_emit(vpc
, arith(SCA
, EX2
, dst
, mask
, none
, none
, swz(tmp
, X
, X
, X
, X
)));
596 case TGSI_OPCODE_RCP
:
597 nvfx_vp_emit(vpc
, arith(SCA
, RCP
, dst
, mask
, none
, none
, src
[0]));
599 case TGSI_OPCODE_RSQ
:
600 nvfx_vp_emit(vpc
, arith(SCA
, RSQ
, dst
, mask
, none
, none
, abs(src
[0])));
602 case TGSI_OPCODE_SEQ
:
603 nvfx_vp_emit(vpc
, arith(VEC
, SEQ
, dst
, mask
, src
[0], src
[1], none
));
605 case TGSI_OPCODE_SFL
:
606 nvfx_vp_emit(vpc
, arith(VEC
, SFL
, dst
, mask
, src
[0], src
[1], none
));
608 case TGSI_OPCODE_SGE
:
609 nvfx_vp_emit(vpc
, arith(VEC
, SGE
, dst
, mask
, src
[0], src
[1], none
));
611 case TGSI_OPCODE_SGT
:
612 nvfx_vp_emit(vpc
, arith(VEC
, SGT
, dst
, mask
, src
[0], src
[1], none
));
614 case TGSI_OPCODE_SIN
:
615 nvfx_vp_emit(vpc
, arith(SCA
, SIN
, dst
, mask
, none
, none
, src
[0]));
617 case TGSI_OPCODE_SLE
:
618 nvfx_vp_emit(vpc
, arith(VEC
, SLE
, dst
, mask
, src
[0], src
[1], none
));
620 case TGSI_OPCODE_SLT
:
621 nvfx_vp_emit(vpc
, arith(VEC
, SLT
, dst
, mask
, src
[0], src
[1], none
));
623 case TGSI_OPCODE_SNE
:
624 nvfx_vp_emit(vpc
, arith(VEC
, SNE
, dst
, mask
, src
[0], src
[1], none
));
626 case TGSI_OPCODE_SSG
:
627 nvfx_vp_emit(vpc
, arith(VEC
, SSG
, dst
, mask
, src
[0], src
[1], none
));
629 case TGSI_OPCODE_STR
:
630 nvfx_vp_emit(vpc
, arith(VEC
, STR
, dst
, mask
, src
[0], src
[1], none
));
632 case TGSI_OPCODE_SUB
:
633 nvfx_vp_emit(vpc
, arith(VEC
, ADD
, dst
, mask
, src
[0], none
, neg(src
[1])));
635 case TGSI_OPCODE_TRUNC
:
636 tmp
= nvfx_src(temp(vpc
));
637 insn
= arith(VEC
, MOV
, none
.reg
, mask
, src
[0], none
, none
);
639 nvfx_vp_emit(vpc
, insn
);
641 nvfx_vp_emit(vpc
, arith(VEC
, FLR
, tmp
.reg
, mask
, abs(src
[0]), none
, none
));
642 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, dst
, mask
, tmp
, none
, none
));
644 insn
= arith(VEC
, MOV
, dst
, mask
, neg(tmp
), none
, none
);
645 insn
.cc_test
= NVFX_COND_LT
;
646 nvfx_vp_emit(vpc
, insn
);
648 case TGSI_OPCODE_XPD
:
649 tmp
= nvfx_src(temp(vpc
));
650 nvfx_vp_emit(vpc
, arith(VEC
, MUL
, tmp
.reg
, mask
, swz(src
[0], Z
, X
, Y
, Y
), swz(src
[1], Y
, Z
, X
, X
), none
));
651 nvfx_vp_emit(vpc
, arith(VEC
, MAD
, dst
, (mask
& ~NVFX_VP_MASK_W
), swz(src
[0], Y
, Z
, X
, X
), swz(src
[1], Z
, X
, Y
, Y
), neg(tmp
)));
655 insn
= arith(VEC
, MOV
, none
.reg
, NVFX_VP_MASK_X
, src
[0], none
, none
);
657 nvfx_vp_emit(vpc
, insn
);
659 reloc
.location
= vpc
->vp
->nr_insns
;
660 reloc
.target
= finst
->Label
.Label
+ 1;
661 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_label_relocation
, reloc
);
663 insn
= arith(SCA
, BRA
, none
.reg
, 0, none
, none
, none
);
664 insn
.cc_test
= NVFX_COND_EQ
;
665 insn
.cc_swz
[0] = insn
.cc_swz
[1] = insn
.cc_swz
[2] = insn
.cc_swz
[3] = 0;
666 nvfx_vp_emit(vpc
, insn
);
669 case TGSI_OPCODE_ELSE
:
670 case TGSI_OPCODE_BRA
:
671 case TGSI_OPCODE_CAL
:
672 reloc
.location
= vpc
->vp
->nr_insns
;
673 reloc
.target
= finst
->Label
.Label
;
674 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_label_relocation
, reloc
);
676 if(finst
->Instruction
.Opcode
== TGSI_OPCODE_CAL
)
677 insn
= arith(SCA
, CAL
, none
.reg
, 0, none
, none
, none
);
679 insn
= arith(SCA
, BRA
, none
.reg
, 0, none
, none
, none
);
680 nvfx_vp_emit(vpc
, insn
);
683 case TGSI_OPCODE_RET
:
685 tmp
.swz
[0] = tmp
.swz
[1] = tmp
.swz
[2] = tmp
.swz
[3] = 0;
686 nvfx_vp_emit(vpc
, arith(SCA
, RET
, none
.reg
, 0, none
, none
, tmp
));
689 case TGSI_OPCODE_BGNSUB
:
690 case TGSI_OPCODE_ENDSUB
:
691 case TGSI_OPCODE_ENDIF
:
692 /* nothing to do here */
695 case TGSI_OPCODE_BGNLOOP
:
696 loop
.cont_target
= idx
;
697 loop
.brk_target
= finst
->Label
.Label
+ 1;
698 util_dynarray_append(&vpc
->loop_stack
, struct nvfx_loop_entry
, loop
);
701 case TGSI_OPCODE_ENDLOOP
:
702 loop
= util_dynarray_pop(&vpc
->loop_stack
, struct nvfx_loop_entry
);
704 reloc
.location
= vpc
->vp
->nr_insns
;
705 reloc
.target
= loop
.cont_target
;
706 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_label_relocation
, reloc
);
708 nvfx_vp_emit(vpc
, arith(SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
711 case TGSI_OPCODE_CONT
:
712 loop
= util_dynarray_top(&vpc
->loop_stack
, struct nvfx_loop_entry
);
714 reloc
.location
= vpc
->vp
->nr_insns
;
715 reloc
.target
= loop
.cont_target
;
716 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_label_relocation
, reloc
);
718 nvfx_vp_emit(vpc
, arith(SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
721 case TGSI_OPCODE_BRK
:
722 loop
= util_dynarray_top(&vpc
->loop_stack
, struct nvfx_loop_entry
);
724 reloc
.location
= vpc
->vp
->nr_insns
;
725 reloc
.target
= loop
.brk_target
;
726 util_dynarray_append(&vpc
->label_relocs
, struct nvfx_label_relocation
, reloc
);
728 nvfx_vp_emit(vpc
, arith(SCA
, BRA
, none
.reg
, 0, none
, none
, none
));
732 NOUVEAU_ERR("invalid opcode %d\n", finst
->Instruction
.Opcode
);
741 nvfx_vertprog_parse_decl_output(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
,
742 const struct tgsi_full_declaration
*fdec
)
744 unsigned idx
= fdec
->Range
.First
;
747 switch (fdec
->Semantic
.Name
) {
748 case TGSI_SEMANTIC_POSITION
:
749 hw
= NVFX_VP(INST_DEST_POS
);
752 case TGSI_SEMANTIC_COLOR
:
753 if (fdec
->Semantic
.Index
== 0) {
754 hw
= NVFX_VP(INST_DEST_COL0
);
756 if (fdec
->Semantic
.Index
== 1) {
757 hw
= NVFX_VP(INST_DEST_COL1
);
759 NOUVEAU_ERR("bad colour semantic index\n");
763 case TGSI_SEMANTIC_BCOLOR
:
764 if (fdec
->Semantic
.Index
== 0) {
765 hw
= NVFX_VP(INST_DEST_BFC0
);
767 if (fdec
->Semantic
.Index
== 1) {
768 hw
= NVFX_VP(INST_DEST_BFC1
);
770 NOUVEAU_ERR("bad bcolour semantic index\n");
774 case TGSI_SEMANTIC_FOG
:
775 hw
= NVFX_VP(INST_DEST_FOGC
);
777 case TGSI_SEMANTIC_PSIZE
:
778 hw
= NVFX_VP(INST_DEST_PSZ
);
780 case TGSI_SEMANTIC_GENERIC
:
781 hw
= (vpc
->vp
->generic_to_fp_input
[fdec
->Semantic
.Index
] & 0xf)
782 + NVFX_VP(INST_DEST_TC(0)) - NVFX_FP_OP_INPUT_SRC_TC(0);
784 case TGSI_SEMANTIC_EDGEFLAG
:
785 /* not really an error just a fallback */
786 NOUVEAU_ERR("cannot handle edgeflag output\n");
789 NOUVEAU_ERR("bad output semantic\n");
793 vpc
->r_result
[idx
] = nvfx_reg(NVFXSR_OUTPUT
, hw
);
798 nvfx_vertprog_prepare(struct nvfx_context
* nvfx
, struct nvfx_vpc
*vpc
)
800 struct tgsi_parse_context p
;
801 int high_temp
= -1, high_addr
= -1, nr_imm
= 0, i
;
802 struct util_semantic_set set
;
803 unsigned char sem_layout
[8];
804 unsigned sem_layout_size
;
805 unsigned num_outputs
;
807 num_outputs
= util_semantic_set_from_program_file(&set
, vpc
->vp
->pipe
.tokens
, TGSI_FILE_OUTPUT
);
809 if(num_outputs
> 8) {
810 NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs
);
813 util_semantic_layout_from_set(sem_layout
, &set
, 8, 8);
815 /* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */
816 memset(vpc
->vp
->generic_to_fp_input
, 0x0f, sizeof(vpc
->vp
->generic_to_fp_input
));
817 vpc
->vp
->texcoord_ouput_mask
= 0;
818 for(int i
= 0; i
< 8; ++i
) {
819 if(sem_layout
[i
] == 0xff)
821 vpc
->vp
->texcoord_ouput_mask
|= (1 << i
);
822 //printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i);
823 vpc
->vp
->generic_to_fp_input
[sem_layout
[i
]] = 0xf0 | (NVFX_FP_OP_INPUT_SRC_TC(0) + i
);
826 tgsi_parse_init(&p
, vpc
->vp
->pipe
.tokens
);
827 while (!tgsi_parse_end_of_tokens(&p
)) {
828 const union tgsi_full_token
*tok
= &p
.FullToken
;
830 tgsi_parse_token(&p
);
831 switch(tok
->Token
.Type
) {
832 case TGSI_TOKEN_TYPE_IMMEDIATE
:
835 case TGSI_TOKEN_TYPE_DECLARATION
:
837 const struct tgsi_full_declaration
*fdec
;
839 fdec
= &p
.FullToken
.FullDeclaration
;
840 switch (fdec
->Declaration
.File
) {
841 case TGSI_FILE_TEMPORARY
:
842 if (fdec
->Range
.Last
> high_temp
) {
847 #if 0 /* this would be nice.. except gallium doesn't track it */
848 case TGSI_FILE_ADDRESS
:
849 if (fdec
->Range
.Last
> high_addr
) {
855 case TGSI_FILE_OUTPUT
:
856 if (!nvfx_vertprog_parse_decl_output(nvfx
, vpc
, fdec
))
864 #if 1 /* yay, parse instructions looking for address regs instead */
865 case TGSI_TOKEN_TYPE_INSTRUCTION
:
867 const struct tgsi_full_instruction
*finst
;
868 const struct tgsi_full_dst_register
*fdst
;
870 finst
= &p
.FullToken
.FullInstruction
;
871 fdst
= &finst
->Dst
[0];
873 if (fdst
->Register
.File
== TGSI_FILE_ADDRESS
) {
874 if (fdst
->Register
.Index
> high_addr
)
875 high_addr
= fdst
->Register
.Index
;
888 vpc
->imm
= CALLOC(nr_imm
, sizeof(struct nvfx_reg
));
893 vpc
->r_temp
= CALLOC(high_temp
, sizeof(struct nvfx_reg
));
894 for (i
= 0; i
< high_temp
; i
++)
895 vpc
->r_temp
[i
] = temp(vpc
);
899 vpc
->r_address
= CALLOC(high_addr
, sizeof(struct nvfx_reg
));
900 for (i
= 0; i
< high_addr
; i
++)
901 vpc
->r_address
[i
] = temp(vpc
);
904 vpc
->r_temps_discard
= 0;
908 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp
, "NVFX_DUMP_VP", FALSE
)
911 nvfx_vertprog_translate(struct nvfx_context
*nvfx
,
912 struct nvfx_vertex_program
*vp
)
914 struct tgsi_parse_context parse
;
915 struct nvfx_vpc
*vpc
= NULL
;
916 struct nvfx_src none
= nvfx_src(nvfx_reg(NVFXSR_NONE
, 0));
917 struct util_dynarray insns
;
920 vpc
= CALLOC(1, sizeof(struct nvfx_vpc
));
926 if (!nvfx_vertprog_prepare(nvfx
, vpc
)) {
931 /* Redirect post-transform vertex position to a temp if user clip
932 * planes are enabled. We need to append code to the vtxprog
933 * to handle clip planes later.
936 vpc
->r_result
[vpc
->hpos_idx
] = temp(vpc
);
937 vpc
->r_temps_discard
= 0;
940 tgsi_parse_init(&parse
, vp
->pipe
.tokens
);
942 util_dynarray_init(&insns
);
943 while (!tgsi_parse_end_of_tokens(&parse
)) {
944 tgsi_parse_token(&parse
);
946 switch (parse
.FullToken
.Token
.Type
) {
947 case TGSI_TOKEN_TYPE_IMMEDIATE
:
949 const struct tgsi_full_immediate
*imm
;
951 imm
= &parse
.FullToken
.FullImmediate
;
952 assert(imm
->Immediate
.DataType
== TGSI_IMM_FLOAT32
);
953 assert(imm
->Immediate
.NrTokens
== 4 + 1);
954 vpc
->imm
[vpc
->nr_imm
++] =
962 case TGSI_TOKEN_TYPE_INSTRUCTION
:
964 const struct tgsi_full_instruction
*finst
;
965 unsigned idx
= insns
.size
>> 2;
966 util_dynarray_append(&insns
, unsigned, vp
->nr_insns
);
967 finst
= &parse
.FullToken
.FullInstruction
;
968 if (!nvfx_vertprog_parse_instruction(nvfx
, vpc
, idx
, finst
))
977 util_dynarray_append(&insns
, unsigned, vp
->nr_insns
);
979 for(unsigned i
= 0; i
< vpc
->label_relocs
.size
; i
+= sizeof(struct nvfx_label_relocation
))
981 struct nvfx_label_relocation
* label_reloc
= (struct nvfx_label_relocation
*)((char*)vpc
->label_relocs
.data
+ i
);
982 struct nvfx_label_relocation hw_reloc
;
984 hw_reloc
.location
= label_reloc
->location
;
985 hw_reloc
.target
= ((unsigned*)insns
.data
)[label_reloc
->target
];
987 //debug_printf("hw %u -> tgsi %u = hw %u\n", hw_reloc.location, label_reloc->target, hw_reloc.target);
989 util_dynarray_append(&vp
->branch_relocs
, struct nvfx_label_relocation
, hw_reloc
);
991 util_dynarray_fini(&insns
);
992 util_dynarray_trim(&vp
->branch_relocs
);
994 /* XXX: what if we add a RET before?! make sure we jump here...*/
996 /* Write out HPOS if it was redirected to a temp earlier */
997 if (vpc
->r_result
[vpc
->hpos_idx
].type
!= NVFXSR_OUTPUT
) {
998 struct nvfx_reg hpos
= nvfx_reg(NVFXSR_OUTPUT
,
999 NVFX_VP(INST_DEST_POS
));
1000 struct nvfx_src htmp
= nvfx_src(vpc
->r_result
[vpc
->hpos_idx
]);
1002 nvfx_vp_emit(vpc
, arith(VEC
, MOV
, hpos
, NVFX_VP_MASK_ALL
, htmp
, none
, none
));
1005 /* Insert code to handle user clip planes */
1006 for (i
= 0; i
< vp
->ucp
.nr
; i
++) {
1007 struct nvfx_reg cdst
= nvfx_reg(NVFXSR_OUTPUT
,
1008 NVFX_VP_INST_DEST_CLIP(i
));
1009 struct nvfx_src ceqn
= nvfx_src(constant(vpc
, -1,
1010 nvfx
->clip
.ucp
[i
][0],
1011 nvfx
->clip
.ucp
[i
][1],
1012 nvfx
->clip
.ucp
[i
][2],
1013 nvfx
->clip
.ucp
[i
][3]));
1014 struct nvfx_src htmp
= nvfx_src(vpc
->r_result
[vpc
->hpos_idx
]);
1018 case 0: case 3: mask
= NVFX_VP_MASK_Y
; break;
1019 case 1: case 4: mask
= NVFX_VP_MASK_Z
; break;
1020 case 2: case 5: mask
= NVFX_VP_MASK_W
; break;
1022 NOUVEAU_ERR("invalid clip dist #%d\n", i
);
1026 nvfx_vp_emit(vpc
, arith(VEC
, DP4
, cdst
, mask
, htmp
, ceqn
, none
));
1029 //vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
1031 /* Append NOP + END instruction for branches to the end of the program */
1032 nvfx_vp_emit(vpc
, arith(VEC
, NOP
, none
.reg
, 0, none
, none
, none
));
1033 vp
->insns
[vp
->nr_insns
- 1].data
[3] |= NVFX_VP_INST_LAST
| 0x1000;
1035 if(debug_get_option_nvfx_dump_vp())
1038 tgsi_dump(vp
->pipe
.tokens
, 0);
1040 debug_printf("\n%s vertex program:\n", nvfx
->is_nv4x
? "nv4x" : "nv3x");
1041 for (i
= 0; i
< vp
->nr_insns
; i
++)
1042 debug_printf("%3u: %08x %08x %08x %08x\n", i
, vp
->insns
[i
].data
[0], vp
->insns
[i
].data
[1], vp
->insns
[i
].data
[2], vp
->insns
[i
].data
[3]);
1046 vp
->exec_start
= -1;
1047 vp
->translated
= TRUE
;
1049 tgsi_parse_free(&parse
);
1050 util_dynarray_fini(&vpc
->label_relocs
);
1051 util_dynarray_fini(&vpc
->loop_stack
);
1055 FREE(vpc
->r_address
);
1062 nvfx_vertprog_validate(struct nvfx_context
*nvfx
)
1064 struct pipe_context
*pipe
= &nvfx
->pipe
;
1065 struct nvfx_screen
*screen
= nvfx
->screen
;
1066 struct nouveau_channel
*chan
= screen
->base
.channel
;
1067 struct nouveau_grobj
*eng3d
= screen
->eng3d
;
1068 struct nvfx_vertex_program
*vp
;
1069 struct pipe_resource
*constbuf
;
1070 boolean upload_code
= FALSE
, upload_data
= FALSE
;
1073 if (nvfx
->render_mode
== HW
) {
1074 vp
= nvfx
->vertprog
;
1075 constbuf
= nvfx
->constbuf
[PIPE_SHADER_VERTEX
];
1077 // TODO: ouch! can't we just use constant slots for these?!
1078 if ((nvfx
->dirty
& NVFX_NEW_UCP
) ||
1079 memcmp(&nvfx
->clip
, &vp
->ucp
, sizeof(vp
->ucp
))) {
1080 nvfx_vertprog_destroy(nvfx
, vp
);
1081 memcpy(&vp
->ucp
, &nvfx
->clip
, sizeof(vp
->ucp
));
1084 vp
= nvfx
->swtnl
.vertprog
;
1088 /* Translate TGSI shader into hw bytecode */
1089 if (!vp
->translated
)
1091 nvfx
->fallback_swtnl
&= ~NVFX_NEW_VERTPROG
;
1092 nvfx_vertprog_translate(nvfx
, vp
);
1093 if (!vp
->translated
) {
1094 nvfx
->fallback_swtnl
|= NVFX_NEW_VERTPROG
;
1099 /* Allocate hw vtxprog exec slots */
1101 struct nouveau_resource
*heap
= nvfx
->screen
->vp_exec_heap
;
1102 uint vplen
= vp
->nr_insns
;
1104 if (nouveau_resource_alloc(heap
, vplen
, vp
, &vp
->exec
)) {
1105 while (heap
->next
&& heap
->size
< vplen
) {
1106 struct nvfx_vertex_program
*evict
;
1108 evict
= heap
->next
->priv
;
1109 nouveau_resource_free(&evict
->exec
);
1112 if (nouveau_resource_alloc(heap
, vplen
, vp
, &vp
->exec
))
1114 debug_printf("Vertex shader too long: %u instructions\n", vplen
);
1115 nvfx
->fallback_swtnl
|= NVFX_NEW_VERTPROG
;
1123 /* Allocate hw vtxprog const slots */
1124 if (vp
->nr_consts
&& !vp
->data
) {
1125 struct nouveau_resource
*heap
= nvfx
->screen
->vp_data_heap
;
1127 if (nouveau_resource_alloc(heap
, vp
->nr_consts
, vp
, &vp
->data
)) {
1128 while (heap
->next
&& heap
->size
< vp
->nr_consts
) {
1129 struct nvfx_vertex_program
*evict
;
1131 evict
= heap
->next
->priv
;
1132 nouveau_resource_free(&evict
->data
);
1135 if (nouveau_resource_alloc(heap
, vp
->nr_consts
, vp
, &vp
->data
))
1137 debug_printf("Vertex shader uses too many constants: %u constants\n", vp
->nr_consts
);
1138 nvfx
->fallback_swtnl
|= NVFX_NEW_VERTPROG
;
1143 /*XXX: handle this some day */
1144 assert(vp
->data
->start
>= vp
->data_start_min
);
1147 if (vp
->data_start
!= vp
->data
->start
)
1151 /* If exec or data segments moved we need to patch the program to
1152 * fixup offsets and register IDs.
1154 if (vp
->exec_start
!= vp
->exec
->start
) {
1155 //printf("vp_relocs %u -> %u\n", vp->exec_start, vp->exec->start);
1156 for(unsigned i
= 0; i
< vp
->branch_relocs
.size
; i
+= sizeof(struct nvfx_label_relocation
))
1158 struct nvfx_label_relocation
* reloc
= (struct nvfx_label_relocation
*)((char*)vp
->branch_relocs
.data
+ i
);
1159 uint32_t* hw
= vp
->insns
[reloc
->location
].data
;
1160 unsigned target
= vp
->exec
->start
+ reloc
->target
;
1162 //debug_printf("vp_reloc hw %u -> hw %u\n", reloc->location, target);
1166 hw
[2] &=~ NV30_VP_INST_IADDR_MASK
;
1167 hw
[2] |= (target
& 0x1ff) << NV30_VP_INST_IADDR_SHIFT
;
1171 hw
[3] &=~ NV40_VP_INST_IADDRL_MASK
;
1172 hw
[3] |= (target
& 7) << NV40_VP_INST_IADDRL_SHIFT
;
1174 hw
[2] &=~ NV40_VP_INST_IADDRH_MASK
;
1175 hw
[2] |= ((target
>> 3) & 0x3f) << NV40_VP_INST_IADDRH_SHIFT
;
1179 vp
->exec_start
= vp
->exec
->start
;
1182 if (vp
->nr_consts
&& vp
->data_start
!= vp
->data
->start
) {
1183 for (i
= 0; i
< vp
->nr_insns
; i
++) {
1184 struct nvfx_vertex_program_exec
*vpi
= &vp
->insns
[i
];
1186 if (vpi
->const_index
>= 0) {
1187 vpi
->data
[1] &= ~NVFX_VP(INST_CONST_SRC_MASK
);
1189 (vpi
->const_index
+ vp
->data
->start
) <<
1190 NVFX_VP(INST_CONST_SRC_SHIFT
);
1195 vp
->data_start
= vp
->data
->start
;
1198 /* Update + Upload constant values */
1199 if (vp
->nr_consts
) {
1203 map
= nvfx_buffer(constbuf
)->data
;
1205 for (i
= 0; i
< vp
->nr_consts
; i
++) {
1206 struct nvfx_vertex_program_data
*vpd
= &vp
->consts
[i
];
1208 if (vpd
->index
>= 0) {
1210 !memcmp(vpd
->value
, &map
[vpd
->index
* 4],
1213 memcpy(vpd
->value
, &map
[vpd
->index
* 4],
1217 BEGIN_RING(chan
, eng3d
, NV34TCL_VP_UPLOAD_CONST_ID
, 5);
1218 OUT_RING (chan
, i
+ vp
->data
->start
);
1219 OUT_RINGp (chan
, (uint32_t *)vpd
->value
, 4);
1223 /* Upload vtxprog */
1225 BEGIN_RING(chan
, eng3d
, NV34TCL_VP_UPLOAD_FROM_ID
, 1);
1226 OUT_RING (chan
, vp
->exec
->start
);
1227 for (i
= 0; i
< vp
->nr_insns
; i
++) {
1228 BEGIN_RING(chan
, eng3d
, NV34TCL_VP_UPLOAD_INST(0), 4);
1229 OUT_RINGp (chan
, vp
->insns
[i
].data
, 4);
1233 if(nvfx
->dirty
& (NVFX_NEW_VERTPROG
| NVFX_NEW_UCP
))
1236 OUT_RING(chan
, RING_3D(NV34TCL_VP_START_FROM_ID
, 1));
1237 OUT_RING(chan
, vp
->exec
->start
);
1239 OUT_RING(chan
, RING_3D(NV40TCL_VP_ATTRIB_EN
, 2));
1240 OUT_RING(chan
, vp
->ir
);
1241 OUT_RING(chan
, vp
->or);
1243 OUT_RING(chan
, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE
, 1));
1244 OUT_RING(chan
, vp
->clip_ctrl
);
1251 nvfx_vertprog_destroy(struct nvfx_context
*nvfx
, struct nvfx_vertex_program
*vp
)
1253 vp
->translated
= FALSE
;
1261 if (vp
->nr_consts
) {
1267 nouveau_resource_free(&vp
->exec
);
1269 nouveau_resource_free(&vp
->data
);
1271 vp
->data_start_min
= 0;
1273 vp
->ir
= vp
->or = vp
->clip_ctrl
= 0;