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ef47e013fa02f669e29e35e4dc150d38fa0006b5
[mesa.git] / src / gallium / drivers / nvfx / nvfx_vertprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_dump.h"
9 #include "tgsi/tgsi_util.h"
10
11 #include "nvfx_context.h"
12 #include "nvfx_state.h"
13
14 /* TODO (at least...):
15 * 1. Indexed consts + ARL
16 * 3. NV_vp11, NV_vp2, NV_vp3 features
17 * - extra arith opcodes
18 * - branching
19 * - texture sampling
20 * - indexed attribs
21 * - indexed results
22 * 4. bugs
23 */
24
25 #include "nv30_vertprog.h"
26 #include "nv40_vertprog.h"
27
28 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
29
30 struct nvfx_vpc {
31 struct nvfx_vertex_program *vp;
32
33 struct nvfx_vertex_program_exec *vpi;
34
35 unsigned r_temps;
36 unsigned r_temps_discard;
37 struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
38 struct nvfx_sreg *r_address;
39 struct nvfx_sreg *r_temp;
40
41 struct nvfx_sreg *imm;
42 unsigned nr_imm;
43
44 unsigned hpos_idx;
45 };
46
47 static struct nvfx_sreg
48 temp(struct nvfx_vpc *vpc)
49 {
50 int idx = ffs(~vpc->r_temps) - 1;
51
52 if (idx < 0) {
53 NOUVEAU_ERR("out of temps!!\n");
54 assert(0);
55 return nvfx_sr(NVFXSR_TEMP, 0);
56 }
57
58 vpc->r_temps |= (1 << idx);
59 vpc->r_temps_discard |= (1 << idx);
60 return nvfx_sr(NVFXSR_TEMP, idx);
61 }
62
63 static INLINE void
64 release_temps(struct nvfx_vpc *vpc)
65 {
66 vpc->r_temps &= ~vpc->r_temps_discard;
67 vpc->r_temps_discard = 0;
68 }
69
70 static struct nvfx_sreg
71 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
72 {
73 struct nvfx_vertex_program *vp = vpc->vp;
74 struct nvfx_vertex_program_data *vpd;
75 int idx;
76
77 if (pipe >= 0) {
78 for (idx = 0; idx < vp->nr_consts; idx++) {
79 if (vp->consts[idx].index == pipe)
80 return nvfx_sr(NVFXSR_CONST, idx);
81 }
82 }
83
84 idx = vp->nr_consts++;
85 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
86 vpd = &vp->consts[idx];
87
88 vpd->index = pipe;
89 vpd->value[0] = x;
90 vpd->value[1] = y;
91 vpd->value[2] = z;
92 vpd->value[3] = w;
93 return nvfx_sr(NVFXSR_CONST, idx);
94 }
95
96 #define arith(cc,s,o,d,m,s0,s1,s2) \
97 nvfx_vp_arith(nvfx, (cc), NVFX_VP_INST_SLOT_##s, NVFX_VP_INST_##s##_OP_##o, (d), (m), (s0), (s1), (s2))
98
99 static void
100 emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_sreg src)
101 {
102 struct nvfx_vertex_program *vp = vpc->vp;
103 uint32_t sr = 0;
104
105 switch (src.type) {
106 case NVFXSR_TEMP:
107 sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
108 sr |= (src.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
109 break;
110 case NVFXSR_INPUT:
111 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
112 NVFX_VP(SRC_REG_TYPE_SHIFT));
113 vp->ir |= (1 << src.index);
114 hw[1] |= (src.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
115 break;
116 case NVFXSR_CONST:
117 sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
118 NVFX_VP(SRC_REG_TYPE_SHIFT));
119 assert(vpc->vpi->const_index == -1 ||
120 vpc->vpi->const_index == src.index);
121 vpc->vpi->const_index = src.index;
122 break;
123 case NVFXSR_NONE:
124 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
125 NVFX_VP(SRC_REG_TYPE_SHIFT));
126 break;
127 default:
128 assert(0);
129 }
130
131 if (src.negate)
132 sr |= NVFX_VP(SRC_NEGATE);
133
134 if (src.abs)
135 hw[0] |= (1 << (21 + pos));
136
137 sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
138 (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
139 (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
140 (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
141
142 switch (pos) {
143 case 0:
144 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
145 NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
146 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
147 NVFX_VP(INST_SRC0L_SHIFT);
148 break;
149 case 1:
150 hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
151 break;
152 case 2:
153 hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
154 NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
155 hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
156 NVFX_VP(INST_SRC2L_SHIFT);
157 break;
158 default:
159 assert(0);
160 }
161 }
162
163 static void
164 emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_sreg dst)
165 {
166 struct nvfx_vertex_program *vp = vpc->vp;
167
168 switch (dst.type) {
169 case NVFXSR_TEMP:
170 if(!nvfx->is_nv4x)
171 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
172 else {
173 hw[3] |= NV40_VP_INST_DEST_MASK;
174 if (slot == 0) {
175 hw[0] |= (dst.index <<
176 NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
177 } else {
178 hw[3] |= (dst.index <<
179 NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
180 }
181 }
182 break;
183 case NVFXSR_OUTPUT:
184 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
185 switch (dst.index) {
186 case NVFX_VP_INST_DEST_CLIP(0):
187 vp->or |= (1 << 6);
188 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0;
189 dst.index = NVFX_VP(INST_DEST_FOGC);
190 break;
191 case NVFX_VP_INST_DEST_CLIP(1):
192 vp->or |= (1 << 7);
193 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1;
194 dst.index = NVFX_VP(INST_DEST_FOGC);
195 break;
196 case NVFX_VP_INST_DEST_CLIP(2):
197 vp->or |= (1 << 8);
198 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2;
199 dst.index = NVFX_VP(INST_DEST_FOGC);
200 break;
201 case NVFX_VP_INST_DEST_CLIP(3):
202 vp->or |= (1 << 9);
203 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3;
204 dst.index = NVFX_VP(INST_DEST_PSZ);
205 break;
206 case NVFX_VP_INST_DEST_CLIP(4):
207 vp->or |= (1 << 10);
208 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4;
209 dst.index = NVFX_VP(INST_DEST_PSZ);
210 break;
211 case NVFX_VP_INST_DEST_CLIP(5):
212 vp->or |= (1 << 11);
213 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5;
214 dst.index = NVFX_VP(INST_DEST_PSZ);
215 break;
216 default:
217 if(!nvfx->is_nv4x) {
218 switch (dst.index) {
219 case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
220 case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
221 case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
222 case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
223 case NV30_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
224 case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
225 case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
226 case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
227 case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
228 case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
229 case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
230 case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
231 case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
232 case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
233 }
234 } else {
235 switch (dst.index) {
236 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
237 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
238 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
239 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
240 case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
241 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
242 case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
243 case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
244 case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
245 case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
246 case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
247 case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
248 case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
249 case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
250 }
251 }
252 break;
253 }
254
255 if(!nvfx->is_nv4x) {
256 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
257 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
258
259 /*XXX: no way this is entirely correct, someone needs to
260 * figure out what exactly it is.
261 */
262 hw[3] |= 0x800;
263 } else {
264 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
265 if (slot == 0) {
266 hw[0] |= NV40_VP_INST_VEC_RESULT;
267 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
268 } else {
269 hw[3] |= NV40_VP_INST_SCA_RESULT;
270 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
271 }
272 }
273 break;
274 default:
275 assert(0);
276 }
277 }
278
279 static void
280 nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
281 struct nvfx_sreg dst, int mask,
282 struct nvfx_sreg s0, struct nvfx_sreg s1,
283 struct nvfx_sreg s2)
284 {
285 struct nvfx_vertex_program *vp = vpc->vp;
286 uint32_t *hw;
287
288 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
289 vpc->vpi = &vp->insns[vp->nr_insns - 1];
290 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
291 vpc->vpi->const_index = -1;
292
293 hw = vpc->vpi->data;
294
295 hw[0] |= (NVFX_COND_TR << NVFX_VP(INST_COND_SHIFT));
296 hw[0] |= ((0 << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
297 (1 << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
298 (2 << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
299 (3 << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
300
301 if(!nvfx->is_nv4x) {
302 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
303 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
304 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
305
306 if (dst.type == NVFXSR_OUTPUT) {
307 if (slot)
308 hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
309 else
310 hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
311 } else {
312 if (slot)
313 hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
314 else
315 hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
316 }
317 } else {
318 if (slot == 0) {
319 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
320 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
321 hw[3] |= (mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
322 } else {
323 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
324 hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
325 hw[3] |= (mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
326 }
327 }
328
329 emit_dst(nvfx, vpc, hw, slot, dst);
330 emit_src(nvfx, vpc, hw, 0, s0);
331 emit_src(nvfx, vpc, hw, 1, s1);
332 emit_src(nvfx, vpc, hw, 2, s2);
333 }
334
335 static INLINE struct nvfx_sreg
336 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
337 struct nvfx_sreg src;
338
339 switch (fsrc->Register.File) {
340 case TGSI_FILE_INPUT:
341 src = nvfx_sr(NVFXSR_INPUT, fsrc->Register.Index);
342 break;
343 case TGSI_FILE_CONSTANT:
344 src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
345 break;
346 case TGSI_FILE_IMMEDIATE:
347 src = vpc->imm[fsrc->Register.Index];
348 break;
349 case TGSI_FILE_TEMPORARY:
350 src = vpc->r_temp[fsrc->Register.Index];
351 break;
352 default:
353 NOUVEAU_ERR("bad src file\n");
354 break;
355 }
356
357 src.abs = fsrc->Register.Absolute;
358 src.negate = fsrc->Register.Negate;
359 src.swz[0] = fsrc->Register.SwizzleX;
360 src.swz[1] = fsrc->Register.SwizzleY;
361 src.swz[2] = fsrc->Register.SwizzleZ;
362 src.swz[3] = fsrc->Register.SwizzleW;
363 return src;
364 }
365
366 static INLINE struct nvfx_sreg
367 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
368 struct nvfx_sreg dst;
369
370 switch (fdst->Register.File) {
371 case TGSI_FILE_OUTPUT:
372 dst = vpc->r_result[fdst->Register.Index];
373 break;
374 case TGSI_FILE_TEMPORARY:
375 dst = vpc->r_temp[fdst->Register.Index];
376 break;
377 case TGSI_FILE_ADDRESS:
378 dst = vpc->r_address[fdst->Register.Index];
379 break;
380 default:
381 NOUVEAU_ERR("bad dst file\n");
382 break;
383 }
384
385 return dst;
386 }
387
388 static INLINE int
389 tgsi_mask(uint tgsi)
390 {
391 int mask = 0;
392
393 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
394 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
395 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
396 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
397 return mask;
398 }
399
400 static boolean
401 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
402 const struct tgsi_full_instruction *finst)
403 {
404 struct nvfx_sreg src[3], dst, tmp;
405 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
406 int mask;
407 int ai = -1, ci = -1, ii = -1;
408 int i;
409
410 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
411 return TRUE;
412
413 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
414 const struct tgsi_full_src_register *fsrc;
415
416 fsrc = &finst->Src[i];
417 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
418 src[i] = tgsi_src(vpc, fsrc);
419 }
420 }
421
422 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
423 const struct tgsi_full_src_register *fsrc;
424
425 fsrc = &finst->Src[i];
426
427 switch (fsrc->Register.File) {
428 case TGSI_FILE_INPUT:
429 if (ai == -1 || ai == fsrc->Register.Index) {
430 ai = fsrc->Register.Index;
431 src[i] = tgsi_src(vpc, fsrc);
432 } else {
433 src[i] = temp(vpc);
434 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
435 tgsi_src(vpc, fsrc), none, none);
436 }
437 break;
438 case TGSI_FILE_CONSTANT:
439 if ((ci == -1 && ii == -1) ||
440 ci == fsrc->Register.Index) {
441 ci = fsrc->Register.Index;
442 src[i] = tgsi_src(vpc, fsrc);
443 } else {
444 src[i] = temp(vpc);
445 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
446 tgsi_src(vpc, fsrc), none, none);
447 }
448 break;
449 case TGSI_FILE_IMMEDIATE:
450 if ((ci == -1 && ii == -1) ||
451 ii == fsrc->Register.Index) {
452 ii = fsrc->Register.Index;
453 src[i] = tgsi_src(vpc, fsrc);
454 } else {
455 src[i] = temp(vpc);
456 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
457 tgsi_src(vpc, fsrc), none, none);
458 }
459 break;
460 case TGSI_FILE_TEMPORARY:
461 /* handled above */
462 break;
463 default:
464 NOUVEAU_ERR("bad src file\n");
465 return FALSE;
466 }
467 }
468
469 dst = tgsi_dst(vpc, &finst->Dst[0]);
470 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
471
472 switch (finst->Instruction.Opcode) {
473 case TGSI_OPCODE_ABS:
474 arith(vpc, VEC, MOV, dst, mask, abs(src[0]), none, none);
475 break;
476 case TGSI_OPCODE_ADD:
477 arith(vpc, VEC, ADD, dst, mask, src[0], none, src[1]);
478 break;
479 case TGSI_OPCODE_ARL:
480 arith(vpc, VEC, ARL, dst, mask, src[0], none, none);
481 break;
482 case TGSI_OPCODE_DP3:
483 arith(vpc, VEC, DP3, dst, mask, src[0], src[1], none);
484 break;
485 case TGSI_OPCODE_DP4:
486 arith(vpc, VEC, DP4, dst, mask, src[0], src[1], none);
487 break;
488 case TGSI_OPCODE_DPH:
489 arith(vpc, VEC, DPH, dst, mask, src[0], src[1], none);
490 break;
491 case TGSI_OPCODE_DST:
492 arith(vpc, VEC, DST, dst, mask, src[0], src[1], none);
493 break;
494 case TGSI_OPCODE_EX2:
495 arith(vpc, SCA, EX2, dst, mask, none, none, src[0]);
496 break;
497 case TGSI_OPCODE_EXP:
498 arith(vpc, SCA, EXP, dst, mask, none, none, src[0]);
499 break;
500 case TGSI_OPCODE_FLR:
501 arith(vpc, VEC, FLR, dst, mask, src[0], none, none);
502 break;
503 case TGSI_OPCODE_FRC:
504 arith(vpc, VEC, FRC, dst, mask, src[0], none, none);
505 break;
506 case TGSI_OPCODE_LG2:
507 arith(vpc, SCA, LG2, dst, mask, none, none, src[0]);
508 break;
509 case TGSI_OPCODE_LIT:
510 arith(vpc, SCA, LIT, dst, mask, none, none, src[0]);
511 break;
512 case TGSI_OPCODE_LOG:
513 arith(vpc, SCA, LOG, dst, mask, none, none, src[0]);
514 break;
515 case TGSI_OPCODE_MAD:
516 arith(vpc, VEC, MAD, dst, mask, src[0], src[1], src[2]);
517 break;
518 case TGSI_OPCODE_MAX:
519 arith(vpc, VEC, MAX, dst, mask, src[0], src[1], none);
520 break;
521 case TGSI_OPCODE_MIN:
522 arith(vpc, VEC, MIN, dst, mask, src[0], src[1], none);
523 break;
524 case TGSI_OPCODE_MOV:
525 arith(vpc, VEC, MOV, dst, mask, src[0], none, none);
526 break;
527 case TGSI_OPCODE_MUL:
528 arith(vpc, VEC, MUL, dst, mask, src[0], src[1], none);
529 break;
530 case TGSI_OPCODE_POW:
531 tmp = temp(vpc);
532 arith(vpc, SCA, LG2, tmp, NVFX_VP_MASK_X, none, none,
533 swz(src[0], X, X, X, X));
534 arith(vpc, VEC, MUL, tmp, NVFX_VP_MASK_X, swz(tmp, X, X, X, X),
535 swz(src[1], X, X, X, X), none);
536 arith(vpc, SCA, EX2, dst, mask, none, none,
537 swz(tmp, X, X, X, X));
538 break;
539 case TGSI_OPCODE_RCP:
540 arith(vpc, SCA, RCP, dst, mask, none, none, src[0]);
541 break;
542 case TGSI_OPCODE_RET:
543 break;
544 case TGSI_OPCODE_RSQ:
545 arith(vpc, SCA, RSQ, dst, mask, none, none, abs(src[0]));
546 break;
547 case TGSI_OPCODE_SEQ:
548 arith(vpc, VEC, SEQ, dst, mask, src[0], src[1], none);
549 break;
550 case TGSI_OPCODE_SFL:
551 arith(vpc, VEC, SFL, dst, mask, src[0], src[1], none);
552 break;
553 case TGSI_OPCODE_SGE:
554 arith(vpc, VEC, SGE, dst, mask, src[0], src[1], none);
555 break;
556 case TGSI_OPCODE_SGT:
557 arith(vpc, VEC, SGT, dst, mask, src[0], src[1], none);
558 break;
559 case TGSI_OPCODE_SLE:
560 arith(vpc, VEC, SLE, dst, mask, src[0], src[1], none);
561 break;
562 case TGSI_OPCODE_SLT:
563 arith(vpc, VEC, SLT, dst, mask, src[0], src[1], none);
564 break;
565 case TGSI_OPCODE_SNE:
566 arith(vpc, VEC, SNE, dst, mask, src[0], src[1], none);
567 break;
568 case TGSI_OPCODE_SSG:
569 arith(vpc, VEC, SSG, dst, mask, src[0], src[1], none);
570 break;
571 case TGSI_OPCODE_STR:
572 arith(vpc, VEC, STR, dst, mask, src[0], src[1], none);
573 break;
574 case TGSI_OPCODE_SUB:
575 arith(vpc, VEC, ADD, dst, mask, src[0], none, neg(src[1]));
576 break;
577 case TGSI_OPCODE_XPD:
578 tmp = temp(vpc);
579 arith(vpc, VEC, MUL, tmp, mask,
580 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
581 arith(vpc, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W),
582 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
583 neg(tmp));
584 break;
585 default:
586 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
587 return FALSE;
588 }
589
590 release_temps(vpc);
591 return TRUE;
592 }
593
594 static boolean
595 nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
596 const struct tgsi_full_declaration *fdec)
597 {
598 unsigned idx = fdec->Range.First;
599 int hw;
600
601 switch (fdec->Semantic.Name) {
602 case TGSI_SEMANTIC_POSITION:
603 hw = NVFX_VP(INST_DEST_POS);
604 vpc->hpos_idx = idx;
605 break;
606 case TGSI_SEMANTIC_COLOR:
607 if (fdec->Semantic.Index == 0) {
608 hw = NVFX_VP(INST_DEST_COL0);
609 } else
610 if (fdec->Semantic.Index == 1) {
611 hw = NVFX_VP(INST_DEST_COL1);
612 } else {
613 NOUVEAU_ERR("bad colour semantic index\n");
614 return FALSE;
615 }
616 break;
617 case TGSI_SEMANTIC_BCOLOR:
618 if (fdec->Semantic.Index == 0) {
619 hw = NVFX_VP(INST_DEST_BFC0);
620 } else
621 if (fdec->Semantic.Index == 1) {
622 hw = NVFX_VP(INST_DEST_BFC1);
623 } else {
624 NOUVEAU_ERR("bad bcolour semantic index\n");
625 return FALSE;
626 }
627 break;
628 case TGSI_SEMANTIC_FOG:
629 hw = NVFX_VP(INST_DEST_FOGC);
630 break;
631 case TGSI_SEMANTIC_PSIZE:
632 hw = NVFX_VP(INST_DEST_PSZ);
633 break;
634 case TGSI_SEMANTIC_GENERIC:
635 if (fdec->Semantic.Index <= 7) {
636 hw = NVFX_VP(INST_DEST_TC(fdec->Semantic.Index));
637 } else {
638 NOUVEAU_ERR("bad generic semantic index\n");
639 return FALSE;
640 }
641 break;
642 case TGSI_SEMANTIC_EDGEFLAG:
643 /* not really an error just a fallback */
644 NOUVEAU_ERR("cannot handle edgeflag output\n");
645 return FALSE;
646 default:
647 NOUVEAU_ERR("bad output semantic\n");
648 return FALSE;
649 }
650
651 vpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
652 return TRUE;
653 }
654
655 static boolean
656 nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
657 {
658 struct tgsi_parse_context p;
659 int high_temp = -1, high_addr = -1, nr_imm = 0, i;
660
661 tgsi_parse_init(&p, vpc->vp->pipe.tokens);
662 while (!tgsi_parse_end_of_tokens(&p)) {
663 const union tgsi_full_token *tok = &p.FullToken;
664
665 tgsi_parse_token(&p);
666 switch(tok->Token.Type) {
667 case TGSI_TOKEN_TYPE_IMMEDIATE:
668 nr_imm++;
669 break;
670 case TGSI_TOKEN_TYPE_DECLARATION:
671 {
672 const struct tgsi_full_declaration *fdec;
673
674 fdec = &p.FullToken.FullDeclaration;
675 switch (fdec->Declaration.File) {
676 case TGSI_FILE_TEMPORARY:
677 if (fdec->Range.Last > high_temp) {
678 high_temp =
679 fdec->Range.Last;
680 }
681 break;
682 #if 0 /* this would be nice.. except gallium doesn't track it */
683 case TGSI_FILE_ADDRESS:
684 if (fdec->Range.Last > high_addr) {
685 high_addr =
686 fdec->Range.Last;
687 }
688 break;
689 #endif
690 case TGSI_FILE_OUTPUT:
691 if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec))
692 return FALSE;
693 break;
694 default:
695 break;
696 }
697 }
698 break;
699 #if 1 /* yay, parse instructions looking for address regs instead */
700 case TGSI_TOKEN_TYPE_INSTRUCTION:
701 {
702 const struct tgsi_full_instruction *finst;
703 const struct tgsi_full_dst_register *fdst;
704
705 finst = &p.FullToken.FullInstruction;
706 fdst = &finst->Dst[0];
707
708 if (fdst->Register.File == TGSI_FILE_ADDRESS) {
709 if (fdst->Register.Index > high_addr)
710 high_addr = fdst->Register.Index;
711 }
712
713 }
714 break;
715 #endif
716 default:
717 break;
718 }
719 }
720 tgsi_parse_free(&p);
721
722 if (nr_imm) {
723 vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_sreg));
724 assert(vpc->imm);
725 }
726
727 if (++high_temp) {
728 vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
729 for (i = 0; i < high_temp; i++)
730 vpc->r_temp[i] = temp(vpc);
731 }
732
733 if (++high_addr) {
734 vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_sreg));
735 for (i = 0; i < high_addr; i++)
736 vpc->r_address[i] = temp(vpc);
737 }
738
739 vpc->r_temps_discard = 0;
740 return TRUE;
741 }
742
743 static void
744 nvfx_vertprog_translate(struct nvfx_context *nvfx,
745 struct nvfx_vertex_program *vp)
746 {
747 struct tgsi_parse_context parse;
748 struct nvfx_vpc *vpc = NULL;
749 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
750 int i;
751
752 vpc = CALLOC(1, sizeof(struct nvfx_vpc));
753 if (!vpc)
754 return;
755 vpc->vp = vp;
756
757 if (!nvfx_vertprog_prepare(nvfx, vpc)) {
758 FREE(vpc);
759 return;
760 }
761
762 /* Redirect post-transform vertex position to a temp if user clip
763 * planes are enabled. We need to append code to the vtxprog
764 * to handle clip planes later.
765 */
766 if (vp->ucp.nr) {
767 vpc->r_result[vpc->hpos_idx] = temp(vpc);
768 vpc->r_temps_discard = 0;
769 }
770
771 tgsi_parse_init(&parse, vp->pipe.tokens);
772
773 while (!tgsi_parse_end_of_tokens(&parse)) {
774 tgsi_parse_token(&parse);
775
776 switch (parse.FullToken.Token.Type) {
777 case TGSI_TOKEN_TYPE_IMMEDIATE:
778 {
779 const struct tgsi_full_immediate *imm;
780
781 imm = &parse.FullToken.FullImmediate;
782 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
783 assert(imm->Immediate.NrTokens == 4 + 1);
784 vpc->imm[vpc->nr_imm++] =
785 constant(vpc, -1,
786 imm->u[0].Float,
787 imm->u[1].Float,
788 imm->u[2].Float,
789 imm->u[3].Float);
790 }
791 break;
792 case TGSI_TOKEN_TYPE_INSTRUCTION:
793 {
794 const struct tgsi_full_instruction *finst;
795 finst = &parse.FullToken.FullInstruction;
796 if (!nvfx_vertprog_parse_instruction(nvfx, vpc, finst))
797 goto out_err;
798 }
799 break;
800 default:
801 break;
802 }
803 }
804
805 /* Write out HPOS if it was redirected to a temp earlier */
806 if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
807 struct nvfx_sreg hpos = nvfx_sr(NVFXSR_OUTPUT,
808 NVFX_VP(INST_DEST_POS));
809 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
810
811 arith(vpc, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none);
812 }
813
814 /* Insert code to handle user clip planes */
815 for (i = 0; i < vp->ucp.nr; i++) {
816 struct nvfx_sreg cdst = nvfx_sr(NVFXSR_OUTPUT,
817 NVFX_VP_INST_DEST_CLIP(i));
818 struct nvfx_sreg ceqn = constant(vpc, -1,
819 nvfx->clip.ucp[i][0],
820 nvfx->clip.ucp[i][1],
821 nvfx->clip.ucp[i][2],
822 nvfx->clip.ucp[i][3]);
823 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
824 unsigned mask;
825
826 switch (i) {
827 case 0: case 3: mask = NVFX_VP_MASK_Y; break;
828 case 1: case 4: mask = NVFX_VP_MASK_Z; break;
829 case 2: case 5: mask = NVFX_VP_MASK_W; break;
830 default:
831 NOUVEAU_ERR("invalid clip dist #%d\n", i);
832 goto out_err;
833 }
834
835 arith(vpc, VEC, DP4, cdst, mask, htmp, ceqn, none);
836 }
837
838 vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
839 vp->translated = TRUE;
840 out_err:
841 tgsi_parse_free(&parse);
842 if (vpc->r_temp)
843 FREE(vpc->r_temp);
844 if (vpc->r_address)
845 FREE(vpc->r_address);
846 if (vpc->imm)
847 FREE(vpc->imm);
848 FREE(vpc);
849 }
850
851 boolean
852 nvfx_vertprog_validate(struct nvfx_context *nvfx)
853 {
854 struct pipe_context *pipe = &nvfx->pipe;
855 struct nvfx_screen *screen = nvfx->screen;
856 struct nouveau_channel *chan = screen->base.channel;
857 struct nouveau_grobj *eng3d = screen->eng3d;
858 struct nvfx_vertex_program *vp;
859 struct pipe_resource *constbuf;
860 struct pipe_transfer *transfer = NULL;
861 boolean upload_code = FALSE, upload_data = FALSE;
862 int i;
863
864 if (nvfx->render_mode == HW) {
865 vp = nvfx->vertprog;
866 constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
867
868 // TODO: ouch! can't we just use constant slots for these?!
869 if ((nvfx->dirty & NVFX_NEW_UCP) ||
870 memcmp(&nvfx->clip, &vp->ucp, sizeof(vp->ucp))) {
871 nvfx_vertprog_destroy(nvfx, vp);
872 memcpy(&vp->ucp, &nvfx->clip, sizeof(vp->ucp));
873 }
874 } else {
875 vp = nvfx->swtnl.vertprog;
876 constbuf = NULL;
877 }
878
879 /* Translate TGSI shader into hw bytecode */
880 if (!vp->translated)
881 {
882 nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG;
883 nvfx_vertprog_translate(nvfx, vp);
884 if (!vp->translated) {
885 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
886 return FALSE;
887 }
888 }
889
890 /* Allocate hw vtxprog exec slots */
891 if (!vp->exec) {
892 struct nouveau_resource *heap = nvfx->screen->vp_exec_heap;
893 uint vplen = vp->nr_insns;
894
895 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
896 while (heap->next && heap->size < vplen) {
897 struct nvfx_vertex_program *evict;
898
899 evict = heap->next->priv;
900 nouveau_resource_free(&evict->exec);
901 }
902
903 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
904 assert(0);
905 }
906
907 upload_code = TRUE;
908 }
909
910 /* Allocate hw vtxprog const slots */
911 if (vp->nr_consts && !vp->data) {
912 struct nouveau_resource *heap = nvfx->screen->vp_data_heap;
913
914 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
915 while (heap->next && heap->size < vp->nr_consts) {
916 struct nvfx_vertex_program *evict;
917
918 evict = heap->next->priv;
919 nouveau_resource_free(&evict->data);
920 }
921
922 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
923 assert(0);
924 }
925
926 /*XXX: handle this some day */
927 assert(vp->data->start >= vp->data_start_min);
928
929 upload_data = TRUE;
930 if (vp->data_start != vp->data->start)
931 upload_code = TRUE;
932 }
933
934 /* If exec or data segments moved we need to patch the program to
935 * fixup offsets and register IDs.
936 */
937 if (vp->exec_start != vp->exec->start) {
938 for (i = 0; i < vp->nr_insns; i++) {
939 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
940
941 if (vpi->has_branch_offset) {
942 assert(0);
943 }
944 }
945
946 vp->exec_start = vp->exec->start;
947 }
948
949 if (vp->nr_consts && vp->data_start != vp->data->start) {
950 for (i = 0; i < vp->nr_insns; i++) {
951 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
952
953 if (vpi->const_index >= 0) {
954 vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
955 vpi->data[1] |=
956 (vpi->const_index + vp->data->start) <<
957 NVFX_VP(INST_CONST_SRC_SHIFT);
958
959 }
960 }
961
962 vp->data_start = vp->data->start;
963 }
964
965 /* Update + Upload constant values */
966 if (vp->nr_consts) {
967 float *map = NULL;
968
969 if (constbuf) {
970 map = pipe_buffer_map(pipe, constbuf,
971 PIPE_TRANSFER_READ,
972 &transfer);
973 }
974
975 for (i = 0; i < vp->nr_consts; i++) {
976 struct nvfx_vertex_program_data *vpd = &vp->consts[i];
977
978 if (vpd->index >= 0) {
979 if (!upload_data &&
980 !memcmp(vpd->value, &map[vpd->index * 4],
981 4 * sizeof(float)))
982 continue;
983 memcpy(vpd->value, &map[vpd->index * 4],
984 4 * sizeof(float));
985 }
986
987 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5);
988 OUT_RING (chan, i + vp->data->start);
989 OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
990 }
991
992 if (constbuf)
993 pipe_buffer_unmap(pipe, constbuf, transfer);
994 }
995
996 /* Upload vtxprog */
997 if (upload_code) {
998 #if 0
999 for (i = 0; i < vp->nr_insns; i++) {
1000 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[0]);
1001 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[1]);
1002 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[2]);
1003 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]);
1004 }
1005 #endif
1006 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
1007 OUT_RING (chan, vp->exec->start);
1008 for (i = 0; i < vp->nr_insns; i++) {
1009 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
1010 OUT_RINGp (chan, vp->insns[i].data, 4);
1011 }
1012 }
1013
1014 if(nvfx->dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP))
1015 {
1016 WAIT_RING(chan, 7);
1017 OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1));
1018 OUT_RING(chan, vp->exec->start);
1019 if(nvfx->is_nv4x) {
1020 OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 2));
1021 OUT_RING(chan, vp->ir);
1022 OUT_RING(chan, vp->or);
1023 }
1024 OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
1025 OUT_RING(chan, vp->clip_ctrl);
1026 }
1027
1028 return TRUE;
1029 }
1030
1031 void
1032 nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
1033 {
1034 vp->translated = FALSE;
1035
1036 if (vp->nr_insns) {
1037 FREE(vp->insns);
1038 vp->insns = NULL;
1039 vp->nr_insns = 0;
1040 }
1041
1042 if (vp->nr_consts) {
1043 FREE(vp->consts);
1044 vp->consts = NULL;
1045 vp->nr_consts = 0;
1046 }
1047
1048 nouveau_resource_free(&vp->exec);
1049 vp->exec_start = 0;
1050 nouveau_resource_free(&vp->data);
1051 vp->data_start = 0;
1052 vp->data_start_min = 0;
1053
1054 vp->ir = vp->or = vp->clip_ctrl = 0;
1055 }