projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge remote branch 'origin/master' into nv50-compiler
[mesa.git] / src / gallium / drivers / nvfx / nvfx_vertprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_inlines.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_dump.h"
9 #include "tgsi/tgsi_util.h"
10
11 #include "nvfx_context.h"
12 #include "nvfx_state.h"
13
14 /* TODO (at least...):
15 * 1. Indexed consts + ARL
16 * 3. NV_vp11, NV_vp2, NV_vp3 features
17 * - extra arith opcodes
18 * - branching
19 * - texture sampling
20 * - indexed attribs
21 * - indexed results
22 * 4. bugs
23 */
24
25 #include "nv30_vertprog.h"
26 #include "nv40_vertprog.h"
27
28 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
29
30 struct nvfx_vpc {
31 struct nvfx_vertex_program *vp;
32
33 struct nvfx_vertex_program_exec *vpi;
34
35 unsigned r_temps;
36 unsigned r_temps_discard;
37 struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
38 struct nvfx_sreg *r_address;
39 struct nvfx_sreg *r_temp;
40
41 struct nvfx_sreg *imm;
42 unsigned nr_imm;
43
44 unsigned hpos_idx;
45 };
46
47 static struct nvfx_sreg
48 temp(struct nvfx_vpc *vpc)
49 {
50 int idx = ffs(~vpc->r_temps) - 1;
51
52 if (idx < 0) {
53 NOUVEAU_ERR("out of temps!!\n");
54 assert(0);
55 return nvfx_sr(NVFXSR_TEMP, 0);
56 }
57
58 vpc->r_temps |= (1 << idx);
59 vpc->r_temps_discard |= (1 << idx);
60 return nvfx_sr(NVFXSR_TEMP, idx);
61 }
62
63 static INLINE void
64 release_temps(struct nvfx_vpc *vpc)
65 {
66 vpc->r_temps &= ~vpc->r_temps_discard;
67 vpc->r_temps_discard = 0;
68 }
69
70 static struct nvfx_sreg
71 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
72 {
73 struct nvfx_vertex_program *vp = vpc->vp;
74 struct nvfx_vertex_program_data *vpd;
75 int idx;
76
77 if (pipe >= 0) {
78 for (idx = 0; idx < vp->nr_consts; idx++) {
79 if (vp->consts[idx].index == pipe)
80 return nvfx_sr(NVFXSR_CONST, idx);
81 }
82 }
83
84 idx = vp->nr_consts++;
85 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
86 vpd = &vp->consts[idx];
87
88 vpd->index = pipe;
89 vpd->value[0] = x;
90 vpd->value[1] = y;
91 vpd->value[2] = z;
92 vpd->value[3] = w;
93 return nvfx_sr(NVFXSR_CONST, idx);
94 }
95
96 #define arith(cc,s,o,d,m,s0,s1,s2) \
97 nvfx_vp_arith(nvfx, (cc), NVFX_VP_INST_SLOT_##s, NVFX_VP_INST_##s##_OP_##o, (d), (m), (s0), (s1), (s2))
98
99 static void
100 emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_sreg src)
101 {
102 struct nvfx_vertex_program *vp = vpc->vp;
103 uint32_t sr = 0;
104
105 switch (src.type) {
106 case NVFXSR_TEMP:
107 sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
108 sr |= (src.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
109 break;
110 case NVFXSR_INPUT:
111 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
112 NVFX_VP(SRC_REG_TYPE_SHIFT));
113 vp->ir |= (1 << src.index);
114 hw[1] |= (src.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
115 break;
116 case NVFXSR_CONST:
117 sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
118 NVFX_VP(SRC_REG_TYPE_SHIFT));
119 assert(vpc->vpi->const_index == -1 ||
120 vpc->vpi->const_index == src.index);
121 vpc->vpi->const_index = src.index;
122 break;
123 case NVFXSR_NONE:
124 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
125 NVFX_VP(SRC_REG_TYPE_SHIFT));
126 break;
127 default:
128 assert(0);
129 }
130
131 if (src.negate)
132 sr |= NVFX_VP(SRC_NEGATE);
133
134 if (src.abs)
135 hw[0] |= (1 << (21 + pos));
136
137 sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
138 (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
139 (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
140 (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
141
142 switch (pos) {
143 case 0:
144 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
145 NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
146 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
147 NVFX_VP(INST_SRC0L_SHIFT);
148 break;
149 case 1:
150 hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
151 break;
152 case 2:
153 hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
154 NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
155 hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
156 NVFX_VP(INST_SRC2L_SHIFT);
157 break;
158 default:
159 assert(0);
160 }
161 }
162
163 static void
164 emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_sreg dst)
165 {
166 struct nvfx_vertex_program *vp = vpc->vp;
167
168 switch (dst.type) {
169 case NVFXSR_TEMP:
170 if(!nvfx->is_nv4x)
171 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
172 else {
173 hw[3] |= NV40_VP_INST_DEST_MASK;
174 if (slot == 0) {
175 hw[0] |= (dst.index <<
176 NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
177 } else {
178 hw[3] |= (dst.index <<
179 NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
180 }
181 }
182 break;
183 case NVFXSR_OUTPUT:
184 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
185 switch (dst.index) {
186 case NVFX_VP_INST_DEST_CLIP(0):
187 vp->or |= (1 << 6);
188 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0;
189 dst.index = NVFX_VP(INST_DEST_FOGC);
190 break;
191 case NVFX_VP_INST_DEST_CLIP(1):
192 vp->or |= (1 << 7);
193 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1;
194 dst.index = NVFX_VP(INST_DEST_FOGC);
195 break;
196 case NVFX_VP_INST_DEST_CLIP(2):
197 vp->or |= (1 << 8);
198 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2;
199 dst.index = NVFX_VP(INST_DEST_FOGC);
200 break;
201 case NVFX_VP_INST_DEST_CLIP(3):
202 vp->or |= (1 << 9);
203 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3;
204 dst.index = NVFX_VP(INST_DEST_PSZ);
205 break;
206 case NVFX_VP_INST_DEST_CLIP(4):
207 vp->or |= (1 << 10);
208 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4;
209 dst.index = NVFX_VP(INST_DEST_PSZ);
210 break;
211 case NVFX_VP_INST_DEST_CLIP(5):
212 vp->or |= (1 << 11);
213 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5;
214 dst.index = NVFX_VP(INST_DEST_PSZ);
215 break;
216 default:
217 if(!nvfx->is_nv4x) {
218 switch (dst.index) {
219 case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
220 case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
221 case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
222 case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
223 case NV30_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
224 case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
225 case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
226 case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
227 case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
228 case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
229 case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
230 case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
231 case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
232 case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
233 }
234 } else {
235 switch (dst.index) {
236 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
237 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
238 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
239 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
240 case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
241 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
242 case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
243 case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
244 case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
245 case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
246 case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
247 case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
248 case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
249 case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
250 }
251 }
252 break;
253 }
254
255 if(!nvfx->is_nv4x) {
256 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
257 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
258
259 /*XXX: no way this is entirely correct, someone needs to
260 * figure out what exactly it is.
261 */
262 hw[3] |= 0x800;
263 } else {
264 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
265 if (slot == 0) {
266 hw[0] |= NV40_VP_INST_VEC_RESULT;
267 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
268 } else {
269 hw[3] |= NV40_VP_INST_SCA_RESULT;
270 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
271 }
272 }
273 break;
274 default:
275 assert(0);
276 }
277 }
278
279 static void
280 nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
281 struct nvfx_sreg dst, int mask,
282 struct nvfx_sreg s0, struct nvfx_sreg s1,
283 struct nvfx_sreg s2)
284 {
285 struct nvfx_vertex_program *vp = vpc->vp;
286 uint32_t *hw;
287
288 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
289 vpc->vpi = &vp->insns[vp->nr_insns - 1];
290 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
291 vpc->vpi->const_index = -1;
292
293 hw = vpc->vpi->data;
294
295 hw[0] |= (NVFX_COND_TR << NVFX_VP(INST_COND_SHIFT));
296 hw[0] |= ((0 << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
297 (1 << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
298 (2 << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
299 (3 << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
300
301 if(!nvfx->is_nv4x) {
302 if(slot == 0)
303 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
304 else
305 {
306 hw[0] |= ((op >> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT);
307 hw[1] |= ((op & 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT);
308 }
309 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
310 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
311
312 if (dst.type == NVFXSR_OUTPUT) {
313 if (slot)
314 hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
315 else
316 hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
317 } else {
318 if (slot)
319 hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
320 else
321 hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
322 }
323 } else {
324 if (slot == 0) {
325 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
326 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
327 hw[3] |= (mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
328 } else {
329 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
330 hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
331 hw[3] |= (mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
332 }
333 }
334
335 emit_dst(nvfx, vpc, hw, slot, dst);
336 emit_src(nvfx, vpc, hw, 0, s0);
337 emit_src(nvfx, vpc, hw, 1, s1);
338 emit_src(nvfx, vpc, hw, 2, s2);
339 }
340
341 static INLINE struct nvfx_sreg
342 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
343 struct nvfx_sreg src = { 0 };
344
345 switch (fsrc->Register.File) {
346 case TGSI_FILE_INPUT:
347 src = nvfx_sr(NVFXSR_INPUT, fsrc->Register.Index);
348 break;
349 case TGSI_FILE_CONSTANT:
350 src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
351 break;
352 case TGSI_FILE_IMMEDIATE:
353 src = vpc->imm[fsrc->Register.Index];
354 break;
355 case TGSI_FILE_TEMPORARY:
356 src = vpc->r_temp[fsrc->Register.Index];
357 break;
358 default:
359 NOUVEAU_ERR("bad src file\n");
360 break;
361 }
362
363 src.abs = fsrc->Register.Absolute;
364 src.negate = fsrc->Register.Negate;
365 src.swz[0] = fsrc->Register.SwizzleX;
366 src.swz[1] = fsrc->Register.SwizzleY;
367 src.swz[2] = fsrc->Register.SwizzleZ;
368 src.swz[3] = fsrc->Register.SwizzleW;
369 return src;
370 }
371
372 static INLINE struct nvfx_sreg
373 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
374 struct nvfx_sreg dst = { 0 };
375
376 switch (fdst->Register.File) {
377 case TGSI_FILE_OUTPUT:
378 dst = vpc->r_result[fdst->Register.Index];
379 break;
380 case TGSI_FILE_TEMPORARY:
381 dst = vpc->r_temp[fdst->Register.Index];
382 break;
383 case TGSI_FILE_ADDRESS:
384 dst = vpc->r_address[fdst->Register.Index];
385 break;
386 default:
387 NOUVEAU_ERR("bad dst file\n");
388 break;
389 }
390
391 return dst;
392 }
393
394 static INLINE int
395 tgsi_mask(uint tgsi)
396 {
397 int mask = 0;
398
399 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
400 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
401 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
402 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
403 return mask;
404 }
405
406 static boolean
407 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
408 const struct tgsi_full_instruction *finst)
409 {
410 struct nvfx_sreg src[3], dst, tmp;
411 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
412 int mask;
413 int ai = -1, ci = -1, ii = -1;
414 int i;
415
416 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
417 return TRUE;
418
419 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
420 const struct tgsi_full_src_register *fsrc;
421
422 fsrc = &finst->Src[i];
423 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
424 src[i] = tgsi_src(vpc, fsrc);
425 }
426 }
427
428 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
429 const struct tgsi_full_src_register *fsrc;
430
431 fsrc = &finst->Src[i];
432
433 switch (fsrc->Register.File) {
434 case TGSI_FILE_INPUT:
435 if (ai == -1 || ai == fsrc->Register.Index) {
436 ai = fsrc->Register.Index;
437 src[i] = tgsi_src(vpc, fsrc);
438 } else {
439 src[i] = temp(vpc);
440 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
441 tgsi_src(vpc, fsrc), none, none);
442 }
443 break;
444 case TGSI_FILE_CONSTANT:
445 if ((ci == -1 && ii == -1) ||
446 ci == fsrc->Register.Index) {
447 ci = fsrc->Register.Index;
448 src[i] = tgsi_src(vpc, fsrc);
449 } else {
450 src[i] = temp(vpc);
451 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
452 tgsi_src(vpc, fsrc), none, none);
453 }
454 break;
455 case TGSI_FILE_IMMEDIATE:
456 if ((ci == -1 && ii == -1) ||
457 ii == fsrc->Register.Index) {
458 ii = fsrc->Register.Index;
459 src[i] = tgsi_src(vpc, fsrc);
460 } else {
461 src[i] = temp(vpc);
462 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
463 tgsi_src(vpc, fsrc), none, none);
464 }
465 break;
466 case TGSI_FILE_TEMPORARY:
467 /* handled above */
468 break;
469 default:
470 NOUVEAU_ERR("bad src file\n");
471 return FALSE;
472 }
473 }
474
475 dst = tgsi_dst(vpc, &finst->Dst[0]);
476 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
477
478 switch (finst->Instruction.Opcode) {
479 case TGSI_OPCODE_ABS:
480 arith(vpc, VEC, MOV, dst, mask, abs(src[0]), none, none);
481 break;
482 case TGSI_OPCODE_ADD:
483 arith(vpc, VEC, ADD, dst, mask, src[0], none, src[1]);
484 break;
485 case TGSI_OPCODE_ARL:
486 arith(vpc, VEC, ARL, dst, mask, src[0], none, none);
487 break;
488 case TGSI_OPCODE_COS:
489 arith(vpc, SCA, COS, dst, mask, none, none, src[0]);
490 break;
491 case TGSI_OPCODE_DP3:
492 arith(vpc, VEC, DP3, dst, mask, src[0], src[1], none);
493 break;
494 case TGSI_OPCODE_DP4:
495 arith(vpc, VEC, DP4, dst, mask, src[0], src[1], none);
496 break;
497 case TGSI_OPCODE_DPH:
498 arith(vpc, VEC, DPH, dst, mask, src[0], src[1], none);
499 break;
500 case TGSI_OPCODE_DST:
501 arith(vpc, VEC, DST, dst, mask, src[0], src[1], none);
502 break;
503 case TGSI_OPCODE_EX2:
504 arith(vpc, SCA, EX2, dst, mask, none, none, src[0]);
505 break;
506 case TGSI_OPCODE_EXP:
507 arith(vpc, SCA, EXP, dst, mask, none, none, src[0]);
508 break;
509 case TGSI_OPCODE_FLR:
510 arith(vpc, VEC, FLR, dst, mask, src[0], none, none);
511 break;
512 case TGSI_OPCODE_FRC:
513 arith(vpc, VEC, FRC, dst, mask, src[0], none, none);
514 break;
515 case TGSI_OPCODE_LG2:
516 arith(vpc, SCA, LG2, dst, mask, none, none, src[0]);
517 break;
518 case TGSI_OPCODE_LIT:
519 arith(vpc, SCA, LIT, dst, mask, none, none, src[0]);
520 break;
521 case TGSI_OPCODE_LOG:
522 arith(vpc, SCA, LOG, dst, mask, none, none, src[0]);
523 break;
524 case TGSI_OPCODE_LRP:
525 tmp = temp(vpc);
526 arith(vpc, VEC, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
527 arith(vpc, VEC, MAD, dst, mask, src[0], src[1], tmp);
528 break;
529 case TGSI_OPCODE_MAD:
530 arith(vpc, VEC, MAD, dst, mask, src[0], src[1], src[2]);
531 break;
532 case TGSI_OPCODE_MAX:
533 arith(vpc, VEC, MAX, dst, mask, src[0], src[1], none);
534 break;
535 case TGSI_OPCODE_MIN:
536 arith(vpc, VEC, MIN, dst, mask, src[0], src[1], none);
537 break;
538 case TGSI_OPCODE_MOV:
539 arith(vpc, VEC, MOV, dst, mask, src[0], none, none);
540 break;
541 case TGSI_OPCODE_MUL:
542 arith(vpc, VEC, MUL, dst, mask, src[0], src[1], none);
543 break;
544 case TGSI_OPCODE_POW:
545 tmp = temp(vpc);
546 arith(vpc, SCA, LG2, tmp, NVFX_VP_MASK_X, none, none,
547 swz(src[0], X, X, X, X));
548 arith(vpc, VEC, MUL, tmp, NVFX_VP_MASK_X, swz(tmp, X, X, X, X),
549 swz(src[1], X, X, X, X), none);
550 arith(vpc, SCA, EX2, dst, mask, none, none,
551 swz(tmp, X, X, X, X));
552 break;
553 case TGSI_OPCODE_RCP:
554 arith(vpc, SCA, RCP, dst, mask, none, none, src[0]);
555 break;
556 case TGSI_OPCODE_RET:
557 break;
558 case TGSI_OPCODE_RSQ:
559 arith(vpc, SCA, RSQ, dst, mask, none, none, abs(src[0]));
560 break;
561 case TGSI_OPCODE_SEQ:
562 arith(vpc, VEC, SEQ, dst, mask, src[0], src[1], none);
563 break;
564 case TGSI_OPCODE_SFL:
565 arith(vpc, VEC, SFL, dst, mask, src[0], src[1], none);
566 break;
567 case TGSI_OPCODE_SGE:
568 arith(vpc, VEC, SGE, dst, mask, src[0], src[1], none);
569 break;
570 case TGSI_OPCODE_SGT:
571 arith(vpc, VEC, SGT, dst, mask, src[0], src[1], none);
572 break;
573 case TGSI_OPCODE_SIN:
574 arith(vpc, SCA, SIN, dst, mask, none, none, src[0]);
575 break;
576 case TGSI_OPCODE_SLE:
577 arith(vpc, VEC, SLE, dst, mask, src[0], src[1], none);
578 break;
579 case TGSI_OPCODE_SLT:
580 arith(vpc, VEC, SLT, dst, mask, src[0], src[1], none);
581 break;
582 case TGSI_OPCODE_SNE:
583 arith(vpc, VEC, SNE, dst, mask, src[0], src[1], none);
584 break;
585 case TGSI_OPCODE_SSG:
586 arith(vpc, VEC, SSG, dst, mask, src[0], src[1], none);
587 break;
588 case TGSI_OPCODE_STR:
589 arith(vpc, VEC, STR, dst, mask, src[0], src[1], none);
590 break;
591 case TGSI_OPCODE_SUB:
592 arith(vpc, VEC, ADD, dst, mask, src[0], none, neg(src[1]));
593 break;
594 case TGSI_OPCODE_XPD:
595 tmp = temp(vpc);
596 arith(vpc, VEC, MUL, tmp, mask,
597 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
598 arith(vpc, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W),
599 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
600 neg(tmp));
601 break;
602 default:
603 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
604 return FALSE;
605 }
606
607 release_temps(vpc);
608 return TRUE;
609 }
610
611 static boolean
612 nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
613 const struct tgsi_full_declaration *fdec)
614 {
615 unsigned idx = fdec->Range.First;
616 int hw;
617
618 switch (fdec->Semantic.Name) {
619 case TGSI_SEMANTIC_POSITION:
620 hw = NVFX_VP(INST_DEST_POS);
621 vpc->hpos_idx = idx;
622 break;
623 case TGSI_SEMANTIC_COLOR:
624 if (fdec->Semantic.Index == 0) {
625 hw = NVFX_VP(INST_DEST_COL0);
626 } else
627 if (fdec->Semantic.Index == 1) {
628 hw = NVFX_VP(INST_DEST_COL1);
629 } else {
630 NOUVEAU_ERR("bad colour semantic index\n");
631 return FALSE;
632 }
633 break;
634 case TGSI_SEMANTIC_BCOLOR:
635 if (fdec->Semantic.Index == 0) {
636 hw = NVFX_VP(INST_DEST_BFC0);
637 } else
638 if (fdec->Semantic.Index == 1) {
639 hw = NVFX_VP(INST_DEST_BFC1);
640 } else {
641 NOUVEAU_ERR("bad bcolour semantic index\n");
642 return FALSE;
643 }
644 break;
645 case TGSI_SEMANTIC_FOG:
646 hw = NVFX_VP(INST_DEST_FOGC);
647 break;
648 case TGSI_SEMANTIC_PSIZE:
649 hw = NVFX_VP(INST_DEST_PSZ);
650 break;
651 case TGSI_SEMANTIC_GENERIC:
652 if (fdec->Semantic.Index <= 7) {
653 hw = NVFX_VP(INST_DEST_TC(fdec->Semantic.Index));
654 } else {
655 NOUVEAU_ERR("bad generic semantic index\n");
656 return FALSE;
657 }
658 break;
659 case TGSI_SEMANTIC_EDGEFLAG:
660 /* not really an error just a fallback */
661 NOUVEAU_ERR("cannot handle edgeflag output\n");
662 return FALSE;
663 default:
664 NOUVEAU_ERR("bad output semantic\n");
665 return FALSE;
666 }
667
668 vpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
669 return TRUE;
670 }
671
672 static boolean
673 nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
674 {
675 struct tgsi_parse_context p;
676 int high_temp = -1, high_addr = -1, nr_imm = 0, i;
677
678 tgsi_parse_init(&p, vpc->vp->pipe.tokens);
679 while (!tgsi_parse_end_of_tokens(&p)) {
680 const union tgsi_full_token *tok = &p.FullToken;
681
682 tgsi_parse_token(&p);
683 switch(tok->Token.Type) {
684 case TGSI_TOKEN_TYPE_IMMEDIATE:
685 nr_imm++;
686 break;
687 case TGSI_TOKEN_TYPE_DECLARATION:
688 {
689 const struct tgsi_full_declaration *fdec;
690
691 fdec = &p.FullToken.FullDeclaration;
692 switch (fdec->Declaration.File) {
693 case TGSI_FILE_TEMPORARY:
694 if (fdec->Range.Last > high_temp) {
695 high_temp =
696 fdec->Range.Last;
697 }
698 break;
699 #if 0 /* this would be nice.. except gallium doesn't track it */
700 case TGSI_FILE_ADDRESS:
701 if (fdec->Range.Last > high_addr) {
702 high_addr =
703 fdec->Range.Last;
704 }
705 break;
706 #endif
707 case TGSI_FILE_OUTPUT:
708 if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec))
709 return FALSE;
710 break;
711 default:
712 break;
713 }
714 }
715 break;
716 #if 1 /* yay, parse instructions looking for address regs instead */
717 case TGSI_TOKEN_TYPE_INSTRUCTION:
718 {
719 const struct tgsi_full_instruction *finst;
720 const struct tgsi_full_dst_register *fdst;
721
722 finst = &p.FullToken.FullInstruction;
723 fdst = &finst->Dst[0];
724
725 if (fdst->Register.File == TGSI_FILE_ADDRESS) {
726 if (fdst->Register.Index > high_addr)
727 high_addr = fdst->Register.Index;
728 }
729
730 }
731 break;
732 #endif
733 default:
734 break;
735 }
736 }
737 tgsi_parse_free(&p);
738
739 if (nr_imm) {
740 vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_sreg));
741 assert(vpc->imm);
742 }
743
744 if (++high_temp) {
745 vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
746 for (i = 0; i < high_temp; i++)
747 vpc->r_temp[i] = temp(vpc);
748 }
749
750 if (++high_addr) {
751 vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_sreg));
752 for (i = 0; i < high_addr; i++)
753 vpc->r_address[i] = temp(vpc);
754 }
755
756 vpc->r_temps_discard = 0;
757 return TRUE;
758 }
759
760 static void
761 nvfx_vertprog_translate(struct nvfx_context *nvfx,
762 struct nvfx_vertex_program *vp)
763 {
764 struct tgsi_parse_context parse;
765 struct nvfx_vpc *vpc = NULL;
766 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
767 int i;
768
769 vpc = CALLOC(1, sizeof(struct nvfx_vpc));
770 if (!vpc)
771 return;
772 vpc->vp = vp;
773
774 if (!nvfx_vertprog_prepare(nvfx, vpc)) {
775 FREE(vpc);
776 return;
777 }
778
779 /* Redirect post-transform vertex position to a temp if user clip
780 * planes are enabled. We need to append code to the vtxprog
781 * to handle clip planes later.
782 */
783 if (vp->ucp.nr) {
784 vpc->r_result[vpc->hpos_idx] = temp(vpc);
785 vpc->r_temps_discard = 0;
786 }
787
788 tgsi_parse_init(&parse, vp->pipe.tokens);
789
790 while (!tgsi_parse_end_of_tokens(&parse)) {
791 tgsi_parse_token(&parse);
792
793 switch (parse.FullToken.Token.Type) {
794 case TGSI_TOKEN_TYPE_IMMEDIATE:
795 {
796 const struct tgsi_full_immediate *imm;
797
798 imm = &parse.FullToken.FullImmediate;
799 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
800 assert(imm->Immediate.NrTokens == 4 + 1);
801 vpc->imm[vpc->nr_imm++] =
802 constant(vpc, -1,
803 imm->u[0].Float,
804 imm->u[1].Float,
805 imm->u[2].Float,
806 imm->u[3].Float);
807 }
808 break;
809 case TGSI_TOKEN_TYPE_INSTRUCTION:
810 {
811 const struct tgsi_full_instruction *finst;
812 finst = &parse.FullToken.FullInstruction;
813 if (!nvfx_vertprog_parse_instruction(nvfx, vpc, finst))
814 goto out_err;
815 }
816 break;
817 default:
818 break;
819 }
820 }
821
822 /* Write out HPOS if it was redirected to a temp earlier */
823 if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
824 struct nvfx_sreg hpos = nvfx_sr(NVFXSR_OUTPUT,
825 NVFX_VP(INST_DEST_POS));
826 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
827
828 arith(vpc, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none);
829 }
830
831 /* Insert code to handle user clip planes */
832 for (i = 0; i < vp->ucp.nr; i++) {
833 struct nvfx_sreg cdst = nvfx_sr(NVFXSR_OUTPUT,
834 NVFX_VP_INST_DEST_CLIP(i));
835 struct nvfx_sreg ceqn = constant(vpc, -1,
836 nvfx->clip.ucp[i][0],
837 nvfx->clip.ucp[i][1],
838 nvfx->clip.ucp[i][2],
839 nvfx->clip.ucp[i][3]);
840 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
841 unsigned mask;
842
843 switch (i) {
844 case 0: case 3: mask = NVFX_VP_MASK_Y; break;
845 case 1: case 4: mask = NVFX_VP_MASK_Z; break;
846 case 2: case 5: mask = NVFX_VP_MASK_W; break;
847 default:
848 NOUVEAU_ERR("invalid clip dist #%d\n", i);
849 goto out_err;
850 }
851
852 arith(vpc, VEC, DP4, cdst, mask, htmp, ceqn, none);
853 }
854
855 vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
856 vp->translated = TRUE;
857 out_err:
858 tgsi_parse_free(&parse);
859 if (vpc->r_temp)
860 FREE(vpc->r_temp);
861 if (vpc->r_address)
862 FREE(vpc->r_address);
863 if (vpc->imm)
864 FREE(vpc->imm);
865 FREE(vpc);
866 }
867
868 boolean
869 nvfx_vertprog_validate(struct nvfx_context *nvfx)
870 {
871 struct pipe_context *pipe = &nvfx->pipe;
872 struct nvfx_screen *screen = nvfx->screen;
873 struct nouveau_channel *chan = screen->base.channel;
874 struct nouveau_grobj *eng3d = screen->eng3d;
875 struct nvfx_vertex_program *vp;
876 struct pipe_resource *constbuf;
877 struct pipe_transfer *transfer = NULL;
878 boolean upload_code = FALSE, upload_data = FALSE;
879 int i;
880
881 if (nvfx->render_mode == HW) {
882 vp = nvfx->vertprog;
883 constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
884
885 // TODO: ouch! can't we just use constant slots for these?!
886 if ((nvfx->dirty & NVFX_NEW_UCP) ||
887 memcmp(&nvfx->clip, &vp->ucp, sizeof(vp->ucp))) {
888 nvfx_vertprog_destroy(nvfx, vp);
889 memcpy(&vp->ucp, &nvfx->clip, sizeof(vp->ucp));
890 }
891 } else {
892 vp = nvfx->swtnl.vertprog;
893 constbuf = NULL;
894 }
895
896 /* Translate TGSI shader into hw bytecode */
897 if (!vp->translated)
898 {
899 nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG;
900 nvfx_vertprog_translate(nvfx, vp);
901 if (!vp->translated) {
902 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
903 return FALSE;
904 }
905 }
906
907 /* Allocate hw vtxprog exec slots */
908 if (!vp->exec) {
909 struct nouveau_resource *heap = nvfx->screen->vp_exec_heap;
910 uint vplen = vp->nr_insns;
911
912 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
913 while (heap->next && heap->size < vplen) {
914 struct nvfx_vertex_program *evict;
915
916 evict = heap->next->priv;
917 nouveau_resource_free(&evict->exec);
918 }
919
920 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
921 assert(0);
922 }
923
924 upload_code = TRUE;
925 }
926
927 /* Allocate hw vtxprog const slots */
928 if (vp->nr_consts && !vp->data) {
929 struct nouveau_resource *heap = nvfx->screen->vp_data_heap;
930
931 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
932 while (heap->next && heap->size < vp->nr_consts) {
933 struct nvfx_vertex_program *evict;
934
935 evict = heap->next->priv;
936 nouveau_resource_free(&evict->data);
937 }
938
939 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
940 assert(0);
941 }
942
943 /*XXX: handle this some day */
944 assert(vp->data->start >= vp->data_start_min);
945
946 upload_data = TRUE;
947 if (vp->data_start != vp->data->start)
948 upload_code = TRUE;
949 }
950
951 /* If exec or data segments moved we need to patch the program to
952 * fixup offsets and register IDs.
953 */
954 if (vp->exec_start != vp->exec->start) {
955 for (i = 0; i < vp->nr_insns; i++) {
956 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
957
958 if (vpi->has_branch_offset) {
959 assert(0);
960 }
961 }
962
963 vp->exec_start = vp->exec->start;
964 }
965
966 if (vp->nr_consts && vp->data_start != vp->data->start) {
967 for (i = 0; i < vp->nr_insns; i++) {
968 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
969
970 if (vpi->const_index >= 0) {
971 vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
972 vpi->data[1] |=
973 (vpi->const_index + vp->data->start) <<
974 NVFX_VP(INST_CONST_SRC_SHIFT);
975
976 }
977 }
978
979 vp->data_start = vp->data->start;
980 }
981
982 /* Update + Upload constant values */
983 if (vp->nr_consts) {
984 float *map = NULL;
985
986 if (constbuf) {
987 map = pipe_buffer_map(pipe, constbuf,
988 PIPE_TRANSFER_READ,
989 &transfer);
990 }
991
992 for (i = 0; i < vp->nr_consts; i++) {
993 struct nvfx_vertex_program_data *vpd = &vp->consts[i];
994
995 if (vpd->index >= 0) {
996 if (!upload_data &&
997 !memcmp(vpd->value, &map[vpd->index * 4],
998 4 * sizeof(float)))
999 continue;
1000 memcpy(vpd->value, &map[vpd->index * 4],
1001 4 * sizeof(float));
1002 }
1003
1004 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5);
1005 OUT_RING (chan, i + vp->data->start);
1006 OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
1007 }
1008
1009 if (constbuf)
1010 pipe_buffer_unmap(pipe, constbuf, transfer);
1011 }
1012
1013 /* Upload vtxprog */
1014 if (upload_code) {
1015 #if 0
1016 for (i = 0; i < vp->nr_insns; i++) {
1017 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[0]);
1018 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[1]);
1019 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[2]);
1020 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]);
1021 }
1022 #endif
1023 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
1024 OUT_RING (chan, vp->exec->start);
1025 for (i = 0; i < vp->nr_insns; i++) {
1026 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
1027 OUT_RINGp (chan, vp->insns[i].data, 4);
1028 }
1029 }
1030
1031 if(nvfx->dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP))
1032 {
1033 WAIT_RING(chan, 7);
1034 OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1));
1035 OUT_RING(chan, vp->exec->start);
1036 if(nvfx->is_nv4x) {
1037 OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 2));
1038 OUT_RING(chan, vp->ir);
1039 OUT_RING(chan, vp->or);
1040 }
1041 OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
1042 OUT_RING(chan, vp->clip_ctrl);
1043 }
1044
1045 return TRUE;
1046 }
1047
1048 void
1049 nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
1050 {
1051 vp->translated = FALSE;
1052
1053 if (vp->nr_insns) {
1054 FREE(vp->insns);
1055 vp->insns = NULL;
1056 vp->nr_insns = 0;
1057 }
1058
1059 if (vp->nr_consts) {
1060 FREE(vp->consts);
1061 vp->consts = NULL;
1062 vp->nr_consts = 0;
1063 }
1064
1065 nouveau_resource_free(&vp->exec);
1066 vp->exec_start = 0;
1067 nouveau_resource_free(&vp->data);
1068 vp->data_start = 0;
1069 vp->data_start_min = 0;
1070
1071 vp->ir = vp->or = vp->clip_ctrl = 0;
1072 }