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nvfx: support proper shader linkage - adds glsl support
[mesa.git] / src / gallium / drivers / nvfx / nvfx_vertprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_linkage.h"
5
6 #include "pipe/p_shader_tokens.h"
7 #include "tgsi/tgsi_parse.h"
8 #include "tgsi/tgsi_dump.h"
9 #include "tgsi/tgsi_util.h"
10
11 #include "nvfx_context.h"
12 #include "nvfx_state.h"
13 #include "nvfx_resource.h"
14
15 /* TODO (at least...):
16 * 1. Indexed consts + ARL
17 * 3. NV_vp11, NV_vp2, NV_vp3 features
18 * - extra arith opcodes
19 * - branching
20 * - texture sampling
21 * - indexed attribs
22 * - indexed results
23 * 4. bugs
24 */
25
26 #include "nv30_vertprog.h"
27 #include "nv40_vertprog.h"
28
29 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
30
31 struct nvfx_vpc {
32 struct nvfx_vertex_program *vp;
33
34 struct nvfx_vertex_program_exec *vpi;
35
36 unsigned r_temps;
37 unsigned r_temps_discard;
38 struct nvfx_sreg r_result[PIPE_MAX_SHADER_OUTPUTS];
39 struct nvfx_sreg *r_address;
40 struct nvfx_sreg *r_temp;
41
42 struct nvfx_sreg *imm;
43 unsigned nr_imm;
44
45 unsigned hpos_idx;
46 };
47
48 static struct nvfx_sreg
49 temp(struct nvfx_vpc *vpc)
50 {
51 int idx = ffs(~vpc->r_temps) - 1;
52
53 if (idx < 0) {
54 NOUVEAU_ERR("out of temps!!\n");
55 assert(0);
56 return nvfx_sr(NVFXSR_TEMP, 0);
57 }
58
59 vpc->r_temps |= (1 << idx);
60 vpc->r_temps_discard |= (1 << idx);
61 return nvfx_sr(NVFXSR_TEMP, idx);
62 }
63
64 static inline void
65 release_temps(struct nvfx_vpc *vpc)
66 {
67 vpc->r_temps &= ~vpc->r_temps_discard;
68 vpc->r_temps_discard = 0;
69 }
70
71 static struct nvfx_sreg
72 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
73 {
74 struct nvfx_vertex_program *vp = vpc->vp;
75 struct nvfx_vertex_program_data *vpd;
76 int idx;
77
78 if (pipe >= 0) {
79 for (idx = 0; idx < vp->nr_consts; idx++) {
80 if (vp->consts[idx].index == pipe)
81 return nvfx_sr(NVFXSR_CONST, idx);
82 }
83 }
84
85 idx = vp->nr_consts++;
86 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
87 vpd = &vp->consts[idx];
88
89 vpd->index = pipe;
90 vpd->value[0] = x;
91 vpd->value[1] = y;
92 vpd->value[2] = z;
93 vpd->value[3] = w;
94 return nvfx_sr(NVFXSR_CONST, idx);
95 }
96
97 #define arith(cc,s,o,d,m,s0,s1,s2) \
98 nvfx_vp_arith(nvfx, (cc), NVFX_VP_INST_SLOT_##s, NVFX_VP_INST_##s##_OP_##o, (d), (m), (s0), (s1), (s2))
99
100 static void
101 emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_sreg src)
102 {
103 struct nvfx_vertex_program *vp = vpc->vp;
104 uint32_t sr = 0;
105
106 switch (src.type) {
107 case NVFXSR_TEMP:
108 sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
109 sr |= (src.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
110 break;
111 case NVFXSR_INPUT:
112 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
113 NVFX_VP(SRC_REG_TYPE_SHIFT));
114 vp->ir |= (1 << src.index);
115 hw[1] |= (src.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
116 break;
117 case NVFXSR_CONST:
118 sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
119 NVFX_VP(SRC_REG_TYPE_SHIFT));
120 assert(vpc->vpi->const_index == -1 ||
121 vpc->vpi->const_index == src.index);
122 vpc->vpi->const_index = src.index;
123 break;
124 case NVFXSR_NONE:
125 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
126 NVFX_VP(SRC_REG_TYPE_SHIFT));
127 break;
128 default:
129 assert(0);
130 }
131
132 if (src.negate)
133 sr |= NVFX_VP(SRC_NEGATE);
134
135 if (src.abs)
136 hw[0] |= (1 << (21 + pos));
137
138 sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
139 (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
140 (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
141 (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
142
143 switch (pos) {
144 case 0:
145 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
146 NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
147 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
148 NVFX_VP(INST_SRC0L_SHIFT);
149 break;
150 case 1:
151 hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
152 break;
153 case 2:
154 hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
155 NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
156 hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
157 NVFX_VP(INST_SRC2L_SHIFT);
158 break;
159 default:
160 assert(0);
161 }
162 }
163
164 static void
165 emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_sreg dst)
166 {
167 struct nvfx_vertex_program *vp = vpc->vp;
168
169 switch (dst.type) {
170 case NVFXSR_TEMP:
171 if(!nvfx->is_nv4x)
172 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
173 else {
174 hw[3] |= NV40_VP_INST_DEST_MASK;
175 if (slot == 0) {
176 hw[0] |= (dst.index <<
177 NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
178 } else {
179 hw[3] |= (dst.index <<
180 NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
181 }
182 }
183 break;
184 case NVFXSR_OUTPUT:
185 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
186 switch (dst.index) {
187 case NVFX_VP_INST_DEST_CLIP(0):
188 vp->or |= (1 << 6);
189 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0;
190 dst.index = NVFX_VP(INST_DEST_FOGC);
191 break;
192 case NVFX_VP_INST_DEST_CLIP(1):
193 vp->or |= (1 << 7);
194 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1;
195 dst.index = NVFX_VP(INST_DEST_FOGC);
196 break;
197 case NVFX_VP_INST_DEST_CLIP(2):
198 vp->or |= (1 << 8);
199 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2;
200 dst.index = NVFX_VP(INST_DEST_FOGC);
201 break;
202 case NVFX_VP_INST_DEST_CLIP(3):
203 vp->or |= (1 << 9);
204 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3;
205 dst.index = NVFX_VP(INST_DEST_PSZ);
206 break;
207 case NVFX_VP_INST_DEST_CLIP(4):
208 vp->or |= (1 << 10);
209 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4;
210 dst.index = NVFX_VP(INST_DEST_PSZ);
211 break;
212 case NVFX_VP_INST_DEST_CLIP(5):
213 vp->or |= (1 << 11);
214 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5;
215 dst.index = NVFX_VP(INST_DEST_PSZ);
216 break;
217 default:
218 if(!nvfx->is_nv4x) {
219 switch (dst.index) {
220 case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
221 case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
222 case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
223 case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
224 case NV30_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
225 case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
226 case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
227 case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
228 case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
229 case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
230 case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
231 case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
232 case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
233 case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
234 }
235 } else {
236 switch (dst.index) {
237 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
238 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
239 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
240 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
241 case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
242 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
243 case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
244 case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
245 case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
246 case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
247 case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
248 case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
249 case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
250 case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
251 }
252 }
253 break;
254 }
255
256 if(!nvfx->is_nv4x) {
257 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
258 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
259
260 /*XXX: no way this is entirely correct, someone needs to
261 * figure out what exactly it is.
262 */
263 hw[3] |= 0x800;
264 } else {
265 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
266 if (slot == 0) {
267 hw[0] |= NV40_VP_INST_VEC_RESULT;
268 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
269 } else {
270 hw[3] |= NV40_VP_INST_SCA_RESULT;
271 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
272 }
273 }
274 break;
275 default:
276 assert(0);
277 }
278 }
279
280 static void
281 nvfx_vp_arith(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, int slot, int op,
282 struct nvfx_sreg dst, int mask,
283 struct nvfx_sreg s0, struct nvfx_sreg s1,
284 struct nvfx_sreg s2)
285 {
286 struct nvfx_vertex_program *vp = vpc->vp;
287 uint32_t *hw;
288
289 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
290 vpc->vpi = &vp->insns[vp->nr_insns - 1];
291 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
292 vpc->vpi->const_index = -1;
293
294 hw = vpc->vpi->data;
295
296 hw[0] |= (NVFX_COND_TR << NVFX_VP(INST_COND_SHIFT));
297 hw[0] |= ((0 << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
298 (1 << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
299 (2 << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
300 (3 << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
301
302 if(!nvfx->is_nv4x) {
303 if(slot == 0)
304 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
305 else
306 {
307 hw[0] |= ((op >> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT);
308 hw[1] |= ((op & 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT);
309 }
310 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
311 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
312
313 if (dst.type == NVFXSR_OUTPUT) {
314 if (slot)
315 hw[3] |= (mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
316 else
317 hw[3] |= (mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
318 } else {
319 if (slot)
320 hw[3] |= (mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
321 else
322 hw[3] |= (mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
323 }
324 } else {
325 if (slot == 0) {
326 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
327 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
328 hw[3] |= (mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
329 } else {
330 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
331 hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
332 hw[3] |= (mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
333 }
334 }
335
336 emit_dst(nvfx, vpc, hw, slot, dst);
337 emit_src(nvfx, vpc, hw, 0, s0);
338 emit_src(nvfx, vpc, hw, 1, s1);
339 emit_src(nvfx, vpc, hw, 2, s2);
340 }
341
342 static inline struct nvfx_sreg
343 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
344 struct nvfx_sreg src = { 0 };
345
346 switch (fsrc->Register.File) {
347 case TGSI_FILE_INPUT:
348 src = nvfx_sr(NVFXSR_INPUT, fsrc->Register.Index);
349 break;
350 case TGSI_FILE_CONSTANT:
351 src = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
352 break;
353 case TGSI_FILE_IMMEDIATE:
354 src = vpc->imm[fsrc->Register.Index];
355 break;
356 case TGSI_FILE_TEMPORARY:
357 src = vpc->r_temp[fsrc->Register.Index];
358 break;
359 default:
360 NOUVEAU_ERR("bad src file\n");
361 break;
362 }
363
364 src.abs = fsrc->Register.Absolute;
365 src.negate = fsrc->Register.Negate;
366 src.swz[0] = fsrc->Register.SwizzleX;
367 src.swz[1] = fsrc->Register.SwizzleY;
368 src.swz[2] = fsrc->Register.SwizzleZ;
369 src.swz[3] = fsrc->Register.SwizzleW;
370 return src;
371 }
372
373 static INLINE struct nvfx_sreg
374 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
375 struct nvfx_sreg dst = { 0 };
376
377 switch (fdst->Register.File) {
378 case TGSI_FILE_OUTPUT:
379 dst = vpc->r_result[fdst->Register.Index];
380 break;
381 case TGSI_FILE_TEMPORARY:
382 dst = vpc->r_temp[fdst->Register.Index];
383 break;
384 case TGSI_FILE_ADDRESS:
385 dst = vpc->r_address[fdst->Register.Index];
386 break;
387 default:
388 NOUVEAU_ERR("bad dst file %i\n", fdst->Register.File);
389 break;
390 }
391
392 return dst;
393 }
394
395 static inline int
396 tgsi_mask(uint tgsi)
397 {
398 int mask = 0;
399
400 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
401 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
402 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
403 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
404 return mask;
405 }
406
407 static boolean
408 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
409 const struct tgsi_full_instruction *finst)
410 {
411 struct nvfx_sreg src[3], dst, tmp;
412 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
413 int mask;
414 int ai = -1, ci = -1, ii = -1;
415 int i;
416
417 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
418 return TRUE;
419
420 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
421 const struct tgsi_full_src_register *fsrc;
422
423 fsrc = &finst->Src[i];
424 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
425 src[i] = tgsi_src(vpc, fsrc);
426 }
427 }
428
429 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
430 const struct tgsi_full_src_register *fsrc;
431
432 fsrc = &finst->Src[i];
433
434 switch (fsrc->Register.File) {
435 case TGSI_FILE_INPUT:
436 if (ai == -1 || ai == fsrc->Register.Index) {
437 ai = fsrc->Register.Index;
438 src[i] = tgsi_src(vpc, fsrc);
439 } else {
440 src[i] = temp(vpc);
441 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
442 tgsi_src(vpc, fsrc), none, none);
443 }
444 break;
445 case TGSI_FILE_CONSTANT:
446 if ((ci == -1 && ii == -1) ||
447 ci == fsrc->Register.Index) {
448 ci = fsrc->Register.Index;
449 src[i] = tgsi_src(vpc, fsrc);
450 } else {
451 src[i] = temp(vpc);
452 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
453 tgsi_src(vpc, fsrc), none, none);
454 }
455 break;
456 case TGSI_FILE_IMMEDIATE:
457 if ((ci == -1 && ii == -1) ||
458 ii == fsrc->Register.Index) {
459 ii = fsrc->Register.Index;
460 src[i] = tgsi_src(vpc, fsrc);
461 } else {
462 src[i] = temp(vpc);
463 arith(vpc, VEC, MOV, src[i], NVFX_VP_MASK_ALL,
464 tgsi_src(vpc, fsrc), none, none);
465 }
466 break;
467 case TGSI_FILE_TEMPORARY:
468 /* handled above */
469 break;
470 default:
471 NOUVEAU_ERR("bad src file\n");
472 return FALSE;
473 }
474 }
475
476 dst = tgsi_dst(vpc, &finst->Dst[0]);
477 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
478
479 switch (finst->Instruction.Opcode) {
480 case TGSI_OPCODE_ABS:
481 arith(vpc, VEC, MOV, dst, mask, abs(src[0]), none, none);
482 break;
483 case TGSI_OPCODE_ADD:
484 arith(vpc, VEC, ADD, dst, mask, src[0], none, src[1]);
485 break;
486 case TGSI_OPCODE_ARL:
487 arith(vpc, VEC, ARL, dst, mask, src[0], none, none);
488 break;
489 case TGSI_OPCODE_COS:
490 arith(vpc, SCA, COS, dst, mask, none, none, src[0]);
491 break;
492 case TGSI_OPCODE_DP3:
493 arith(vpc, VEC, DP3, dst, mask, src[0], src[1], none);
494 break;
495 case TGSI_OPCODE_DP4:
496 arith(vpc, VEC, DP4, dst, mask, src[0], src[1], none);
497 break;
498 case TGSI_OPCODE_DPH:
499 arith(vpc, VEC, DPH, dst, mask, src[0], src[1], none);
500 break;
501 case TGSI_OPCODE_DST:
502 arith(vpc, VEC, DST, dst, mask, src[0], src[1], none);
503 break;
504 case TGSI_OPCODE_EX2:
505 arith(vpc, SCA, EX2, dst, mask, none, none, src[0]);
506 break;
507 case TGSI_OPCODE_EXP:
508 arith(vpc, SCA, EXP, dst, mask, none, none, src[0]);
509 break;
510 case TGSI_OPCODE_FLR:
511 arith(vpc, VEC, FLR, dst, mask, src[0], none, none);
512 break;
513 case TGSI_OPCODE_FRC:
514 arith(vpc, VEC, FRC, dst, mask, src[0], none, none);
515 break;
516 case TGSI_OPCODE_LG2:
517 arith(vpc, SCA, LG2, dst, mask, none, none, src[0]);
518 break;
519 case TGSI_OPCODE_LIT:
520 arith(vpc, SCA, LIT, dst, mask, none, none, src[0]);
521 break;
522 case TGSI_OPCODE_LOG:
523 arith(vpc, SCA, LOG, dst, mask, none, none, src[0]);
524 break;
525 case TGSI_OPCODE_LRP:
526 tmp = temp(vpc);
527 arith(vpc, VEC, MAD, tmp, mask, neg(src[0]), src[2], src[2]);
528 arith(vpc, VEC, MAD, dst, mask, src[0], src[1], tmp);
529 break;
530 case TGSI_OPCODE_MAD:
531 arith(vpc, VEC, MAD, dst, mask, src[0], src[1], src[2]);
532 break;
533 case TGSI_OPCODE_MAX:
534 arith(vpc, VEC, MAX, dst, mask, src[0], src[1], none);
535 break;
536 case TGSI_OPCODE_MIN:
537 arith(vpc, VEC, MIN, dst, mask, src[0], src[1], none);
538 break;
539 case TGSI_OPCODE_MOV:
540 arith(vpc, VEC, MOV, dst, mask, src[0], none, none);
541 break;
542 case TGSI_OPCODE_MUL:
543 arith(vpc, VEC, MUL, dst, mask, src[0], src[1], none);
544 break;
545 case TGSI_OPCODE_POW:
546 tmp = temp(vpc);
547 arith(vpc, SCA, LG2, tmp, NVFX_VP_MASK_X, none, none,
548 swz(src[0], X, X, X, X));
549 arith(vpc, VEC, MUL, tmp, NVFX_VP_MASK_X, swz(tmp, X, X, X, X),
550 swz(src[1], X, X, X, X), none);
551 arith(vpc, SCA, EX2, dst, mask, none, none,
552 swz(tmp, X, X, X, X));
553 break;
554 case TGSI_OPCODE_RCP:
555 arith(vpc, SCA, RCP, dst, mask, none, none, src[0]);
556 break;
557 case TGSI_OPCODE_RET:
558 break;
559 case TGSI_OPCODE_RSQ:
560 arith(vpc, SCA, RSQ, dst, mask, none, none, abs(src[0]));
561 break;
562 case TGSI_OPCODE_SEQ:
563 arith(vpc, VEC, SEQ, dst, mask, src[0], src[1], none);
564 break;
565 case TGSI_OPCODE_SFL:
566 arith(vpc, VEC, SFL, dst, mask, src[0], src[1], none);
567 break;
568 case TGSI_OPCODE_SGE:
569 arith(vpc, VEC, SGE, dst, mask, src[0], src[1], none);
570 break;
571 case TGSI_OPCODE_SGT:
572 arith(vpc, VEC, SGT, dst, mask, src[0], src[1], none);
573 break;
574 case TGSI_OPCODE_SIN:
575 arith(vpc, SCA, SIN, dst, mask, none, none, src[0]);
576 break;
577 case TGSI_OPCODE_SLE:
578 arith(vpc, VEC, SLE, dst, mask, src[0], src[1], none);
579 break;
580 case TGSI_OPCODE_SLT:
581 arith(vpc, VEC, SLT, dst, mask, src[0], src[1], none);
582 break;
583 case TGSI_OPCODE_SNE:
584 arith(vpc, VEC, SNE, dst, mask, src[0], src[1], none);
585 break;
586 case TGSI_OPCODE_SSG:
587 arith(vpc, VEC, SSG, dst, mask, src[0], src[1], none);
588 break;
589 case TGSI_OPCODE_STR:
590 arith(vpc, VEC, STR, dst, mask, src[0], src[1], none);
591 break;
592 case TGSI_OPCODE_SUB:
593 arith(vpc, VEC, ADD, dst, mask, src[0], none, neg(src[1]));
594 break;
595 case TGSI_OPCODE_XPD:
596 tmp = temp(vpc);
597 arith(vpc, VEC, MUL, tmp, mask,
598 swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none);
599 arith(vpc, VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W),
600 swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y),
601 neg(tmp));
602 break;
603 default:
604 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
605 return FALSE;
606 }
607
608 release_temps(vpc);
609 return TRUE;
610 }
611
612 static boolean
613 nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
614 const struct tgsi_full_declaration *fdec)
615 {
616 unsigned idx = fdec->Range.First;
617 int hw;
618
619 switch (fdec->Semantic.Name) {
620 case TGSI_SEMANTIC_POSITION:
621 hw = NVFX_VP(INST_DEST_POS);
622 vpc->hpos_idx = idx;
623 break;
624 case TGSI_SEMANTIC_COLOR:
625 if (fdec->Semantic.Index == 0) {
626 hw = NVFX_VP(INST_DEST_COL0);
627 } else
628 if (fdec->Semantic.Index == 1) {
629 hw = NVFX_VP(INST_DEST_COL1);
630 } else {
631 NOUVEAU_ERR("bad colour semantic index\n");
632 return FALSE;
633 }
634 break;
635 case TGSI_SEMANTIC_BCOLOR:
636 if (fdec->Semantic.Index == 0) {
637 hw = NVFX_VP(INST_DEST_BFC0);
638 } else
639 if (fdec->Semantic.Index == 1) {
640 hw = NVFX_VP(INST_DEST_BFC1);
641 } else {
642 NOUVEAU_ERR("bad bcolour semantic index\n");
643 return FALSE;
644 }
645 break;
646 case TGSI_SEMANTIC_FOG:
647 hw = NVFX_VP(INST_DEST_FOGC);
648 break;
649 case TGSI_SEMANTIC_PSIZE:
650 hw = NVFX_VP(INST_DEST_PSZ);
651 break;
652 case TGSI_SEMANTIC_GENERIC:
653 hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf)
654 + NVFX_VP(INST_DEST_TC(0)) - NVFX_FP_OP_INPUT_SRC_TC(0);
655 break;
656 case TGSI_SEMANTIC_EDGEFLAG:
657 /* not really an error just a fallback */
658 NOUVEAU_ERR("cannot handle edgeflag output\n");
659 return FALSE;
660 default:
661 NOUVEAU_ERR("bad output semantic\n");
662 return FALSE;
663 }
664
665 vpc->r_result[idx] = nvfx_sr(NVFXSR_OUTPUT, hw);
666 return TRUE;
667 }
668
669 static boolean
670 nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
671 {
672 struct tgsi_parse_context p;
673 int high_temp = -1, high_addr = -1, nr_imm = 0, i;
674 struct util_semantic_set set;
675 unsigned char sem_layout[8];
676 unsigned sem_layout_size;
677 unsigned num_outputs;
678
679 num_outputs = util_semantic_set_from_program_file(&set, vpc->vp->pipe.tokens, TGSI_FILE_OUTPUT);
680
681 if(num_outputs > 8) {
682 NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs);
683 return FALSE;
684 }
685 util_semantic_layout_from_set(sem_layout, &set, 8, 8);
686
687 /* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */
688 memset(vpc->vp->generic_to_fp_input, 0x0f, sizeof(vpc->vp->generic_to_fp_input));
689 vpc->vp->texcoord_ouput_mask = 0;
690 for(int i = 0; i < 8; ++i) {
691 if(sem_layout[i] == 0xff)
692 continue;
693 vpc->vp->texcoord_ouput_mask |= (1 << i);
694 //printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i);
695 vpc->vp->generic_to_fp_input[sem_layout[i]] = 0xf0 | (NVFX_FP_OP_INPUT_SRC_TC(0) + i);
696 }
697
698 tgsi_parse_init(&p, vpc->vp->pipe.tokens);
699 while (!tgsi_parse_end_of_tokens(&p)) {
700 const union tgsi_full_token *tok = &p.FullToken;
701
702 tgsi_parse_token(&p);
703 switch(tok->Token.Type) {
704 case TGSI_TOKEN_TYPE_IMMEDIATE:
705 nr_imm++;
706 break;
707 case TGSI_TOKEN_TYPE_DECLARATION:
708 {
709 const struct tgsi_full_declaration *fdec;
710
711 fdec = &p.FullToken.FullDeclaration;
712 switch (fdec->Declaration.File) {
713 case TGSI_FILE_TEMPORARY:
714 if (fdec->Range.Last > high_temp) {
715 high_temp =
716 fdec->Range.Last;
717 }
718 break;
719 #if 0 /* this would be nice.. except gallium doesn't track it */
720 case TGSI_FILE_ADDRESS:
721 if (fdec->Range.Last > high_addr) {
722 high_addr =
723 fdec->Range.Last;
724 }
725 break;
726 #endif
727 case TGSI_FILE_OUTPUT:
728 if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec))
729 return FALSE;
730 break;
731 default:
732 break;
733 }
734 }
735 break;
736 #if 1 /* yay, parse instructions looking for address regs instead */
737 case TGSI_TOKEN_TYPE_INSTRUCTION:
738 {
739 const struct tgsi_full_instruction *finst;
740 const struct tgsi_full_dst_register *fdst;
741
742 finst = &p.FullToken.FullInstruction;
743 fdst = &finst->Dst[0];
744
745 if (fdst->Register.File == TGSI_FILE_ADDRESS) {
746 if (fdst->Register.Index > high_addr)
747 high_addr = fdst->Register.Index;
748 }
749
750 }
751 break;
752 #endif
753 default:
754 break;
755 }
756 }
757 tgsi_parse_free(&p);
758
759 if (nr_imm) {
760 vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_sreg));
761 assert(vpc->imm);
762 }
763
764 if (++high_temp) {
765 vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_sreg));
766 for (i = 0; i < high_temp; i++)
767 vpc->r_temp[i] = temp(vpc);
768 }
769
770 if (++high_addr) {
771 vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_sreg));
772 for (i = 0; i < high_addr; i++)
773 vpc->r_address[i] = temp(vpc);
774 }
775
776 vpc->r_temps_discard = 0;
777 return TRUE;
778 }
779
780 static void
781 nvfx_vertprog_translate(struct nvfx_context *nvfx,
782 struct nvfx_vertex_program *vp)
783 {
784 struct tgsi_parse_context parse;
785 struct nvfx_vpc *vpc = NULL;
786 struct nvfx_sreg none = nvfx_sr(NVFXSR_NONE, 0);
787 int i;
788
789 vpc = CALLOC(1, sizeof(struct nvfx_vpc));
790 if (!vpc)
791 return;
792 vpc->vp = vp;
793
794 if (!nvfx_vertprog_prepare(nvfx, vpc)) {
795 FREE(vpc);
796 return;
797 }
798
799 /* Redirect post-transform vertex position to a temp if user clip
800 * planes are enabled. We need to append code to the vtxprog
801 * to handle clip planes later.
802 */
803 if (vp->ucp.nr) {
804 vpc->r_result[vpc->hpos_idx] = temp(vpc);
805 vpc->r_temps_discard = 0;
806 }
807
808 tgsi_parse_init(&parse, vp->pipe.tokens);
809
810 while (!tgsi_parse_end_of_tokens(&parse)) {
811 tgsi_parse_token(&parse);
812
813 switch (parse.FullToken.Token.Type) {
814 case TGSI_TOKEN_TYPE_IMMEDIATE:
815 {
816 const struct tgsi_full_immediate *imm;
817
818 imm = &parse.FullToken.FullImmediate;
819 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
820 assert(imm->Immediate.NrTokens == 4 + 1);
821 vpc->imm[vpc->nr_imm++] =
822 constant(vpc, -1,
823 imm->u[0].Float,
824 imm->u[1].Float,
825 imm->u[2].Float,
826 imm->u[3].Float);
827 }
828 break;
829 case TGSI_TOKEN_TYPE_INSTRUCTION:
830 {
831 const struct tgsi_full_instruction *finst;
832 finst = &parse.FullToken.FullInstruction;
833 if (!nvfx_vertprog_parse_instruction(nvfx, vpc, finst))
834 goto out_err;
835 }
836 break;
837 default:
838 break;
839 }
840 }
841
842 /* Write out HPOS if it was redirected to a temp earlier */
843 if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
844 struct nvfx_sreg hpos = nvfx_sr(NVFXSR_OUTPUT,
845 NVFX_VP(INST_DEST_POS));
846 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
847
848 arith(vpc, VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none);
849 }
850
851 /* Insert code to handle user clip planes */
852 for (i = 0; i < vp->ucp.nr; i++) {
853 struct nvfx_sreg cdst = nvfx_sr(NVFXSR_OUTPUT,
854 NVFX_VP_INST_DEST_CLIP(i));
855 struct nvfx_sreg ceqn = constant(vpc, -1,
856 nvfx->clip.ucp[i][0],
857 nvfx->clip.ucp[i][1],
858 nvfx->clip.ucp[i][2],
859 nvfx->clip.ucp[i][3]);
860 struct nvfx_sreg htmp = vpc->r_result[vpc->hpos_idx];
861 unsigned mask;
862
863 switch (i) {
864 case 0: case 3: mask = NVFX_VP_MASK_Y; break;
865 case 1: case 4: mask = NVFX_VP_MASK_Z; break;
866 case 2: case 5: mask = NVFX_VP_MASK_W; break;
867 default:
868 NOUVEAU_ERR("invalid clip dist #%d\n", i);
869 goto out_err;
870 }
871
872 arith(vpc, VEC, DP4, cdst, mask, htmp, ceqn, none);
873 }
874
875 vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
876 vp->translated = TRUE;
877 out_err:
878 tgsi_parse_free(&parse);
879 if (vpc->r_temp)
880 FREE(vpc->r_temp);
881 if (vpc->r_address)
882 FREE(vpc->r_address);
883 if (vpc->imm)
884 FREE(vpc->imm);
885 FREE(vpc);
886 }
887
888 boolean
889 nvfx_vertprog_validate(struct nvfx_context *nvfx)
890 {
891 struct pipe_context *pipe = &nvfx->pipe;
892 struct nvfx_screen *screen = nvfx->screen;
893 struct nouveau_channel *chan = screen->base.channel;
894 struct nouveau_grobj *eng3d = screen->eng3d;
895 struct nvfx_vertex_program *vp;
896 struct pipe_resource *constbuf;
897 boolean upload_code = FALSE, upload_data = FALSE;
898 int i;
899
900 if (nvfx->render_mode == HW) {
901 vp = nvfx->vertprog;
902 constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
903
904 // TODO: ouch! can't we just use constant slots for these?!
905 if ((nvfx->dirty & NVFX_NEW_UCP) ||
906 memcmp(&nvfx->clip, &vp->ucp, sizeof(vp->ucp))) {
907 nvfx_vertprog_destroy(nvfx, vp);
908 memcpy(&vp->ucp, &nvfx->clip, sizeof(vp->ucp));
909 }
910 } else {
911 vp = nvfx->swtnl.vertprog;
912 constbuf = NULL;
913 }
914
915 /* Translate TGSI shader into hw bytecode */
916 if (!vp->translated)
917 {
918 nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG;
919 nvfx_vertprog_translate(nvfx, vp);
920 if (!vp->translated) {
921 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
922 return FALSE;
923 }
924 }
925
926 /* Allocate hw vtxprog exec slots */
927 if (!vp->exec) {
928 struct nouveau_resource *heap = nvfx->screen->vp_exec_heap;
929 uint vplen = vp->nr_insns;
930
931 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
932 while (heap->next && heap->size < vplen) {
933 struct nvfx_vertex_program *evict;
934
935 evict = heap->next->priv;
936 nouveau_resource_free(&evict->exec);
937 }
938
939 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
940 assert(0);
941 }
942
943 upload_code = TRUE;
944 }
945
946 /* Allocate hw vtxprog const slots */
947 if (vp->nr_consts && !vp->data) {
948 struct nouveau_resource *heap = nvfx->screen->vp_data_heap;
949
950 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
951 while (heap->next && heap->size < vp->nr_consts) {
952 struct nvfx_vertex_program *evict;
953
954 evict = heap->next->priv;
955 nouveau_resource_free(&evict->data);
956 }
957
958 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
959 assert(0);
960 }
961
962 /*XXX: handle this some day */
963 assert(vp->data->start >= vp->data_start_min);
964
965 upload_data = TRUE;
966 if (vp->data_start != vp->data->start)
967 upload_code = TRUE;
968 }
969
970 /* If exec or data segments moved we need to patch the program to
971 * fixup offsets and register IDs.
972 */
973 if (vp->exec_start != vp->exec->start) {
974 for (i = 0; i < vp->nr_insns; i++) {
975 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
976
977 if (vpi->has_branch_offset) {
978 assert(0);
979 }
980 }
981
982 vp->exec_start = vp->exec->start;
983 }
984
985 if (vp->nr_consts && vp->data_start != vp->data->start) {
986 for (i = 0; i < vp->nr_insns; i++) {
987 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
988
989 if (vpi->const_index >= 0) {
990 vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
991 vpi->data[1] |=
992 (vpi->const_index + vp->data->start) <<
993 NVFX_VP(INST_CONST_SRC_SHIFT);
994
995 }
996 }
997
998 vp->data_start = vp->data->start;
999 }
1000
1001 /* Update + Upload constant values */
1002 if (vp->nr_consts) {
1003 float *map = NULL;
1004
1005 if (constbuf)
1006 map = nvfx_buffer(constbuf)->data;
1007
1008 for (i = 0; i < vp->nr_consts; i++) {
1009 struct nvfx_vertex_program_data *vpd = &vp->consts[i];
1010
1011 if (vpd->index >= 0) {
1012 if (!upload_data &&
1013 !memcmp(vpd->value, &map[vpd->index * 4],
1014 4 * sizeof(float)))
1015 continue;
1016 memcpy(vpd->value, &map[vpd->index * 4],
1017 4 * sizeof(float));
1018 }
1019
1020 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5);
1021 OUT_RING (chan, i + vp->data->start);
1022 OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
1023 }
1024 }
1025
1026 /* Upload vtxprog */
1027 if (upload_code) {
1028 #if 0
1029 for (i = 0; i < vp->nr_insns; i++) {
1030 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[0]);
1031 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[1]);
1032 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[2]);
1033 NOUVEAU_MSG("VP %d: 0x%08x\n", i, vp->insns[i].data[3]);
1034 }
1035 #endif
1036 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
1037 OUT_RING (chan, vp->exec->start);
1038 for (i = 0; i < vp->nr_insns; i++) {
1039 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
1040 OUT_RINGp (chan, vp->insns[i].data, 4);
1041 }
1042 }
1043
1044 if(nvfx->dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP))
1045 {
1046 WAIT_RING(chan, 7);
1047 OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1));
1048 OUT_RING(chan, vp->exec->start);
1049 if(nvfx->is_nv4x) {
1050 OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 2));
1051 OUT_RING(chan, vp->ir);
1052 OUT_RING(chan, vp->or);
1053 }
1054 OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
1055 OUT_RING(chan, vp->clip_ctrl);
1056 }
1057
1058 return TRUE;
1059 }
1060
1061 void
1062 nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
1063 {
1064 vp->translated = FALSE;
1065
1066 if (vp->nr_insns) {
1067 FREE(vp->insns);
1068 vp->insns = NULL;
1069 vp->nr_insns = 0;
1070 }
1071
1072 if (vp->nr_consts) {
1073 FREE(vp->consts);
1074 vp->consts = NULL;
1075 vp->nr_consts = 0;
1076 }
1077
1078 nouveau_resource_free(&vp->exec);
1079 vp->exec_start = 0;
1080 nouveau_resource_free(&vp->data);
1081 vp->data_start = 0;
1082 vp->data_start_min = 0;
1083
1084 vp->ir = vp->or = vp->clip_ctrl = 0;
1085 }