projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
nvfx: refactor shader assembler
[mesa.git] / src / gallium / drivers / nvfx / nvfx_vertprog.c
1 #include "pipe/p_context.h"
2 #include "pipe/p_defines.h"
3 #include "pipe/p_state.h"
4 #include "util/u_linkage.h"
5 #include "util/u_debug.h"
6
7 #include "pipe/p_shader_tokens.h"
8 #include "tgsi/tgsi_parse.h"
9 #include "tgsi/tgsi_dump.h"
10 #include "tgsi/tgsi_util.h"
11
12 #include "nvfx_context.h"
13 #include "nvfx_state.h"
14 #include "nvfx_resource.h"
15
16 /* TODO (at least...):
17 * 1. Indexed consts + ARL
18 * 3. NV_vp11, NV_vp2, NV_vp3 features
19 * - extra arith opcodes
20 * - branching
21 * - texture sampling
22 * - indexed attribs
23 * - indexed results
24 * 4. bugs
25 */
26
27 #include "nv30_vertprog.h"
28 #include "nv40_vertprog.h"
29
30 #define NVFX_VP_INST_DEST_CLIP(n) ((~0 - 6) + (n))
31
32 struct nvfx_vpc {
33 struct nvfx_context* nvfx;
34 struct nvfx_vertex_program *vp;
35
36 struct nvfx_vertex_program_exec *vpi;
37
38 unsigned r_temps;
39 unsigned r_temps_discard;
40 struct nvfx_reg r_result[PIPE_MAX_SHADER_OUTPUTS];
41 struct nvfx_reg *r_address;
42 struct nvfx_reg *r_temp;
43
44 struct nvfx_reg *imm;
45 unsigned nr_imm;
46
47 unsigned hpos_idx;
48 };
49
50 static struct nvfx_reg
51 temp(struct nvfx_vpc *vpc)
52 {
53 int idx = ffs(~vpc->r_temps) - 1;
54
55 if (idx < 0) {
56 NOUVEAU_ERR("out of temps!!\n");
57 assert(0);
58 return nvfx_reg(NVFXSR_TEMP, 0);
59 }
60
61 vpc->r_temps |= (1 << idx);
62 vpc->r_temps_discard |= (1 << idx);
63 return nvfx_reg(NVFXSR_TEMP, idx);
64 }
65
66 static inline void
67 release_temps(struct nvfx_vpc *vpc)
68 {
69 vpc->r_temps &= ~vpc->r_temps_discard;
70 vpc->r_temps_discard = 0;
71 }
72
73 static struct nvfx_reg
74 constant(struct nvfx_vpc *vpc, int pipe, float x, float y, float z, float w)
75 {
76 struct nvfx_vertex_program *vp = vpc->vp;
77 struct nvfx_vertex_program_data *vpd;
78 int idx;
79
80 if (pipe >= 0) {
81 for (idx = 0; idx < vp->nr_consts; idx++) {
82 if (vp->consts[idx].index == pipe)
83 return nvfx_reg(NVFXSR_CONST, idx);
84 }
85 }
86
87 idx = vp->nr_consts++;
88 vp->consts = realloc(vp->consts, sizeof(*vpd) * vp->nr_consts);
89 vpd = &vp->consts[idx];
90
91 vpd->index = pipe;
92 vpd->value[0] = x;
93 vpd->value[1] = y;
94 vpd->value[2] = z;
95 vpd->value[3] = w;
96 return nvfx_reg(NVFXSR_CONST, idx);
97 }
98
99 #define arith(s,o,d,m,s0,s1,s2) \
100 nvfx_insn(0, (NVFX_VP_INST_SLOT_##s << 7) | NVFX_VP_INST_##s##_OP_##o, -1, (d), (m), (s0), (s1), (s2))
101
102 static void
103 emit_src(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int pos, struct nvfx_src src)
104 {
105 struct nvfx_vertex_program *vp = vpc->vp;
106 uint32_t sr = 0;
107
108 switch (src.reg.type) {
109 case NVFXSR_TEMP:
110 sr |= (NVFX_VP(SRC_REG_TYPE_TEMP) << NVFX_VP(SRC_REG_TYPE_SHIFT));
111 sr |= (src.reg.index << NVFX_VP(SRC_TEMP_SRC_SHIFT));
112 break;
113 case NVFXSR_INPUT:
114 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
115 NVFX_VP(SRC_REG_TYPE_SHIFT));
116 vp->ir |= (1 << src.reg.index);
117 hw[1] |= (src.reg.index << NVFX_VP(INST_INPUT_SRC_SHIFT));
118 break;
119 case NVFXSR_CONST:
120 sr |= (NVFX_VP(SRC_REG_TYPE_CONST) <<
121 NVFX_VP(SRC_REG_TYPE_SHIFT));
122 assert(vpc->vpi->const_index == -1 ||
123 vpc->vpi->const_index == src.reg.index);
124 vpc->vpi->const_index = src.reg.index;
125 break;
126 case NVFXSR_NONE:
127 sr |= (NVFX_VP(SRC_REG_TYPE_INPUT) <<
128 NVFX_VP(SRC_REG_TYPE_SHIFT));
129 break;
130 default:
131 assert(0);
132 }
133
134 if (src.negate)
135 sr |= NVFX_VP(SRC_NEGATE);
136
137 if (src.abs)
138 hw[0] |= (1 << (21 + pos));
139
140 sr |= ((src.swz[0] << NVFX_VP(SRC_SWZ_X_SHIFT)) |
141 (src.swz[1] << NVFX_VP(SRC_SWZ_Y_SHIFT)) |
142 (src.swz[2] << NVFX_VP(SRC_SWZ_Z_SHIFT)) |
143 (src.swz[3] << NVFX_VP(SRC_SWZ_W_SHIFT)));
144
145 switch (pos) {
146 case 0:
147 hw[1] |= ((sr & NVFX_VP(SRC0_HIGH_MASK)) >>
148 NVFX_VP(SRC0_HIGH_SHIFT)) << NVFX_VP(INST_SRC0H_SHIFT);
149 hw[2] |= (sr & NVFX_VP(SRC0_LOW_MASK)) <<
150 NVFX_VP(INST_SRC0L_SHIFT);
151 break;
152 case 1:
153 hw[2] |= sr << NVFX_VP(INST_SRC1_SHIFT);
154 break;
155 case 2:
156 hw[2] |= ((sr & NVFX_VP(SRC2_HIGH_MASK)) >>
157 NVFX_VP(SRC2_HIGH_SHIFT)) << NVFX_VP(INST_SRC2H_SHIFT);
158 hw[3] |= (sr & NVFX_VP(SRC2_LOW_MASK)) <<
159 NVFX_VP(INST_SRC2L_SHIFT);
160 break;
161 default:
162 assert(0);
163 }
164 }
165
166 static void
167 emit_dst(struct nvfx_context* nvfx, struct nvfx_vpc *vpc, uint32_t *hw, int slot, struct nvfx_reg dst)
168 {
169 struct nvfx_vertex_program *vp = vpc->vp;
170
171 switch (dst.type) {
172 case NVFXSR_TEMP:
173 if(!nvfx->is_nv4x)
174 hw[0] |= (dst.index << NV30_VP_INST_DEST_TEMP_ID_SHIFT);
175 else {
176 hw[3] |= NV40_VP_INST_DEST_MASK;
177 if (slot == 0)
178 hw[0] |= (dst.index << NV40_VP_INST_VEC_DEST_TEMP_SHIFT);
179 else
180 hw[3] |= (dst.index << NV40_VP_INST_SCA_DEST_TEMP_SHIFT);
181 }
182 break;
183 case NVFXSR_OUTPUT:
184 /* TODO: this may be wrong because on nv30 COL0 and BFC0 are swapped */
185 switch (dst.index) {
186 case NVFX_VP_INST_DEST_CLIP(0):
187 vp->or |= (1 << 6);
188 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE0;
189 dst.index = NVFX_VP(INST_DEST_FOGC);
190 break;
191 case NVFX_VP_INST_DEST_CLIP(1):
192 vp->or |= (1 << 7);
193 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE1;
194 dst.index = NVFX_VP(INST_DEST_FOGC);
195 break;
196 case NVFX_VP_INST_DEST_CLIP(2):
197 vp->or |= (1 << 8);
198 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE2;
199 dst.index = NVFX_VP(INST_DEST_FOGC);
200 break;
201 case NVFX_VP_INST_DEST_CLIP(3):
202 vp->or |= (1 << 9);
203 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE3;
204 dst.index = NVFX_VP(INST_DEST_PSZ);
205 break;
206 case NVFX_VP_INST_DEST_CLIP(4):
207 vp->or |= (1 << 10);
208 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE4;
209 dst.index = NVFX_VP(INST_DEST_PSZ);
210 break;
211 case NVFX_VP_INST_DEST_CLIP(5):
212 vp->or |= (1 << 11);
213 vp->clip_ctrl |= NV34TCL_VP_CLIP_PLANES_ENABLE_PLANE5;
214 dst.index = NVFX_VP(INST_DEST_PSZ);
215 break;
216 default:
217 if(!nvfx->is_nv4x) {
218 switch (dst.index) {
219 case NV30_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
220 case NV30_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
221 case NV30_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
222 case NV30_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
223 case NV30_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
224 case NV30_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
225 case NV30_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
226 case NV30_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
227 case NV30_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
228 case NV30_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
229 case NV30_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
230 case NV30_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
231 case NV30_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
232 case NV30_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
233 }
234 } else {
235 switch (dst.index) {
236 case NV40_VP_INST_DEST_COL0 : vp->or |= (1 << 0); break;
237 case NV40_VP_INST_DEST_COL1 : vp->or |= (1 << 1); break;
238 case NV40_VP_INST_DEST_BFC0 : vp->or |= (1 << 2); break;
239 case NV40_VP_INST_DEST_BFC1 : vp->or |= (1 << 3); break;
240 case NV40_VP_INST_DEST_FOGC: vp->or |= (1 << 4); break;
241 case NV40_VP_INST_DEST_PSZ : vp->or |= (1 << 5); break;
242 case NV40_VP_INST_DEST_TC(0): vp->or |= (1 << 14); break;
243 case NV40_VP_INST_DEST_TC(1): vp->or |= (1 << 15); break;
244 case NV40_VP_INST_DEST_TC(2): vp->or |= (1 << 16); break;
245 case NV40_VP_INST_DEST_TC(3): vp->or |= (1 << 17); break;
246 case NV40_VP_INST_DEST_TC(4): vp->or |= (1 << 18); break;
247 case NV40_VP_INST_DEST_TC(5): vp->or |= (1 << 19); break;
248 case NV40_VP_INST_DEST_TC(6): vp->or |= (1 << 20); break;
249 case NV40_VP_INST_DEST_TC(7): vp->or |= (1 << 21); break;
250 }
251 }
252 break;
253 }
254
255 if(!nvfx->is_nv4x) {
256 hw[3] |= (dst.index << NV30_VP_INST_DEST_SHIFT);
257 hw[0] |= NV30_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
258
259 /*XXX: no way this is entirely correct, someone needs to
260 * figure out what exactly it is.
261 */
262 hw[3] |= 0x800;
263 } else {
264 hw[3] |= (dst.index << NV40_VP_INST_DEST_SHIFT);
265 if (slot == 0) {
266 hw[0] |= NV40_VP_INST_VEC_RESULT;
267 hw[0] |= NV40_VP_INST_VEC_DEST_TEMP_MASK | (1<<20);
268 } else {
269 hw[3] |= NV40_VP_INST_SCA_RESULT;
270 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
271 }
272 }
273 break;
274 default:
275 assert(0);
276 }
277 }
278
279 static void
280 nvfx_vp_emit(struct nvfx_vpc *vpc, struct nvfx_insn insn)
281 {
282 struct nvfx_context* nvfx = vpc->nvfx;
283 struct nvfx_vertex_program *vp = vpc->vp;
284 unsigned slot = insn.op >> 7;
285 unsigned op = insn.op & 0x7f;
286 uint32_t *hw;
287
288 vp->insns = realloc(vp->insns, ++vp->nr_insns * sizeof(*vpc->vpi));
289 vpc->vpi = &vp->insns[vp->nr_insns - 1];
290 memset(vpc->vpi, 0, sizeof(*vpc->vpi));
291 vpc->vpi->const_index = -1;
292
293 hw = vpc->vpi->data;
294
295 hw[0] |= (NVFX_COND_TR << NVFX_VP(INST_COND_SHIFT));
296 hw[0] |= ((0 << NVFX_VP(INST_COND_SWZ_X_SHIFT)) |
297 (1 << NVFX_VP(INST_COND_SWZ_Y_SHIFT)) |
298 (2 << NVFX_VP(INST_COND_SWZ_Z_SHIFT)) |
299 (3 << NVFX_VP(INST_COND_SWZ_W_SHIFT)));
300
301 if(!nvfx->is_nv4x) {
302 if(slot == 0)
303 hw[1] |= (op << NV30_VP_INST_VEC_OPCODE_SHIFT);
304 else
305 {
306 hw[0] |= ((op >> 4) << NV30_VP_INST_SCA_OPCODEH_SHIFT);
307 hw[1] |= ((op & 0xf) << NV30_VP_INST_SCA_OPCODEL_SHIFT);
308 }
309 // hw[3] |= NVFX_VP(INST_SCA_DEST_TEMP_MASK);
310 // hw[3] |= (mask << NVFX_VP(INST_VEC_WRITEMASK_SHIFT));
311
312 if (insn.dst.type == NVFXSR_OUTPUT) {
313 if (slot)
314 hw[3] |= (insn.mask << NV30_VP_INST_SDEST_WRITEMASK_SHIFT);
315 else
316 hw[3] |= (insn.mask << NV30_VP_INST_VDEST_WRITEMASK_SHIFT);
317 } else {
318 if (slot)
319 hw[3] |= (insn.mask << NV30_VP_INST_STEMP_WRITEMASK_SHIFT);
320 else
321 hw[3] |= (insn.mask << NV30_VP_INST_VTEMP_WRITEMASK_SHIFT);
322 }
323 } else {
324 if (slot == 0) {
325 hw[1] |= (op << NV40_VP_INST_VEC_OPCODE_SHIFT);
326 hw[3] |= NV40_VP_INST_SCA_DEST_TEMP_MASK;
327 hw[3] |= (insn.mask << NV40_VP_INST_VEC_WRITEMASK_SHIFT);
328 } else {
329 hw[1] |= (op << NV40_VP_INST_SCA_OPCODE_SHIFT);
330 hw[0] |= (NV40_VP_INST_VEC_DEST_TEMP_MASK | (1 << 20));
331 hw[3] |= (insn.mask << NV40_VP_INST_SCA_WRITEMASK_SHIFT);
332 }
333 }
334
335 emit_dst(nvfx, vpc, hw, slot, insn.dst);
336 emit_src(nvfx, vpc, hw, 0, insn.src[0]);
337 emit_src(nvfx, vpc, hw, 1, insn.src[1]);
338 emit_src(nvfx, vpc, hw, 2, insn.src[2]);
339 }
340
341 static inline struct nvfx_src
342 tgsi_src(struct nvfx_vpc *vpc, const struct tgsi_full_src_register *fsrc) {
343 struct nvfx_src src;
344
345 switch (fsrc->Register.File) {
346 case TGSI_FILE_INPUT:
347 src.reg = nvfx_reg(NVFXSR_INPUT, fsrc->Register.Index);
348 break;
349 case TGSI_FILE_CONSTANT:
350 src.reg = constant(vpc, fsrc->Register.Index, 0, 0, 0, 0);
351 break;
352 case TGSI_FILE_IMMEDIATE:
353 src.reg = vpc->imm[fsrc->Register.Index];
354 break;
355 case TGSI_FILE_TEMPORARY:
356 src.reg = vpc->r_temp[fsrc->Register.Index];
357 break;
358 default:
359 NOUVEAU_ERR("bad src file\n");
360 break;
361 }
362
363 src.abs = fsrc->Register.Absolute;
364 src.negate = fsrc->Register.Negate;
365 src.swz[0] = fsrc->Register.SwizzleX;
366 src.swz[1] = fsrc->Register.SwizzleY;
367 src.swz[2] = fsrc->Register.SwizzleZ;
368 src.swz[3] = fsrc->Register.SwizzleW;
369 return src;
370 }
371
372 static INLINE struct nvfx_reg
373 tgsi_dst(struct nvfx_vpc *vpc, const struct tgsi_full_dst_register *fdst) {
374 struct nvfx_reg dst;
375
376 switch (fdst->Register.File) {
377 case TGSI_FILE_OUTPUT:
378 dst = vpc->r_result[fdst->Register.Index];
379 break;
380 case TGSI_FILE_TEMPORARY:
381 dst = vpc->r_temp[fdst->Register.Index];
382 break;
383 case TGSI_FILE_ADDRESS:
384 dst = vpc->r_address[fdst->Register.Index];
385 break;
386 default:
387 NOUVEAU_ERR("bad dst file %i\n", fdst->Register.File);
388 break;
389 }
390
391 return dst;
392 }
393
394 static inline int
395 tgsi_mask(uint tgsi)
396 {
397 int mask = 0;
398
399 if (tgsi & TGSI_WRITEMASK_X) mask |= NVFX_VP_MASK_X;
400 if (tgsi & TGSI_WRITEMASK_Y) mask |= NVFX_VP_MASK_Y;
401 if (tgsi & TGSI_WRITEMASK_Z) mask |= NVFX_VP_MASK_Z;
402 if (tgsi & TGSI_WRITEMASK_W) mask |= NVFX_VP_MASK_W;
403 return mask;
404 }
405
406 static boolean
407 nvfx_vertprog_parse_instruction(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
408 const struct tgsi_full_instruction *finst)
409 {
410 struct nvfx_src src[3], tmp;
411 struct nvfx_reg dst;
412 struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
413 int mask;
414 int ai = -1, ci = -1, ii = -1;
415 int i;
416
417 if (finst->Instruction.Opcode == TGSI_OPCODE_END)
418 return TRUE;
419
420 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
421 const struct tgsi_full_src_register *fsrc;
422
423 fsrc = &finst->Src[i];
424 if (fsrc->Register.File == TGSI_FILE_TEMPORARY) {
425 src[i] = tgsi_src(vpc, fsrc);
426 }
427 }
428
429 for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
430 const struct tgsi_full_src_register *fsrc;
431
432 fsrc = &finst->Src[i];
433
434 switch (fsrc->Register.File) {
435 case TGSI_FILE_INPUT:
436 if (ai == -1 || ai == fsrc->Register.Index) {
437 ai = fsrc->Register.Index;
438 src[i] = tgsi_src(vpc, fsrc);
439 } else {
440 src[i] = nvfx_src(temp(vpc));
441 nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
442 }
443 break;
444 case TGSI_FILE_CONSTANT:
445 if ((ci == -1 && ii == -1) ||
446 ci == fsrc->Register.Index) {
447 ci = fsrc->Register.Index;
448 src[i] = tgsi_src(vpc, fsrc);
449 } else {
450 src[i] = nvfx_src(temp(vpc));
451 nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
452 }
453 break;
454 case TGSI_FILE_IMMEDIATE:
455 if ((ci == -1 && ii == -1) ||
456 ii == fsrc->Register.Index) {
457 ii = fsrc->Register.Index;
458 src[i] = tgsi_src(vpc, fsrc);
459 } else {
460 src[i] = nvfx_src(temp(vpc));
461 nvfx_vp_emit(vpc, arith(VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, tgsi_src(vpc, fsrc), none, none));
462 }
463 break;
464 case TGSI_FILE_TEMPORARY:
465 /* handled above */
466 break;
467 default:
468 NOUVEAU_ERR("bad src file\n");
469 return FALSE;
470 }
471 }
472
473 dst = tgsi_dst(vpc, &finst->Dst[0]);
474 mask = tgsi_mask(finst->Dst[0].Register.WriteMask);
475
476 switch (finst->Instruction.Opcode) {
477 case TGSI_OPCODE_ABS:
478 nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, abs(src[0]), none, none));
479 break;
480 case TGSI_OPCODE_ADD:
481 nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, src[1]));
482 break;
483 case TGSI_OPCODE_ARL:
484 nvfx_vp_emit(vpc, arith(VEC, ARL, dst, mask, src[0], none, none));
485 break;
486 case TGSI_OPCODE_COS:
487 nvfx_vp_emit(vpc, arith(SCA, COS, dst, mask, none, none, src[0]));
488 break;
489 case TGSI_OPCODE_DP3:
490 nvfx_vp_emit(vpc, arith(VEC, DP3, dst, mask, src[0], src[1], none));
491 break;
492 case TGSI_OPCODE_DP4:
493 nvfx_vp_emit(vpc, arith(VEC, DP4, dst, mask, src[0], src[1], none));
494 break;
495 case TGSI_OPCODE_DPH:
496 nvfx_vp_emit(vpc, arith(VEC, DPH, dst, mask, src[0], src[1], none));
497 break;
498 case TGSI_OPCODE_DST:
499 nvfx_vp_emit(vpc, arith(VEC, DST, dst, mask, src[0], src[1], none));
500 break;
501 case TGSI_OPCODE_EX2:
502 nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, src[0]));
503 break;
504 case TGSI_OPCODE_EXP:
505 nvfx_vp_emit(vpc, arith(SCA, EXP, dst, mask, none, none, src[0]));
506 break;
507 case TGSI_OPCODE_FLR:
508 nvfx_vp_emit(vpc, arith(VEC, FLR, dst, mask, src[0], none, none));
509 break;
510 case TGSI_OPCODE_FRC:
511 nvfx_vp_emit(vpc, arith(VEC, FRC, dst, mask, src[0], none, none));
512 break;
513 case TGSI_OPCODE_LG2:
514 nvfx_vp_emit(vpc, arith(SCA, LG2, dst, mask, none, none, src[0]));
515 break;
516 case TGSI_OPCODE_LIT:
517 nvfx_vp_emit(vpc, arith(SCA, LIT, dst, mask, none, none, src[0]));
518 break;
519 case TGSI_OPCODE_LOG:
520 nvfx_vp_emit(vpc, arith(SCA, LOG, dst, mask, none, none, src[0]));
521 break;
522 case TGSI_OPCODE_LRP:
523 tmp = nvfx_src(temp(vpc));
524 nvfx_vp_emit(vpc, arith(VEC, MAD, tmp.reg, mask, neg(src[0]), src[2], src[2]));
525 nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], tmp));
526 break;
527 case TGSI_OPCODE_MAD:
528 nvfx_vp_emit(vpc, arith(VEC, MAD, dst, mask, src[0], src[1], src[2]));
529 break;
530 case TGSI_OPCODE_MAX:
531 nvfx_vp_emit(vpc, arith(VEC, MAX, dst, mask, src[0], src[1], none));
532 break;
533 case TGSI_OPCODE_MIN:
534 nvfx_vp_emit(vpc, arith(VEC, MIN, dst, mask, src[0], src[1], none));
535 break;
536 case TGSI_OPCODE_MOV:
537 nvfx_vp_emit(vpc, arith(VEC, MOV, dst, mask, src[0], none, none));
538 break;
539 case TGSI_OPCODE_MUL:
540 nvfx_vp_emit(vpc, arith(VEC, MUL, dst, mask, src[0], src[1], none));
541 break;
542 case TGSI_OPCODE_POW:
543 tmp = nvfx_src(temp(vpc));
544 nvfx_vp_emit(vpc, arith(SCA, LG2, tmp.reg, NVFX_VP_MASK_X, none, none, swz(src[0], X, X, X, X)));
545 nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, NVFX_VP_MASK_X, swz(tmp, X, X, X, X), swz(src[1], X, X, X, X), none));
546 nvfx_vp_emit(vpc, arith(SCA, EX2, dst, mask, none, none, swz(tmp, X, X, X, X)));
547 break;
548 case TGSI_OPCODE_RCP:
549 nvfx_vp_emit(vpc, arith(SCA, RCP, dst, mask, none, none, src[0]));
550 break;
551 case TGSI_OPCODE_RET:
552 break;
553 case TGSI_OPCODE_RSQ:
554 nvfx_vp_emit(vpc, arith(SCA, RSQ, dst, mask, none, none, abs(src[0])));
555 break;
556 case TGSI_OPCODE_SEQ:
557 nvfx_vp_emit(vpc, arith(VEC, SEQ, dst, mask, src[0], src[1], none));
558 break;
559 case TGSI_OPCODE_SFL:
560 nvfx_vp_emit(vpc, arith(VEC, SFL, dst, mask, src[0], src[1], none));
561 break;
562 case TGSI_OPCODE_SGE:
563 nvfx_vp_emit(vpc, arith(VEC, SGE, dst, mask, src[0], src[1], none));
564 break;
565 case TGSI_OPCODE_SGT:
566 nvfx_vp_emit(vpc, arith(VEC, SGT, dst, mask, src[0], src[1], none));
567 break;
568 case TGSI_OPCODE_SIN:
569 nvfx_vp_emit(vpc, arith(SCA, SIN, dst, mask, none, none, src[0]));
570 break;
571 case TGSI_OPCODE_SLE:
572 nvfx_vp_emit(vpc, arith(VEC, SLE, dst, mask, src[0], src[1], none));
573 break;
574 case TGSI_OPCODE_SLT:
575 nvfx_vp_emit(vpc, arith(VEC, SLT, dst, mask, src[0], src[1], none));
576 break;
577 case TGSI_OPCODE_SNE:
578 nvfx_vp_emit(vpc, arith(VEC, SNE, dst, mask, src[0], src[1], none));
579 break;
580 case TGSI_OPCODE_SSG:
581 nvfx_vp_emit(vpc, arith(VEC, SSG, dst, mask, src[0], src[1], none));
582 break;
583 case TGSI_OPCODE_STR:
584 nvfx_vp_emit(vpc, arith(VEC, STR, dst, mask, src[0], src[1], none));
585 break;
586 case TGSI_OPCODE_SUB:
587 nvfx_vp_emit(vpc, arith(VEC, ADD, dst, mask, src[0], none, neg(src[1])));
588 break;
589 case TGSI_OPCODE_XPD:
590 tmp = nvfx_src(temp(vpc));
591 nvfx_vp_emit(vpc, arith(VEC, MUL, tmp.reg, mask, swz(src[0], Z, X, Y, Y), swz(src[1], Y, Z, X, X), none));
592 nvfx_vp_emit(vpc, arith(VEC, MAD, dst, (mask & ~NVFX_VP_MASK_W), swz(src[0], Y, Z, X, X), swz(src[1], Z, X, Y, Y), neg(tmp)));
593 break;
594 default:
595 NOUVEAU_ERR("invalid opcode %d\n", finst->Instruction.Opcode);
596 return FALSE;
597 }
598
599 release_temps(vpc);
600 return TRUE;
601 }
602
603 static boolean
604 nvfx_vertprog_parse_decl_output(struct nvfx_context* nvfx, struct nvfx_vpc *vpc,
605 const struct tgsi_full_declaration *fdec)
606 {
607 unsigned idx = fdec->Range.First;
608 int hw;
609
610 switch (fdec->Semantic.Name) {
611 case TGSI_SEMANTIC_POSITION:
612 hw = NVFX_VP(INST_DEST_POS);
613 vpc->hpos_idx = idx;
614 break;
615 case TGSI_SEMANTIC_COLOR:
616 if (fdec->Semantic.Index == 0) {
617 hw = NVFX_VP(INST_DEST_COL0);
618 } else
619 if (fdec->Semantic.Index == 1) {
620 hw = NVFX_VP(INST_DEST_COL1);
621 } else {
622 NOUVEAU_ERR("bad colour semantic index\n");
623 return FALSE;
624 }
625 break;
626 case TGSI_SEMANTIC_BCOLOR:
627 if (fdec->Semantic.Index == 0) {
628 hw = NVFX_VP(INST_DEST_BFC0);
629 } else
630 if (fdec->Semantic.Index == 1) {
631 hw = NVFX_VP(INST_DEST_BFC1);
632 } else {
633 NOUVEAU_ERR("bad bcolour semantic index\n");
634 return FALSE;
635 }
636 break;
637 case TGSI_SEMANTIC_FOG:
638 hw = NVFX_VP(INST_DEST_FOGC);
639 break;
640 case TGSI_SEMANTIC_PSIZE:
641 hw = NVFX_VP(INST_DEST_PSZ);
642 break;
643 case TGSI_SEMANTIC_GENERIC:
644 hw = (vpc->vp->generic_to_fp_input[fdec->Semantic.Index] & 0xf)
645 + NVFX_VP(INST_DEST_TC(0)) - NVFX_FP_OP_INPUT_SRC_TC(0);
646 break;
647 case TGSI_SEMANTIC_EDGEFLAG:
648 /* not really an error just a fallback */
649 NOUVEAU_ERR("cannot handle edgeflag output\n");
650 return FALSE;
651 default:
652 NOUVEAU_ERR("bad output semantic\n");
653 return FALSE;
654 }
655
656 vpc->r_result[idx] = nvfx_reg(NVFXSR_OUTPUT, hw);
657 return TRUE;
658 }
659
660 static boolean
661 nvfx_vertprog_prepare(struct nvfx_context* nvfx, struct nvfx_vpc *vpc)
662 {
663 struct tgsi_parse_context p;
664 int high_temp = -1, high_addr = -1, nr_imm = 0, i;
665 struct util_semantic_set set;
666 unsigned char sem_layout[8];
667 unsigned sem_layout_size;
668 unsigned num_outputs;
669
670 num_outputs = util_semantic_set_from_program_file(&set, vpc->vp->pipe.tokens, TGSI_FILE_OUTPUT);
671
672 if(num_outputs > 8) {
673 NOUVEAU_ERR("too many vertex program outputs: %i\n", num_outputs);
674 return FALSE;
675 }
676 util_semantic_layout_from_set(sem_layout, &set, 8, 8);
677
678 /* hope 0xf is (0, 0, 0, 1) initialized; otherwise, we are _probably_ not required to do this */
679 memset(vpc->vp->generic_to_fp_input, 0x0f, sizeof(vpc->vp->generic_to_fp_input));
680 vpc->vp->texcoord_ouput_mask = 0;
681 for(int i = 0; i < 8; ++i) {
682 if(sem_layout[i] == 0xff)
683 continue;
684 vpc->vp->texcoord_ouput_mask |= (1 << i);
685 //printf("vp: GENERIC[%i] to fpreg %i\n", sem_layout[i], NVFX_FP_OP_INPUT_SRC_TC(0) + i);
686 vpc->vp->generic_to_fp_input[sem_layout[i]] = 0xf0 | (NVFX_FP_OP_INPUT_SRC_TC(0) + i);
687 }
688
689 tgsi_parse_init(&p, vpc->vp->pipe.tokens);
690 while (!tgsi_parse_end_of_tokens(&p)) {
691 const union tgsi_full_token *tok = &p.FullToken;
692
693 tgsi_parse_token(&p);
694 switch(tok->Token.Type) {
695 case TGSI_TOKEN_TYPE_IMMEDIATE:
696 nr_imm++;
697 break;
698 case TGSI_TOKEN_TYPE_DECLARATION:
699 {
700 const struct tgsi_full_declaration *fdec;
701
702 fdec = &p.FullToken.FullDeclaration;
703 switch (fdec->Declaration.File) {
704 case TGSI_FILE_TEMPORARY:
705 if (fdec->Range.Last > high_temp) {
706 high_temp =
707 fdec->Range.Last;
708 }
709 break;
710 #if 0 /* this would be nice.. except gallium doesn't track it */
711 case TGSI_FILE_ADDRESS:
712 if (fdec->Range.Last > high_addr) {
713 high_addr =
714 fdec->Range.Last;
715 }
716 break;
717 #endif
718 case TGSI_FILE_OUTPUT:
719 if (!nvfx_vertprog_parse_decl_output(nvfx, vpc, fdec))
720 return FALSE;
721 break;
722 default:
723 break;
724 }
725 }
726 break;
727 #if 1 /* yay, parse instructions looking for address regs instead */
728 case TGSI_TOKEN_TYPE_INSTRUCTION:
729 {
730 const struct tgsi_full_instruction *finst;
731 const struct tgsi_full_dst_register *fdst;
732
733 finst = &p.FullToken.FullInstruction;
734 fdst = &finst->Dst[0];
735
736 if (fdst->Register.File == TGSI_FILE_ADDRESS) {
737 if (fdst->Register.Index > high_addr)
738 high_addr = fdst->Register.Index;
739 }
740
741 }
742 break;
743 #endif
744 default:
745 break;
746 }
747 }
748 tgsi_parse_free(&p);
749
750 if (nr_imm) {
751 vpc->imm = CALLOC(nr_imm, sizeof(struct nvfx_reg));
752 assert(vpc->imm);
753 }
754
755 if (++high_temp) {
756 vpc->r_temp = CALLOC(high_temp, sizeof(struct nvfx_reg));
757 for (i = 0; i < high_temp; i++)
758 vpc->r_temp[i] = temp(vpc);
759 }
760
761 if (++high_addr) {
762 vpc->r_address = CALLOC(high_addr, sizeof(struct nvfx_reg));
763 for (i = 0; i < high_addr; i++)
764 vpc->r_address[i] = temp(vpc);
765 }
766
767 vpc->r_temps_discard = 0;
768 return TRUE;
769 }
770
771 DEBUG_GET_ONCE_BOOL_OPTION(nvfx_dump_vp, "NVFX_DUMP_VP", FALSE)
772
773 static void
774 nvfx_vertprog_translate(struct nvfx_context *nvfx,
775 struct nvfx_vertex_program *vp)
776 {
777 struct tgsi_parse_context parse;
778 struct nvfx_vpc *vpc = NULL;
779 struct nvfx_src none = nvfx_src(nvfx_reg(NVFXSR_NONE, 0));
780 int i;
781
782 vpc = CALLOC(1, sizeof(struct nvfx_vpc));
783 if (!vpc)
784 return;
785 vpc->nvfx = nvfx;
786 vpc->vp = vp;
787
788 if (!nvfx_vertprog_prepare(nvfx, vpc)) {
789 FREE(vpc);
790 return;
791 }
792
793 /* Redirect post-transform vertex position to a temp if user clip
794 * planes are enabled. We need to append code to the vtxprog
795 * to handle clip planes later.
796 */
797 if (vp->ucp.nr) {
798 vpc->r_result[vpc->hpos_idx] = temp(vpc);
799 vpc->r_temps_discard = 0;
800 }
801
802 tgsi_parse_init(&parse, vp->pipe.tokens);
803
804 while (!tgsi_parse_end_of_tokens(&parse)) {
805 tgsi_parse_token(&parse);
806
807 switch (parse.FullToken.Token.Type) {
808 case TGSI_TOKEN_TYPE_IMMEDIATE:
809 {
810 const struct tgsi_full_immediate *imm;
811
812 imm = &parse.FullToken.FullImmediate;
813 assert(imm->Immediate.DataType == TGSI_IMM_FLOAT32);
814 assert(imm->Immediate.NrTokens == 4 + 1);
815 vpc->imm[vpc->nr_imm++] =
816 constant(vpc, -1,
817 imm->u[0].Float,
818 imm->u[1].Float,
819 imm->u[2].Float,
820 imm->u[3].Float);
821 }
822 break;
823 case TGSI_TOKEN_TYPE_INSTRUCTION:
824 {
825 const struct tgsi_full_instruction *finst;
826 finst = &parse.FullToken.FullInstruction;
827 if (!nvfx_vertprog_parse_instruction(nvfx, vpc, finst))
828 goto out_err;
829 }
830 break;
831 default:
832 break;
833 }
834 }
835
836 /* Write out HPOS if it was redirected to a temp earlier */
837 if (vpc->r_result[vpc->hpos_idx].type != NVFXSR_OUTPUT) {
838 struct nvfx_reg hpos = nvfx_reg(NVFXSR_OUTPUT,
839 NVFX_VP(INST_DEST_POS));
840 struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
841
842 nvfx_vp_emit(vpc, arith(VEC, MOV, hpos, NVFX_VP_MASK_ALL, htmp, none, none));
843 }
844
845 /* Insert code to handle user clip planes */
846 for (i = 0; i < vp->ucp.nr; i++) {
847 struct nvfx_reg cdst = nvfx_reg(NVFXSR_OUTPUT,
848 NVFX_VP_INST_DEST_CLIP(i));
849 struct nvfx_src ceqn = nvfx_src(constant(vpc, -1,
850 nvfx->clip.ucp[i][0],
851 nvfx->clip.ucp[i][1],
852 nvfx->clip.ucp[i][2],
853 nvfx->clip.ucp[i][3]));
854 struct nvfx_src htmp = nvfx_src(vpc->r_result[vpc->hpos_idx]);
855 unsigned mask;
856
857 switch (i) {
858 case 0: case 3: mask = NVFX_VP_MASK_Y; break;
859 case 1: case 4: mask = NVFX_VP_MASK_Z; break;
860 case 2: case 5: mask = NVFX_VP_MASK_W; break;
861 default:
862 NOUVEAU_ERR("invalid clip dist #%d\n", i);
863 goto out_err;
864 }
865
866 nvfx_vp_emit(vpc, arith(VEC, DP4, cdst, mask, htmp, ceqn, none));
867 }
868
869 vp->insns[vp->nr_insns - 1].data[3] |= NVFX_VP_INST_LAST;
870
871 if(debug_get_option_nvfx_dump_vp())
872 {
873 debug_printf("\n");
874 tgsi_dump(vp->pipe.tokens, 0);
875
876 debug_printf("\n%s vertex program:\n", nvfx->is_nv4x ? "nv4x" : "nv3x");
877 for (i = 0; i < vp->nr_insns; i++)
878 debug_printf("%3u: %08x %08x %08x %08x\n", i, vp->insns[i].data[0], vp->insns[i].data[1], vp->insns[i].data[2], vp->insns[i].data[3]);
879 debug_printf("\n");
880 }
881
882 vp->translated = TRUE;
883 out_err:
884 tgsi_parse_free(&parse);
885 if (vpc->r_temp)
886 FREE(vpc->r_temp);
887 if (vpc->r_address)
888 FREE(vpc->r_address);
889 if (vpc->imm)
890 FREE(vpc->imm);
891 FREE(vpc);
892 }
893
894 boolean
895 nvfx_vertprog_validate(struct nvfx_context *nvfx)
896 {
897 struct pipe_context *pipe = &nvfx->pipe;
898 struct nvfx_screen *screen = nvfx->screen;
899 struct nouveau_channel *chan = screen->base.channel;
900 struct nouveau_grobj *eng3d = screen->eng3d;
901 struct nvfx_vertex_program *vp;
902 struct pipe_resource *constbuf;
903 boolean upload_code = FALSE, upload_data = FALSE;
904 int i;
905
906 if (nvfx->render_mode == HW) {
907 vp = nvfx->vertprog;
908 constbuf = nvfx->constbuf[PIPE_SHADER_VERTEX];
909
910 // TODO: ouch! can't we just use constant slots for these?!
911 if ((nvfx->dirty & NVFX_NEW_UCP) ||
912 memcmp(&nvfx->clip, &vp->ucp, sizeof(vp->ucp))) {
913 nvfx_vertprog_destroy(nvfx, vp);
914 memcpy(&vp->ucp, &nvfx->clip, sizeof(vp->ucp));
915 }
916 } else {
917 vp = nvfx->swtnl.vertprog;
918 constbuf = NULL;
919 }
920
921 /* Translate TGSI shader into hw bytecode */
922 if (!vp->translated)
923 {
924 nvfx->fallback_swtnl &= ~NVFX_NEW_VERTPROG;
925 nvfx_vertprog_translate(nvfx, vp);
926 if (!vp->translated) {
927 nvfx->fallback_swtnl |= NVFX_NEW_VERTPROG;
928 return FALSE;
929 }
930 }
931
932 /* Allocate hw vtxprog exec slots */
933 if (!vp->exec) {
934 struct nouveau_resource *heap = nvfx->screen->vp_exec_heap;
935 uint vplen = vp->nr_insns;
936
937 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec)) {
938 while (heap->next && heap->size < vplen) {
939 struct nvfx_vertex_program *evict;
940
941 evict = heap->next->priv;
942 nouveau_resource_free(&evict->exec);
943 }
944
945 if (nouveau_resource_alloc(heap, vplen, vp, &vp->exec))
946 assert(0);
947 }
948
949 upload_code = TRUE;
950 }
951
952 /* Allocate hw vtxprog const slots */
953 if (vp->nr_consts && !vp->data) {
954 struct nouveau_resource *heap = nvfx->screen->vp_data_heap;
955
956 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data)) {
957 while (heap->next && heap->size < vp->nr_consts) {
958 struct nvfx_vertex_program *evict;
959
960 evict = heap->next->priv;
961 nouveau_resource_free(&evict->data);
962 }
963
964 if (nouveau_resource_alloc(heap, vp->nr_consts, vp, &vp->data))
965 assert(0);
966 }
967
968 /*XXX: handle this some day */
969 assert(vp->data->start >= vp->data_start_min);
970
971 upload_data = TRUE;
972 if (vp->data_start != vp->data->start)
973 upload_code = TRUE;
974 }
975
976 /* If exec or data segments moved we need to patch the program to
977 * fixup offsets and register IDs.
978 */
979 if (vp->exec_start != vp->exec->start) {
980 for (i = 0; i < vp->nr_insns; i++) {
981 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
982
983 if (vpi->has_branch_offset) {
984 assert(0);
985 }
986 }
987
988 vp->exec_start = vp->exec->start;
989 }
990
991 if (vp->nr_consts && vp->data_start != vp->data->start) {
992 for (i = 0; i < vp->nr_insns; i++) {
993 struct nvfx_vertex_program_exec *vpi = &vp->insns[i];
994
995 if (vpi->const_index >= 0) {
996 vpi->data[1] &= ~NVFX_VP(INST_CONST_SRC_MASK);
997 vpi->data[1] |=
998 (vpi->const_index + vp->data->start) <<
999 NVFX_VP(INST_CONST_SRC_SHIFT);
1000
1001 }
1002 }
1003
1004 vp->data_start = vp->data->start;
1005 }
1006
1007 /* Update + Upload constant values */
1008 if (vp->nr_consts) {
1009 float *map = NULL;
1010
1011 if (constbuf)
1012 map = nvfx_buffer(constbuf)->data;
1013
1014 for (i = 0; i < vp->nr_consts; i++) {
1015 struct nvfx_vertex_program_data *vpd = &vp->consts[i];
1016
1017 if (vpd->index >= 0) {
1018 if (!upload_data &&
1019 !memcmp(vpd->value, &map[vpd->index * 4],
1020 4 * sizeof(float)))
1021 continue;
1022 memcpy(vpd->value, &map[vpd->index * 4],
1023 4 * sizeof(float));
1024 }
1025
1026 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_CONST_ID, 5);
1027 OUT_RING (chan, i + vp->data->start);
1028 OUT_RINGp (chan, (uint32_t *)vpd->value, 4);
1029 }
1030 }
1031
1032 /* Upload vtxprog */
1033 if (upload_code) {
1034 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_FROM_ID, 1);
1035 OUT_RING (chan, vp->exec->start);
1036 for (i = 0; i < vp->nr_insns; i++) {
1037 BEGIN_RING(chan, eng3d, NV34TCL_VP_UPLOAD_INST(0), 4);
1038 OUT_RINGp (chan, vp->insns[i].data, 4);
1039 }
1040 }
1041
1042 if(nvfx->dirty & (NVFX_NEW_VERTPROG | NVFX_NEW_UCP))
1043 {
1044 WAIT_RING(chan, 7);
1045 OUT_RING(chan, RING_3D(NV34TCL_VP_START_FROM_ID, 1));
1046 OUT_RING(chan, vp->exec->start);
1047 if(nvfx->is_nv4x) {
1048 OUT_RING(chan, RING_3D(NV40TCL_VP_ATTRIB_EN, 2));
1049 OUT_RING(chan, vp->ir);
1050 OUT_RING(chan, vp->or);
1051 }
1052 OUT_RING(chan, RING_3D(NV34TCL_VP_CLIP_PLANES_ENABLE, 1));
1053 OUT_RING(chan, vp->clip_ctrl);
1054 }
1055
1056 return TRUE;
1057 }
1058
1059 void
1060 nvfx_vertprog_destroy(struct nvfx_context *nvfx, struct nvfx_vertex_program *vp)
1061 {
1062 vp->translated = FALSE;
1063
1064 if (vp->nr_insns) {
1065 FREE(vp->insns);
1066 vp->insns = NULL;
1067 vp->nr_insns = 0;
1068 }
1069
1070 if (vp->nr_consts) {
1071 FREE(vp->consts);
1072 vp->consts = NULL;
1073 vp->nr_consts = 0;
1074 }
1075
1076 nouveau_resource_free(&vp->exec);
1077 vp->exec_start = 0;
1078 nouveau_resource_free(&vp->data);
1079 vp->data_start = 0;
1080 vp->data_start_min = 0;
1081
1082 vp->ir = vp->or = vp->clip_ctrl = 0;
1083 }