2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
31 #include "util/hash_table.h"
32 #include "util/u_dynarray.h"
34 #include "util/list.h"
36 #include "main/mtypes.h"
37 #include "compiler/nir_types.h"
38 #include "compiler/nir/nir.h"
43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
44 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
45 * instruction is actually a discard op. */
48 #define TARGET_BREAK 1
49 #define TARGET_CONTINUE 2
50 #define TARGET_DISCARD 3
52 typedef struct midgard_branch
{
53 /* If conditional, the condition is specified in r31.w */
56 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
57 bool invert_conditional
;
59 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
62 /* The actual target */
70 /* Instruction arguments represented as block-local SSA indices, rather than
71 * registers. Negative values mean unused. */
78 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
79 * in. Only valid for ALU ops. */
83 /* Generic in-memory data type repesenting a single logical instruction, rather
84 * than a single instruction group. This is the preferred form for code gen.
85 * Multiple midgard_insturctions will later be combined during scheduling,
86 * though this is not represented in this structure. Its format bridges
87 * the low-level binary representation with the higher level semantic meaning.
89 * Notably, it allows registers to be specified as block local SSA, for code
90 * emitted before the register allocation pass.
93 typedef struct midgard_instruction
{
94 /* Must be first for casting */
95 struct list_head link
;
97 unsigned type
; /* ALU, load/store, texture */
99 /* If the register allocator has not run yet... */
102 /* Special fields for an ALU instruction */
103 midgard_reg_info registers
;
105 /* I.e. (1 << alu_bit) */
108 /* When emitting bundle, should this instruction have a break forced
109 * before it? Used for r31 writes which are valid only within a single
110 * bundle and *need* to happen as early as possible... this is a hack,
111 * TODO remove when we have a scheduler */
116 uint16_t inline_constant
;
117 bool has_blend_constant
;
121 bool prepacked_branch
;
124 midgard_load_store_word load_store
;
125 midgard_vector_alu alu
;
126 midgard_texture_word texture
;
127 midgard_branch_extended branch_extended
;
130 /* General branch, rather than packed br_compact. Higher level
131 * than the other components */
132 midgard_branch branch
;
134 } midgard_instruction
;
136 typedef struct midgard_block
{
137 /* Link to next block. Must be first for mir_get_block */
138 struct list_head link
;
140 /* List of midgard_instructions emitted for the current block */
141 struct list_head instructions
;
145 /* List of midgard_bundles emitted (after the scheduler has run) */
146 struct util_dynarray bundles
;
148 /* Number of quadwords _actually_ emitted, as determined after scheduling */
149 unsigned quadword_count
;
151 /* Successors: always one forward (the block after us), maybe
152 * one backwards (for a backward branch). No need for a second
153 * forward, since graph traversal would get there eventually
155 struct midgard_block
*successors
[2];
156 unsigned nr_successors
;
158 /* The successors pointer form a graph, and in the case of
159 * complex control flow, this graph has a cycles. To aid
160 * traversal during liveness analysis, we have a visited?
161 * boolean for passes to use as they see fit, provided they
166 typedef struct midgard_bundle
{
167 /* Tag for the overall bundle */
170 /* Instructions contained by the bundle */
171 int instruction_count
;
172 midgard_instruction
*instructions
[5];
174 /* Bundle-wide ALU configuration */
177 bool has_embedded_constants
;
179 bool has_blend_constant
;
182 typedef struct compiler_context
{
184 gl_shader_stage stage
;
186 /* Is internally a blend shader? Depends on stage == FRAGMENT */
189 /* Tracking for blend constant patching */
190 int blend_constant_offset
;
192 /* Current NIR function */
195 /* Unordered list of midgard_blocks */
197 struct list_head blocks
;
199 midgard_block
*initial_block
;
200 midgard_block
*previous_source_block
;
201 midgard_block
*final_block
;
203 /* List of midgard_instructions emitted for the current block */
204 midgard_block
*current_block
;
206 /* The current "depth" of the loop, for disambiguating breaks/continues
207 * when using nested loops */
208 int current_loop_depth
;
210 /* Constants which have been loaded, for later inlining */
211 struct hash_table_u64
*ssa_constants
;
213 /* SSA values / registers which have been aliased. Naively, these
214 * demand a fmov output; instead, we alias them in a later pass to
215 * avoid the wasted op.
217 * A note on encoding: to avoid dynamic memory management here, rather
218 * than ampping to a pointer, we map to the source index; the key
219 * itself is just the destination index. */
221 struct hash_table_u64
*ssa_to_alias
;
222 struct set
*leftover_ssa_to_alias
;
224 /* Actual SSA-to-register for RA */
225 struct hash_table_u64
*ssa_to_register
;
227 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
228 struct hash_table_u64
*hash_to_temp
;
232 /* Just the count of the max register used. Higher count => higher
233 * register pressure */
236 /* Used for cont/last hinting. Increase when a tex op is added.
237 * Decrease when a tex op is removed. */
238 int texture_op_count
;
240 /* Mapping of texture register -> SSA index for unaliasing */
241 int texture_index
[2];
243 /* If any path hits a discard instruction */
246 /* The number of uniforms allowable for the fast path */
249 /* Count of instructions emitted from NIR overall, across all blocks */
250 int instruction_count
;
252 /* Alpha ref value passed in */
255 /* The index corresponding to the fragment output */
256 unsigned fragment_output
;
258 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
259 unsigned sysvals
[MAX_SYSVAL_COUNT
];
260 unsigned sysval_count
;
261 struct hash_table_u64
*sysval_to_id
;
264 /* Helpers for manipulating the above structures (forming the driver IR) */
266 /* Append instruction to end of current block */
268 static inline midgard_instruction
*
269 mir_upload_ins(struct midgard_instruction ins
)
271 midgard_instruction
*heap
= malloc(sizeof(ins
));
272 memcpy(heap
, &ins
, sizeof(ins
));
277 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
279 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
283 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
285 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
289 mir_remove_instruction(struct midgard_instruction
*ins
)
291 list_del(&ins
->link
);
294 static inline midgard_instruction
*
295 mir_prev_op(struct midgard_instruction
*ins
)
297 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
300 static inline midgard_instruction
*
301 mir_next_op(struct midgard_instruction
*ins
)
303 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
306 #define mir_foreach_block(ctx, v) \
307 list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
309 #define mir_foreach_block_from(ctx, from, v) \
310 list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
312 #define mir_foreach_instr(ctx, v) \
313 list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
315 #define mir_foreach_instr_safe(ctx, v) \
316 list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
318 #define mir_foreach_instr_in_block(block, v) \
319 list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
321 #define mir_foreach_instr_in_block_safe(block, v) \
322 list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
324 #define mir_foreach_instr_in_block_safe_rev(block, v) \
325 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
327 #define mir_foreach_instr_in_block_from(block, v, from) \
328 list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
330 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
331 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
333 #define mir_foreach_bundle_in_block(block, v) \
334 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
336 #define mir_foreach_instr_global(ctx, v) \
337 mir_foreach_block(ctx, v_block) \
338 mir_foreach_instr_in_block(v_block, v)
341 static inline midgard_instruction
*
342 mir_last_in_block(struct midgard_block
*block
)
344 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
347 static inline midgard_block
*
348 mir_get_block(compiler_context
*ctx
, int idx
)
350 struct list_head
*lst
= &ctx
->blocks
;
355 return (struct midgard_block
*) lst
;
359 mir_is_alu_bundle(midgard_bundle
*bundle
)
361 return IS_ALU(bundle
->tag
);
364 /* MIR manipulation */
366 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
367 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
368 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
372 void mir_print_instruction(midgard_instruction
*ins
);
373 void mir_print_bundle(midgard_bundle
*ctx
);
374 void mir_print_block(midgard_block
*block
);
375 void mir_print_shader(compiler_context
*ctx
);
379 static const midgard_vector_alu_src blank_alu_src
= {
380 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
383 static const midgard_vector_alu_src blank_alu_src_xxxx
= {
384 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
387 static const midgard_scalar_alu_src blank_scalar_alu_src
= {
391 /* Used for encoding the unused source of 1-op instructions */
392 static const midgard_vector_alu_src zero_alu_src
= { 0 };
394 /* 'Intrinsic' move for aliasing */
396 static inline midgard_instruction
397 v_mov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
399 midgard_instruction ins
= {
402 .src0
= SSA_UNUSED_1
,
407 .op
= midgard_alu_op_imov
,
408 .reg_mode
= midgard_reg_mode_32
,
409 .dest_override
= midgard_dest_override_none
,
410 .outmod
= midgard_outmod_int_wrap
,
412 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
413 .src2
= vector_alu_srco_unsigned(mod
)
422 void schedule_program(compiler_context
*ctx
);
424 /* Register allocation */
428 struct ra_graph
* allocate_registers(compiler_context
*ctx
);
429 void install_registers(compiler_context
*ctx
, struct ra_graph
*g
);
430 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
431 bool mir_has_multiple_writes(compiler_context
*ctx
, int src
);
433 void mir_create_pipeline_registers(compiler_context
*ctx
);
437 void emit_binary_bundle(
438 compiler_context
*ctx
,
439 midgard_bundle
*bundle
,
440 struct util_dynarray
*emission
,