src/gallium/drivers/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Instruction arguments represented as block-local SSA indices, rather than
  71  * registers. Negative values mean unused. */
  72
  73 typedef struct {
  74         int src0;
  75         int src1;
  76         int dest;
  77
  78         /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
  79          * in. Only valid for ALU ops. */
  80         bool inline_constant;
  81 } ssa_args;
  82
  83 /* Generic in-memory data type repesenting a single logical instruction, rather
  84  * than a single instruction group. This is the preferred form for code gen.
  85  * Multiple midgard_insturctions will later be combined during scheduling,
  86  * though this is not represented in this structure.  Its format bridges
  87  * the low-level binary representation with the higher level semantic meaning.
  88  *
  89  * Notably, it allows registers to be specified as block local SSA, for code
  90  * emitted before the register allocation pass.
  91  */
  92
  93 typedef struct midgard_instruction {
  94         /* Must be first for casting */
  95         struct list_head link;
  96
  97         unsigned type; /* ALU, load/store, texture */
  98
  99         /* If the register allocator has not run yet... */
 100         ssa_args ssa_args;
 101
 102         /* Special fields for an ALU instruction */
 103         midgard_reg_info registers;
 104
 105         /* I.e. (1 << alu_bit) */
 106         int unit;
 107
 108         /* When emitting bundle, should this instruction have a break forced
 109          * before it? Used for r31 writes which are valid only within a single
 110          * bundle and *need* to happen as early as possible... this is a hack,
 111          * TODO remove when we have a scheduler */
 112         bool precede_break;
 113
 114         bool has_constants;
 115         float constants[4];
 116         uint16_t inline_constant;
 117         bool has_blend_constant;
 118
 119         bool compact_branch;
 120         bool writeout;
 121         bool prepacked_branch;
 122
 123         /* Masks in a saneish format. One bit per channel, not packed fancy.
 124          * Use this instead of the op specific ones, and switch over at emit
 125          * time */
 126         uint16_t mask;
 127
 128         union {
 129                 midgard_load_store_word load_store;
 130                 midgard_vector_alu alu;
 131                 midgard_texture_word texture;
 132                 midgard_branch_extended branch_extended;
 133                 uint16_t br_compact;
 134
 135                 /* General branch, rather than packed br_compact. Higher level
 136                  * than the other components */
 137                 midgard_branch branch;
 138         };
 139 } midgard_instruction;
 140
 141 typedef struct midgard_block {
 142         /* Link to next block. Must be first for mir_get_block */
 143         struct list_head link;
 144
 145         /* List of midgard_instructions emitted for the current block */
 146         struct list_head instructions;
 147
 148         bool is_scheduled;
 149
 150         /* List of midgard_bundles emitted (after the scheduler has run) */
 151         struct util_dynarray bundles;
 152
 153         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 154         unsigned quadword_count;
 155
 156         /* Successors: always one forward (the block after us), maybe
 157          * one backwards (for a backward branch). No need for a second
 158          * forward, since graph traversal would get there eventually
 159          * anyway */
 160         struct midgard_block *successors[2];
 161         unsigned nr_successors;
 162
 163         /* The successors pointer form a graph, and in the case of
 164          * complex control flow, this graph has a cycles. To aid
 165          * traversal during liveness analysis, we have a visited?
 166          * boolean for passes to use as they see fit, provided they
 167          * clean up later */
 168         bool visited;
 169 } midgard_block;
 170
 171 typedef struct midgard_bundle {
 172         /* Tag for the overall bundle */
 173         int tag;
 174
 175         /* Instructions contained by the bundle */
 176         int instruction_count;
 177         midgard_instruction *instructions[5];
 178
 179         /* Bundle-wide ALU configuration */
 180         int padding;
 181         int control;
 182         bool has_embedded_constants;
 183         float constants[4];
 184         bool has_blend_constant;
 185 } midgard_bundle;
 186
 187 typedef struct compiler_context {
 188         nir_shader *nir;
 189         gl_shader_stage stage;
 190
 191         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 192         bool is_blend;
 193
 194         /* Tracking for blend constant patching */
 195         int blend_constant_offset;
 196
 197         /* Current NIR function */
 198         nir_function *func;
 199
 200         /* Unordered list of midgard_blocks */
 201         int block_count;
 202         struct list_head blocks;
 203
 204         midgard_block *initial_block;
 205         midgard_block *previous_source_block;
 206         midgard_block *final_block;
 207
 208         /* List of midgard_instructions emitted for the current block */
 209         midgard_block *current_block;
 210
 211         /* The current "depth" of the loop, for disambiguating breaks/continues
 212          * when using nested loops */
 213         int current_loop_depth;
 214
 215         /* Constants which have been loaded, for later inlining */
 216         struct hash_table_u64 *ssa_constants;
 217
 218         /* SSA values / registers which have been aliased. Naively, these
 219          * demand a fmov output; instead, we alias them in a later pass to
 220          * avoid the wasted op.
 221          *
 222          * A note on encoding: to avoid dynamic memory management here, rather
 223          * than ampping to a pointer, we map to the source index; the key
 224          * itself is just the destination index. */
 225
 226         struct hash_table_u64 *ssa_to_alias;
 227         struct set *leftover_ssa_to_alias;
 228
 229         /* Actual SSA-to-register for RA */
 230         struct hash_table_u64 *ssa_to_register;
 231
 232         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 233         struct hash_table_u64 *hash_to_temp;
 234         int temp_count;
 235         int max_hash;
 236
 237         /* Just the count of the max register used. Higher count => higher
 238          * register pressure */
 239         int work_registers;
 240
 241         /* Used for cont/last hinting. Increase when a tex op is added.
 242          * Decrease when a tex op is removed. */
 243         int texture_op_count;
 244
 245         /* Mapping of texture register -> SSA index for unaliasing */
 246         int texture_index[2];
 247
 248         /* If any path hits a discard instruction */
 249         bool can_discard;
 250
 251         /* The number of uniforms allowable for the fast path */
 252         int uniform_cutoff;
 253
 254         /* Count of instructions emitted from NIR overall, across all blocks */
 255         int instruction_count;
 256
 257         /* Alpha ref value passed in */
 258         float alpha_ref;
 259
 260         /* The index corresponding to the fragment output */
 261         unsigned fragment_output;
 262
 263         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 264         unsigned sysvals[MAX_SYSVAL_COUNT];
 265         unsigned sysval_count;
 266         struct hash_table_u64 *sysval_to_id;
 267 } compiler_context;
 268
 269 /* Helpers for manipulating the above structures (forming the driver IR) */
 270
 271 /* Append instruction to end of current block */
 272
 273 static inline midgard_instruction *
 274 mir_upload_ins(struct midgard_instruction ins)
 275 {
 276         midgard_instruction *heap = malloc(sizeof(ins));
 277         memcpy(heap, &ins, sizeof(ins));
 278         return heap;
 279 }
 280
 281 static inline void
 282 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 283 {
 284         list_addtail(&(mir_upload_ins(ins))->link, &ctx->current_block->instructions);
 285 }
 286
 287 static inline void
 288 mir_insert_instruction_before(struct midgard_instruction *tag, struct midgard_instruction ins)
 289 {
 290         list_addtail(&(mir_upload_ins(ins))->link, &tag->link);
 291 }
 292
 293 static inline void
 294 mir_remove_instruction(struct midgard_instruction *ins)
 295 {
 296         list_del(&ins->link);
 297 }
 298
 299 static inline midgard_instruction*
 300 mir_prev_op(struct midgard_instruction *ins)
 301 {
 302         return list_last_entry(&(ins->link), midgard_instruction, link);
 303 }
 304
 305 static inline midgard_instruction*
 306 mir_next_op(struct midgard_instruction *ins)
 307 {
 308         return list_first_entry(&(ins->link), midgard_instruction, link);
 309 }
 310
 311 #define mir_foreach_block(ctx, v) \
 312         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 313
 314 #define mir_foreach_block_from(ctx, from, v) \
 315         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 316
 317 #define mir_foreach_instr(ctx, v) \
 318         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 319
 320 #define mir_foreach_instr_safe(ctx, v) \
 321         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 322
 323 #define mir_foreach_instr_in_block(block, v) \
 324         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 325
 326 #define mir_foreach_instr_in_block_safe(block, v) \
 327         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 328
 329 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 330         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 331
 332 #define mir_foreach_instr_in_block_from(block, v, from) \
 333         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 334
 335 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 336         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 337
 338 #define mir_foreach_bundle_in_block(block, v) \
 339         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 340
 341 #define mir_foreach_instr_global(ctx, v) \
 342         mir_foreach_block(ctx, v_block) \
 343                 mir_foreach_instr_in_block(v_block, v)
 344
 345
 346 static inline midgard_instruction *
 347 mir_last_in_block(struct midgard_block *block)
 348 {
 349         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 350 }
 351
 352 static inline midgard_block *
 353 mir_get_block(compiler_context *ctx, int idx)
 354 {
 355         struct list_head *lst = &ctx->blocks;
 356
 357         while ((idx--) + 1)
 358                 lst = lst->next;
 359
 360         return (struct midgard_block *) lst;
 361 }
 362
 363 static inline bool
 364 mir_is_alu_bundle(midgard_bundle *bundle)
 365 {
 366         return IS_ALU(bundle->tag);
 367 }
 368
 369 /* MIR manipulation */
 370
 371 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 372 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 373 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 374
 375 /* MIR printing */
 376
 377 void mir_print_instruction(midgard_instruction *ins);
 378 void mir_print_bundle(midgard_bundle *ctx);
 379 void mir_print_block(midgard_block *block);
 380 void mir_print_shader(compiler_context *ctx);
 381
 382 /* MIR goodies */
 383
 384 static const midgard_vector_alu_src blank_alu_src = {
 385         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 386 };
 387
 388 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 389         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 390 };
 391
 392 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 393         .full = true
 394 };
 395
 396 /* Used for encoding the unused source of 1-op instructions */
 397 static const midgard_vector_alu_src zero_alu_src = { 0 };
 398
 399 /* 'Intrinsic' move for aliasing */
 400
 401 static inline midgard_instruction
 402 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 403 {
 404         midgard_instruction ins = {
 405                 .type = TAG_ALU_4,
 406                 .mask = 0xF,
 407                 .ssa_args = {
 408                         .src0 = SSA_UNUSED_1,
 409                         .src1 = src,
 410                         .dest = dest,
 411                 },
 412                 .alu = {
 413                         .op = midgard_alu_op_imov,
 414                         .reg_mode = midgard_reg_mode_32,
 415                         .dest_override = midgard_dest_override_none,
 416                         .outmod = midgard_outmod_int_wrap,
 417                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 418                         .src2 = vector_alu_srco_unsigned(mod)
 419                 },
 420         };
 421
 422         return ins;
 423 }
 424
 425 /* Scheduling */
 426
 427 void schedule_program(compiler_context *ctx);
 428
 429 /* Register allocation */
 430
 431 struct ra_graph;
 432
 433 struct ra_graph* allocate_registers(compiler_context *ctx);
 434 void install_registers(compiler_context *ctx, struct ra_graph *g);
 435 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 436 bool mir_has_multiple_writes(compiler_context *ctx, int src);
 437
 438 void mir_create_pipeline_registers(compiler_context *ctx);
 439
 440 /* Final emission */
 441
 442 void emit_binary_bundle(
 443                 compiler_context *ctx,
 444                 midgard_bundle *bundle,
 445                 struct util_dynarray *emission,
 446                 int next_tag);
 447 #endif