src/gallium/drivers/panfrost/midgard/helpers.h

   1 /* Author(s):
   2  *  Alyssa Rosenzweig
   3  *
   4  * Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  19  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /* Some constants and macros not found in the disassembler */
  26
  27 #define OP_IS_STORE(op) (\
  28                 op == midgard_op_store_vary_16 || \
  29                 op == midgard_op_store_vary_32 \
  30         )
  31
  32 /* ALU control words are single bit fields with a lot of space */
  33
  34 #define ALU_ENAB_VEC_MUL  (1 << 17)
  35 #define ALU_ENAB_SCAL_ADD  (1 << 19)
  36 #define ALU_ENAB_VEC_ADD  (1 << 21)
  37 #define ALU_ENAB_SCAL_MUL  (1 << 23)
  38 #define ALU_ENAB_VEC_LUT  (1 << 25)
  39 #define ALU_ENAB_BR_COMPACT (1 << 26)
  40 #define ALU_ENAB_BRANCH   (1 << 27)
  41
  42 /* Other opcode properties that don't conflict with the ALU_ENABs, non-ISA */
  43
  44 /* Denotes an opcode that takes a vector input with a fixed-number of
  45  * channels, but outputs to only a single output channel, like dot products.
  46  * For these, to determine the effective mask, this quirk can be set. We have
  47  * an intentional off-by-one (a la MALI_POSITIVE), since 0-channel makes no
  48  * sense but we need to fit 4 channels in 2-bits. Similarly, 1-channel doesn't
  49  * make sense (since then why are we quirked?), so that corresponds to "no
  50  * count set" */
  51
  52 #define OP_CHANNEL_COUNT(c) ((c - 1) << 0)
  53 #define GET_CHANNEL_COUNT(c) ((c & (0x3 << 0)) ? ((c & (0x3 << 0)) + 1) : 0)
  54
  55 /* For instructions that take a single argument, normally the first argument
  56  * slot is used for the argument and the second slot is a dummy #0 constant.
  57  * However, there are exceptions: instructions like fmov store their argument
  58  * in the _second_ slot and store a dummy r24 in the first slot, designated by
  59  * QUIRK_FLIPPED_R24 */
  60
  61 #define QUIRK_FLIPPED_R24 (1 << 2)
  62
  63 /* Vector-independant shorthands for the above; these numbers are arbitrary and
  64  * not from the ISA. Convert to the above with unit_enum_to_midgard */
  65
  66 #define UNIT_MUL 0
  67 #define UNIT_ADD 1
  68 #define UNIT_LUT 2
  69
  70 /* 4-bit type tags */
  71
  72 #define TAG_TEXTURE_4 0x3
  73 #define TAG_LOAD_STORE_4 0x5
  74 #define TAG_ALU_4 0x8
  75 #define TAG_ALU_8 0x9
  76 #define TAG_ALU_12 0xA
  77 #define TAG_ALU_16 0xB
  78
  79 /* Special register aliases */
  80
  81 #define MAX_WORK_REGISTERS 16
  82
  83 /* Uniforms are begin at (REGISTER_UNIFORMS - uniform_count) */
  84 #define REGISTER_UNIFORMS 24
  85
  86 #define REGISTER_UNUSED 24
  87 #define REGISTER_CONSTANT 26
  88 #define REGISTER_VARYING_BASE 26
  89 #define REGISTER_OFFSET 27
  90 #define REGISTER_TEXTURE_BASE 28
  91 #define REGISTER_SELECT 31
  92
  93 /* Special uniforms used for e.g. vertex epilogues */
  94 #define SPECIAL_UNIFORM_BASE (1 << 24)
  95 #define UNIFORM_VIEWPORT (SPECIAL_UNIFORM_BASE + 0)
  96
  97 /* SSA helper aliases to mimic the registers. UNUSED_0 encoded as an inline
  98  * constant. UNUSED_1 encoded as REGISTER_UNUSED */
  99
 100 #define SSA_UNUSED_0 0
 101 #define SSA_UNUSED_1 -2
 102
 103 #define SSA_FIXED_SHIFT 24
 104 #define SSA_FIXED_REGISTER(reg) ((1 + reg) << SSA_FIXED_SHIFT)
 105 #define SSA_REG_FROM_FIXED(reg) ((reg >> SSA_FIXED_SHIFT) - 1)
 106 #define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
 107
 108 /* Swizzle support */
 109
 110 #define SWIZZLE(A, B, C, D) ((D << 6) | (C << 4) | (B << 2) | (A << 0))
 111 #define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
 112 #define COMPONENT_X 0x0
 113 #define COMPONENT_Y 0x1
 114 #define COMPONENT_Z 0x2
 115 #define COMPONENT_W 0x3
 116
 117 /* See ISA notes */
 118
 119 #define LDST_NOP (3)
 120
 121 /* Is this opcode that of an integer? */
 122 static bool
 123 midgard_is_integer_op(int op)
 124 {
 125         switch (op) {
 126         case midgard_alu_op_iadd:
 127         case midgard_alu_op_ishladd:
 128         case midgard_alu_op_isub:
 129         case midgard_alu_op_imul:
 130         case midgard_alu_op_imin:
 131         case midgard_alu_op_imax:
 132         case midgard_alu_op_iasr:
 133         case midgard_alu_op_ilsr:
 134         case midgard_alu_op_ishl:
 135         case midgard_alu_op_iand:
 136         case midgard_alu_op_ior:
 137         case midgard_alu_op_inot:
 138         case midgard_alu_op_iandnot:
 139         case midgard_alu_op_ixor:
 140         case midgard_alu_op_imov:
 141
 142         //case midgard_alu_op_f2i:
 143         //case midgard_alu_op_f2u:
 144         case midgard_alu_op_ieq:
 145         case midgard_alu_op_ine:
 146         case midgard_alu_op_ilt:
 147         case midgard_alu_op_ile:
 148         case midgard_alu_op_iball_eq:
 149         case midgard_alu_op_ibany_neq:
 150
 151         //case midgard_alu_op_i2f:
 152         //case midgard_alu_op_u2f:
 153         case midgard_alu_op_icsel:
 154                 return true;
 155
 156         default:
 157                 return false;
 158         }
 159 }
 160
 161 /* Is this unit a branch? */
 162 static bool
 163 midgard_is_branch_unit(unsigned unit)
 164 {
 165         return (unit == ALU_ENAB_BRANCH) || (unit == ALU_ENAB_BR_COMPACT);
 166 }
 167
 168 /* There are five ALU units: VMUL, VADD, SMUL, SADD, LUT. A given opcode is
 169  * implemented on some subset of these units (or occassionally all of them).
 170  * This table encodes a bit mask of valid units for each opcode, so the
 171  * scheduler can figure where to plonk the instruction. */
 172
 173 /* Shorthands for each unit */
 174 #define UNIT_VMUL ALU_ENAB_VEC_MUL
 175 #define UNIT_SADD ALU_ENAB_SCAL_ADD
 176 #define UNIT_VADD ALU_ENAB_VEC_ADD
 177 #define UNIT_SMUL ALU_ENAB_SCAL_MUL
 178 #define UNIT_VLUT ALU_ENAB_VEC_LUT
 179
 180 /* Shorthands for usual combinations of units */
 181
 182 #define UNITS_MUL (UNIT_VMUL | UNIT_SMUL)
 183 #define UNITS_ADD (UNIT_VADD | UNIT_SADD)
 184 #define UNITS_MOST (UNITS_MUL | UNITS_ADD)
 185 #define UNITS_ALL (UNITS_MOST | UNIT_VLUT)
 186 #define UNITS_SCALAR (UNIT_SADD | UNIT_SMUL)
 187 #define UNITS_VECTOR (UNIT_VMUL | UNIT_VADD)
 188 #define UNITS_ANY_VECTOR (UNITS_VECTOR | UNIT_VLUT)
 189
 190 static unsigned alu_opcode_props[256] = {
 191         [midgard_alu_op_fadd]            = UNITS_ADD,
 192         [midgard_alu_op_fmul]            = UNITS_MUL | UNIT_VLUT,
 193         [midgard_alu_op_fmin]            = UNITS_MUL | UNITS_ADD,
 194         [midgard_alu_op_fmax]            = UNITS_MUL | UNITS_ADD,
 195         [midgard_alu_op_imin]            = UNITS_MOST,
 196         [midgard_alu_op_imax]            = UNITS_MOST,
 197         [midgard_alu_op_fmov]            = UNITS_ALL | QUIRK_FLIPPED_R24,
 198         [midgard_alu_op_fround]          = UNITS_ADD,
 199         [midgard_alu_op_froundeven]      = UNITS_ADD,
 200         [midgard_alu_op_ftrunc]          = UNITS_ADD,
 201         [midgard_alu_op_ffloor]          = UNITS_ADD,
 202         [midgard_alu_op_fceil]           = UNITS_ADD,
 203         [midgard_alu_op_ffma]            = UNIT_VLUT,
 204
 205         /* Though they output a scalar, they need to run on a vector unit
 206          * since they process vectors */
 207         [midgard_alu_op_fdot3]           = UNIT_VMUL | OP_CHANNEL_COUNT(3),
 208         [midgard_alu_op_fdot4]           = UNIT_VMUL | OP_CHANNEL_COUNT(4),
 209
 210         /* Incredibly, iadd can run on vmul, etc */
 211         [midgard_alu_op_iadd]            = UNITS_MOST,
 212         [midgard_alu_op_isub]            = UNITS_MOST,
 213         [midgard_alu_op_imul]            = UNITS_MOST,
 214         [midgard_alu_op_imov]            = UNITS_MOST | QUIRK_FLIPPED_R24,
 215
 216         /* For vector comparisons, use ball etc */
 217         [midgard_alu_op_feq]             = UNITS_MOST,
 218         [midgard_alu_op_fne]             = UNITS_MOST,
 219         [midgard_alu_op_flt]             = UNIT_SADD,
 220         [midgard_alu_op_ieq]             = UNITS_MOST,
 221         [midgard_alu_op_ine]             = UNITS_MOST,
 222         [midgard_alu_op_ilt]             = UNITS_MOST,
 223         [midgard_alu_op_ile]             = UNITS_MOST,
 224
 225         [midgard_alu_op_icsel]           = UNITS_ADD,
 226         [midgard_alu_op_fcsel]           = UNITS_ADD | UNIT_SMUL,
 227
 228         [midgard_alu_op_frcp]            = UNIT_VLUT,
 229         [midgard_alu_op_frsqrt]          = UNIT_VLUT,
 230         [midgard_alu_op_fsqrt]           = UNIT_VLUT,
 231         [midgard_alu_op_fexp2]           = UNIT_VLUT,
 232         [midgard_alu_op_flog2]           = UNIT_VLUT,
 233
 234         [midgard_alu_op_f2i]             = UNITS_ADD,
 235         [midgard_alu_op_f2u]             = UNITS_ADD,
 236         [midgard_alu_op_f2u8]            = UNITS_ADD,
 237         [midgard_alu_op_i2f]             = UNITS_ADD,
 238         [midgard_alu_op_u2f]             = UNITS_ADD,
 239
 240         [midgard_alu_op_fsin]            = UNIT_VLUT,
 241         [midgard_alu_op_fcos]            = UNIT_VLUT,
 242
 243         [midgard_alu_op_iand]            = UNITS_ADD, /* XXX: Test case where it's right on smul but not sadd */
 244         [midgard_alu_op_ior]             = UNITS_ADD,
 245         [midgard_alu_op_ixor]            = UNITS_ADD,
 246         [midgard_alu_op_inot]            = UNITS_MOST,
 247         [midgard_alu_op_ishl]            = UNITS_ADD,
 248         [midgard_alu_op_iasr]            = UNITS_ADD,
 249         [midgard_alu_op_ilsr]            = UNITS_ADD,
 250         [midgard_alu_op_ilsr]            = UNITS_ADD,
 251
 252         [midgard_alu_op_fball_eq]        = UNITS_MOST,
 253         [midgard_alu_op_fbany_neq]       = UNITS_MOST,
 254         [midgard_alu_op_iball_eq]        = UNITS_MOST,
 255         [midgard_alu_op_ibany_neq]       = UNITS_MOST
 256 };