2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "compiler/glsl/glsl_to_nir.h"
34 #include "compiler/nir_types.h"
35 #include "main/imports.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/register_allocate.h"
39 #include "util/u_dynarray.h"
40 #include "util/list.h"
41 #include "main/mtypes.h"
44 #include "midgard_nir.h"
45 #include "midgard_compile.h"
48 #include "disassemble.h"
50 /* Instruction arguments represented as block-local SSA indices, rather than
51 * registers. Negative values mean unused. */
58 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
59 * in. Only valid for ALU ops. */
63 /* Forward declare so midgard_branch can reference */
66 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
67 * the hardware), hence why that must be zero */
70 #define TARGET_BREAK 1
71 #define TARGET_CONTINUE 2
73 typedef struct midgard_branch
{
74 /* If conditional, the condition is specified in r31.w */
77 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
78 bool invert_conditional
;
80 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
83 /* The actual target */
91 /* Generic in-memory data type repesenting a single logical instruction, rather
92 * than a single instruction group. This is the preferred form for code gen.
93 * Multiple midgard_insturctions will later be combined during scheduling,
94 * though this is not represented in this structure. Its format bridges
95 * the low-level binary representation with the higher level semantic meaning.
97 * Notably, it allows registers to be specified as block local SSA, for code
98 * emitted before the register allocation pass.
101 typedef struct midgard_instruction
{
102 /* Must be first for casting */
103 struct list_head link
;
105 unsigned type
; /* ALU, load/store, texture */
107 /* If the register allocator has not run yet... */
110 /* Special fields for an ALU instruction */
111 midgard_reg_info registers
;
113 /* I.e. (1 << alu_bit) */
118 uint16_t inline_constant
;
119 bool has_blend_constant
;
123 bool prepacked_branch
;
126 midgard_load_store_word load_store
;
127 midgard_vector_alu alu
;
128 midgard_texture_word texture
;
131 /* General branch, rather than packed br_compact. Higher level
132 * than the other components */
133 midgard_branch branch
;
135 } midgard_instruction
;
137 typedef struct midgard_block
{
138 /* Link to next block. Must be first for mir_get_block */
139 struct list_head link
;
141 /* List of midgard_instructions emitted for the current block */
142 struct list_head instructions
;
146 /* List of midgard_bundles emitted (after the scheduler has run) */
147 struct util_dynarray bundles
;
149 /* Number of quadwords _actually_ emitted, as determined after scheduling */
150 unsigned quadword_count
;
152 struct midgard_block
*next_fallthrough
;
155 /* Helpers to generate midgard_instruction's using macro magic, since every
156 * driver seems to do it that way */
158 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
160 #define M_LOAD_STORE(name, rname, uname) \
161 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
162 midgard_instruction i = { \
163 .type = TAG_LOAD_STORE_4, \
170 .op = midgard_op_##name, \
172 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W), \
180 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
181 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
183 const midgard_vector_alu_src blank_alu_src
= {
184 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
187 const midgard_scalar_alu_src blank_scalar_alu_src
= {
191 /* Used for encoding the unused source of 1-op instructions */
192 const midgard_vector_alu_src zero_alu_src
= { 0 };
194 /* Coerce structs to integer */
197 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
200 memcpy(&u
, &src
, sizeof(src
));
204 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
205 * the corresponding Midgard source */
207 static midgard_vector_alu_src
208 vector_alu_modifiers(nir_alu_src
*src
)
210 if (!src
) return blank_alu_src
;
212 midgard_vector_alu_src alu_src
= {
214 .negate
= src
->negate
,
217 .half
= 0, /* TODO */
218 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
224 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
226 static midgard_instruction
227 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
229 midgard_instruction ins
= {
232 .src0
= SSA_UNUSED_1
,
237 .op
= midgard_alu_op_fmov
,
238 .reg_mode
= midgard_reg_mode_full
,
239 .dest_override
= midgard_dest_override_none
,
241 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
242 .src2
= vector_alu_srco_unsigned(mod
)
249 /* load/store instructions have both 32-bit and 16-bit variants, depending on
250 * whether we are using vectors composed of highp or mediump. At the moment, we
251 * don't support half-floats -- this requires changes in other parts of the
252 * compiler -- therefore the 16-bit versions are commented out. */
254 //M_LOAD(load_attr_16);
255 M_LOAD(load_attr_32
);
256 //M_LOAD(load_vary_16);
257 M_LOAD(load_vary_32
);
258 //M_LOAD(load_uniform_16);
259 M_LOAD(load_uniform_32
);
260 M_LOAD(load_color_buffer_8
);
261 //M_STORE(store_vary_16);
262 M_STORE(store_vary_32
);
264 static midgard_instruction
265 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
267 midgard_branch_cond branch
= {
275 memcpy(&compact
, &branch
, sizeof(branch
));
277 midgard_instruction ins
= {
279 .unit
= ALU_ENAB_BR_COMPACT
,
280 .prepacked_branch
= true,
281 .compact_branch
= true,
282 .br_compact
= compact
285 if (op
== midgard_jmp_writeout_op_writeout
)
291 static midgard_instruction
292 v_branch(bool conditional
, bool invert
)
294 midgard_instruction ins
= {
296 .unit
= ALU_ENAB_BR_COMPACT
,
297 .compact_branch
= true,
299 .conditional
= conditional
,
300 .invert_conditional
= invert
307 typedef struct midgard_bundle
{
308 /* Tag for the overall bundle */
311 /* Instructions contained by the bundle */
312 int instruction_count
;
313 midgard_instruction instructions
[5];
315 /* Bundle-wide ALU configuration */
318 bool has_embedded_constants
;
320 bool has_blend_constant
;
322 uint16_t register_words
[8];
323 int register_words_count
;
325 uint64_t body_words
[8];
327 int body_words_count
;
330 typedef struct compiler_context
{
332 gl_shader_stage stage
;
334 /* Is internally a blend shader? Depends on stage == FRAGMENT */
337 /* Tracking for blend constant patching */
338 int blend_constant_number
;
339 int blend_constant_offset
;
341 /* Current NIR function */
344 /* Unordered list of midgard_blocks */
346 struct list_head blocks
;
348 midgard_block
*initial_block
;
349 midgard_block
*previous_source_block
;
350 midgard_block
*final_block
;
352 /* List of midgard_instructions emitted for the current block */
353 midgard_block
*current_block
;
355 /* The index corresponding to the current loop, e.g. for breaks/contineus */
358 /* Constants which have been loaded, for later inlining */
359 struct hash_table_u64
*ssa_constants
;
361 /* SSA indices to be outputted to corresponding varying offset */
362 struct hash_table_u64
*ssa_varyings
;
364 /* SSA values / registers which have been aliased. Naively, these
365 * demand a fmov output; instead, we alias them in a later pass to
366 * avoid the wasted op.
368 * A note on encoding: to avoid dynamic memory management here, rather
369 * than ampping to a pointer, we map to the source index; the key
370 * itself is just the destination index. */
372 struct hash_table_u64
*ssa_to_alias
;
373 struct set
*leftover_ssa_to_alias
;
375 /* Actual SSA-to-register for RA */
376 struct hash_table_u64
*ssa_to_register
;
378 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
379 struct hash_table_u64
*hash_to_temp
;
383 /* Uniform IDs for mdg */
384 struct hash_table_u64
*uniform_nir_to_mdg
;
387 struct hash_table_u64
*varying_nir_to_mdg
;
390 /* Just the count of the max register used. Higher count => higher
391 * register pressure */
394 /* Used for cont/last hinting. Increase when a tex op is added.
395 * Decrease when a tex op is removed. */
396 int texture_op_count
;
398 /* Mapping of texture register -> SSA index for unaliasing */
399 int texture_index
[2];
401 /* Count of special uniforms (viewport, etc) in vec4 units */
402 int special_uniforms
;
404 /* If any path hits a discard instruction */
407 /* The number of uniforms allowable for the fast path */
410 /* Count of instructions emitted from NIR overall, across all blocks */
411 int instruction_count
;
413 /* Alpha ref value passed in */
416 /* The index corresponding to the fragment output */
417 unsigned fragment_output
;
420 /* Append instruction to end of current block */
422 static midgard_instruction
*
423 mir_upload_ins(struct midgard_instruction ins
)
425 midgard_instruction
*heap
= malloc(sizeof(ins
));
426 memcpy(heap
, &ins
, sizeof(ins
));
431 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
433 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
437 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
439 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
443 mir_remove_instruction(struct midgard_instruction
*ins
)
445 list_del(&ins
->link
);
448 static midgard_instruction
*
449 mir_prev_op(struct midgard_instruction
*ins
)
451 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
454 static midgard_instruction
*
455 mir_next_op(struct midgard_instruction
*ins
)
457 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
460 static midgard_block
*
461 mir_next_block(struct midgard_block
*blk
)
463 return list_first_entry(&(blk
->link
), midgard_block
, link
);
467 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
468 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
470 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
471 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
472 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
473 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
474 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
475 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
478 static midgard_instruction
*
479 mir_last_in_block(struct midgard_block
*block
)
481 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
484 static midgard_block
*
485 mir_get_block(compiler_context
*ctx
, int idx
)
487 struct list_head
*lst
= &ctx
->blocks
;
492 return (struct midgard_block
*) lst
;
495 /* Pretty printer for internal Midgard IR */
498 print_mir_source(int source
)
500 if (source
>= SSA_FIXED_MINIMUM
) {
501 /* Specific register */
502 int reg
= SSA_REG_FROM_FIXED(source
);
504 /* TODO: Moving threshold */
505 if (reg
> 16 && reg
< 24)
506 printf("u%d", 23 - reg
);
510 printf("%d", source
);
515 print_mir_instruction(midgard_instruction
*ins
)
521 midgard_alu_op op
= ins
->alu
.op
;
522 const char *name
= alu_opcode_names
[op
];
525 printf("%d.", ins
->unit
);
527 printf("%s", name
? name
: "??");
531 case TAG_LOAD_STORE_4
: {
532 midgard_load_store_op op
= ins
->load_store
.op
;
533 const char *name
= load_store_opcode_names
[op
];
540 case TAG_TEXTURE_4
: {
549 ssa_args
*args
= &ins
->ssa_args
;
551 printf(" %d, ", args
->dest
);
553 print_mir_source(args
->src0
);
556 if (args
->inline_constant
)
557 printf("#%d", ins
->inline_constant
);
559 print_mir_source(args
->src1
);
561 if (ins
->has_constants
)
562 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
568 print_mir_block(midgard_block
*block
)
572 mir_foreach_instr_in_block(block
, ins
) {
573 print_mir_instruction(ins
);
582 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
584 ins
->has_constants
= true;
585 memcpy(&ins
->constants
, constants
, 16);
587 /* If this is the special blend constant, mark this instruction */
589 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
590 ins
->has_blend_constant
= true;
594 glsl_type_size(const struct glsl_type
*type
)
596 return glsl_count_attribute_slots(type
, false);
599 /* Lower fdot2 to a vector multiplication followed by channel addition */
601 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
603 if (alu
->op
!= nir_op_fdot2
)
606 b
->cursor
= nir_before_instr(&alu
->instr
);
608 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
609 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
611 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
613 nir_ssa_def
*sum
= nir_fadd(b
,
614 nir_channel(b
, product
, 0),
615 nir_channel(b
, product
, 1));
617 /* Replace the fdot2 with this sum */
618 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
622 midgard_nir_lower_fdot2(nir_shader
*shader
)
624 bool progress
= false;
626 nir_foreach_function(function
, shader
) {
627 if (!function
->impl
) continue;
630 nir_builder
*b
= &_b
;
631 nir_builder_init(b
, function
->impl
);
633 nir_foreach_block(block
, function
->impl
) {
634 nir_foreach_instr_safe(instr
, block
) {
635 if (instr
->type
!= nir_instr_type_alu
) continue;
637 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
638 midgard_nir_lower_fdot2_body(b
, alu
);
644 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
652 optimise_nir(nir_shader
*nir
)
656 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
657 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
659 nir_lower_tex_options lower_tex_options
= {
663 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
668 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
669 NIR_PASS(progress
, nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
670 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
671 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
673 NIR_PASS(progress
, nir
, nir_copy_prop
);
674 NIR_PASS(progress
, nir
, nir_opt_dce
);
675 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
676 NIR_PASS(progress
, nir
, nir_opt_cse
);
677 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
678 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
679 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
680 NIR_PASS(progress
, nir
, nir_opt_undef
);
681 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
684 nir_var_function_temp
);
686 /* TODO: Enable vectorize when merged upstream */
687 // NIR_PASS(progress, nir, nir_opt_vectorize);
690 /* Must be run at the end to prevent creation of fsin/fcos ops */
691 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
696 NIR_PASS(progress
, nir
, nir_opt_dce
);
697 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
698 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
699 NIR_PASS(progress
, nir
, nir_copy_prop
);
702 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
705 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_all_source_mods
);
706 NIR_PASS(progress
, nir
, nir_copy_prop
);
707 NIR_PASS(progress
, nir
, nir_opt_dce
);
709 /* Take us out of SSA */
710 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
711 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
713 /* We are a vector architecture; write combine where possible */
714 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
715 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
717 NIR_PASS(progress
, nir
, nir_opt_dce
);
720 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
721 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
722 * r0. See the comments in compiler_context */
725 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
727 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
728 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
731 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
734 unalias_ssa(compiler_context
*ctx
, int dest
)
736 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
737 /* TODO: Remove from leftover or no? */
741 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
743 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
747 midgard_is_pinned(compiler_context
*ctx
, int index
)
749 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
752 /* Do not actually emit a load; instead, cache the constant for inlining */
755 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
757 nir_ssa_def def
= instr
->def
;
759 float *v
= ralloc_array(NULL
, float, 4);
760 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
761 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
764 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
768 expand_writemask(unsigned mask
)
772 for (int i
= 0; i
< 4; ++i
)
780 squeeze_writemask(unsigned mask
)
784 for (int i
= 0; i
< 4; ++i
)
785 if (mask
& (3 << (2 * i
)))
792 /* Determines effective writemask, taking quirks and expansion into account */
794 effective_writemask(midgard_vector_alu
*alu
)
796 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
799 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
801 /* If there is a fixed channel count, construct the appropriate mask */
804 return (1 << channel_count
) - 1;
806 /* Otherwise, just squeeze the existing mask */
807 return squeeze_writemask(alu
->mask
);
811 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
813 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
816 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
821 /* If no temp is find, allocate one */
822 temp
= ctx
->temp_count
++;
823 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
825 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
831 nir_src_index(nir_src
*src
)
834 return src
->ssa
->index
;
836 return 4096 + src
->reg
.reg
->index
;
840 nir_dest_index(nir_dest
*dst
)
843 return dst
->ssa
.index
;
845 return 4096 + dst
->reg
.reg
->index
;
849 nir_alu_src_index(nir_alu_src
*src
)
851 return nir_src_index(&src
->src
);
854 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
855 * a conditional test) into that register */
858 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
860 /* XXX: Force component correct */
861 int condition
= nir_src_index(src
);
863 const midgard_vector_alu_src alu_src
= {
864 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
867 /* There is no boolean move instruction. Instead, we simulate a move by
868 * ANDing the condition with itself to get it into r31.w */
870 midgard_instruction ins
= {
872 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
876 .dest
= SSA_FIXED_REGISTER(31),
879 .op
= midgard_alu_op_iand
,
880 .reg_mode
= midgard_reg_mode_full
,
881 .dest_override
= midgard_dest_override_none
,
882 .mask
= (0x3 << 6), /* w */
883 .src1
= vector_alu_srco_unsigned(alu_src
),
884 .src2
= vector_alu_srco_unsigned(alu_src
)
888 emit_mir_instruction(ctx
, ins
);
891 /* Components: Number/style of arguments:
892 * 3: One-argument op with r24 (i2f, f2i)
893 * 2: Standard two argument op (fadd, fmul)
894 * 1: Flipped one-argument op (fmov, imov)
895 * 0: Standard one-argument op (frcp)
896 * NIR: NIR instruction op.
897 * Op: Midgard instruction op.
900 #define ALU_CASE(_components, nir, _op) \
902 components = _components; \
903 op = midgard_alu_op_##_op; \
907 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
909 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
911 unsigned dest
= nir_dest_index(&instr
->dest
.dest
);
912 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
914 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
915 * supported. A few do not and are commented for now. Also, there are a
916 * number of NIR ops which Midgard does not support and need to be
917 * lowered, also TODO. This switch block emits the opcode and calling
918 * convention of the Midgard instruction; actual packing is done in
921 unsigned op
, components
;
924 ALU_CASE(2, fadd
, fadd
);
925 ALU_CASE(2, fmul
, fmul
);
926 ALU_CASE(2, fmin
, fmin
);
927 ALU_CASE(2, fmax
, fmax
);
928 ALU_CASE(2, imin
, imin
);
929 ALU_CASE(2, imax
, imax
);
930 ALU_CASE(1, fmov
, fmov
);
931 ALU_CASE(0, ffloor
, ffloor
);
932 ALU_CASE(0, fceil
, fceil
);
933 ALU_CASE(2, fdot3
, fdot3
);
934 //ALU_CASE(2, fdot3r);
935 ALU_CASE(2, fdot4
, fdot4
);
936 //ALU_CASE(2, freduce);
937 ALU_CASE(2, iadd
, iadd
);
938 ALU_CASE(2, isub
, isub
);
939 ALU_CASE(2, imul
, imul
);
941 /* XXX: Use fmov, not imov, since imov was causing major
942 * issues with texture precision? XXX research */
943 ALU_CASE(1, imov
, fmov
);
945 ALU_CASE(2, feq
, feq
);
946 ALU_CASE(2, fne
, fne
);
947 ALU_CASE(2, flt
, flt
);
948 ALU_CASE(2, ieq
, ieq
);
949 ALU_CASE(2, ine
, ine
);
950 ALU_CASE(2, ilt
, ilt
);
951 //ALU_CASE(2, icsel, icsel);
952 ALU_CASE(0, frcp
, frcp
);
953 ALU_CASE(0, frsq
, frsqrt
);
954 ALU_CASE(0, fsqrt
, fsqrt
);
955 ALU_CASE(0, fexp2
, fexp2
);
956 ALU_CASE(0, flog2
, flog2
);
958 ALU_CASE(3, f2i32
, f2i
);
959 ALU_CASE(3, f2u32
, f2u
);
960 ALU_CASE(3, i2f32
, i2f
);
961 ALU_CASE(3, u2f32
, u2f
);
963 ALU_CASE(0, fsin
, fsin
);
964 ALU_CASE(0, fcos
, fcos
);
966 ALU_CASE(2, iand
, iand
);
967 ALU_CASE(2, ior
, ior
);
968 ALU_CASE(2, ixor
, ixor
);
969 ALU_CASE(0, inot
, inot
);
970 ALU_CASE(2, ishl
, ishl
);
971 ALU_CASE(2, ishr
, iasr
);
972 ALU_CASE(2, ushr
, ilsr
);
973 //ALU_CASE(2, ilsr, ilsr);
975 ALU_CASE(2, ball_fequal4
, fball_eq
);
976 ALU_CASE(2, bany_fnequal4
, fbany_neq
);
977 ALU_CASE(2, ball_iequal4
, iball_eq
);
978 ALU_CASE(2, bany_inequal4
, ibany_neq
);
980 /* For greater-or-equal, we use less-or-equal and flip the
985 op
= midgard_alu_op_ile
;
987 /* Swap via temporary */
988 nir_alu_src temp
= instr
->src
[1];
989 instr
->src
[1] = instr
->src
[0];
990 instr
->src
[0] = temp
;
997 op
= midgard_alu_op_fcsel
;
999 emit_condition(ctx
, &instr
->src
[0].src
, false);
1001 /* The condition is the first argument; move the other
1002 * arguments up one to be a binary instruction for
1005 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1009 /* We don't have a native b2f32 instruction. Instead, like many GPUs,
1010 * we exploit booleans as 0/~0 for false/true, and correspondingly AND
1011 * by 1.0 to do the type conversion. For the moment, prime us to emit:
1013 * iand [whatever], #0
1015 * At the end of emit_alu (as MIR), we'll fix-up the constant */
1017 case nir_op_b2f32
: {
1018 op
= midgard_alu_op_iand
;
1024 printf("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1029 int _unit
= alu_opcode_props
[op
];
1031 /* Initialise fields common between scalar/vector instructions */
1032 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1034 /* src0 will always exist afaik, but src1 will not for 1-argument
1035 * instructions. The latter can only be fetched if the instruction
1036 * needs it, or else we may segfault. */
1038 unsigned src0
= nir_alu_src_index(&instr
->src
[0]);
1039 unsigned src1
= components
== 2 ? nir_alu_src_index(&instr
->src
[1]) : SSA_UNUSED_0
;
1041 /* Rather than use the instruction generation helpers, we do it
1042 * ourselves here to avoid the mess */
1044 midgard_instruction ins
= {
1047 .src0
= components
== 3 || components
== 2 || components
== 0 ? src0
: SSA_UNUSED_1
,
1048 .src1
= components
== 2 ? src1
: components
== 1 ? src0
: components
== 0 ? SSA_UNUSED_0
: SSA_UNUSED_1
,
1050 .inline_constant
= components
== 0
1054 nir_alu_src
*nirmod0
= NULL
;
1055 nir_alu_src
*nirmod1
= NULL
;
1057 if (components
== 2) {
1058 nirmod0
= &instr
->src
[0];
1059 nirmod1
= &instr
->src
[1];
1060 } else if (components
== 1) {
1061 nirmod1
= &instr
->src
[0];
1062 } else if (components
== 0) {
1063 nirmod0
= &instr
->src
[0];
1066 midgard_vector_alu alu
= {
1068 .reg_mode
= midgard_reg_mode_full
,
1069 .dest_override
= midgard_dest_override_none
,
1072 /* Writemask only valid for non-SSA NIR */
1073 .mask
= expand_writemask((1 << nr_components
) - 1),
1075 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmod0
)),
1076 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmod1
)),
1079 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1082 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1086 /* Late fixup for emulated instructions */
1088 if (instr
->op
== nir_op_b2f32
) {
1089 /* Presently, our second argument is an inline #0 constant.
1090 * Switch over to an embedded 1.0 constant (that can't fit
1091 * inline, since we're 32-bit, not 16-bit like the inline
1094 ins
.ssa_args
.inline_constant
= false;
1095 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1096 ins
.has_constants
= true;
1097 ins
.constants
[0] = 1.0;
1100 if (_unit
== UNIT_VLUT
) {
1101 /* To avoid duplicating the LUTs (we think?), LUT instructions can only
1102 * operate as if they were scalars. Lower them here by changing the
1105 assert(components
== 0);
1107 uint8_t original_swizzle
[4];
1108 memcpy(original_swizzle
, nirmod0
->swizzle
, sizeof(nirmod0
->swizzle
));
1110 for (int i
= 0; i
< nr_components
; ++i
) {
1111 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1113 for (int j
= 0; j
< 4; ++j
)
1114 nirmod0
->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1116 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmod0
));
1117 emit_mir_instruction(ctx
, ins
);
1120 emit_mir_instruction(ctx
, ins
);
1125 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1127 nir_const_value
*const_offset
;
1128 unsigned offset
, reg
;
1130 switch (instr
->intrinsic
) {
1131 case nir_intrinsic_discard_if
:
1132 emit_condition(ctx
, &instr
->src
[0], true);
1136 case nir_intrinsic_discard
: {
1137 midgard_condition cond
= instr
->intrinsic
== nir_intrinsic_discard_if
?
1138 midgard_condition_true
: midgard_condition_always
;
1140 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_discard
, 0, 2, cond
);
1141 ctx
->can_discard
= true;
1145 case nir_intrinsic_load_uniform
:
1146 case nir_intrinsic_load_input
:
1147 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1148 assert (const_offset
&& "no indirect inputs");
1150 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1152 reg
= nir_dest_index(&instr
->dest
);
1154 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1155 /* TODO: half-floats */
1157 int uniform_offset
= 0;
1159 if (offset
>= SPECIAL_UNIFORM_BASE
) {
1160 /* XXX: Resolve which uniform */
1163 /* Offset away from the special
1166 void *entry
= _mesa_hash_table_u64_search(ctx
->uniform_nir_to_mdg
, offset
+ 1);
1170 printf("WARNING: Unknown uniform %d\n", offset
);
1174 uniform_offset
= (uintptr_t) (entry
) - 1;
1175 uniform_offset
+= ctx
->special_uniforms
;
1178 if (uniform_offset
< ctx
->uniform_cutoff
) {
1179 /* Fast path: For the first 16 uniform,
1180 * accesses are 0-cycle, since they're
1181 * just a register fetch in the usual
1182 * case. So, we alias the registers
1183 * while we're still in SSA-space */
1185 int reg_slot
= 23 - uniform_offset
;
1186 alias_ssa(ctx
, reg
, SSA_FIXED_REGISTER(reg_slot
));
1188 /* Otherwise, read from the 'special'
1189 * UBO to access higher-indexed
1190 * uniforms, at a performance cost */
1192 midgard_instruction ins
= m_load_uniform_32(reg
, uniform_offset
);
1194 /* TODO: Don't split */
1195 ins
.load_store
.varying_parameters
= (uniform_offset
& 7) << 7;
1196 ins
.load_store
.address
= uniform_offset
>> 3;
1198 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1199 emit_mir_instruction(ctx
, ins
);
1201 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1202 /* XXX: Half-floats? */
1203 /* TODO: swizzle, mask */
1205 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1207 midgard_varying_parameter p
= {
1209 .interpolation
= midgard_interp_default
,
1210 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1214 memcpy(&u
, &p
, sizeof(p
));
1215 ins
.load_store
.varying_parameters
= u
;
1217 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1218 emit_mir_instruction(ctx
, ins
);
1219 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1220 /* Constant encoded as a pinned constant */
1222 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1223 ins
.has_constants
= true;
1224 ins
.has_blend_constant
= true;
1225 emit_mir_instruction(ctx
, ins
);
1226 } else if (ctx
->is_blend
) {
1227 /* For blend shaders, a load might be
1228 * translated various ways depending on what
1229 * we're loading. Figure out how this is used */
1231 nir_variable
*out
= NULL
;
1233 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1234 int drvloc
= var
->data
.driver_location
;
1236 if (nir_intrinsic_base(instr
) == drvloc
) {
1244 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1245 /* Source color preloaded to r0 */
1247 midgard_pin_output(ctx
, reg
, 0);
1248 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1249 /* Destination color must be read from framebuffer */
1251 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1252 ins
.load_store
.swizzle
= 0; /* xxxx */
1254 /* Read each component sequentially */
1256 for (int c
= 0; c
< 4; ++c
) {
1257 ins
.load_store
.mask
= (1 << c
);
1258 ins
.load_store
.unknown
= c
;
1259 emit_mir_instruction(ctx
, ins
);
1262 /* vadd.u2f hr2, abs(hr2), #0 */
1264 midgard_vector_alu_src alu_src
= blank_alu_src
;
1266 alu_src
.half
= true;
1268 midgard_instruction u2f
= {
1272 .src1
= SSA_UNUSED_0
,
1274 .inline_constant
= true
1277 .op
= midgard_alu_op_u2f
,
1278 .reg_mode
= midgard_reg_mode_half
,
1279 .dest_override
= midgard_dest_override_none
,
1281 .src1
= vector_alu_srco_unsigned(alu_src
),
1282 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1286 emit_mir_instruction(ctx
, u2f
);
1288 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1290 alu_src
.abs
= false;
1292 midgard_instruction fmul
= {
1294 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1298 .src1
= SSA_UNUSED_0
,
1299 .inline_constant
= true
1302 .op
= midgard_alu_op_fmul
,
1303 .reg_mode
= midgard_reg_mode_full
,
1304 .dest_override
= midgard_dest_override_none
,
1305 .outmod
= midgard_outmod_sat
,
1307 .src1
= vector_alu_srco_unsigned(alu_src
),
1308 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1312 emit_mir_instruction(ctx
, fmul
);
1314 printf("Unknown input in blend shader\n");
1317 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1318 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1319 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1320 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1321 emit_mir_instruction(ctx
, ins
);
1323 printf("Unknown load\n");
1329 case nir_intrinsic_store_output
:
1330 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1331 assert(const_offset
&& "no indirect outputs");
1333 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1335 reg
= nir_src_index(&instr
->src
[0]);
1337 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1338 /* gl_FragColor is not emitted with load/store
1339 * instructions. Instead, it gets plonked into
1340 * r0 at the end of the shader and we do the
1341 * framebuffer writeout dance. TODO: Defer
1344 midgard_pin_output(ctx
, reg
, 0);
1346 /* Save the index we're writing to for later reference
1347 * in the epilogue */
1349 ctx
->fragment_output
= reg
;
1350 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1351 /* Varyings are written into one of two special
1352 * varying register, r26 or r27. The register itself is selected as the register
1353 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1355 * Normally emitting fmov's is frowned upon,
1356 * but due to unique constraints of
1357 * REGISTER_VARYING, fmov emission + a
1358 * dedicated cleanup pass is the only way to
1359 * guarantee correctness when considering some
1360 * (common) edge cases XXX: FIXME */
1362 /* Look up how it was actually laid out */
1364 void *entry
= _mesa_hash_table_u64_search(ctx
->varying_nir_to_mdg
, offset
+ 1);
1367 printf("WARNING: skipping varying\n");
1371 offset
= (uintptr_t) (entry
) - 1;
1373 /* If this varying corresponds to a constant (why?!),
1374 * emit that now since it won't get picked up by
1375 * hoisting (since there is no corresponding move
1376 * emitted otherwise) */
1378 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1380 if (constant_value
) {
1381 /* Special case: emit the varying write
1382 * directly to r26 (looks funny in asm but it's
1383 * fine) and emit the store _now_. Possibly
1384 * slightly slower, but this is a really stupid
1385 * special case anyway (why on earth would you
1386 * have a constant varying? Your own fault for
1387 * slightly worse perf :P) */
1389 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1390 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1391 emit_mir_instruction(ctx
, ins
);
1393 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1394 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1395 emit_mir_instruction(ctx
, st
);
1397 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1399 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1402 printf("Unknown store\n");
1408 case nir_intrinsic_load_alpha_ref_float
:
1409 assert(instr
->dest
.is_ssa
);
1411 float ref_value
= ctx
->alpha_ref
;
1413 float *v
= ralloc_array(NULL
, float, 4);
1414 memcpy(v
, &ref_value
, sizeof(float));
1415 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1420 printf ("Unhandled intrinsic\n");
1427 midgard_tex_format(enum glsl_sampler_dim dim
)
1430 case GLSL_SAMPLER_DIM_2D
:
1431 case GLSL_SAMPLER_DIM_EXTERNAL
:
1434 case GLSL_SAMPLER_DIM_3D
:
1437 case GLSL_SAMPLER_DIM_CUBE
:
1438 return TEXTURE_CUBE
;
1441 printf("Unknown sampler dim type\n");
1448 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1451 //assert (!instr->sampler);
1452 //assert (!instr->texture_array_size);
1453 assert (instr
->op
== nir_texop_tex
);
1455 /* Allocate registers via a round robin scheme to alternate between the two registers */
1456 int reg
= ctx
->texture_op_count
& 1;
1457 int in_reg
= reg
, out_reg
= reg
;
1459 /* Make room for the reg */
1461 if (ctx
->texture_index
[reg
] > -1)
1462 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1464 int texture_index
= instr
->texture_index
;
1465 int sampler_index
= texture_index
;
1467 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1468 switch (instr
->src
[i
].src_type
) {
1469 case nir_tex_src_coord
: {
1470 int index
= nir_src_index(&instr
->src
[i
].src
);
1472 midgard_vector_alu_src alu_src
= blank_alu_src
;
1473 alu_src
.swizzle
= (COMPONENT_Y
<< 2);
1475 midgard_instruction ins
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
));
1476 emit_mir_instruction(ctx
, ins
);
1478 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1484 printf("Unknown source type\n");
1491 /* No helper to build texture words -- we do it all here */
1492 midgard_instruction ins
= {
1493 .type
= TAG_TEXTURE_4
,
1495 .op
= TEXTURE_OP_NORMAL
,
1496 .format
= midgard_tex_format(instr
->sampler_dim
),
1497 .texture_handle
= texture_index
,
1498 .sampler_handle
= sampler_index
,
1500 /* TODO: Don't force xyzw */
1501 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1513 /* Assume we can continue; hint it out later */
1518 /* Set registers to read and write from the same place */
1519 ins
.texture
.in_reg_select
= in_reg
;
1520 ins
.texture
.out_reg_select
= out_reg
;
1522 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1523 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1524 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1525 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1526 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1528 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1529 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1530 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1533 emit_mir_instruction(ctx
, ins
);
1535 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1537 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(&instr
->dest
);
1538 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1539 ctx
->texture_index
[reg
] = o_index
;
1541 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1542 emit_mir_instruction(ctx
, ins2
);
1544 /* Used for .cont and .last hinting */
1545 ctx
->texture_op_count
++;
1549 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1551 switch (instr
->type
) {
1552 case nir_jump_break
: {
1553 /* Emit a branch out of the loop */
1554 struct midgard_instruction br
= v_branch(false, false);
1555 br
.branch
.target_type
= TARGET_BREAK
;
1556 br
.branch
.target_break
= ctx
->current_loop
;
1557 emit_mir_instruction(ctx
, br
);
1559 printf("break..\n");
1564 printf("Unknown jump type %d\n", instr
->type
);
1570 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1572 switch (instr
->type
) {
1573 case nir_instr_type_load_const
:
1574 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1577 case nir_instr_type_intrinsic
:
1578 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1581 case nir_instr_type_alu
:
1582 emit_alu(ctx
, nir_instr_as_alu(instr
));
1585 case nir_instr_type_tex
:
1586 emit_tex(ctx
, nir_instr_as_tex(instr
));
1589 case nir_instr_type_jump
:
1590 emit_jump(ctx
, nir_instr_as_jump(instr
));
1593 case nir_instr_type_ssa_undef
:
1598 printf("Unhandled instruction type\n");
1603 /* Determine the actual hardware from the index based on the RA results or special values */
1606 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1608 if (reg
>= SSA_FIXED_MINIMUM
)
1609 return SSA_REG_FROM_FIXED(reg
);
1612 assert(reg
< maxreg
);
1613 int r
= ra_get_node_reg(g
, reg
);
1614 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1619 /* fmov style unused */
1621 return REGISTER_UNUSED
;
1623 /* lut style unused */
1625 return REGISTER_UNUSED
;
1628 printf("Unknown SSA register alias %d\n", reg
);
1635 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1637 /* Choose the first available register to minimise reported register pressure */
1639 for (int i
= 0; i
< 16; ++i
) {
1640 if (BITSET_TEST(regs
, i
)) {
1650 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1652 if (ins
->ssa_args
.src0
== src
) return true;
1653 if (ins
->ssa_args
.src1
== src
) return true;
1659 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1661 /* Check the rest of the block for liveness */
1662 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1663 if (midgard_is_live_in_instr(ins
, src
))
1667 /* Check the rest of the blocks for liveness */
1668 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1669 mir_foreach_instr_in_block(b
, ins
) {
1670 if (midgard_is_live_in_instr(ins
, src
))
1675 /* TODO: How does control flow interact in complex shaders? */
1681 allocate_registers(compiler_context
*ctx
)
1683 /* First, initialize the RA */
1684 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1686 /* Create a primary (general purpose) class, as well as special purpose
1687 * pipeline register classes */
1689 int primary_class
= ra_alloc_reg_class(regs
);
1690 int varying_class
= ra_alloc_reg_class(regs
);
1692 /* Add the full set of work registers */
1693 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1694 for (int i
= 0; i
< work_count
; ++i
)
1695 ra_class_add_reg(regs
, primary_class
, i
);
1697 /* Add special registers */
1698 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1699 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1701 /* We're done setting up */
1702 ra_set_finalize(regs
, NULL
);
1704 /* Transform the MIR into squeezed index form */
1705 mir_foreach_block(ctx
, block
) {
1706 mir_foreach_instr_in_block(block
, ins
) {
1707 if (ins
->compact_branch
) continue;
1709 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1710 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1711 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1714 print_mir_block(block
);
1717 /* Let's actually do register allocation */
1718 int nodes
= ctx
->temp_count
;
1719 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1721 /* Set everything to the work register class, unless it has somewhere
1724 mir_foreach_block(ctx
, block
) {
1725 mir_foreach_instr_in_block(block
, ins
) {
1726 if (ins
->compact_branch
) continue;
1728 if (ins
->ssa_args
.dest
< 0) continue;
1730 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1732 int class = primary_class
;
1734 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1738 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1739 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1742 unsigned reg
= temp
- 1;
1743 int t
= find_or_allocate_temp(ctx
, index
);
1744 ra_set_node_reg(g
, t
, reg
);
1748 /* Determine liveness */
1750 int *live_start
= malloc(nodes
* sizeof(int));
1751 int *live_end
= malloc(nodes
* sizeof(int));
1753 /* Initialize as non-existent */
1755 for (int i
= 0; i
< nodes
; ++i
) {
1756 live_start
[i
] = live_end
[i
] = -1;
1761 mir_foreach_block(ctx
, block
) {
1762 mir_foreach_instr_in_block(block
, ins
) {
1763 if (ins
->compact_branch
) continue;
1765 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1766 /* If this destination is not yet live, it is now since we just wrote it */
1768 int dest
= ins
->ssa_args
.dest
;
1770 if (live_start
[dest
] == -1)
1771 live_start
[dest
] = d
;
1774 /* Since we just used a source, the source might be
1775 * dead now. Scan the rest of the block for
1776 * invocations, and if there are none, the source dies
1779 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1781 for (int src
= 0; src
< 2; ++src
) {
1782 int s
= sources
[src
];
1784 if (s
< 0) continue;
1786 if (s
>= SSA_FIXED_MINIMUM
) continue;
1788 if (!is_live_after(ctx
, block
, ins
, s
)) {
1797 /* If a node still hasn't been killed, kill it now */
1799 for (int i
= 0; i
< nodes
; ++i
) {
1800 /* live_start == -1 most likely indicates a pinned output */
1802 if (live_end
[i
] == -1)
1806 /* Setup interference between nodes that are live at the same time */
1808 for (int i
= 0; i
< nodes
; ++i
) {
1809 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1810 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1811 ra_add_node_interference(g
, i
, j
);
1815 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1817 if (!ra_allocate(g
)) {
1818 printf("Error allocating registers\n");
1826 mir_foreach_block(ctx
, block
) {
1827 mir_foreach_instr_in_block(block
, ins
) {
1828 if (ins
->compact_branch
) continue;
1830 ssa_args args
= ins
->ssa_args
;
1832 switch (ins
->type
) {
1834 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1836 ins
->registers
.src2_imm
= args
.inline_constant
;
1838 if (args
.inline_constant
) {
1839 /* Encode inline 16-bit constant as a vector by default */
1841 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1843 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1845 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1846 ins
->alu
.src2
= imm
<< 2;
1848 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
1851 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
1855 case TAG_LOAD_STORE_4
: {
1856 if (OP_IS_STORE(ins
->load_store
.op
)) {
1857 /* TODO: use ssa_args for store_vary */
1858 ins
->load_store
.reg
= 0;
1860 bool has_dest
= args
.dest
>= 0;
1861 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
1863 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
1876 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1877 * use scalar ALU instructions, for functional or performance reasons. To do
1878 * this, we just demote vector ALU payloads to scalar. */
1881 component_from_mask(unsigned mask
)
1883 for (int c
= 0; c
< 4; ++c
) {
1884 if (mask
& (3 << (2 * c
)))
1893 is_single_component_mask(unsigned mask
)
1897 for (int c
= 0; c
< 4; ++c
)
1898 if (mask
& (3 << (2 * c
)))
1901 return components
== 1;
1904 /* Create a mask of accessed components from a swizzle to figure out vector
1908 swizzle_to_access_mask(unsigned swizzle
)
1910 unsigned component_mask
= 0;
1912 for (int i
= 0; i
< 4; ++i
) {
1913 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1914 component_mask
|= (1 << c
);
1917 return component_mask
;
1921 vector_to_scalar_source(unsigned u
)
1923 midgard_vector_alu_src v
;
1924 memcpy(&v
, &u
, sizeof(v
));
1926 midgard_scalar_alu_src s
= {
1930 .component
= (v
.swizzle
& 3) << 1
1934 memcpy(&o
, &s
, sizeof(s
));
1936 return o
& ((1 << 6) - 1);
1939 static midgard_scalar_alu
1940 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
1942 /* The output component is from the mask */
1943 midgard_scalar_alu s
= {
1945 .src1
= vector_to_scalar_source(v
.src1
),
1946 .src2
= vector_to_scalar_source(v
.src2
),
1949 .output_full
= 1, /* TODO: Half */
1950 .output_component
= component_from_mask(v
.mask
) << 1,
1953 /* Inline constant is passed along rather than trying to extract it
1956 if (ins
->ssa_args
.inline_constant
) {
1958 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1959 imm
|= (lower_11
>> 9) & 3;
1960 imm
|= (lower_11
>> 6) & 4;
1961 imm
|= (lower_11
>> 2) & 0x38;
1962 imm
|= (lower_11
& 63) << 6;
1970 /* Midgard prefetches instruction types, so during emission we need to
1971 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1972 * if this is the second to last and the last is an ALU, then it's also 1... */
1974 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
1975 tag == TAG_ALU_12 || tag == TAG_ALU_16)
1977 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
1978 bytes_emitted += sizeof(type)
1981 emit_binary_vector_instruction(midgard_instruction
*ains
,
1982 uint16_t *register_words
, int *register_words_count
,
1983 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
1984 size_t *bytes_emitted
)
1986 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
1987 *bytes_emitted
+= sizeof(midgard_reg_info
);
1989 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
1990 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
1991 *bytes_emitted
+= sizeof(midgard_vector_alu
);
1994 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
1995 * mind that we are a vector architecture and we can write to different
1996 * components simultaneously */
1999 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2001 /* Each instruction reads some registers and writes to a register. See
2002 * where the first writes */
2004 /* Figure out where exactly we wrote to */
2005 int source
= first
->ssa_args
.dest
;
2006 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2008 /* As long as the second doesn't read from the first, we're okay */
2009 if (second
->ssa_args
.src0
== source
) {
2010 if (first
->type
== TAG_ALU_4
) {
2011 /* Figure out which components we just read from */
2013 int q
= second
->alu
.src1
;
2014 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2016 /* Check if there are components in common, and fail if so */
2017 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2024 if (second
->ssa_args
.src1
== source
)
2027 /* Otherwise, it's safe in that regard. Another data hazard is both
2028 * writing to the same place, of course */
2030 if (second
->ssa_args
.dest
== source
) {
2031 /* ...but only if the components overlap */
2032 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2034 if (dest_mask
& source_mask
)
2042 /* Schedules, but does not emit, a single basic block. After scheduling, the
2043 * final tag and size of the block are known, which are necessary for branching
2046 static midgard_bundle
2047 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2049 int instructions_emitted
= 0, instructions_consumed
= -1;
2050 midgard_bundle bundle
= { 0 };
2052 uint8_t tag
= ins
->type
;
2054 /* Default to the instruction's tag */
2057 switch (ins
->type
) {
2059 uint32_t control
= 0;
2060 size_t bytes_emitted
= sizeof(control
);
2062 /* TODO: Constant combining */
2063 int index
= 0, last_unit
= 0;
2065 /* Previous instructions, for the purpose of parallelism */
2066 midgard_instruction
*segment
[4] = {0};
2067 int segment_size
= 0;
2069 instructions_emitted
= -1;
2070 midgard_instruction
*pins
= ins
;
2073 midgard_instruction
*ains
= pins
;
2075 /* Advance instruction pointer */
2077 ains
= mir_next_op(pins
);
2081 /* Out-of-work condition */
2082 if ((struct list_head
*) ains
== &block
->instructions
)
2085 /* Ensure that the chain can continue */
2086 if (ains
->type
!= TAG_ALU_4
) break;
2088 /* According to the presentation "The ARM
2089 * Mali-T880 Mobile GPU" from HotChips 27,
2090 * there are two pipeline stages. Branching
2091 * position determined experimentally. Lines
2092 * are executed in parallel:
2095 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2097 * Verify that there are no ordering dependencies here.
2099 * TODO: Allow for parallelism!!!
2102 /* Pick a unit for it if it doesn't force a particular unit */
2104 int unit
= ains
->unit
;
2107 int op
= ains
->alu
.op
;
2108 int units
= alu_opcode_props
[op
];
2110 /* TODO: Promotion of scalars to vectors */
2111 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2114 assert(units
& UNITS_SCALAR
);
2117 if (last_unit
>= UNIT_VADD
) {
2118 if (units
& UNIT_VLUT
)
2123 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2125 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2127 else if (units
& UNIT_VLUT
)
2133 if (last_unit
>= UNIT_VADD
) {
2134 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2136 else if (units
& UNIT_VLUT
)
2141 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
))
2143 else if (units
& UNIT_SMUL
)
2145 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2152 assert(unit
& units
);
2155 /* Late unit check, this time for encoding (not parallelism) */
2156 if (unit
<= last_unit
) break;
2158 /* Clear the segment */
2159 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2162 /* Check for data hazards */
2163 int has_hazard
= false;
2165 for (int s
= 0; s
< segment_size
; ++s
)
2166 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2172 /* We're good to go -- emit the instruction */
2175 segment
[segment_size
++] = ains
;
2177 /* Only one set of embedded constants per
2178 * bundle possible; if we have more, we must
2179 * break the chain early, unfortunately */
2181 if (ains
->has_constants
) {
2182 if (bundle
.has_embedded_constants
) {
2183 /* ...but if there are already
2184 * constants but these are the
2185 * *same* constants, we let it
2188 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2191 bundle
.has_embedded_constants
= true;
2192 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2194 /* If this is a blend shader special constant, track it for patching */
2195 if (ains
->has_blend_constant
)
2196 bundle
.has_blend_constant
= true;
2200 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2201 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2202 &bundle
.register_words_count
, bundle
.body_words
,
2203 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2204 } else if (ains
->compact_branch
) {
2205 /* All of r0 has to be written out
2206 * along with the branch writeout.
2209 if (ains
->writeout
) {
2211 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2212 ins
.unit
= UNIT_VMUL
;
2214 control
|= ins
.unit
;
2216 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2217 &bundle
.register_words_count
, bundle
.body_words
,
2218 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2220 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2221 bool written_late
= false;
2222 bool components
[4] = { 0 };
2223 uint16_t register_dep_mask
= 0;
2224 uint16_t written_mask
= 0;
2226 midgard_instruction
*qins
= ins
;
2227 for (int t
= 0; t
< index
; ++t
) {
2228 if (qins
->registers
.out_reg
!= 0) {
2229 /* Mark down writes */
2231 written_mask
|= (1 << qins
->registers
.out_reg
);
2233 /* Mark down the register dependencies for errata check */
2235 if (qins
->registers
.src1_reg
< 16)
2236 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2238 if (qins
->registers
.src2_reg
< 16)
2239 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2241 int mask
= qins
->alu
.mask
;
2243 for (int c
= 0; c
< 4; ++c
)
2244 if (mask
& (0x3 << (2 * c
)))
2245 components
[c
] = true;
2247 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2249 if (qins
->unit
== UNIT_VLUT
)
2250 written_late
= true;
2253 /* Advance instruction pointer */
2254 qins
= mir_next_op(qins
);
2258 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2259 if (register_dep_mask
& written_mask
) {
2260 printf("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2267 /* If even a single component is not written, break it up (conservative check). */
2268 bool breakup
= false;
2270 for (int c
= 0; c
< 4; ++c
)
2277 /* Otherwise, we're free to proceed */
2281 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2282 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2283 bytes_emitted
+= sizeof(ains
->br_compact
);
2285 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2286 bytes_emitted
+= sizeof(midgard_reg_info
);
2288 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2289 bundle
.body_words_count
++;
2290 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2293 /* Defer marking until after writing to allow for break */
2294 control
|= ains
->unit
;
2295 last_unit
= ains
->unit
;
2296 ++instructions_emitted
;
2300 /* Bubble up the number of instructions for skipping */
2301 instructions_consumed
= index
- 1;
2305 /* Pad ALU op to nearest word */
2307 if (bytes_emitted
& 15) {
2308 padding
= 16 - (bytes_emitted
& 15);
2309 bytes_emitted
+= padding
;
2312 /* Constants must always be quadwords */
2313 if (bundle
.has_embedded_constants
)
2314 bytes_emitted
+= 16;
2316 /* Size ALU instruction for tag */
2317 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2318 bundle
.padding
= padding
;
2319 bundle
.control
= bundle
.tag
| control
;
2324 case TAG_LOAD_STORE_4
: {
2325 /* Load store instructions have two words at once. If
2326 * we only have one queued up, we need to NOP pad.
2327 * Otherwise, we store both in succession to save space
2328 * and cycles -- letting them go in parallel -- skip
2329 * the next. The usefulness of this optimisation is
2330 * greatly dependent on the quality of the instruction
2334 midgard_instruction
*next_op
= mir_next_op(ins
);
2336 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2337 /* As the two operate concurrently, make sure
2338 * they are not dependent */
2340 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2341 /* Skip ahead, since it's redundant with the pair */
2342 instructions_consumed
= 1 + (instructions_emitted
++);
2352 /* TODO: Schedule texture ops */
2357 /* XXX: What happens with textures? */
2361 /* Copy the instructions into the bundle */
2362 bundle
.instruction_count
= instructions_emitted
+ 1;
2366 midgard_instruction
*uins
= ins
;
2367 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2368 bundle
.instructions
[used_idx
++] = *uins
;
2369 uins
= mir_next_op(uins
);
2372 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2378 quadword_size(int tag
)
2393 case TAG_LOAD_STORE_4
:
2405 /* Schedule a single block by iterating its instruction to create bundles.
2406 * While we go, tally about the bundle sizes to compute the block size. */
2409 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2411 util_dynarray_init(&block
->bundles
, NULL
);
2413 block
->quadword_count
= 0;
2415 mir_foreach_instr_in_block(block
, ins
) {
2417 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2418 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2420 if (bundle
.has_blend_constant
) {
2421 /* TODO: Multiblock? */
2422 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2423 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2427 ins
= mir_next_op(ins
);
2429 block
->quadword_count
+= quadword_size(bundle
.tag
);
2432 block
->is_scheduled
= true;
2436 schedule_program(compiler_context
*ctx
)
2438 allocate_registers(ctx
);
2440 mir_foreach_block(ctx
, block
) {
2441 schedule_block(ctx
, block
);
2445 /* After everything is scheduled, emit whole bundles at a time */
2448 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2450 int lookahead
= next_tag
<< 4;
2452 switch (bundle
->tag
) {
2457 /* Actually emit each component */
2458 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2460 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2461 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2463 /* Emit body words based on the instructions bundled */
2464 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2465 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2467 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2468 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2469 } else if (ins
->compact_branch
) {
2470 /* Dummy move, XXX DRY */
2471 if ((i
== 0) && ins
->writeout
) {
2472 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2473 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2476 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2479 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2480 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2484 /* Emit padding (all zero) */
2485 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2487 /* Tack on constants */
2489 if (bundle
->has_embedded_constants
) {
2490 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2491 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2492 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2493 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2499 case TAG_LOAD_STORE_4
: {
2500 /* One or two composing instructions */
2502 uint64_t current64
, next64
= LDST_NOP
;
2504 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2506 if (bundle
->instruction_count
== 2)
2507 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2509 midgard_load_store instruction
= {
2510 .type
= bundle
->tag
,
2511 .next_type
= next_tag
,
2516 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2521 case TAG_TEXTURE_4
: {
2522 /* Texture instructions are easy, since there is no
2523 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2525 midgard_instruction
*ins
= &bundle
->instructions
[0];
2527 ins
->texture
.type
= TAG_TEXTURE_4
;
2528 ins
->texture
.next_type
= next_tag
;
2530 ctx
->texture_op_count
--;
2532 if (!ctx
->texture_op_count
) {
2533 ins
->texture
.cont
= 0;
2534 ins
->texture
.last
= 1;
2537 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2542 printf("Unknown midgard instruction type\n");
2549 /* ALU instructions can inline or embed constants, which decreases register
2550 * pressure and saves space. */
2552 #define CONDITIONAL_ATTACH(src) { \
2553 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2556 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2557 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2562 inline_alu_constants(compiler_context
*ctx
)
2564 mir_foreach_instr(ctx
, alu
) {
2565 /* Other instructions cannot inline constants */
2566 if (alu
->type
!= TAG_ALU_4
) continue;
2568 /* If there is already a constant here, we can do nothing */
2569 if (alu
->has_constants
) continue;
2571 CONDITIONAL_ATTACH(src0
);
2573 if (!alu
->has_constants
) {
2574 CONDITIONAL_ATTACH(src1
)
2575 } else if (!alu
->inline_constant
) {
2576 /* Corner case: _two_ vec4 constants, for instance with a
2577 * csel. For this case, we can only use a constant
2578 * register for one, we'll have to emit a move for the
2579 * other. Note, if both arguments are constants, then
2580 * necessarily neither argument depends on the value of
2581 * any particular register. As the destination register
2582 * will be wiped, that means we can spill the constant
2583 * to the destination register.
2586 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2587 unsigned scratch
= alu
->ssa_args
.dest
;
2590 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2591 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2593 /* Force a break XXX Defer r31 writes */
2594 ins
.unit
= UNIT_VLUT
;
2596 /* Set the source */
2597 alu
->ssa_args
.src1
= scratch
;
2599 /* Inject us -before- the last instruction which set r31 */
2600 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2606 /* Midgard supports two types of constants, embedded constants (128-bit) and
2607 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2608 * constants can be demoted to inline constants, for space savings and
2609 * sometimes a performance boost */
2612 embedded_to_inline_constant(compiler_context
*ctx
)
2614 mir_foreach_instr(ctx
, ins
) {
2615 if (!ins
->has_constants
) continue;
2617 if (ins
->ssa_args
.inline_constant
) continue;
2619 /* Blend constants must not be inlined by definition */
2620 if (ins
->has_blend_constant
) continue;
2622 /* src1 cannot be an inline constant due to encoding
2623 * restrictions. So, if possible we try to flip the arguments
2626 int op
= ins
->alu
.op
;
2628 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2629 /* Flip based on op. Fallthrough intentional */
2632 /* These ops require an operational change to flip their arguments TODO */
2633 case midgard_alu_op_flt
:
2634 case midgard_alu_op_fle
:
2635 case midgard_alu_op_ilt
:
2636 case midgard_alu_op_ile
:
2637 case midgard_alu_op_fcsel
:
2638 case midgard_alu_op_icsel
:
2639 case midgard_alu_op_isub
:
2640 printf("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2643 /* These ops are commutative and Just Flip */
2644 case midgard_alu_op_fne
:
2645 case midgard_alu_op_fadd
:
2646 case midgard_alu_op_fmul
:
2647 case midgard_alu_op_fmin
:
2648 case midgard_alu_op_fmax
:
2649 case midgard_alu_op_iadd
:
2650 case midgard_alu_op_imul
:
2651 case midgard_alu_op_feq
:
2652 case midgard_alu_op_ieq
:
2653 case midgard_alu_op_ine
:
2654 case midgard_alu_op_iand
:
2655 case midgard_alu_op_ior
:
2656 case midgard_alu_op_ixor
:
2657 /* Flip the SSA numbers */
2658 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2659 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2661 /* And flip the modifiers */
2665 src_temp
= ins
->alu
.src2
;
2666 ins
->alu
.src2
= ins
->alu
.src1
;
2667 ins
->alu
.src1
= src_temp
;
2674 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2675 /* Extract the source information */
2677 midgard_vector_alu_src
*src
;
2678 int q
= ins
->alu
.src2
;
2679 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2682 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2683 int component
= src
->swizzle
& 3;
2685 /* Scale constant appropriately, if we can legally */
2686 uint16_t scaled_constant
= 0;
2688 /* XXX: Check legality */
2689 if (midgard_is_integer_op(op
)) {
2690 /* TODO: Inline integer */
2693 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2694 scaled_constant
= (uint16_t) iconstants
[component
];
2696 /* Constant overflow after resize */
2697 if (scaled_constant
!= iconstants
[component
])
2700 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2703 /* We don't know how to handle these with a constant */
2705 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2706 printf("Bailing inline constant...\n");
2710 /* Make sure that the constant is not itself a
2711 * vector by checking if all accessed values
2712 * (by the swizzle) are the same. */
2714 uint32_t *cons
= (uint32_t *) ins
->constants
;
2715 uint32_t value
= cons
[component
];
2717 bool is_vector
= false;
2718 unsigned mask
= effective_writemask(&ins
->alu
);
2720 for (int c
= 1; c
< 4; ++c
) {
2721 /* We only care if this component is actually used */
2722 if (!(mask
& (1 << c
)))
2725 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2727 if (test
!= value
) {
2736 /* Get rid of the embedded constant */
2737 ins
->has_constants
= false;
2738 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2739 ins
->ssa_args
.inline_constant
= true;
2740 ins
->inline_constant
= scaled_constant
;
2745 /* Map normal SSA sources to other SSA sources / fixed registers (like
2749 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2751 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2754 /* Remove entry in leftovers to avoid a redunant fmov */
2756 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2759 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2761 /* Assign the alias map */
2767 #define AS_SRC(to, u) \
2768 int q##to = ins->alu.src2; \
2769 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2771 /* Removing unused moves is necessary to clean up the texture pipeline results.
2773 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2776 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2778 mir_foreach_instr_in_block_safe(block
, ins
) {
2779 if (ins
->type
!= TAG_ALU_4
) continue;
2781 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2783 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2785 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2787 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2789 mir_remove_instruction(ins
);
2793 /* The following passes reorder MIR instructions to enable better scheduling */
2796 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2798 mir_foreach_instr_in_block_safe(block
, ins
) {
2799 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2801 /* We've found a load/store op. Check if next is also load/store. */
2802 midgard_instruction
*next_op
= mir_next_op(ins
);
2803 if (&next_op
->link
!= &block
->instructions
) {
2804 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2805 /* If so, we're done since we're a pair */
2806 ins
= mir_next_op(ins
);
2810 /* Maximum search distance to pair, to avoid register pressure disasters */
2811 int search_distance
= 8;
2813 /* Otherwise, we have an orphaned load/store -- search for another load */
2814 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2815 /* Terminate search if necessary */
2816 if (!(search_distance
--)) break;
2818 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2820 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2822 /* We found one! Move it up to pair and remove it from the old location */
2824 mir_insert_instruction_before(ins
, *c
);
2825 mir_remove_instruction(c
);
2833 /* Emit varying stores late */
2836 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2837 /* Iterate in reverse to get the final write, rather than the first */
2839 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2840 /* Check if what we just wrote needs a store */
2841 int idx
= ins
->ssa_args
.dest
;
2842 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2844 if (!varying
) continue;
2848 /* We need to store to the appropriate varying, so emit the
2851 /* TODO: Integrate with special purpose RA (and scheduler?) */
2852 bool high_varying_register
= false;
2854 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2856 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2857 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2859 mir_insert_instruction_before(mir_next_op(ins
), st
);
2860 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2862 /* We no longer need to store this varying */
2863 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2867 /* If there are leftovers after the below pass, emit actual fmov
2868 * instructions for the slow-but-correct path */
2871 emit_leftover_move(compiler_context
*ctx
)
2873 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2874 int base
= ((uintptr_t) leftover
->key
) - 1;
2877 map_ssa_to_alias(ctx
, &mapped
);
2878 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2883 actualise_ssa_to_alias(compiler_context
*ctx
)
2885 mir_foreach_instr(ctx
, ins
) {
2886 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2887 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2890 emit_leftover_move(ctx
);
2893 /* Vertex shaders do not write gl_Position as is; instead, they write a
2894 * transformed screen space position as a varying. See section 12.5 "Coordinate
2895 * Transformation" of the ES 3.2 full specification for details.
2897 * This transformation occurs early on, as NIR and prior to optimisation, in
2898 * order to take advantage of NIR optimisation passes of the transform itself.
2902 write_transformed_position(nir_builder
*b
, nir_src input_point_src
, int uniform_no
)
2904 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
2906 /* Get viewport from the uniforms */
2907 nir_intrinsic_instr
*load
;
2908 load
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
2909 load
->num_components
= 4;
2910 load
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, uniform_no
));
2911 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
2912 nir_builder_instr_insert(b
, &load
->instr
);
2914 /* Formatted as <width, height, centerx, centery> */
2915 nir_ssa_def
*viewport_vec4
= &load
->dest
.ssa
;
2916 nir_ssa_def
*viewport_width_2
= nir_channel(b
, viewport_vec4
, 0);
2917 nir_ssa_def
*viewport_height_2
= nir_channel(b
, viewport_vec4
, 1);
2918 nir_ssa_def
*viewport_offset
= nir_channels(b
, viewport_vec4
, 0x8 | 0x4);
2920 /* XXX: From uniforms? */
2921 nir_ssa_def
*depth_near
= nir_imm_float(b
, 0.0);
2922 nir_ssa_def
*depth_far
= nir_imm_float(b
, 1.0);
2924 /* World space to normalised device coordinates */
2926 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
2927 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
2929 /* Normalised device coordinates to screen space */
2931 nir_ssa_def
*viewport_multiplier
= nir_vec2(b
, viewport_width_2
, viewport_height_2
);
2932 nir_ssa_def
*viewport_xy
= nir_fadd(b
, nir_fmul(b
, nir_channels(b
, ndc_point
, 0x3), viewport_multiplier
), viewport_offset
);
2934 nir_ssa_def
*depth_multiplier
= nir_fmul(b
, nir_fsub(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2935 nir_ssa_def
*depth_offset
= nir_fmul(b
, nir_fadd(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2936 nir_ssa_def
*screen_depth
= nir_fadd(b
, nir_fmul(b
, nir_channel(b
, ndc_point
, 2), depth_multiplier
), depth_offset
);
2938 /* gl_Position will be written out in screenspace xyz, with w set to
2939 * the reciprocal we computed earlier. The transformed w component is
2940 * then used for perspective-correct varying interpolation */
2942 nir_ssa_def
*screen_space
= nir_vec4(b
,
2943 nir_channel(b
, viewport_xy
, 0),
2944 nir_channel(b
, viewport_xy
, 1),
2946 nir_fabs(b
, w_recip
));
2948 /* Finally, write out the transformed values to the varying */
2950 nir_intrinsic_instr
*store
;
2951 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
2952 store
->num_components
= 4;
2953 nir_intrinsic_set_base(store
, 0);
2954 nir_intrinsic_set_write_mask(store
, 0xf);
2955 store
->src
[0].ssa
= screen_space
;
2956 store
->src
[0].is_ssa
= true;
2957 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
2958 nir_builder_instr_insert(b
, &store
->instr
);
2962 transform_position_writes(nir_shader
*shader
)
2964 nir_foreach_function(func
, shader
) {
2965 nir_foreach_block(block
, func
->impl
) {
2966 nir_foreach_instr_safe(instr
, block
) {
2967 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
2969 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
2970 nir_variable
*out
= NULL
;
2972 switch (intr
->intrinsic
) {
2973 case nir_intrinsic_store_output
:
2974 /* already had i/o lowered.. lookup the matching output var: */
2975 nir_foreach_variable(var
, &shader
->outputs
) {
2976 int drvloc
= var
->data
.driver_location
;
2978 if (nir_intrinsic_base(intr
) == drvloc
) {
2992 if (out
->data
.mode
!= nir_var_shader_out
)
2995 if (out
->data
.location
!= VARYING_SLOT_POS
)
2999 nir_builder_init(&b
, func
->impl
);
3000 b
.cursor
= nir_before_instr(instr
);
3002 write_transformed_position(&b
, intr
->src
[0], UNIFORM_VIEWPORT
);
3003 nir_instr_remove(instr
);
3010 emit_fragment_epilogue(compiler_context
*ctx
)
3012 /* Special case: writing out constants requires us to include the move
3013 * explicitly now, so shove it into r0 */
3015 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3017 if (constant_value
) {
3018 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3019 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3020 emit_mir_instruction(ctx
, ins
);
3023 /* Perform the actual fragment writeout. We have two writeout/branch
3024 * instructions, forming a loop until writeout is successful as per the
3025 * docs. TODO: gl_FragDepth */
3027 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3028 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3031 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3032 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3033 * with the int8 analogue to the fragment epilogue */
3036 emit_blend_epilogue(compiler_context
*ctx
)
3038 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3040 midgard_instruction scale
= {
3043 .inline_constant
= _mesa_float_to_half(255.0),
3045 .src0
= SSA_FIXED_REGISTER(0),
3046 .src1
= SSA_UNUSED_0
,
3047 .dest
= SSA_FIXED_REGISTER(24),
3048 .inline_constant
= true
3051 .op
= midgard_alu_op_fmul
,
3052 .reg_mode
= midgard_reg_mode_full
,
3053 .dest_override
= midgard_dest_override_lower
,
3055 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3056 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3060 emit_mir_instruction(ctx
, scale
);
3062 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3064 midgard_vector_alu_src alu_src
= blank_alu_src
;
3065 alu_src
.half
= true;
3067 midgard_instruction f2u8
= {
3070 .src0
= SSA_FIXED_REGISTER(24),
3071 .src1
= SSA_UNUSED_0
,
3072 .dest
= SSA_FIXED_REGISTER(0),
3073 .inline_constant
= true
3076 .op
= midgard_alu_op_f2u8
,
3077 .reg_mode
= midgard_reg_mode_half
,
3078 .dest_override
= midgard_dest_override_lower
,
3079 .outmod
= midgard_outmod_pos
,
3081 .src1
= vector_alu_srco_unsigned(alu_src
),
3082 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3086 emit_mir_instruction(ctx
, f2u8
);
3088 /* vmul.imov.quarter r0, r0, r0 */
3090 midgard_instruction imov_8
= {
3093 .src0
= SSA_UNUSED_1
,
3094 .src1
= SSA_FIXED_REGISTER(0),
3095 .dest
= SSA_FIXED_REGISTER(0),
3098 .op
= midgard_alu_op_imov
,
3099 .reg_mode
= midgard_reg_mode_quarter
,
3100 .dest_override
= midgard_dest_override_none
,
3102 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3103 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3107 /* Emit branch epilogue with the 8-bit move as the source */
3109 emit_mir_instruction(ctx
, imov_8
);
3110 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3112 emit_mir_instruction(ctx
, imov_8
);
3113 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3116 static midgard_block
*
3117 emit_block(compiler_context
*ctx
, nir_block
*block
)
3119 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3120 list_addtail(&this_block
->link
, &ctx
->blocks
);
3122 this_block
->is_scheduled
= false;
3125 ctx
->texture_index
[0] = -1;
3126 ctx
->texture_index
[1] = -1;
3128 /* Set up current block */
3129 list_inithead(&this_block
->instructions
);
3130 ctx
->current_block
= this_block
;
3132 nir_foreach_instr(instr
, block
) {
3133 emit_instr(ctx
, instr
);
3134 ++ctx
->instruction_count
;
3137 inline_alu_constants(ctx
);
3138 embedded_to_inline_constant(ctx
);
3140 /* Perform heavylifting for aliasing */
3141 actualise_ssa_to_alias(ctx
);
3143 midgard_emit_store(ctx
, this_block
);
3144 midgard_eliminate_orphan_moves(ctx
, this_block
);
3145 midgard_pair_load_store(ctx
, this_block
);
3147 /* Append fragment shader epilogue (value writeout) */
3148 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3149 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3151 emit_blend_epilogue(ctx
);
3153 emit_fragment_epilogue(ctx
);
3157 /* Fallthrough save */
3158 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3160 if (block
== nir_start_block(ctx
->func
->impl
))
3161 ctx
->initial_block
= this_block
;
3163 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3164 ctx
->final_block
= this_block
;
3166 /* Allow the next control flow to access us retroactively, for
3168 ctx
->current_block
= this_block
;
3170 /* Document the fallthrough chain */
3171 ctx
->previous_source_block
= this_block
;
3176 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3179 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3181 /* Conditional branches expect the condition in r31.w; emit a move for
3182 * that in the _previous_ block (which is the current block). */
3183 emit_condition(ctx
, &nif
->condition
, true);
3185 /* Speculatively emit the branch, but we can't fill it in until later */
3186 EMIT(branch
, true, true);
3187 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3189 /* Emit the two subblocks */
3190 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3192 /* Emit a jump from the end of the then block to the end of the else */
3193 EMIT(branch
, false, false);
3194 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3196 /* Emit second block, and check if it's empty */
3198 int else_idx
= ctx
->block_count
;
3199 int count_in
= ctx
->instruction_count
;
3200 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3202 /* Now that we have the subblocks emitted, fix up the branches */
3208 if (ctx
->instruction_count
== count_in
) {
3209 /* The else block is empty, so don't emit an exit jump */
3210 mir_remove_instruction(then_exit
);
3211 then_branch
->branch
.target_block
= else_idx
+ 1;
3213 then_branch
->branch
.target_block
= else_idx
;
3214 then_exit
->branch
.target_block
= else_idx
+ 1;
3219 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3221 /* Remember where we are */
3222 midgard_block
*start_block
= ctx
->current_block
;
3224 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3225 * single current_loop variable, maybe we need a stack */
3227 int loop_idx
= ++ctx
->current_loop
;
3229 /* Get index from before the body so we can loop back later */
3230 int start_idx
= ctx
->block_count
;
3232 /* Emit the body itself */
3233 emit_cf_list(ctx
, &nloop
->body
);
3235 /* Branch back to loop back */
3236 struct midgard_instruction br_back
= v_branch(false, false);
3237 br_back
.branch
.target_block
= start_idx
;
3238 emit_mir_instruction(ctx
, br_back
);
3240 /* Find the index of the block about to follow us (note: we don't add
3241 * one; blocks are 0-indexed so we get a fencepost problem) */
3242 int break_block_idx
= ctx
->block_count
;
3244 /* Fix up the break statements we emitted to point to the right place,
3245 * now that we can allocate a block number for them */
3247 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3248 print_mir_block(block
);
3249 mir_foreach_instr_in_block(block
, ins
) {
3250 if (ins
->type
!= TAG_ALU_4
) continue;
3251 if (!ins
->compact_branch
) continue;
3252 if (ins
->prepacked_branch
) continue;
3254 /* We found a branch -- check the type to see if we need to do anything */
3255 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3257 /* It's a break! Check if it's our break */
3258 if (ins
->branch
.target_break
!= loop_idx
) continue;
3260 /* Okay, cool, we're breaking out of this loop.
3261 * Rewrite from a break to a goto */
3263 ins
->branch
.target_type
= TARGET_GOTO
;
3264 ins
->branch
.target_block
= break_block_idx
;
3269 static midgard_block
*
3270 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3272 midgard_block
*start_block
= NULL
;
3274 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3275 switch (node
->type
) {
3276 case nir_cf_node_block
: {
3277 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3280 start_block
= block
;
3285 case nir_cf_node_if
:
3286 emit_if(ctx
, nir_cf_node_as_if(node
));
3289 case nir_cf_node_loop
:
3290 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3293 case nir_cf_node_function
:
3303 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3305 struct util_dynarray
*compiled
= &program
->compiled
;
3307 compiler_context ictx
= {
3309 .stage
= nir
->info
.stage
,
3311 .is_blend
= is_blend
,
3312 .blend_constant_offset
= -1,
3314 .alpha_ref
= program
->alpha_ref
3317 compiler_context
*ctx
= &ictx
;
3319 /* TODO: Decide this at runtime */
3320 ctx
->uniform_cutoff
= 8;
3322 switch (ctx
->stage
) {
3323 case MESA_SHADER_VERTEX
:
3324 ctx
->special_uniforms
= 1;
3328 ctx
->special_uniforms
= 0;
3332 /* Append epilogue uniforms if necessary. The cmdstream depends on
3333 * these being at the -end-; see assign_var_locations. */
3335 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3336 nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "viewport");
3339 /* Assign var locations early, so the epilogue can use them if necessary */
3341 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3342 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3343 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3345 /* Initialize at a global (not block) level hash tables */
3347 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3348 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3349 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3350 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3351 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3352 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3354 /* Assign actual uniform location, skipping over samplers */
3356 ctx
->uniform_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3358 nir_foreach_variable(var
, &nir
->uniforms
) {
3359 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_SAMPLER
) continue;
3361 unsigned length
= glsl_get_aoa_size(var
->type
);
3364 length
= glsl_get_length(var
->type
);
3368 length
= glsl_get_matrix_columns(var
->type
);
3371 for (int col
= 0; col
< length
; ++col
) {
3372 int id
= ctx
->uniform_count
++;
3373 _mesa_hash_table_u64_insert(ctx
->uniform_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3377 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3378 ctx
->varying_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3380 /* First, collect the special varyings */
3381 nir_foreach_variable(var
, &nir
->outputs
) {
3382 if (var
->data
.location
== VARYING_SLOT_POS
) {
3383 /* Set position first, always. It takes up two
3384 * spots, the latter one is de facto unused (at
3385 * least from the shader's perspective), we
3386 * just need to skip over the spot*/
3388 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (0 + 1)));
3389 ctx
->varying_count
= MAX2(ctx
->varying_count
, 2);
3390 } else if (var
->data
.location
== VARYING_SLOT_PSIZ
) {
3391 /* Set point size second (third, see above) */
3392 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (2 + 1)));
3393 ctx
->varying_count
= MAX2(ctx
->varying_count
, 3);
3395 program
->writes_point_size
= true;
3399 /* Now, collect normal varyings */
3401 nir_foreach_variable(var
, &nir
->outputs
) {
3402 if (var
->data
.location
== VARYING_SLOT_POS
|| var
->data
.location
== VARYING_SLOT_PSIZ
) continue;
3404 for (int col
= 0; col
< glsl_get_matrix_columns(var
->type
); ++col
) {
3405 int id
= ctx
->varying_count
++;
3406 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3413 /* Lower vars -- not I/O -- before epilogue */
3415 NIR_PASS_V(nir
, nir_lower_var_copies
);
3416 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3417 NIR_PASS_V(nir
, nir_split_var_copies
);
3418 NIR_PASS_V(nir
, nir_lower_var_copies
);
3419 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3420 NIR_PASS_V(nir
, nir_lower_var_copies
);
3421 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3422 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3424 /* Append vertex epilogue before optimisation, so the epilogue itself
3427 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3428 transform_position_writes(nir
);
3430 /* Optimisation passes */
3434 nir_print_shader(nir
, stdout
);
3436 /* Assign counts, now that we're sure (post-optimisation) */
3437 program
->uniform_count
= nir
->num_uniforms
;
3439 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3440 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3443 nir_foreach_function(func
, nir
) {
3447 list_inithead(&ctx
->blocks
);
3448 ctx
->block_count
= 0;
3451 emit_cf_list(ctx
, &func
->impl
->body
);
3452 emit_block(ctx
, func
->impl
->end_block
);
3454 break; /* TODO: Multi-function shaders */
3457 util_dynarray_init(compiled
, NULL
);
3460 schedule_program(ctx
);
3462 /* Now that all the bundles are scheduled and we can calculate block
3463 * sizes, emit actual branch instructions rather than placeholders */
3465 int br_block_idx
= 0;
3467 mir_foreach_block(ctx
, block
) {
3468 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3469 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3470 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3472 if (ins
->unit
!= ALU_ENAB_BR_COMPACT
) continue;
3474 if (ins
->prepacked_branch
) continue;
3478 /* Determine the block we're jumping to */
3479 int target_number
= ins
->branch
.target_block
;
3481 midgard_block
*target
= mir_get_block(ctx
, target_number
);
3484 /* Determine the destination tag */
3485 midgard_bundle
*first
= util_dynarray_element(&target
->bundles
, midgard_bundle
, 0);
3488 int dest_tag
= first
->tag
;
3490 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3491 int quadword_offset
= 0;
3493 if (target_number
> br_block_idx
) {
3496 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3497 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3500 quadword_offset
+= blk
->quadword_count
;
3503 /* Jump backwards */
3505 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3506 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3509 quadword_offset
-= blk
->quadword_count
;
3513 if (ins
->branch
.conditional
) {
3514 midgard_branch_cond branch
= {
3515 .op
= midgard_jmp_writeout_op_branch_cond
,
3516 .dest_tag
= dest_tag
,
3517 .offset
= quadword_offset
,
3518 .cond
= ins
->branch
.invert_conditional
? midgard_condition_false
: midgard_condition_true
3521 memcpy(&compact
, &branch
, sizeof(branch
));
3523 midgard_branch_uncond branch
= {
3524 .op
= midgard_jmp_writeout_op_branch_uncond
,
3525 .dest_tag
= dest_tag
,
3526 .offset
= quadword_offset
,
3530 memcpy(&compact
, &branch
, sizeof(branch
));
3533 /* Swap in the generic branch for our actual branch */
3534 ins
->unit
= ALU_ENAB_BR_COMPACT
;
3535 ins
->br_compact
= compact
;
3543 /* Emit flat binary from the instruction arrays. Iterate each block in
3544 * sequence. Save instruction boundaries such that lookahead tags can
3545 * be assigned easily */
3547 /* Cache _all_ bundles in source order for lookahead across failed branches */
3549 int bundle_count
= 0;
3550 mir_foreach_block(ctx
, block
) {
3551 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3553 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3555 mir_foreach_block(ctx
, block
) {
3556 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3557 source_order_bundles
[bundle_idx
++] = bundle
;
3561 int current_bundle
= 0;
3563 mir_foreach_block(ctx
, block
) {
3564 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3567 if (current_bundle
+ 1 < bundle_count
) {
3568 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3570 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3577 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3581 /* TODO: Free deeper */
3582 //util_dynarray_fini(&block->instructions);
3585 free(source_order_bundles
);
3587 /* Due to lookahead, we need to report in the command stream the first
3588 * tag executed. An initial block might be empty, so iterate until we
3589 * find one that 'works' */
3591 midgard_block
*initial_block
= list_first_entry(&ctx
->blocks
, midgard_block
, link
);
3593 program
->first_tag
= 0;
3596 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3598 if (initial_bundle
) {
3599 program
->first_tag
= initial_bundle
->tag
;
3603 /* Initial block is empty, try the next block */
3604 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3605 } while(initial_block
!= NULL
);
3607 /* Make sure we actually set the tag */
3608 assert(program
->first_tag
);
3610 /* Deal with off-by-one related to the fencepost problem */
3611 program
->work_register_count
= ctx
->work_registers
+ 1;
3613 program
->can_discard
= ctx
->can_discard
;
3614 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3616 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3618 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);