2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
111 midgard_is_branch_unit(unsigned unit
)
113 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
116 /* Generic in-memory data type repesenting a single logical instruction, rather
117 * than a single instruction group. This is the preferred form for code gen.
118 * Multiple midgard_insturctions will later be combined during scheduling,
119 * though this is not represented in this structure. Its format bridges
120 * the low-level binary representation with the higher level semantic meaning.
122 * Notably, it allows registers to be specified as block local SSA, for code
123 * emitted before the register allocation pass.
126 typedef struct midgard_instruction
{
127 /* Must be first for casting */
128 struct list_head link
;
130 unsigned type
; /* ALU, load/store, texture */
132 /* If the register allocator has not run yet... */
135 /* Special fields for an ALU instruction */
136 midgard_reg_info registers
;
138 /* I.e. (1 << alu_bit) */
143 uint16_t inline_constant
;
144 bool has_blend_constant
;
148 bool prepacked_branch
;
151 midgard_load_store_word load_store
;
152 midgard_vector_alu alu
;
153 midgard_texture_word texture
;
154 midgard_branch_extended branch_extended
;
157 /* General branch, rather than packed br_compact. Higher level
158 * than the other components */
159 midgard_branch branch
;
161 } midgard_instruction
;
163 typedef struct midgard_block
{
164 /* Link to next block. Must be first for mir_get_block */
165 struct list_head link
;
167 /* List of midgard_instructions emitted for the current block */
168 struct list_head instructions
;
172 /* List of midgard_bundles emitted (after the scheduler has run) */
173 struct util_dynarray bundles
;
175 /* Number of quadwords _actually_ emitted, as determined after scheduling */
176 unsigned quadword_count
;
178 /* Successors: always one forward (the block after us), maybe
179 * one backwards (for a backward branch). No need for a second
180 * forward, since graph traversal would get there eventually
182 struct midgard_block
*successors
[2];
183 unsigned nr_successors
;
185 /* The successors pointer form a graph, and in the case of
186 * complex control flow, this graph has a cycles. To aid
187 * traversal during liveness analysis, we have a visited?
188 * boolean for passes to use as they see fit, provided they
194 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
196 block
->successors
[block
->nr_successors
++] = successor
;
197 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
200 /* Helpers to generate midgard_instruction's using macro magic, since every
201 * driver seems to do it that way */
203 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
204 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
206 #define M_LOAD_STORE(name, rname, uname) \
207 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
208 midgard_instruction i = { \
209 .type = TAG_LOAD_STORE_4, \
216 .op = midgard_op_##name, \
218 .swizzle = SWIZZLE_XYZW, \
226 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
227 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
229 const midgard_vector_alu_src blank_alu_src
= {
230 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
233 const midgard_vector_alu_src blank_alu_src_xxxx
= {
234 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
237 const midgard_scalar_alu_src blank_scalar_alu_src
= {
241 /* Used for encoding the unused source of 1-op instructions */
242 const midgard_vector_alu_src zero_alu_src
= { 0 };
244 /* Coerce structs to integer */
247 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
250 memcpy(&u
, &src
, sizeof(src
));
254 static midgard_vector_alu_src
255 vector_alu_from_unsigned(unsigned u
)
257 midgard_vector_alu_src s
;
258 memcpy(&s
, &u
, sizeof(s
));
262 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
263 * the corresponding Midgard source */
265 static midgard_vector_alu_src
266 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
268 if (!src
) return blank_alu_src
;
270 midgard_vector_alu_src alu_src
= {
273 .half
= 0, /* TODO */
274 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
278 /* TODO: sign-extend/zero-extend */
279 alu_src
.mod
= midgard_int_normal
;
281 /* These should have been lowered away */
282 assert(!(src
->abs
|| src
->negate
));
284 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
291 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
294 if (!is_int
&& src
.mod
) return true;
297 for (unsigned c
= 0; c
< 4; ++c
) {
298 if (!(mask
& (1 << c
))) continue;
299 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
305 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
307 static midgard_instruction
308 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
310 midgard_instruction ins
= {
313 .src0
= SSA_UNUSED_1
,
318 .op
= midgard_alu_op_fmov
,
319 .reg_mode
= midgard_reg_mode_full
,
320 .dest_override
= midgard_dest_override_none
,
322 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
323 .src2
= vector_alu_srco_unsigned(mod
)
330 /* load/store instructions have both 32-bit and 16-bit variants, depending on
331 * whether we are using vectors composed of highp or mediump. At the moment, we
332 * don't support half-floats -- this requires changes in other parts of the
333 * compiler -- therefore the 16-bit versions are commented out. */
335 //M_LOAD(load_attr_16);
336 M_LOAD(load_attr_32
);
337 //M_LOAD(load_vary_16);
338 M_LOAD(load_vary_32
);
339 //M_LOAD(load_uniform_16);
340 M_LOAD(load_uniform_32
);
341 M_LOAD(load_color_buffer_8
);
342 //M_STORE(store_vary_16);
343 M_STORE(store_vary_32
);
344 M_STORE(store_cubemap_coords
);
346 static midgard_instruction
347 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
349 midgard_branch_cond branch
= {
357 memcpy(&compact
, &branch
, sizeof(branch
));
359 midgard_instruction ins
= {
361 .unit
= ALU_ENAB_BR_COMPACT
,
362 .prepacked_branch
= true,
363 .compact_branch
= true,
364 .br_compact
= compact
367 if (op
== midgard_jmp_writeout_op_writeout
)
373 static midgard_instruction
374 v_branch(bool conditional
, bool invert
)
376 midgard_instruction ins
= {
378 .unit
= ALU_ENAB_BRANCH
,
379 .compact_branch
= true,
381 .conditional
= conditional
,
382 .invert_conditional
= invert
389 static midgard_branch_extended
390 midgard_create_branch_extended( midgard_condition cond
,
391 midgard_jmp_writeout_op op
,
393 signed quadword_offset
)
395 /* For unclear reasons, the condition code is repeated 8 times */
396 uint16_t duplicated_cond
=
406 midgard_branch_extended branch
= {
408 .dest_tag
= dest_tag
,
409 .offset
= quadword_offset
,
410 .cond
= duplicated_cond
416 typedef struct midgard_bundle
{
417 /* Tag for the overall bundle */
420 /* Instructions contained by the bundle */
421 int instruction_count
;
422 midgard_instruction instructions
[5];
424 /* Bundle-wide ALU configuration */
427 bool has_embedded_constants
;
429 bool has_blend_constant
;
431 uint16_t register_words
[8];
432 int register_words_count
;
434 uint64_t body_words
[8];
436 int body_words_count
;
439 typedef struct compiler_context
{
441 gl_shader_stage stage
;
443 /* Is internally a blend shader? Depends on stage == FRAGMENT */
446 /* Tracking for blend constant patching */
447 int blend_constant_number
;
448 int blend_constant_offset
;
450 /* Current NIR function */
453 /* Unordered list of midgard_blocks */
455 struct list_head blocks
;
457 midgard_block
*initial_block
;
458 midgard_block
*previous_source_block
;
459 midgard_block
*final_block
;
461 /* List of midgard_instructions emitted for the current block */
462 midgard_block
*current_block
;
464 /* The current "depth" of the loop, for disambiguating breaks/continues
465 * when using nested loops */
466 int current_loop_depth
;
468 /* Constants which have been loaded, for later inlining */
469 struct hash_table_u64
*ssa_constants
;
471 /* SSA indices to be outputted to corresponding varying offset */
472 struct hash_table_u64
*ssa_varyings
;
474 /* SSA values / registers which have been aliased. Naively, these
475 * demand a fmov output; instead, we alias them in a later pass to
476 * avoid the wasted op.
478 * A note on encoding: to avoid dynamic memory management here, rather
479 * than ampping to a pointer, we map to the source index; the key
480 * itself is just the destination index. */
482 struct hash_table_u64
*ssa_to_alias
;
483 struct set
*leftover_ssa_to_alias
;
485 /* Actual SSA-to-register for RA */
486 struct hash_table_u64
*ssa_to_register
;
488 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
489 struct hash_table_u64
*hash_to_temp
;
493 /* Just the count of the max register used. Higher count => higher
494 * register pressure */
497 /* Used for cont/last hinting. Increase when a tex op is added.
498 * Decrease when a tex op is removed. */
499 int texture_op_count
;
501 /* Mapping of texture register -> SSA index for unaliasing */
502 int texture_index
[2];
504 /* If any path hits a discard instruction */
507 /* The number of uniforms allowable for the fast path */
510 /* Count of instructions emitted from NIR overall, across all blocks */
511 int instruction_count
;
513 /* Alpha ref value passed in */
516 /* The index corresponding to the fragment output */
517 unsigned fragment_output
;
519 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
520 unsigned sysvals
[MAX_SYSVAL_COUNT
];
521 unsigned sysval_count
;
522 struct hash_table_u64
*sysval_to_id
;
525 /* Append instruction to end of current block */
527 static midgard_instruction
*
528 mir_upload_ins(struct midgard_instruction ins
)
530 midgard_instruction
*heap
= malloc(sizeof(ins
));
531 memcpy(heap
, &ins
, sizeof(ins
));
536 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
538 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
542 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
544 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
548 mir_remove_instruction(struct midgard_instruction
*ins
)
550 list_del(&ins
->link
);
553 static midgard_instruction
*
554 mir_prev_op(struct midgard_instruction
*ins
)
556 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
559 static midgard_instruction
*
560 mir_next_op(struct midgard_instruction
*ins
)
562 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
565 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
566 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
568 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
569 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
570 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
571 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
572 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
573 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
574 #define mir_foreach_instr_in_block_from_rev(block, v, from) list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
577 static midgard_instruction
*
578 mir_last_in_block(struct midgard_block
*block
)
580 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
583 static midgard_block
*
584 mir_get_block(compiler_context
*ctx
, int idx
)
586 struct list_head
*lst
= &ctx
->blocks
;
591 return (struct midgard_block
*) lst
;
594 /* Pretty printer for internal Midgard IR */
597 print_mir_source(int source
)
599 if (source
>= SSA_FIXED_MINIMUM
) {
600 /* Specific register */
601 int reg
= SSA_REG_FROM_FIXED(source
);
603 /* TODO: Moving threshold */
604 if (reg
> 16 && reg
< 24)
605 printf("u%d", 23 - reg
);
609 printf("%d", source
);
614 print_mir_instruction(midgard_instruction
*ins
)
620 midgard_alu_op op
= ins
->alu
.op
;
621 const char *name
= alu_opcode_props
[op
].name
;
624 printf("%d.", ins
->unit
);
626 printf("%s", name
? name
: "??");
630 case TAG_LOAD_STORE_4
: {
631 midgard_load_store_op op
= ins
->load_store
.op
;
632 const char *name
= load_store_opcode_names
[op
];
639 case TAG_TEXTURE_4
: {
648 ssa_args
*args
= &ins
->ssa_args
;
650 printf(" %d, ", args
->dest
);
652 print_mir_source(args
->src0
);
655 if (args
->inline_constant
)
656 printf("#%d", ins
->inline_constant
);
658 print_mir_source(args
->src1
);
660 if (ins
->has_constants
)
661 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
667 print_mir_block(midgard_block
*block
)
671 mir_foreach_instr_in_block(block
, ins
) {
672 print_mir_instruction(ins
);
679 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
681 ins
->has_constants
= true;
682 memcpy(&ins
->constants
, constants
, 16);
684 /* If this is the special blend constant, mark this instruction */
686 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
687 ins
->has_blend_constant
= true;
691 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
693 return glsl_count_attribute_slots(type
, false);
696 /* Lower fdot2 to a vector multiplication followed by channel addition */
698 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
700 if (alu
->op
!= nir_op_fdot2
)
703 b
->cursor
= nir_before_instr(&alu
->instr
);
705 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
706 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
708 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
710 nir_ssa_def
*sum
= nir_fadd(b
,
711 nir_channel(b
, product
, 0),
712 nir_channel(b
, product
, 1));
714 /* Replace the fdot2 with this sum */
715 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
719 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
721 switch (instr
->intrinsic
) {
722 case nir_intrinsic_load_viewport_scale
:
723 return PAN_SYSVAL_VIEWPORT_SCALE
;
724 case nir_intrinsic_load_viewport_offset
:
725 return PAN_SYSVAL_VIEWPORT_OFFSET
;
732 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
736 if (instr
->type
== nir_instr_type_intrinsic
) {
737 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
738 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
744 /* We have a sysval load; check if it's already been assigned */
746 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
749 /* It hasn't -- so assign it now! */
751 unsigned id
= ctx
->sysval_count
++;
752 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
753 ctx
->sysvals
[id
] = sysval
;
757 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
759 ctx
->sysval_count
= 0;
761 nir_foreach_function(function
, shader
) {
762 if (!function
->impl
) continue;
764 nir_foreach_block(block
, function
->impl
) {
765 nir_foreach_instr_safe(instr
, block
) {
766 midgard_nir_assign_sysval_body(ctx
, instr
);
773 midgard_nir_lower_fdot2(nir_shader
*shader
)
775 bool progress
= false;
777 nir_foreach_function(function
, shader
) {
778 if (!function
->impl
) continue;
781 nir_builder
*b
= &_b
;
782 nir_builder_init(b
, function
->impl
);
784 nir_foreach_block(block
, function
->impl
) {
785 nir_foreach_instr_safe(instr
, block
) {
786 if (instr
->type
!= nir_instr_type_alu
) continue;
788 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
789 midgard_nir_lower_fdot2_body(b
, alu
);
795 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
803 optimise_nir(nir_shader
*nir
)
807 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
808 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
810 nir_lower_tex_options lower_tex_options
= {
814 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
819 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
820 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
822 NIR_PASS(progress
, nir
, nir_copy_prop
);
823 NIR_PASS(progress
, nir
, nir_opt_dce
);
824 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
825 NIR_PASS(progress
, nir
, nir_opt_cse
);
826 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
827 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
828 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
829 NIR_PASS(progress
, nir
, nir_opt_undef
);
830 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
833 nir_var_function_temp
);
835 /* TODO: Enable vectorize when merged upstream */
836 // NIR_PASS(progress, nir, nir_opt_vectorize);
839 /* Must be run at the end to prevent creation of fsin/fcos ops */
840 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
845 NIR_PASS(progress
, nir
, nir_opt_dce
);
846 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
847 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
848 NIR_PASS(progress
, nir
, nir_copy_prop
);
851 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
852 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
854 /* Lower mods for float ops only. Integer ops don't support modifiers
855 * (saturate doesn't make sense on integers, neg/abs require dedicated
858 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
859 NIR_PASS(progress
, nir
, nir_copy_prop
);
860 NIR_PASS(progress
, nir
, nir_opt_dce
);
862 /* We implement booleans as 32-bit 0/~0 */
863 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
865 /* Take us out of SSA */
866 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
867 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
869 /* We are a vector architecture; write combine where possible */
870 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
871 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
873 NIR_PASS(progress
, nir
, nir_opt_dce
);
876 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
877 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
878 * r0. See the comments in compiler_context */
881 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
883 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
884 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
887 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
890 unalias_ssa(compiler_context
*ctx
, int dest
)
892 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
893 /* TODO: Remove from leftover or no? */
897 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
899 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
903 midgard_is_pinned(compiler_context
*ctx
, int index
)
905 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
908 /* Do not actually emit a load; instead, cache the constant for inlining */
911 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
913 nir_ssa_def def
= instr
->def
;
915 float *v
= ralloc_array(NULL
, float, 4);
916 nir_const_load_to_arr(v
, instr
, f32
);
917 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
920 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
924 expand_writemask(unsigned mask
)
928 for (int i
= 0; i
< 4; ++i
)
936 squeeze_writemask(unsigned mask
)
940 for (int i
= 0; i
< 4; ++i
)
941 if (mask
& (3 << (2 * i
)))
948 /* Determines effective writemask, taking quirks and expansion into account */
950 effective_writemask(midgard_vector_alu
*alu
)
952 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
955 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
].props
);
957 /* If there is a fixed channel count, construct the appropriate mask */
960 return (1 << channel_count
) - 1;
962 /* Otherwise, just squeeze the existing mask */
963 return squeeze_writemask(alu
->mask
);
967 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
969 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
972 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
977 /* If no temp is find, allocate one */
978 temp
= ctx
->temp_count
++;
979 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
981 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
987 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
990 return src
->ssa
->index
;
992 assert(!src
->reg
.indirect
);
993 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
998 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
1001 return dst
->ssa
.index
;
1003 assert(!dst
->reg
.indirect
);
1004 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
1009 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
1011 return nir_src_index(ctx
, &src
->src
);
1014 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
1015 * a conditional test) into that register */
1018 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
1020 int condition
= nir_src_index(ctx
, src
);
1022 /* Source to swizzle the desired component into w */
1024 const midgard_vector_alu_src alu_src
= {
1025 .swizzle
= SWIZZLE(component
, component
, component
, component
),
1028 /* There is no boolean move instruction. Instead, we simulate a move by
1029 * ANDing the condition with itself to get it into r31.w */
1031 midgard_instruction ins
= {
1033 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
1037 .dest
= SSA_FIXED_REGISTER(31),
1040 .op
= midgard_alu_op_iand
,
1041 .reg_mode
= midgard_reg_mode_full
,
1042 .dest_override
= midgard_dest_override_none
,
1043 .mask
= (0x3 << 6), /* w */
1044 .src1
= vector_alu_srco_unsigned(alu_src
),
1045 .src2
= vector_alu_srco_unsigned(alu_src
)
1049 emit_mir_instruction(ctx
, ins
);
1052 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1053 * pinning to eliminate this move in all known cases */
1056 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1058 int offset
= nir_src_index(ctx
, src
);
1060 midgard_instruction ins
= {
1063 .src0
= SSA_UNUSED_1
,
1065 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1068 .op
= midgard_alu_op_imov
,
1069 .reg_mode
= midgard_reg_mode_full
,
1070 .dest_override
= midgard_dest_override_none
,
1071 .mask
= (0x3 << 6), /* w */
1072 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1073 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1077 emit_mir_instruction(ctx
, ins
);
1080 #define ALU_CASE(nir, _op) \
1081 case nir_op_##nir: \
1082 op = midgard_alu_op_##_op; \
1086 nir_is_fzero_constant(nir_src src
)
1088 if (!nir_src_is_const(src
))
1091 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
1092 if (nir_src_comp_as_float(src
, c
) != 0.0)
1100 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1102 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1104 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1105 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1106 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1108 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1109 * supported. A few do not and are commented for now. Also, there are a
1110 * number of NIR ops which Midgard does not support and need to be
1111 * lowered, also TODO. This switch block emits the opcode and calling
1112 * convention of the Midgard instruction; actual packing is done in
1117 switch (instr
->op
) {
1118 ALU_CASE(fadd
, fadd
);
1119 ALU_CASE(fmul
, fmul
);
1120 ALU_CASE(fmin
, fmin
);
1121 ALU_CASE(fmax
, fmax
);
1122 ALU_CASE(imin
, imin
);
1123 ALU_CASE(imax
, imax
);
1124 ALU_CASE(umin
, umin
);
1125 ALU_CASE(umax
, umax
);
1126 ALU_CASE(fmov
, fmov
);
1127 ALU_CASE(ffloor
, ffloor
);
1128 ALU_CASE(fround_even
, froundeven
);
1129 ALU_CASE(ftrunc
, ftrunc
);
1130 ALU_CASE(fceil
, fceil
);
1131 ALU_CASE(fdot3
, fdot3
);
1132 ALU_CASE(fdot4
, fdot4
);
1133 ALU_CASE(iadd
, iadd
);
1134 ALU_CASE(isub
, isub
);
1135 ALU_CASE(imul
, imul
);
1136 ALU_CASE(iabs
, iabs
);
1138 /* XXX: Use fmov, not imov, since imov was causing major
1139 * issues with texture precision? XXX research */
1140 ALU_CASE(imov
, imov
);
1142 ALU_CASE(feq32
, feq
);
1143 ALU_CASE(fne32
, fne
);
1144 ALU_CASE(flt32
, flt
);
1145 ALU_CASE(ieq32
, ieq
);
1146 ALU_CASE(ine32
, ine
);
1147 ALU_CASE(ilt32
, ilt
);
1148 ALU_CASE(ult32
, ult
);
1150 /* We don't have a native b2f32 instruction. Instead, like many
1151 * GPUs, we exploit booleans as 0/~0 for false/true, and
1152 * correspondingly AND
1153 * by 1.0 to do the type conversion. For the moment, prime us
1156 * iand [whatever], #0
1158 * At the end of emit_alu (as MIR), we'll fix-up the constant
1161 ALU_CASE(b2f32
, iand
);
1162 ALU_CASE(b2i32
, iand
);
1164 /* Likewise, we don't have a dedicated f2b32 instruction, but
1165 * we can do a "not equal to 0.0" test. */
1167 ALU_CASE(f2b32
, fne
);
1168 ALU_CASE(i2b32
, ine
);
1170 ALU_CASE(frcp
, frcp
);
1171 ALU_CASE(frsq
, frsqrt
);
1172 ALU_CASE(fsqrt
, fsqrt
);
1173 ALU_CASE(fexp2
, fexp2
);
1174 ALU_CASE(flog2
, flog2
);
1176 ALU_CASE(f2i32
, f2i
);
1177 ALU_CASE(f2u32
, f2u
);
1178 ALU_CASE(i2f32
, i2f
);
1179 ALU_CASE(u2f32
, u2f
);
1181 ALU_CASE(fsin
, fsin
);
1182 ALU_CASE(fcos
, fcos
);
1184 ALU_CASE(iand
, iand
);
1186 ALU_CASE(ixor
, ixor
);
1187 ALU_CASE(inot
, inand
);
1188 ALU_CASE(ishl
, ishl
);
1189 ALU_CASE(ishr
, iasr
);
1190 ALU_CASE(ushr
, ilsr
);
1192 ALU_CASE(b32all_fequal2
, fball_eq
);
1193 ALU_CASE(b32all_fequal3
, fball_eq
);
1194 ALU_CASE(b32all_fequal4
, fball_eq
);
1196 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1197 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1198 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1200 ALU_CASE(b32all_iequal2
, iball_eq
);
1201 ALU_CASE(b32all_iequal3
, iball_eq
);
1202 ALU_CASE(b32all_iequal4
, iball_eq
);
1204 ALU_CASE(b32any_inequal2
, ibany_neq
);
1205 ALU_CASE(b32any_inequal3
, ibany_neq
);
1206 ALU_CASE(b32any_inequal4
, ibany_neq
);
1208 /* For greater-or-equal, we lower to less-or-equal and flip the
1214 case nir_op_uge32
: {
1216 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1217 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1218 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1219 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1222 /* Swap via temporary */
1223 nir_alu_src temp
= instr
->src
[1];
1224 instr
->src
[1] = instr
->src
[0];
1225 instr
->src
[0] = temp
;
1230 /* For a few special csel cases not handled by NIR, we can opt to
1231 * bitwise. Otherwise, we emit the condition and do a real csel */
1233 case nir_op_b32csel
: {
1234 if (nir_is_fzero_constant(instr
->src
[2].src
)) {
1235 /* (b ? v : 0) = (b & v) */
1236 op
= midgard_alu_op_iand
;
1238 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1239 /* (b ? 0 : v) = (!b ? v : 0) = (~b & v) = (v & ~b) */
1240 op
= midgard_alu_op_iandnot
;
1242 instr
->src
[1] = instr
->src
[0];
1243 instr
->src
[0] = instr
->src
[2];
1245 op
= midgard_alu_op_fcsel
;
1247 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1250 /* Figure out which component the condition is in */
1252 unsigned comp
= instr
->src
[0].swizzle
[0];
1254 /* Make sure NIR isn't throwing a mixed condition at us */
1256 for (unsigned c
= 1; c
< nr_components
; ++c
)
1257 assert(instr
->src
[0].swizzle
[c
] == comp
);
1259 /* Emit the condition into r31.w */
1260 emit_condition(ctx
, &instr
->src
[0].src
, false, comp
);
1262 /* The condition is the first argument; move the other
1263 * arguments up one to be a binary instruction for
1266 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1272 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1277 /* Midgard can perform certain modifiers on output ofa n ALU op */
1278 midgard_outmod outmod
=
1279 instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1281 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1283 if (instr
->op
== nir_op_fmax
) {
1284 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1285 op
= midgard_alu_op_fmov
;
1287 outmod
= midgard_outmod_pos
;
1288 instr
->src
[0] = instr
->src
[1];
1289 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1290 op
= midgard_alu_op_fmov
;
1292 outmod
= midgard_outmod_pos
;
1296 /* Fetch unit, quirks, etc information */
1297 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1298 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1300 /* src0 will always exist afaik, but src1 will not for 1-argument
1301 * instructions. The latter can only be fetched if the instruction
1302 * needs it, or else we may segfault. */
1304 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1305 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1307 /* Rather than use the instruction generation helpers, we do it
1308 * ourselves here to avoid the mess */
1310 midgard_instruction ins
= {
1313 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1314 .src1
= quirk_flipped_r24
? src0
: src1
,
1319 nir_alu_src
*nirmods
[2] = { NULL
};
1321 if (nr_inputs
== 2) {
1322 nirmods
[0] = &instr
->src
[0];
1323 nirmods
[1] = &instr
->src
[1];
1324 } else if (nr_inputs
== 1) {
1325 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1330 bool is_int
= midgard_is_integer_op(op
);
1332 midgard_vector_alu alu
= {
1334 .reg_mode
= midgard_reg_mode_full
,
1335 .dest_override
= midgard_dest_override_none
,
1338 /* Writemask only valid for non-SSA NIR */
1339 .mask
= expand_writemask((1 << nr_components
) - 1),
1341 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
1342 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
1345 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1348 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1352 /* Late fixup for emulated instructions */
1354 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1355 /* Presently, our second argument is an inline #0 constant.
1356 * Switch over to an embedded 1.0 constant (that can't fit
1357 * inline, since we're 32-bit, not 16-bit like the inline
1360 ins
.ssa_args
.inline_constant
= false;
1361 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1362 ins
.has_constants
= true;
1364 if (instr
->op
== nir_op_b2f32
) {
1365 ins
.constants
[0] = 1.0f
;
1367 /* Type pun it into place */
1369 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1372 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1373 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1374 ins
.ssa_args
.inline_constant
= false;
1375 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1376 ins
.has_constants
= true;
1377 ins
.constants
[0] = 0.0f
;
1378 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1379 } else if (instr
->op
== nir_op_inot
) {
1380 /* ~b = ~(b & b), so duplicate the source */
1381 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1382 ins
.alu
.src2
= ins
.alu
.src1
;
1385 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1386 /* To avoid duplicating the lookup tables (probably), true LUT
1387 * instructions can only operate as if they were scalars. Lower
1388 * them here by changing the component. */
1390 uint8_t original_swizzle
[4];
1391 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1393 for (int i
= 0; i
< nr_components
; ++i
) {
1394 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1396 for (int j
= 0; j
< 4; ++j
)
1397 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1399 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
1400 emit_mir_instruction(ctx
, ins
);
1403 emit_mir_instruction(ctx
, ins
);
1410 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1412 /* TODO: half-floats */
1414 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1415 /* Fast path: For the first 16 uniforms, direct accesses are
1416 * 0-cycle, since they're just a register fetch in the usual
1417 * case. So, we alias the registers while we're still in
1420 int reg_slot
= 23 - offset
;
1421 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1423 /* Otherwise, read from the 'special' UBO to access
1424 * higher-indexed uniforms, at a performance cost. More
1425 * generally, we're emitting a UBO read instruction. */
1427 midgard_instruction ins
= m_load_uniform_32(dest
, offset
);
1429 /* TODO: Don't split */
1430 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1431 ins
.load_store
.address
= offset
>> 3;
1433 if (indirect_offset
) {
1434 emit_indirect_offset(ctx
, indirect_offset
);
1435 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1437 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1440 emit_mir_instruction(ctx
, ins
);
1445 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1447 /* First, pull out the destination */
1448 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1450 /* Now, figure out which uniform this is */
1451 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1452 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1454 /* Sysvals are prefix uniforms */
1455 unsigned uniform
= ((uintptr_t) val
) - 1;
1457 /* Emit the read itself -- this is never indirect */
1458 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1462 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1464 unsigned offset
, reg
;
1466 switch (instr
->intrinsic
) {
1467 case nir_intrinsic_discard_if
:
1468 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1472 case nir_intrinsic_discard
: {
1473 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1474 struct midgard_instruction discard
= v_branch(conditional
, false);
1475 discard
.branch
.target_type
= TARGET_DISCARD
;
1476 emit_mir_instruction(ctx
, discard
);
1478 ctx
->can_discard
= true;
1482 case nir_intrinsic_load_uniform
:
1483 case nir_intrinsic_load_input
:
1484 offset
= nir_intrinsic_base(instr
);
1486 bool direct
= nir_src_is_const(instr
->src
[0]);
1489 offset
+= nir_src_as_uint(instr
->src
[0]);
1492 reg
= nir_dest_index(ctx
, &instr
->dest
);
1494 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1495 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1496 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1497 /* XXX: Half-floats? */
1498 /* TODO: swizzle, mask */
1500 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1502 midgard_varying_parameter p
= {
1504 .interpolation
= midgard_interp_default
,
1505 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1509 memcpy(&u
, &p
, sizeof(p
));
1510 ins
.load_store
.varying_parameters
= u
;
1513 /* We have the offset totally ready */
1514 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1516 /* We have it partially ready, but we need to
1517 * add in the dynamic index, moved to r27.w */
1518 emit_indirect_offset(ctx
, &instr
->src
[0]);
1519 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1522 emit_mir_instruction(ctx
, ins
);
1523 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1524 /* Constant encoded as a pinned constant */
1526 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1527 ins
.has_constants
= true;
1528 ins
.has_blend_constant
= true;
1529 emit_mir_instruction(ctx
, ins
);
1530 } else if (ctx
->is_blend
) {
1531 /* For blend shaders, a load might be
1532 * translated various ways depending on what
1533 * we're loading. Figure out how this is used */
1535 nir_variable
*out
= NULL
;
1537 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1538 int drvloc
= var
->data
.driver_location
;
1540 if (nir_intrinsic_base(instr
) == drvloc
) {
1548 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1549 /* Source color preloaded to r0 */
1551 midgard_pin_output(ctx
, reg
, 0);
1552 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1553 /* Destination color must be read from framebuffer */
1555 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1556 ins
.load_store
.swizzle
= 0; /* xxxx */
1558 /* Read each component sequentially */
1560 for (int c
= 0; c
< 4; ++c
) {
1561 ins
.load_store
.mask
= (1 << c
);
1562 ins
.load_store
.unknown
= c
;
1563 emit_mir_instruction(ctx
, ins
);
1566 /* vadd.u2f hr2, zext(hr2), #0 */
1568 midgard_vector_alu_src alu_src
= blank_alu_src
;
1569 alu_src
.mod
= midgard_int_zero_extend
;
1570 alu_src
.half
= true;
1572 midgard_instruction u2f
= {
1576 .src1
= SSA_UNUSED_0
,
1578 .inline_constant
= true
1581 .op
= midgard_alu_op_u2f
,
1582 .reg_mode
= midgard_reg_mode_half
,
1583 .dest_override
= midgard_dest_override_none
,
1585 .src1
= vector_alu_srco_unsigned(alu_src
),
1586 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1590 emit_mir_instruction(ctx
, u2f
);
1592 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1596 midgard_instruction fmul
= {
1598 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1602 .src1
= SSA_UNUSED_0
,
1603 .inline_constant
= true
1606 .op
= midgard_alu_op_fmul
,
1607 .reg_mode
= midgard_reg_mode_full
,
1608 .dest_override
= midgard_dest_override_none
,
1609 .outmod
= midgard_outmod_sat
,
1611 .src1
= vector_alu_srco_unsigned(alu_src
),
1612 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1616 emit_mir_instruction(ctx
, fmul
);
1618 DBG("Unknown input in blend shader\n");
1621 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1622 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1623 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1624 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1625 emit_mir_instruction(ctx
, ins
);
1627 DBG("Unknown load\n");
1633 case nir_intrinsic_store_output
:
1634 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1636 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1638 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1640 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1641 /* gl_FragColor is not emitted with load/store
1642 * instructions. Instead, it gets plonked into
1643 * r0 at the end of the shader and we do the
1644 * framebuffer writeout dance. TODO: Defer
1647 midgard_pin_output(ctx
, reg
, 0);
1649 /* Save the index we're writing to for later reference
1650 * in the epilogue */
1652 ctx
->fragment_output
= reg
;
1653 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1654 /* Varyings are written into one of two special
1655 * varying register, r26 or r27. The register itself is selected as the register
1656 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1658 * Normally emitting fmov's is frowned upon,
1659 * but due to unique constraints of
1660 * REGISTER_VARYING, fmov emission + a
1661 * dedicated cleanup pass is the only way to
1662 * guarantee correctness when considering some
1663 * (common) edge cases XXX: FIXME */
1665 /* If this varying corresponds to a constant (why?!),
1666 * emit that now since it won't get picked up by
1667 * hoisting (since there is no corresponding move
1668 * emitted otherwise) */
1670 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1672 if (constant_value
) {
1673 /* Special case: emit the varying write
1674 * directly to r26 (looks funny in asm but it's
1675 * fine) and emit the store _now_. Possibly
1676 * slightly slower, but this is a really stupid
1677 * special case anyway (why on earth would you
1678 * have a constant varying? Your own fault for
1679 * slightly worse perf :P) */
1681 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1682 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1683 emit_mir_instruction(ctx
, ins
);
1685 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1686 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1687 emit_mir_instruction(ctx
, st
);
1689 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1691 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1694 DBG("Unknown store\n");
1700 case nir_intrinsic_load_alpha_ref_float
:
1701 assert(instr
->dest
.is_ssa
);
1703 float ref_value
= ctx
->alpha_ref
;
1705 float *v
= ralloc_array(NULL
, float, 4);
1706 memcpy(v
, &ref_value
, sizeof(float));
1707 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1710 case nir_intrinsic_load_viewport_scale
:
1711 case nir_intrinsic_load_viewport_offset
:
1712 emit_sysval_read(ctx
, instr
);
1716 printf ("Unhandled intrinsic\n");
1723 midgard_tex_format(enum glsl_sampler_dim dim
)
1726 case GLSL_SAMPLER_DIM_2D
:
1727 case GLSL_SAMPLER_DIM_EXTERNAL
:
1730 case GLSL_SAMPLER_DIM_3D
:
1733 case GLSL_SAMPLER_DIM_CUBE
:
1734 return TEXTURE_CUBE
;
1737 DBG("Unknown sampler dim type\n");
1744 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1747 //assert (!instr->sampler);
1748 //assert (!instr->texture_array_size);
1749 assert (instr
->op
== nir_texop_tex
);
1751 /* Allocate registers via a round robin scheme to alternate between the two registers */
1752 int reg
= ctx
->texture_op_count
& 1;
1753 int in_reg
= reg
, out_reg
= reg
;
1755 /* Make room for the reg */
1757 if (ctx
->texture_index
[reg
] > -1)
1758 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1760 int texture_index
= instr
->texture_index
;
1761 int sampler_index
= texture_index
;
1763 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1764 switch (instr
->src
[i
].src_type
) {
1765 case nir_tex_src_coord
: {
1766 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1768 midgard_vector_alu_src alu_src
= blank_alu_src
;
1770 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1772 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1773 /* For cubemaps, we need to load coords into
1774 * special r27, and then use a special ld/st op
1775 * to copy into the texture register */
1777 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1779 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1780 emit_mir_instruction(ctx
, move
);
1782 midgard_instruction st
= m_store_cubemap_coords(reg
, 0);
1783 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1784 st
.load_store
.mask
= 0x3; /* xy? */
1785 st
.load_store
.swizzle
= alu_src
.swizzle
;
1786 emit_mir_instruction(ctx
, st
);
1789 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1791 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1792 emit_mir_instruction(ctx
, ins
);
1799 DBG("Unknown source type\n");
1806 /* No helper to build texture words -- we do it all here */
1807 midgard_instruction ins
= {
1808 .type
= TAG_TEXTURE_4
,
1810 .op
= TEXTURE_OP_NORMAL
,
1811 .format
= midgard_tex_format(instr
->sampler_dim
),
1812 .texture_handle
= texture_index
,
1813 .sampler_handle
= sampler_index
,
1815 /* TODO: Don't force xyzw */
1816 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1828 /* Assume we can continue; hint it out later */
1833 /* Set registers to read and write from the same place */
1834 ins
.texture
.in_reg_select
= in_reg
;
1835 ins
.texture
.out_reg_select
= out_reg
;
1837 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1838 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1839 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1840 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1841 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1843 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1844 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1845 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1848 emit_mir_instruction(ctx
, ins
);
1850 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1852 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1853 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1854 ctx
->texture_index
[reg
] = o_index
;
1856 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1857 emit_mir_instruction(ctx
, ins2
);
1859 /* Used for .cont and .last hinting */
1860 ctx
->texture_op_count
++;
1864 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1866 switch (instr
->type
) {
1867 case nir_jump_break
: {
1868 /* Emit a branch out of the loop */
1869 struct midgard_instruction br
= v_branch(false, false);
1870 br
.branch
.target_type
= TARGET_BREAK
;
1871 br
.branch
.target_break
= ctx
->current_loop_depth
;
1872 emit_mir_instruction(ctx
, br
);
1879 DBG("Unknown jump type %d\n", instr
->type
);
1885 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1887 switch (instr
->type
) {
1888 case nir_instr_type_load_const
:
1889 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1892 case nir_instr_type_intrinsic
:
1893 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1896 case nir_instr_type_alu
:
1897 emit_alu(ctx
, nir_instr_as_alu(instr
));
1900 case nir_instr_type_tex
:
1901 emit_tex(ctx
, nir_instr_as_tex(instr
));
1904 case nir_instr_type_jump
:
1905 emit_jump(ctx
, nir_instr_as_jump(instr
));
1908 case nir_instr_type_ssa_undef
:
1913 DBG("Unhandled instruction type\n");
1918 /* Determine the actual hardware from the index based on the RA results or special values */
1921 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1923 if (reg
>= SSA_FIXED_MINIMUM
)
1924 return SSA_REG_FROM_FIXED(reg
);
1927 assert(reg
< maxreg
);
1928 int r
= ra_get_node_reg(g
, reg
);
1929 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1934 /* fmov style unused */
1936 return REGISTER_UNUSED
;
1938 /* lut style unused */
1940 return REGISTER_UNUSED
;
1943 DBG("Unknown SSA register alias %d\n", reg
);
1950 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1952 /* Choose the first available register to minimise reported register pressure */
1954 for (int i
= 0; i
< 16; ++i
) {
1955 if (BITSET_TEST(regs
, i
)) {
1965 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1967 if (ins
->ssa_args
.src0
== src
) return true;
1968 if (ins
->ssa_args
.src1
== src
) return true;
1973 /* Determine if a variable is live in the successors of a block */
1975 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
1977 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
1978 midgard_block
*succ
= bl
->successors
[i
];
1980 /* If we already visited, the value we're seeking
1981 * isn't down this path (or we would have short
1984 if (succ
->visited
) continue;
1986 /* Otherwise (it's visited *now*), check the block */
1988 succ
->visited
= true;
1990 mir_foreach_instr_in_block(succ
, ins
) {
1991 if (midgard_is_live_in_instr(ins
, src
))
1995 /* ...and also, check *its* successors */
1996 if (is_live_after_successors(ctx
, succ
, src
))
2001 /* Welp. We're really not live. */
2007 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
2009 /* Check the rest of the block for liveness */
2011 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
2012 if (midgard_is_live_in_instr(ins
, src
))
2016 /* Check the rest of the blocks for liveness recursively */
2018 bool succ
= is_live_after_successors(ctx
, block
, src
);
2020 mir_foreach_block(ctx
, block
) {
2021 block
->visited
= false;
2028 allocate_registers(compiler_context
*ctx
)
2030 /* First, initialize the RA */
2031 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
2033 /* Create a primary (general purpose) class, as well as special purpose
2034 * pipeline register classes */
2036 int primary_class
= ra_alloc_reg_class(regs
);
2037 int varying_class
= ra_alloc_reg_class(regs
);
2039 /* Add the full set of work registers */
2040 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
2041 for (int i
= 0; i
< work_count
; ++i
)
2042 ra_class_add_reg(regs
, primary_class
, i
);
2044 /* Add special registers */
2045 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
2046 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
2048 /* We're done setting up */
2049 ra_set_finalize(regs
, NULL
);
2051 /* Transform the MIR into squeezed index form */
2052 mir_foreach_block(ctx
, block
) {
2053 mir_foreach_instr_in_block(block
, ins
) {
2054 if (ins
->compact_branch
) continue;
2056 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
2057 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
2058 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
2060 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2061 print_mir_block(block
);
2064 /* Let's actually do register allocation */
2065 int nodes
= ctx
->temp_count
;
2066 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
2068 /* Set everything to the work register class, unless it has somewhere
2071 mir_foreach_block(ctx
, block
) {
2072 mir_foreach_instr_in_block(block
, ins
) {
2073 if (ins
->compact_branch
) continue;
2075 if (ins
->ssa_args
.dest
< 0) continue;
2077 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2079 int class = primary_class
;
2081 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2085 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2086 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2089 unsigned reg
= temp
- 1;
2090 int t
= find_or_allocate_temp(ctx
, index
);
2091 ra_set_node_reg(g
, t
, reg
);
2095 /* Determine liveness */
2097 int *live_start
= malloc(nodes
* sizeof(int));
2098 int *live_end
= malloc(nodes
* sizeof(int));
2100 /* Initialize as non-existent */
2102 for (int i
= 0; i
< nodes
; ++i
) {
2103 live_start
[i
] = live_end
[i
] = -1;
2108 mir_foreach_block(ctx
, block
) {
2109 mir_foreach_instr_in_block(block
, ins
) {
2110 if (ins
->compact_branch
) continue;
2112 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2113 /* If this destination is not yet live, it is now since we just wrote it */
2115 int dest
= ins
->ssa_args
.dest
;
2117 if (live_start
[dest
] == -1)
2118 live_start
[dest
] = d
;
2121 /* Since we just used a source, the source might be
2122 * dead now. Scan the rest of the block for
2123 * invocations, and if there are none, the source dies
2126 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2128 for (int src
= 0; src
< 2; ++src
) {
2129 int s
= sources
[src
];
2131 if (s
< 0) continue;
2133 if (s
>= SSA_FIXED_MINIMUM
) continue;
2135 if (!is_live_after(ctx
, block
, ins
, s
)) {
2144 /* If a node still hasn't been killed, kill it now */
2146 for (int i
= 0; i
< nodes
; ++i
) {
2147 /* live_start == -1 most likely indicates a pinned output */
2149 if (live_end
[i
] == -1)
2153 /* Setup interference between nodes that are live at the same time */
2155 for (int i
= 0; i
< nodes
; ++i
) {
2156 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2157 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2158 ra_add_node_interference(g
, i
, j
);
2162 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2164 if (!ra_allocate(g
)) {
2165 DBG("Error allocating registers\n");
2173 mir_foreach_block(ctx
, block
) {
2174 mir_foreach_instr_in_block(block
, ins
) {
2175 if (ins
->compact_branch
) continue;
2177 ssa_args args
= ins
->ssa_args
;
2179 switch (ins
->type
) {
2181 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
2183 ins
->registers
.src2_imm
= args
.inline_constant
;
2185 if (args
.inline_constant
) {
2186 /* Encode inline 16-bit constant as a vector by default */
2188 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2190 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2192 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2193 ins
->alu
.src2
= imm
<< 2;
2195 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
2198 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
2202 case TAG_LOAD_STORE_4
: {
2203 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2204 /* TODO: use ssa_args for store_vary */
2205 ins
->load_store
.reg
= 0;
2207 bool has_dest
= args
.dest
>= 0;
2208 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2210 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
2223 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2224 * use scalar ALU instructions, for functional or performance reasons. To do
2225 * this, we just demote vector ALU payloads to scalar. */
2228 component_from_mask(unsigned mask
)
2230 for (int c
= 0; c
< 4; ++c
) {
2231 if (mask
& (3 << (2 * c
)))
2240 is_single_component_mask(unsigned mask
)
2244 for (int c
= 0; c
< 4; ++c
)
2245 if (mask
& (3 << (2 * c
)))
2248 return components
== 1;
2251 /* Create a mask of accessed components from a swizzle to figure out vector
2255 swizzle_to_access_mask(unsigned swizzle
)
2257 unsigned component_mask
= 0;
2259 for (int i
= 0; i
< 4; ++i
) {
2260 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2261 component_mask
|= (1 << c
);
2264 return component_mask
;
2268 vector_to_scalar_source(unsigned u
, bool is_int
)
2270 midgard_vector_alu_src v
;
2271 memcpy(&v
, &u
, sizeof(v
));
2273 /* TODO: Integers */
2275 midgard_scalar_alu_src s
= {
2277 .component
= (v
.swizzle
& 3) << 1
2283 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
2284 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
2288 memcpy(&o
, &s
, sizeof(s
));
2290 return o
& ((1 << 6) - 1);
2293 static midgard_scalar_alu
2294 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2296 bool is_int
= midgard_is_integer_op(v
.op
);
2298 /* The output component is from the mask */
2299 midgard_scalar_alu s
= {
2301 .src1
= vector_to_scalar_source(v
.src1
, is_int
),
2302 .src2
= vector_to_scalar_source(v
.src2
, is_int
),
2305 .output_full
= 1, /* TODO: Half */
2306 .output_component
= component_from_mask(v
.mask
) << 1,
2309 /* Inline constant is passed along rather than trying to extract it
2312 if (ins
->ssa_args
.inline_constant
) {
2314 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2315 imm
|= (lower_11
>> 9) & 3;
2316 imm
|= (lower_11
>> 6) & 4;
2317 imm
|= (lower_11
>> 2) & 0x38;
2318 imm
|= (lower_11
& 63) << 6;
2326 /* Midgard prefetches instruction types, so during emission we need to
2327 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2328 * if this is the second to last and the last is an ALU, then it's also 1... */
2330 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2331 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2333 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2334 bytes_emitted += sizeof(type)
2337 emit_binary_vector_instruction(midgard_instruction
*ains
,
2338 uint16_t *register_words
, int *register_words_count
,
2339 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2340 size_t *bytes_emitted
)
2342 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2343 *bytes_emitted
+= sizeof(midgard_reg_info
);
2345 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2346 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2347 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2350 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2351 * mind that we are a vector architecture and we can write to different
2352 * components simultaneously */
2355 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2357 /* Each instruction reads some registers and writes to a register. See
2358 * where the first writes */
2360 /* Figure out where exactly we wrote to */
2361 int source
= first
->ssa_args
.dest
;
2362 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2364 /* As long as the second doesn't read from the first, we're okay */
2365 if (second
->ssa_args
.src0
== source
) {
2366 if (first
->type
== TAG_ALU_4
) {
2367 /* Figure out which components we just read from */
2369 int q
= second
->alu
.src1
;
2370 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2372 /* Check if there are components in common, and fail if so */
2373 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2380 if (second
->ssa_args
.src1
== source
)
2383 /* Otherwise, it's safe in that regard. Another data hazard is both
2384 * writing to the same place, of course */
2386 if (second
->ssa_args
.dest
== source
) {
2387 /* ...but only if the components overlap */
2388 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2390 if (dest_mask
& source_mask
)
2400 midgard_instruction
**segment
, unsigned segment_size
,
2401 midgard_instruction
*ains
)
2403 for (int s
= 0; s
< segment_size
; ++s
)
2404 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2412 /* Schedules, but does not emit, a single basic block. After scheduling, the
2413 * final tag and size of the block are known, which are necessary for branching
2416 static midgard_bundle
2417 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2419 int instructions_emitted
= 0, instructions_consumed
= -1;
2420 midgard_bundle bundle
= { 0 };
2422 uint8_t tag
= ins
->type
;
2424 /* Default to the instruction's tag */
2427 switch (ins
->type
) {
2429 uint32_t control
= 0;
2430 size_t bytes_emitted
= sizeof(control
);
2432 /* TODO: Constant combining */
2433 int index
= 0, last_unit
= 0;
2435 /* Previous instructions, for the purpose of parallelism */
2436 midgard_instruction
*segment
[4] = {0};
2437 int segment_size
= 0;
2439 instructions_emitted
= -1;
2440 midgard_instruction
*pins
= ins
;
2443 midgard_instruction
*ains
= pins
;
2445 /* Advance instruction pointer */
2447 ains
= mir_next_op(pins
);
2451 /* Out-of-work condition */
2452 if ((struct list_head
*) ains
== &block
->instructions
)
2455 /* Ensure that the chain can continue */
2456 if (ains
->type
!= TAG_ALU_4
) break;
2458 /* According to the presentation "The ARM
2459 * Mali-T880 Mobile GPU" from HotChips 27,
2460 * there are two pipeline stages. Branching
2461 * position determined experimentally. Lines
2462 * are executed in parallel:
2465 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2467 * Verify that there are no ordering dependencies here.
2469 * TODO: Allow for parallelism!!!
2472 /* Pick a unit for it if it doesn't force a particular unit */
2474 int unit
= ains
->unit
;
2477 int op
= ains
->alu
.op
;
2478 int units
= alu_opcode_props
[op
].props
;
2480 /* TODO: Promotion of scalars to vectors */
2481 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2484 assert(units
& UNITS_SCALAR
);
2487 if (last_unit
>= UNIT_VADD
) {
2488 if (units
& UNIT_VLUT
)
2493 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2495 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2497 else if (units
& UNIT_VLUT
)
2503 if (last_unit
>= UNIT_VADD
) {
2504 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2506 else if (units
& UNIT_VLUT
)
2511 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2513 else if (units
& UNIT_SMUL
)
2514 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2515 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2522 assert(unit
& units
);
2525 /* Late unit check, this time for encoding (not parallelism) */
2526 if (unit
<= last_unit
) break;
2528 /* Clear the segment */
2529 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2532 if (midgard_has_hazard(segment
, segment_size
, ains
))
2535 /* We're good to go -- emit the instruction */
2538 segment
[segment_size
++] = ains
;
2540 /* Only one set of embedded constants per
2541 * bundle possible; if we have more, we must
2542 * break the chain early, unfortunately */
2544 if (ains
->has_constants
) {
2545 if (bundle
.has_embedded_constants
) {
2546 /* ...but if there are already
2547 * constants but these are the
2548 * *same* constants, we let it
2551 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2554 bundle
.has_embedded_constants
= true;
2555 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2557 /* If this is a blend shader special constant, track it for patching */
2558 if (ains
->has_blend_constant
)
2559 bundle
.has_blend_constant
= true;
2563 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2564 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2565 &bundle
.register_words_count
, bundle
.body_words
,
2566 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2567 } else if (ains
->compact_branch
) {
2568 /* All of r0 has to be written out
2569 * along with the branch writeout.
2572 if (ains
->writeout
) {
2574 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2575 ins
.unit
= UNIT_VMUL
;
2577 control
|= ins
.unit
;
2579 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2580 &bundle
.register_words_count
, bundle
.body_words
,
2581 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2583 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2584 bool written_late
= false;
2585 bool components
[4] = { 0 };
2586 uint16_t register_dep_mask
= 0;
2587 uint16_t written_mask
= 0;
2589 midgard_instruction
*qins
= ins
;
2590 for (int t
= 0; t
< index
; ++t
) {
2591 if (qins
->registers
.out_reg
!= 0) {
2592 /* Mark down writes */
2594 written_mask
|= (1 << qins
->registers
.out_reg
);
2596 /* Mark down the register dependencies for errata check */
2598 if (qins
->registers
.src1_reg
< 16)
2599 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2601 if (qins
->registers
.src2_reg
< 16)
2602 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2604 int mask
= qins
->alu
.mask
;
2606 for (int c
= 0; c
< 4; ++c
)
2607 if (mask
& (0x3 << (2 * c
)))
2608 components
[c
] = true;
2610 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2612 if (qins
->unit
== UNIT_VLUT
)
2613 written_late
= true;
2616 /* Advance instruction pointer */
2617 qins
= mir_next_op(qins
);
2621 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2622 if (register_dep_mask
& written_mask
) {
2623 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2630 /* If even a single component is not written, break it up (conservative check). */
2631 bool breakup
= false;
2633 for (int c
= 0; c
< 4; ++c
)
2640 /* Otherwise, we're free to proceed */
2644 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2645 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2646 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2647 bytes_emitted
+= sizeof(midgard_branch_extended
);
2649 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2650 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2651 bytes_emitted
+= sizeof(ains
->br_compact
);
2654 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2655 bytes_emitted
+= sizeof(midgard_reg_info
);
2657 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2658 bundle
.body_words_count
++;
2659 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2662 /* Defer marking until after writing to allow for break */
2663 control
|= ains
->unit
;
2664 last_unit
= ains
->unit
;
2665 ++instructions_emitted
;
2669 /* Bubble up the number of instructions for skipping */
2670 instructions_consumed
= index
- 1;
2674 /* Pad ALU op to nearest word */
2676 if (bytes_emitted
& 15) {
2677 padding
= 16 - (bytes_emitted
& 15);
2678 bytes_emitted
+= padding
;
2681 /* Constants must always be quadwords */
2682 if (bundle
.has_embedded_constants
)
2683 bytes_emitted
+= 16;
2685 /* Size ALU instruction for tag */
2686 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2687 bundle
.padding
= padding
;
2688 bundle
.control
= bundle
.tag
| control
;
2693 case TAG_LOAD_STORE_4
: {
2694 /* Load store instructions have two words at once. If
2695 * we only have one queued up, we need to NOP pad.
2696 * Otherwise, we store both in succession to save space
2697 * and cycles -- letting them go in parallel -- skip
2698 * the next. The usefulness of this optimisation is
2699 * greatly dependent on the quality of the instruction
2703 midgard_instruction
*next_op
= mir_next_op(ins
);
2705 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2706 /* As the two operate concurrently, make sure
2707 * they are not dependent */
2709 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2710 /* Skip ahead, since it's redundant with the pair */
2711 instructions_consumed
= 1 + (instructions_emitted
++);
2719 /* Texture ops default to single-op-per-bundle scheduling */
2723 /* Copy the instructions into the bundle */
2724 bundle
.instruction_count
= instructions_emitted
+ 1;
2728 midgard_instruction
*uins
= ins
;
2729 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2730 bundle
.instructions
[used_idx
++] = *uins
;
2731 uins
= mir_next_op(uins
);
2734 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2740 quadword_size(int tag
)
2755 case TAG_LOAD_STORE_4
:
2767 /* Schedule a single block by iterating its instruction to create bundles.
2768 * While we go, tally about the bundle sizes to compute the block size. */
2771 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2773 util_dynarray_init(&block
->bundles
, NULL
);
2775 block
->quadword_count
= 0;
2777 mir_foreach_instr_in_block(block
, ins
) {
2779 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2780 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2782 if (bundle
.has_blend_constant
) {
2783 /* TODO: Multiblock? */
2784 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2785 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2789 ins
= mir_next_op(ins
);
2791 block
->quadword_count
+= quadword_size(bundle
.tag
);
2794 block
->is_scheduled
= true;
2798 schedule_program(compiler_context
*ctx
)
2800 allocate_registers(ctx
);
2802 mir_foreach_block(ctx
, block
) {
2803 schedule_block(ctx
, block
);
2807 /* After everything is scheduled, emit whole bundles at a time */
2810 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2812 int lookahead
= next_tag
<< 4;
2814 switch (bundle
->tag
) {
2819 /* Actually emit each component */
2820 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2822 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2823 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2825 /* Emit body words based on the instructions bundled */
2826 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2827 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2829 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2830 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2831 } else if (ins
->compact_branch
) {
2832 /* Dummy move, XXX DRY */
2833 if ((i
== 0) && ins
->writeout
) {
2834 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2835 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2838 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2839 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2841 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2845 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2846 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2850 /* Emit padding (all zero) */
2851 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2853 /* Tack on constants */
2855 if (bundle
->has_embedded_constants
) {
2856 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2857 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2858 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2859 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2865 case TAG_LOAD_STORE_4
: {
2866 /* One or two composing instructions */
2868 uint64_t current64
, next64
= LDST_NOP
;
2870 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2872 if (bundle
->instruction_count
== 2)
2873 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2875 midgard_load_store instruction
= {
2876 .type
= bundle
->tag
,
2877 .next_type
= next_tag
,
2882 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2887 case TAG_TEXTURE_4
: {
2888 /* Texture instructions are easy, since there is no
2889 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2891 midgard_instruction
*ins
= &bundle
->instructions
[0];
2893 ins
->texture
.type
= TAG_TEXTURE_4
;
2894 ins
->texture
.next_type
= next_tag
;
2896 ctx
->texture_op_count
--;
2898 if (!ctx
->texture_op_count
) {
2899 ins
->texture
.cont
= 0;
2900 ins
->texture
.last
= 1;
2903 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2908 DBG("Unknown midgard instruction type\n");
2915 /* ALU instructions can inline or embed constants, which decreases register
2916 * pressure and saves space. */
2918 #define CONDITIONAL_ATTACH(src) { \
2919 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2922 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2923 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2928 inline_alu_constants(compiler_context
*ctx
)
2930 mir_foreach_instr(ctx
, alu
) {
2931 /* Other instructions cannot inline constants */
2932 if (alu
->type
!= TAG_ALU_4
) continue;
2934 /* If there is already a constant here, we can do nothing */
2935 if (alu
->has_constants
) continue;
2937 /* It makes no sense to inline constants on a branch */
2938 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
2940 CONDITIONAL_ATTACH(src0
);
2942 if (!alu
->has_constants
) {
2943 CONDITIONAL_ATTACH(src1
)
2944 } else if (!alu
->inline_constant
) {
2945 /* Corner case: _two_ vec4 constants, for instance with a
2946 * csel. For this case, we can only use a constant
2947 * register for one, we'll have to emit a move for the
2948 * other. Note, if both arguments are constants, then
2949 * necessarily neither argument depends on the value of
2950 * any particular register. As the destination register
2951 * will be wiped, that means we can spill the constant
2952 * to the destination register.
2955 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2956 unsigned scratch
= alu
->ssa_args
.dest
;
2959 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2960 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2962 /* Force a break XXX Defer r31 writes */
2963 ins
.unit
= UNIT_VLUT
;
2965 /* Set the source */
2966 alu
->ssa_args
.src1
= scratch
;
2968 /* Inject us -before- the last instruction which set r31 */
2969 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2975 /* Midgard supports two types of constants, embedded constants (128-bit) and
2976 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2977 * constants can be demoted to inline constants, for space savings and
2978 * sometimes a performance boost */
2981 embedded_to_inline_constant(compiler_context
*ctx
)
2983 mir_foreach_instr(ctx
, ins
) {
2984 if (!ins
->has_constants
) continue;
2986 if (ins
->ssa_args
.inline_constant
) continue;
2988 /* Blend constants must not be inlined by definition */
2989 if (ins
->has_blend_constant
) continue;
2991 /* src1 cannot be an inline constant due to encoding
2992 * restrictions. So, if possible we try to flip the arguments
2995 int op
= ins
->alu
.op
;
2997 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2999 /* These ops require an operational change to flip
3000 * their arguments TODO */
3001 case midgard_alu_op_flt
:
3002 case midgard_alu_op_fle
:
3003 case midgard_alu_op_ilt
:
3004 case midgard_alu_op_ile
:
3005 case midgard_alu_op_fcsel
:
3006 case midgard_alu_op_icsel
:
3007 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
3012 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
3013 /* Flip the SSA numbers */
3014 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
3015 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
3017 /* And flip the modifiers */
3021 src_temp
= ins
->alu
.src2
;
3022 ins
->alu
.src2
= ins
->alu
.src1
;
3023 ins
->alu
.src1
= src_temp
;
3027 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
3028 /* Extract the source information */
3030 midgard_vector_alu_src
*src
;
3031 int q
= ins
->alu
.src2
;
3032 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
3035 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
3036 int component
= src
->swizzle
& 3;
3038 /* Scale constant appropriately, if we can legally */
3039 uint16_t scaled_constant
= 0;
3041 /* XXX: Check legality */
3042 if (midgard_is_integer_op(op
)) {
3043 /* TODO: Inline integer */
3046 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
3047 scaled_constant
= (uint16_t) iconstants
[component
];
3049 /* Constant overflow after resize */
3050 if (scaled_constant
!= iconstants
[component
])
3053 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
3056 /* We don't know how to handle these with a constant */
3058 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
3059 DBG("Bailing inline constant...\n");
3063 /* Make sure that the constant is not itself a
3064 * vector by checking if all accessed values
3065 * (by the swizzle) are the same. */
3067 uint32_t *cons
= (uint32_t *) ins
->constants
;
3068 uint32_t value
= cons
[component
];
3070 bool is_vector
= false;
3071 unsigned mask
= effective_writemask(&ins
->alu
);
3073 for (int c
= 1; c
< 4; ++c
) {
3074 /* We only care if this component is actually used */
3075 if (!(mask
& (1 << c
)))
3078 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3080 if (test
!= value
) {
3089 /* Get rid of the embedded constant */
3090 ins
->has_constants
= false;
3091 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3092 ins
->ssa_args
.inline_constant
= true;
3093 ins
->inline_constant
= scaled_constant
;
3098 /* Map normal SSA sources to other SSA sources / fixed registers (like
3102 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3104 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3107 /* Remove entry in leftovers to avoid a redunant fmov */
3109 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3112 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3114 /* Assign the alias map */
3120 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
3121 * texture pipeline */
3124 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
3126 bool progress
= false;
3128 mir_foreach_instr_in_block_safe(block
, ins
) {
3129 if (ins
->type
!= TAG_ALU_4
) continue;
3130 if (ins
->compact_branch
) continue;
3132 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3133 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3134 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3136 mir_remove_instruction(ins
);
3144 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
3146 bool progress
= false;
3148 mir_foreach_instr_in_block_safe(block
, ins
) {
3149 if (ins
->type
!= TAG_ALU_4
) continue;
3150 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3152 unsigned from
= ins
->ssa_args
.src1
;
3153 unsigned to
= ins
->ssa_args
.dest
;
3155 /* We only work on pure SSA */
3157 if (to
>= SSA_FIXED_MINIMUM
) continue;
3158 if (from
>= SSA_FIXED_MINIMUM
) continue;
3160 /* Also, if the move has side effects, we're helpless */
3162 midgard_vector_alu_src src
=
3163 vector_alu_from_unsigned(ins
->alu
.src2
);
3164 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
3165 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
3167 if (mir_nontrivial_mod(src
, is_int
, mask
)) continue;
3169 mir_foreach_instr_in_block_from(block
, v
, mir_next_op(ins
)) {
3170 if (v
->ssa_args
.src0
== to
) {
3171 v
->ssa_args
.src0
= from
;
3175 if (v
->ssa_args
.src1
== to
&& !v
->ssa_args
.inline_constant
) {
3176 v
->ssa_args
.src1
= from
;
3186 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
3188 bool progress
= false;
3190 mir_foreach_instr_in_block_safe(block
, ins
) {
3191 if (ins
->type
!= TAG_ALU_4
) continue;
3192 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3194 unsigned from
= ins
->ssa_args
.src1
;
3195 unsigned to
= ins
->ssa_args
.dest
;
3197 /* Make sure it's a familiar type of special move. Basically we
3198 * just handle the special dummy moves emitted by the texture
3199 * pipeline. TODO: verify. TODO: why does this break varyings?
3202 if (from
>= SSA_FIXED_MINIMUM
) continue;
3203 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
3204 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
3206 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
3207 if (v
->ssa_args
.dest
== from
) {
3208 v
->ssa_args
.dest
= to
;
3213 mir_remove_instruction(ins
);
3219 /* The following passes reorder MIR instructions to enable better scheduling */
3222 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3224 mir_foreach_instr_in_block_safe(block
, ins
) {
3225 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3227 /* We've found a load/store op. Check if next is also load/store. */
3228 midgard_instruction
*next_op
= mir_next_op(ins
);
3229 if (&next_op
->link
!= &block
->instructions
) {
3230 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3231 /* If so, we're done since we're a pair */
3232 ins
= mir_next_op(ins
);
3236 /* Maximum search distance to pair, to avoid register pressure disasters */
3237 int search_distance
= 8;
3239 /* Otherwise, we have an orphaned load/store -- search for another load */
3240 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3241 /* Terminate search if necessary */
3242 if (!(search_distance
--)) break;
3244 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3246 /* Stores cannot be reordered, since they have
3247 * dependencies. For the same reason, indirect
3248 * loads cannot be reordered as their index is
3249 * loaded in r27.w */
3251 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3253 /* It appears the 0x800 bit is set whenever a
3254 * load is direct, unset when it is indirect.
3255 * Skip indirect loads. */
3257 if (!(c
->load_store
.unknown
& 0x800)) continue;
3259 /* We found one! Move it up to pair and remove it from the old location */
3261 mir_insert_instruction_before(ins
, *c
);
3262 mir_remove_instruction(c
);
3270 /* Emit varying stores late */
3273 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3274 /* Iterate in reverse to get the final write, rather than the first */
3276 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3277 /* Check if what we just wrote needs a store */
3278 int idx
= ins
->ssa_args
.dest
;
3279 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3281 if (!varying
) continue;
3285 /* We need to store to the appropriate varying, so emit the
3288 /* TODO: Integrate with special purpose RA (and scheduler?) */
3289 bool high_varying_register
= false;
3291 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3293 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3294 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3296 mir_insert_instruction_before(mir_next_op(ins
), st
);
3297 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3299 /* We no longer need to store this varying */
3300 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3304 /* If there are leftovers after the below pass, emit actual fmov
3305 * instructions for the slow-but-correct path */
3308 emit_leftover_move(compiler_context
*ctx
)
3310 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3311 int base
= ((uintptr_t) leftover
->key
) - 1;
3314 map_ssa_to_alias(ctx
, &mapped
);
3315 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3320 actualise_ssa_to_alias(compiler_context
*ctx
)
3322 mir_foreach_instr(ctx
, ins
) {
3323 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3324 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3327 emit_leftover_move(ctx
);
3331 emit_fragment_epilogue(compiler_context
*ctx
)
3333 /* Special case: writing out constants requires us to include the move
3334 * explicitly now, so shove it into r0 */
3336 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3338 if (constant_value
) {
3339 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3340 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3341 emit_mir_instruction(ctx
, ins
);
3344 /* Perform the actual fragment writeout. We have two writeout/branch
3345 * instructions, forming a loop until writeout is successful as per the
3346 * docs. TODO: gl_FragDepth */
3348 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3349 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3352 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3353 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3354 * with the int8 analogue to the fragment epilogue */
3357 emit_blend_epilogue(compiler_context
*ctx
)
3359 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3361 midgard_instruction scale
= {
3364 .inline_constant
= _mesa_float_to_half(255.0),
3366 .src0
= SSA_FIXED_REGISTER(0),
3367 .src1
= SSA_UNUSED_0
,
3368 .dest
= SSA_FIXED_REGISTER(24),
3369 .inline_constant
= true
3372 .op
= midgard_alu_op_fmul
,
3373 .reg_mode
= midgard_reg_mode_full
,
3374 .dest_override
= midgard_dest_override_lower
,
3376 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3377 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3381 emit_mir_instruction(ctx
, scale
);
3383 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3385 midgard_vector_alu_src alu_src
= blank_alu_src
;
3386 alu_src
.half
= true;
3388 midgard_instruction f2u8
= {
3391 .src0
= SSA_FIXED_REGISTER(24),
3392 .src1
= SSA_UNUSED_0
,
3393 .dest
= SSA_FIXED_REGISTER(0),
3394 .inline_constant
= true
3397 .op
= midgard_alu_op_f2u8
,
3398 .reg_mode
= midgard_reg_mode_half
,
3399 .dest_override
= midgard_dest_override_lower
,
3400 .outmod
= midgard_outmod_pos
,
3402 .src1
= vector_alu_srco_unsigned(alu_src
),
3403 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3407 emit_mir_instruction(ctx
, f2u8
);
3409 /* vmul.imov.quarter r0, r0, r0 */
3411 midgard_instruction imov_8
= {
3414 .src0
= SSA_UNUSED_1
,
3415 .src1
= SSA_FIXED_REGISTER(0),
3416 .dest
= SSA_FIXED_REGISTER(0),
3419 .op
= midgard_alu_op_imov
,
3420 .reg_mode
= midgard_reg_mode_quarter
,
3421 .dest_override
= midgard_dest_override_none
,
3423 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3424 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3428 /* Emit branch epilogue with the 8-bit move as the source */
3430 emit_mir_instruction(ctx
, imov_8
);
3431 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3433 emit_mir_instruction(ctx
, imov_8
);
3434 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3437 static midgard_block
*
3438 emit_block(compiler_context
*ctx
, nir_block
*block
)
3440 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3441 list_addtail(&this_block
->link
, &ctx
->blocks
);
3443 this_block
->is_scheduled
= false;
3446 ctx
->texture_index
[0] = -1;
3447 ctx
->texture_index
[1] = -1;
3449 /* Add us as a successor to the block we are following */
3450 if (ctx
->current_block
)
3451 midgard_block_add_successor(ctx
->current_block
, this_block
);
3453 /* Set up current block */
3454 list_inithead(&this_block
->instructions
);
3455 ctx
->current_block
= this_block
;
3457 nir_foreach_instr(instr
, block
) {
3458 emit_instr(ctx
, instr
);
3459 ++ctx
->instruction_count
;
3462 inline_alu_constants(ctx
);
3463 embedded_to_inline_constant(ctx
);
3465 /* Perform heavylifting for aliasing */
3466 actualise_ssa_to_alias(ctx
);
3468 midgard_emit_store(ctx
, this_block
);
3469 midgard_pair_load_store(ctx
, this_block
);
3471 /* Append fragment shader epilogue (value writeout) */
3472 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3473 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3475 emit_blend_epilogue(ctx
);
3477 emit_fragment_epilogue(ctx
);
3481 if (block
== nir_start_block(ctx
->func
->impl
))
3482 ctx
->initial_block
= this_block
;
3484 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3485 ctx
->final_block
= this_block
;
3487 /* Allow the next control flow to access us retroactively, for
3489 ctx
->current_block
= this_block
;
3491 /* Document the fallthrough chain */
3492 ctx
->previous_source_block
= this_block
;
3497 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3500 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3502 /* Conditional branches expect the condition in r31.w; emit a move for
3503 * that in the _previous_ block (which is the current block). */
3504 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3506 /* Speculatively emit the branch, but we can't fill it in until later */
3507 EMIT(branch
, true, true);
3508 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3510 /* Emit the two subblocks */
3511 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3513 /* Emit a jump from the end of the then block to the end of the else */
3514 EMIT(branch
, false, false);
3515 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3517 /* Emit second block, and check if it's empty */
3519 int else_idx
= ctx
->block_count
;
3520 int count_in
= ctx
->instruction_count
;
3521 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3522 int after_else_idx
= ctx
->block_count
;
3524 /* Now that we have the subblocks emitted, fix up the branches */
3529 if (ctx
->instruction_count
== count_in
) {
3530 /* The else block is empty, so don't emit an exit jump */
3531 mir_remove_instruction(then_exit
);
3532 then_branch
->branch
.target_block
= after_else_idx
;
3534 then_branch
->branch
.target_block
= else_idx
;
3535 then_exit
->branch
.target_block
= after_else_idx
;
3540 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3542 /* Remember where we are */
3543 midgard_block
*start_block
= ctx
->current_block
;
3545 /* Allocate a loop number, growing the current inner loop depth */
3546 int loop_idx
= ++ctx
->current_loop_depth
;
3548 /* Get index from before the body so we can loop back later */
3549 int start_idx
= ctx
->block_count
;
3551 /* Emit the body itself */
3552 emit_cf_list(ctx
, &nloop
->body
);
3554 /* Branch back to loop back */
3555 struct midgard_instruction br_back
= v_branch(false, false);
3556 br_back
.branch
.target_block
= start_idx
;
3557 emit_mir_instruction(ctx
, br_back
);
3559 /* Mark down that branch in the graph. Note that we're really branching
3560 * to the block *after* we started in. TODO: Why doesn't the branch
3561 * itself have an off-by-one then...? */
3562 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
3564 /* Find the index of the block about to follow us (note: we don't add
3565 * one; blocks are 0-indexed so we get a fencepost problem) */
3566 int break_block_idx
= ctx
->block_count
;
3568 /* Fix up the break statements we emitted to point to the right place,
3569 * now that we can allocate a block number for them */
3571 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3572 mir_foreach_instr_in_block(block
, ins
) {
3573 if (ins
->type
!= TAG_ALU_4
) continue;
3574 if (!ins
->compact_branch
) continue;
3575 if (ins
->prepacked_branch
) continue;
3577 /* We found a branch -- check the type to see if we need to do anything */
3578 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3580 /* It's a break! Check if it's our break */
3581 if (ins
->branch
.target_break
!= loop_idx
) continue;
3583 /* Okay, cool, we're breaking out of this loop.
3584 * Rewrite from a break to a goto */
3586 ins
->branch
.target_type
= TARGET_GOTO
;
3587 ins
->branch
.target_block
= break_block_idx
;
3591 /* Now that we've finished emitting the loop, free up the depth again
3592 * so we play nice with recursion amid nested loops */
3593 --ctx
->current_loop_depth
;
3596 static midgard_block
*
3597 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3599 midgard_block
*start_block
= NULL
;
3601 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3602 switch (node
->type
) {
3603 case nir_cf_node_block
: {
3604 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3607 start_block
= block
;
3612 case nir_cf_node_if
:
3613 emit_if(ctx
, nir_cf_node_as_if(node
));
3616 case nir_cf_node_loop
:
3617 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3620 case nir_cf_node_function
:
3629 /* Due to lookahead, we need to report the first tag executed in the command
3630 * stream and in branch targets. An initial block might be empty, so iterate
3631 * until we find one that 'works' */
3634 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3636 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3638 unsigned first_tag
= 0;
3641 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3643 if (initial_bundle
) {
3644 first_tag
= initial_bundle
->tag
;
3648 /* Initial block is empty, try the next block */
3649 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3650 } while(initial_block
!= NULL
);
3657 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3659 struct util_dynarray
*compiled
= &program
->compiled
;
3661 midgard_debug
= debug_get_option_midgard_debug();
3663 compiler_context ictx
= {
3665 .stage
= nir
->info
.stage
,
3667 .is_blend
= is_blend
,
3668 .blend_constant_offset
= -1,
3670 .alpha_ref
= program
->alpha_ref
3673 compiler_context
*ctx
= &ictx
;
3675 /* TODO: Decide this at runtime */
3676 ctx
->uniform_cutoff
= 8;
3678 /* Assign var locations early, so the epilogue can use them if necessary */
3680 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3681 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3682 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3684 /* Initialize at a global (not block) level hash tables */
3686 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3687 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3688 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3689 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3690 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3691 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3692 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3694 /* Record the varying mapping for the command stream's bookkeeping */
3696 struct exec_list
*varyings
=
3697 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3699 nir_foreach_variable(var
, varyings
) {
3700 unsigned loc
= var
->data
.driver_location
;
3701 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3703 for (int c
= 0; c
< sz
; ++c
) {
3704 program
->varyings
[loc
+ c
] = var
->data
.location
;
3708 /* Lower gl_Position pre-optimisation */
3710 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3711 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3713 NIR_PASS_V(nir
, nir_lower_var_copies
);
3714 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3715 NIR_PASS_V(nir
, nir_split_var_copies
);
3716 NIR_PASS_V(nir
, nir_lower_var_copies
);
3717 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3718 NIR_PASS_V(nir
, nir_lower_var_copies
);
3719 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3721 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3723 /* Optimisation passes */
3727 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3728 nir_print_shader(nir
, stdout
);
3731 /* Assign sysvals and counts, now that we're sure
3732 * (post-optimisation) */
3734 midgard_nir_assign_sysvals(ctx
, nir
);
3736 program
->uniform_count
= nir
->num_uniforms
;
3737 program
->sysval_count
= ctx
->sysval_count
;
3738 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3740 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3741 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3743 nir_foreach_function(func
, nir
) {
3747 list_inithead(&ctx
->blocks
);
3748 ctx
->block_count
= 0;
3751 emit_cf_list(ctx
, &func
->impl
->body
);
3752 emit_block(ctx
, func
->impl
->end_block
);
3754 break; /* TODO: Multi-function shaders */
3757 util_dynarray_init(compiled
, NULL
);
3759 /* MIR-level optimizations */
3761 bool progress
= false;
3766 mir_foreach_block(ctx
, block
) {
3767 progress
|= midgard_opt_copy_prop(ctx
, block
);
3768 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
3769 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
3774 schedule_program(ctx
);
3776 /* Now that all the bundles are scheduled and we can calculate block
3777 * sizes, emit actual branch instructions rather than placeholders */
3779 int br_block_idx
= 0;
3781 mir_foreach_block(ctx
, block
) {
3782 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3783 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3784 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3786 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3788 if (ins
->prepacked_branch
) continue;
3790 /* Parse some basic branch info */
3791 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3792 bool is_conditional
= ins
->branch
.conditional
;
3793 bool is_inverted
= ins
->branch
.invert_conditional
;
3794 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3796 /* Determine the block we're jumping to */
3797 int target_number
= ins
->branch
.target_block
;
3799 /* Report the destination tag. Discards don't need this */
3800 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3802 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3803 int quadword_offset
= 0;
3806 /* Jump to the end of the shader. We
3807 * need to include not only the
3808 * following blocks, but also the
3809 * contents of our current block (since
3810 * discard can come in the middle of
3813 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3815 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3816 quadword_offset
+= quadword_size(bun
->tag
);
3819 mir_foreach_block_from(ctx
, blk
, b
) {
3820 quadword_offset
+= b
->quadword_count
;
3823 } else if (target_number
> br_block_idx
) {
3826 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3827 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3830 quadword_offset
+= blk
->quadword_count
;
3833 /* Jump backwards */
3835 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3836 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3839 quadword_offset
-= blk
->quadword_count
;
3843 /* Unconditional extended branches (far jumps)
3844 * have issues, so we always use a conditional
3845 * branch, setting the condition to always for
3846 * unconditional. For compact unconditional
3847 * branches, cond isn't used so it doesn't
3848 * matter what we pick. */
3850 midgard_condition cond
=
3851 !is_conditional
? midgard_condition_always
:
3852 is_inverted
? midgard_condition_false
:
3853 midgard_condition_true
;
3855 midgard_jmp_writeout_op op
=
3856 is_discard
? midgard_jmp_writeout_op_discard
:
3857 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3858 midgard_jmp_writeout_op_branch_cond
;
3861 midgard_branch_extended branch
=
3862 midgard_create_branch_extended(
3867 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3868 } else if (is_conditional
|| is_discard
) {
3869 midgard_branch_cond branch
= {
3871 .dest_tag
= dest_tag
,
3872 .offset
= quadword_offset
,
3876 assert(branch
.offset
== quadword_offset
);
3878 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3880 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3882 midgard_branch_uncond branch
= {
3884 .dest_tag
= dest_tag
,
3885 .offset
= quadword_offset
,
3889 assert(branch
.offset
== quadword_offset
);
3891 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3899 /* Emit flat binary from the instruction arrays. Iterate each block in
3900 * sequence. Save instruction boundaries such that lookahead tags can
3901 * be assigned easily */
3903 /* Cache _all_ bundles in source order for lookahead across failed branches */
3905 int bundle_count
= 0;
3906 mir_foreach_block(ctx
, block
) {
3907 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3909 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3911 mir_foreach_block(ctx
, block
) {
3912 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3913 source_order_bundles
[bundle_idx
++] = bundle
;
3917 int current_bundle
= 0;
3919 mir_foreach_block(ctx
, block
) {
3920 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3923 if (current_bundle
+ 1 < bundle_count
) {
3924 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3926 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3933 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3937 /* TODO: Free deeper */
3938 //util_dynarray_fini(&block->instructions);
3941 free(source_order_bundles
);
3943 /* Report the very first tag executed */
3944 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3946 /* Deal with off-by-one related to the fencepost problem */
3947 program
->work_register_count
= ctx
->work_registers
+ 1;
3949 program
->can_discard
= ctx
->can_discard
;
3950 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3952 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3954 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3955 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);