2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
60 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
62 int midgard_debug
= 0;
64 #define DBG(fmt, ...) \
65 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
66 fprintf(stderr, "%s:%d: "fmt, \
67 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
70 midgard_is_branch_unit(unsigned unit
)
72 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
76 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
78 block
->successors
[block
->nr_successors
++] = successor
;
79 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
82 /* Helpers to generate midgard_instruction's using macro magic, since every
83 * driver seems to do it that way */
85 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
98 .op = midgard_op_##name, \
99 .swizzle = SWIZZLE_XYZW, \
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
115 bool half
, bool sext
)
117 if (!src
) return blank_alu_src
;
119 /* Figure out how many components there are so we can adjust the
120 * swizzle. Specifically we want to broadcast the last channel so
121 * things like ball2/3 work
124 if (broadcast_count
) {
125 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
127 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
128 src
->swizzle
[c
] = last_component
;
132 midgard_vector_alu_src alu_src
= {
136 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
140 alu_src
.mod
= midgard_int_normal
;
142 /* Sign/zero-extend if needed */
146 midgard_int_sign_extend
147 : midgard_int_zero_extend
;
150 /* These should have been lowered away */
151 assert(!(src
->abs
|| src
->negate
));
153 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
159 /* load/store instructions have both 32-bit and 16-bit variants, depending on
160 * whether we are using vectors composed of highp or mediump. At the moment, we
161 * don't support half-floats -- this requires changes in other parts of the
162 * compiler -- therefore the 16-bit versions are commented out. */
164 //M_LOAD(ld_attr_16);
166 //M_LOAD(ld_vary_16);
168 //M_LOAD(ld_uniform_16);
169 M_LOAD(ld_uniform_32
);
170 M_LOAD(ld_color_buffer_8
);
171 //M_STORE(st_vary_16);
173 M_STORE(st_cubemap_coords
);
175 static midgard_instruction
176 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
178 midgard_branch_cond branch
= {
186 memcpy(&compact
, &branch
, sizeof(branch
));
188 midgard_instruction ins
= {
190 .unit
= ALU_ENAB_BR_COMPACT
,
191 .prepacked_branch
= true,
192 .compact_branch
= true,
193 .br_compact
= compact
196 if (op
== midgard_jmp_writeout_op_writeout
)
202 static midgard_instruction
203 v_branch(bool conditional
, bool invert
)
205 midgard_instruction ins
= {
207 .unit
= ALU_ENAB_BRANCH
,
208 .compact_branch
= true,
210 .conditional
= conditional
,
211 .invert_conditional
= invert
218 static midgard_branch_extended
219 midgard_create_branch_extended( midgard_condition cond
,
220 midgard_jmp_writeout_op op
,
222 signed quadword_offset
)
224 /* For unclear reasons, the condition code is repeated 8 times */
225 uint16_t duplicated_cond
=
235 midgard_branch_extended branch
= {
237 .dest_tag
= dest_tag
,
238 .offset
= quadword_offset
,
239 .cond
= duplicated_cond
246 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
248 ins
->has_constants
= true;
249 memcpy(&ins
->constants
, constants
, 16);
253 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
255 return glsl_count_attribute_slots(type
, false);
258 /* Lower fdot2 to a vector multiplication followed by channel addition */
260 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
262 if (alu
->op
!= nir_op_fdot2
)
265 b
->cursor
= nir_before_instr(&alu
->instr
);
267 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
268 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
270 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
272 nir_ssa_def
*sum
= nir_fadd(b
,
273 nir_channel(b
, product
, 0),
274 nir_channel(b
, product
, 1));
276 /* Replace the fdot2 with this sum */
277 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
281 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
283 switch (instr
->intrinsic
) {
284 case nir_intrinsic_load_viewport_scale
:
285 return PAN_SYSVAL_VIEWPORT_SCALE
;
286 case nir_intrinsic_load_viewport_offset
:
287 return PAN_SYSVAL_VIEWPORT_OFFSET
;
294 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
297 return dst
->ssa
.index
;
299 assert(!dst
->reg
.indirect
);
300 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
304 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
307 nir_intrinsic_instr
*intr
;
308 nir_dest
*dst
= NULL
;
312 switch (instr
->type
) {
313 case nir_instr_type_intrinsic
:
314 intr
= nir_instr_as_intrinsic(instr
);
315 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
318 case nir_instr_type_tex
:
319 tex
= nir_instr_as_tex(instr
);
320 if (tex
->op
!= nir_texop_txs
)
323 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
324 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
325 nir_tex_instr_dest_size(tex
) -
326 (tex
->is_array
? 1 : 0),
335 *dest
= nir_dest_index(ctx
, dst
);
341 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
345 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
349 /* We have a sysval load; check if it's already been assigned */
351 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
354 /* It hasn't -- so assign it now! */
356 unsigned id
= ctx
->sysval_count
++;
357 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
358 ctx
->sysvals
[id
] = sysval
;
362 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
364 ctx
->sysval_count
= 0;
366 nir_foreach_function(function
, shader
) {
367 if (!function
->impl
) continue;
369 nir_foreach_block(block
, function
->impl
) {
370 nir_foreach_instr_safe(instr
, block
) {
371 midgard_nir_assign_sysval_body(ctx
, instr
);
378 midgard_nir_lower_fdot2(nir_shader
*shader
)
380 bool progress
= false;
382 nir_foreach_function(function
, shader
) {
383 if (!function
->impl
) continue;
386 nir_builder
*b
= &_b
;
387 nir_builder_init(b
, function
->impl
);
389 nir_foreach_block(block
, function
->impl
) {
390 nir_foreach_instr_safe(instr
, block
) {
391 if (instr
->type
!= nir_instr_type_alu
) continue;
393 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
394 midgard_nir_lower_fdot2_body(b
, alu
);
400 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
408 optimise_nir(nir_shader
*nir
)
411 unsigned lower_flrp
=
412 (nir
->options
->lower_flrp16
? 16 : 0) |
413 (nir
->options
->lower_flrp32
? 32 : 0) |
414 (nir
->options
->lower_flrp64
? 64 : 0);
416 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
417 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
418 NIR_PASS(progress
, nir
, nir_lower_idiv
);
420 nir_lower_tex_options lower_tex_1st_pass_options
= {
425 nir_lower_tex_options lower_tex_2nd_pass_options
= {
426 .lower_txs_lod
= true,
429 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
430 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
435 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
436 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
438 NIR_PASS(progress
, nir
, nir_copy_prop
);
439 NIR_PASS(progress
, nir
, nir_opt_dce
);
440 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
441 NIR_PASS(progress
, nir
, nir_opt_cse
);
442 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
443 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
444 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
446 if (lower_flrp
!= 0) {
447 bool lower_flrp_progress
= false;
448 NIR_PASS(lower_flrp_progress
,
452 false /* always_precise */,
453 nir
->options
->lower_ffma
);
454 if (lower_flrp_progress
) {
455 NIR_PASS(progress
, nir
,
456 nir_opt_constant_folding
);
460 /* Nothing should rematerialize any flrps, so we only
461 * need to do this lowering once.
466 NIR_PASS(progress
, nir
, nir_opt_undef
);
467 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
470 nir_var_function_temp
);
472 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
475 /* Must be run at the end to prevent creation of fsin/fcos ops */
476 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
481 NIR_PASS(progress
, nir
, nir_opt_dce
);
482 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
483 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
484 NIR_PASS(progress
, nir
, nir_copy_prop
);
487 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
489 /* We implement booleans as 32-bit 0/~0 */
490 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
492 /* Now that booleans are lowered, we can run out late opts */
493 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
495 /* Lower mods for float ops only. Integer ops don't support modifiers
496 * (saturate doesn't make sense on integers, neg/abs require dedicated
499 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
500 NIR_PASS(progress
, nir
, nir_copy_prop
);
501 NIR_PASS(progress
, nir
, nir_opt_dce
);
503 /* Take us out of SSA */
504 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
505 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
507 /* We are a vector architecture; write combine where possible */
508 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
509 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
511 NIR_PASS(progress
, nir
, nir_opt_dce
);
514 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
515 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
516 * r0. See the comments in compiler_context */
519 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
521 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
522 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
525 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
528 unalias_ssa(compiler_context
*ctx
, int dest
)
530 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
531 /* TODO: Remove from leftover or no? */
534 /* Do not actually emit a load; instead, cache the constant for inlining */
537 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
539 nir_ssa_def def
= instr
->def
;
541 float *v
= rzalloc_array(NULL
, float, 4);
542 nir_const_load_to_arr(v
, instr
, f32
);
543 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
547 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
550 return src
->ssa
->index
;
552 assert(!src
->reg
.indirect
);
553 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
558 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
560 return nir_src_index(ctx
, &src
->src
);
564 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
566 unsigned comp
= src
->swizzle
[0];
568 for (unsigned c
= 1; c
< nr_components
; ++c
) {
569 if (src
->swizzle
[c
] != comp
)
576 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
577 * output of a conditional test) into that register */
580 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
582 int condition
= nir_src_index(ctx
, src
);
584 /* Source to swizzle the desired component into w */
586 const midgard_vector_alu_src alu_src
= {
587 .swizzle
= SWIZZLE(component
, component
, component
, component
),
590 /* There is no boolean move instruction. Instead, we simulate a move by
591 * ANDing the condition with itself to get it into r31.w */
593 midgard_instruction ins
= {
596 /* We need to set the conditional as close as possible */
597 .precede_break
= true,
598 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
599 .mask
= 1 << COMPONENT_W
,
604 .dest
= SSA_FIXED_REGISTER(31),
608 .op
= midgard_alu_op_iand
,
609 .outmod
= midgard_outmod_int_wrap
,
610 .reg_mode
= midgard_reg_mode_32
,
611 .dest_override
= midgard_dest_override_none
,
612 .src1
= vector_alu_srco_unsigned(alu_src
),
613 .src2
= vector_alu_srco_unsigned(alu_src
)
617 emit_mir_instruction(ctx
, ins
);
620 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
624 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
626 int condition
= nir_src_index(ctx
, &src
->src
);
628 /* Source to swizzle the desired component into w */
630 const midgard_vector_alu_src alu_src
= {
631 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
634 /* There is no boolean move instruction. Instead, we simulate a move by
635 * ANDing the condition with itself to get it into r31.w */
637 midgard_instruction ins
= {
639 .precede_break
= true,
640 .mask
= mask_of(nr_comp
),
644 .dest
= SSA_FIXED_REGISTER(31),
647 .op
= midgard_alu_op_iand
,
648 .outmod
= midgard_outmod_int_wrap
,
649 .reg_mode
= midgard_reg_mode_32
,
650 .dest_override
= midgard_dest_override_none
,
651 .src1
= vector_alu_srco_unsigned(alu_src
),
652 .src2
= vector_alu_srco_unsigned(alu_src
)
656 emit_mir_instruction(ctx
, ins
);
661 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
662 * pinning to eliminate this move in all known cases */
665 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
667 int offset
= nir_src_index(ctx
, src
);
669 midgard_instruction ins
= {
671 .mask
= 1 << COMPONENT_W
,
673 .src0
= SSA_UNUSED_1
,
675 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
678 .op
= midgard_alu_op_imov
,
679 .outmod
= midgard_outmod_int_wrap
,
680 .reg_mode
= midgard_reg_mode_32
,
681 .dest_override
= midgard_dest_override_none
,
682 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
683 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
687 emit_mir_instruction(ctx
, ins
);
690 #define ALU_CASE(nir, _op) \
692 op = midgard_alu_op_##_op; \
693 assert(src_bitsize == dst_bitsize); \
696 #define ALU_CASE_BCAST(nir, _op, count) \
698 op = midgard_alu_op_##_op; \
699 broadcast_swizzle = count; \
700 assert(src_bitsize == dst_bitsize); \
703 nir_is_fzero_constant(nir_src src
)
705 if (!nir_src_is_const(src
))
708 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
709 if (nir_src_comp_as_float(src
, c
) != 0.0)
716 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
717 * special treatment override this anyway. */
719 static midgard_reg_mode
720 reg_mode_for_nir(nir_alu_instr
*instr
)
722 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
724 switch (src_bitsize
) {
726 return midgard_reg_mode_8
;
728 return midgard_reg_mode_16
;
730 return midgard_reg_mode_32
;
732 return midgard_reg_mode_64
;
734 unreachable("Invalid bit size");
739 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
741 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
743 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
744 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
745 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
747 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
748 * supported. A few do not and are commented for now. Also, there are a
749 * number of NIR ops which Midgard does not support and need to be
750 * lowered, also TODO. This switch block emits the opcode and calling
751 * convention of the Midgard instruction; actual packing is done in
756 /* Number of components valid to check for the instruction (the rest
757 * will be forced to the last), or 0 to use as-is. Relevant as
758 * ball-type instructions have a channel count in NIR but are all vec4
761 unsigned broadcast_swizzle
= 0;
763 /* What register mode should we operate in? */
764 midgard_reg_mode reg_mode
=
765 reg_mode_for_nir(instr
);
767 /* Do we need a destination override? Used for inline
770 midgard_dest_override dest_override
=
771 midgard_dest_override_none
;
773 /* Should we use a smaller respective source and sign-extend? */
775 bool half_1
= false, sext_1
= false;
776 bool half_2
= false, sext_2
= false;
778 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
779 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
782 ALU_CASE(fadd
, fadd
);
783 ALU_CASE(fmul
, fmul
);
784 ALU_CASE(fmin
, fmin
);
785 ALU_CASE(fmax
, fmax
);
786 ALU_CASE(imin
, imin
);
787 ALU_CASE(imax
, imax
);
788 ALU_CASE(umin
, umin
);
789 ALU_CASE(umax
, umax
);
790 ALU_CASE(ffloor
, ffloor
);
791 ALU_CASE(fround_even
, froundeven
);
792 ALU_CASE(ftrunc
, ftrunc
);
793 ALU_CASE(fceil
, fceil
);
794 ALU_CASE(fdot3
, fdot3
);
795 ALU_CASE(fdot4
, fdot4
);
796 ALU_CASE(iadd
, iadd
);
797 ALU_CASE(isub
, isub
);
798 ALU_CASE(imul
, imul
);
800 /* Zero shoved as second-arg */
801 ALU_CASE(iabs
, iabsdiff
);
805 ALU_CASE(feq32
, feq
);
806 ALU_CASE(fne32
, fne
);
807 ALU_CASE(flt32
, flt
);
808 ALU_CASE(ieq32
, ieq
);
809 ALU_CASE(ine32
, ine
);
810 ALU_CASE(ilt32
, ilt
);
811 ALU_CASE(ult32
, ult
);
813 /* We don't have a native b2f32 instruction. Instead, like many
814 * GPUs, we exploit booleans as 0/~0 for false/true, and
815 * correspondingly AND
816 * by 1.0 to do the type conversion. For the moment, prime us
819 * iand [whatever], #0
821 * At the end of emit_alu (as MIR), we'll fix-up the constant
824 ALU_CASE(b2f32
, iand
);
825 ALU_CASE(b2i32
, iand
);
827 /* Likewise, we don't have a dedicated f2b32 instruction, but
828 * we can do a "not equal to 0.0" test. */
830 ALU_CASE(f2b32
, fne
);
831 ALU_CASE(i2b32
, ine
);
833 ALU_CASE(frcp
, frcp
);
834 ALU_CASE(frsq
, frsqrt
);
835 ALU_CASE(fsqrt
, fsqrt
);
836 ALU_CASE(fexp2
, fexp2
);
837 ALU_CASE(flog2
, flog2
);
839 ALU_CASE(f2i32
, f2i_rtz
);
840 ALU_CASE(f2u32
, f2u_rtz
);
841 ALU_CASE(i2f32
, i2f_rtz
);
842 ALU_CASE(u2f32
, u2f_rtz
);
844 ALU_CASE(f2i16
, f2i_rtz
);
845 ALU_CASE(f2u16
, f2u_rtz
);
846 ALU_CASE(i2f16
, i2f_rtz
);
847 ALU_CASE(u2f16
, u2f_rtz
);
849 ALU_CASE(fsin
, fsin
);
850 ALU_CASE(fcos
, fcos
);
852 /* Second op implicit #0 */
853 ALU_CASE(inot
, inor
);
854 ALU_CASE(iand
, iand
);
856 ALU_CASE(ixor
, ixor
);
857 ALU_CASE(ishl
, ishl
);
858 ALU_CASE(ishr
, iasr
);
859 ALU_CASE(ushr
, ilsr
);
861 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
862 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
863 ALU_CASE(b32all_fequal4
, fball_eq
);
865 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
866 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
867 ALU_CASE(b32any_fnequal4
, fbany_neq
);
869 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
870 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
871 ALU_CASE(b32all_iequal4
, iball_eq
);
873 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
874 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
875 ALU_CASE(b32any_inequal4
, ibany_neq
);
877 /* Source mods will be shoved in later */
878 ALU_CASE(fabs
, fmov
);
879 ALU_CASE(fneg
, fmov
);
880 ALU_CASE(fsat
, fmov
);
882 /* For size conversion, we use a move. Ideally though we would squash
883 * these ops together; maybe that has to happen after in NIR as part of
884 * propagation...? An earlier algebraic pass ensured we step down by
885 * only / exactly one size. If stepping down, we use a dest override to
886 * reduce the size; if stepping up, we use a larger-sized move with a
887 * half source and a sign/zero-extension modifier */
892 /* If we end up upscale, we'll need a sign-extend on the
893 * operand (the second argument) */
899 op
= midgard_alu_op_imov
;
901 if (dst_bitsize
== (src_bitsize
* 2)) {
905 /* Use a greater register mode */
907 } else if (src_bitsize
== (dst_bitsize
* 2)) {
908 /* Converting down */
909 dest_override
= midgard_dest_override_lower
;
916 assert(src_bitsize
== 32);
918 op
= midgard_alu_op_fmov
;
919 dest_override
= midgard_dest_override_lower
;
924 assert(src_bitsize
== 16);
926 op
= midgard_alu_op_fmov
;
933 /* For greater-or-equal, we lower to less-or-equal and flip the
941 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
942 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
943 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
944 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
947 /* Swap via temporary */
948 nir_alu_src temp
= instr
->src
[1];
949 instr
->src
[1] = instr
->src
[0];
950 instr
->src
[0] = temp
;
955 case nir_op_b32csel
: {
956 /* Midgard features both fcsel and icsel, depending on
957 * the type of the arguments/output. However, as long
958 * as we're careful we can _always_ use icsel and
959 * _never_ need fcsel, since the latter does additional
960 * floating-point-specific processing whereas the
961 * former just moves bits on the wire. It's not obvious
962 * why these are separate opcodes, save for the ability
963 * to do things like sat/pos/abs/neg for free */
965 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
966 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
968 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
971 /* Emit the condition into r31 */
974 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
976 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
978 /* The condition is the first argument; move the other
979 * arguments up one to be a binary instruction for
982 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
987 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
992 /* Midgard can perform certain modifiers on output of an ALU op */
995 if (midgard_is_integer_out_op(op
)) {
996 outmod
= midgard_outmod_int_wrap
;
998 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
999 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
1002 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1004 if (instr
->op
== nir_op_fmax
) {
1005 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1006 op
= midgard_alu_op_fmov
;
1008 outmod
= midgard_outmod_pos
;
1009 instr
->src
[0] = instr
->src
[1];
1010 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1011 op
= midgard_alu_op_fmov
;
1013 outmod
= midgard_outmod_pos
;
1017 /* Fetch unit, quirks, etc information */
1018 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1019 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1021 /* src0 will always exist afaik, but src1 will not for 1-argument
1022 * instructions. The latter can only be fetched if the instruction
1023 * needs it, or else we may segfault. */
1025 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1026 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1028 /* Rather than use the instruction generation helpers, we do it
1029 * ourselves here to avoid the mess */
1031 midgard_instruction ins
= {
1034 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1035 .src1
= quirk_flipped_r24
? src0
: src1
,
1040 nir_alu_src
*nirmods
[2] = { NULL
};
1042 if (nr_inputs
== 2) {
1043 nirmods
[0] = &instr
->src
[0];
1044 nirmods
[1] = &instr
->src
[1];
1045 } else if (nr_inputs
== 1) {
1046 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1051 /* These were lowered to a move, so apply the corresponding mod */
1053 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1054 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1056 if (instr
->op
== nir_op_fneg
)
1057 s
->negate
= !s
->negate
;
1059 if (instr
->op
== nir_op_fabs
)
1063 bool is_int
= midgard_is_integer_op(op
);
1065 ins
.mask
= mask_of(nr_components
);
1067 midgard_vector_alu alu
= {
1069 .reg_mode
= reg_mode
,
1070 .dest_override
= dest_override
,
1073 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1074 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1077 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1080 ins
.mask
&= instr
->dest
.write_mask
;
1084 /* Late fixup for emulated instructions */
1086 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1087 /* Presently, our second argument is an inline #0 constant.
1088 * Switch over to an embedded 1.0 constant (that can't fit
1089 * inline, since we're 32-bit, not 16-bit like the inline
1092 ins
.ssa_args
.inline_constant
= false;
1093 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1094 ins
.has_constants
= true;
1096 if (instr
->op
== nir_op_b2f32
) {
1097 ins
.constants
[0] = 1.0f
;
1099 /* Type pun it into place */
1101 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1104 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1105 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1106 /* Lots of instructions need a 0 plonked in */
1107 ins
.ssa_args
.inline_constant
= false;
1108 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1109 ins
.has_constants
= true;
1110 ins
.constants
[0] = 0.0f
;
1111 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1112 } else if (instr
->op
== nir_op_inot
) {
1113 /* ~b = ~(b & b), so duplicate the source */
1114 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1115 ins
.alu
.src2
= ins
.alu
.src1
;
1118 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1119 /* To avoid duplicating the lookup tables (probably), true LUT
1120 * instructions can only operate as if they were scalars. Lower
1121 * them here by changing the component. */
1123 uint8_t original_swizzle
[4];
1124 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1125 unsigned orig_mask
= ins
.mask
;
1127 for (int i
= 0; i
< nr_components
; ++i
) {
1128 /* Mask the associated component, dropping the
1129 * instruction if needed */
1132 ins
.mask
&= orig_mask
;
1137 for (int j
= 0; j
< 4; ++j
)
1138 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1140 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1141 emit_mir_instruction(ctx
, ins
);
1144 emit_mir_instruction(ctx
, ins
);
1150 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1151 * optimized) versions of UBO #0 */
1155 compiler_context
*ctx
,
1158 nir_src
*indirect_offset
,
1161 /* TODO: half-floats */
1163 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
&& index
== 0) {
1164 /* Fast path: For the first 16 uniforms, direct accesses are
1165 * 0-cycle, since they're just a register fetch in the usual
1166 * case. So, we alias the registers while we're still in
1169 int reg_slot
= 23 - offset
;
1170 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1172 /* Otherwise, read from the 'special' UBO to access
1173 * higher-indexed uniforms, at a performance cost. More
1174 * generally, we're emitting a UBO read instruction. */
1176 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1178 /* TODO: Don't split */
1179 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1180 ins
.load_store
.address
= offset
>> 3;
1182 if (indirect_offset
) {
1183 emit_indirect_offset(ctx
, indirect_offset
);
1184 ins
.load_store
.unknown
= 0x8700 | index
; /* xxx: what is this? */
1186 ins
.load_store
.unknown
= 0x1E00 | index
; /* xxx: what is this? */
1189 /* TODO respect index */
1191 emit_mir_instruction(ctx
, ins
);
1197 compiler_context
*ctx
,
1198 unsigned dest
, unsigned offset
,
1199 unsigned nr_comp
, unsigned component
,
1200 nir_src
*indirect_offset
, nir_alu_type type
)
1202 /* XXX: Half-floats? */
1203 /* TODO: swizzle, mask */
1205 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1206 ins
.mask
= mask_of(nr_comp
);
1207 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1209 midgard_varying_parameter p
= {
1211 .interpolation
= midgard_interp_default
,
1212 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1216 memcpy(&u
, &p
, sizeof(p
));
1217 ins
.load_store
.varying_parameters
= u
;
1219 if (indirect_offset
) {
1220 /* We need to add in the dynamic index, moved to r27.w */
1221 emit_indirect_offset(ctx
, indirect_offset
);
1222 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1224 /* Just a direct load */
1225 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1228 /* Use the type appropriate load */
1232 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1235 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1237 case nir_type_float
:
1238 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1241 unreachable("Attempted to load unknown type");
1245 emit_mir_instruction(ctx
, ins
);
1249 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1252 /* Figure out which uniform this is */
1253 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1254 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1256 /* Sysvals are prefix uniforms */
1257 unsigned uniform
= ((uintptr_t) val
) - 1;
1259 /* Emit the read itself -- this is never indirect */
1260 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1264 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1266 unsigned offset
= 0, reg
;
1268 switch (instr
->intrinsic
) {
1269 case nir_intrinsic_discard_if
:
1270 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1274 case nir_intrinsic_discard
: {
1275 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1276 struct midgard_instruction discard
= v_branch(conditional
, false);
1277 discard
.branch
.target_type
= TARGET_DISCARD
;
1278 emit_mir_instruction(ctx
, discard
);
1280 ctx
->can_discard
= true;
1284 case nir_intrinsic_load_uniform
:
1285 case nir_intrinsic_load_ubo
:
1286 case nir_intrinsic_load_input
: {
1287 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1288 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1290 /* Get the base type of the intrinsic */
1291 /* TODO: Infer type? Does it matter? */
1293 is_ubo
? nir_type_uint
: nir_intrinsic_type(instr
);
1294 t
= nir_alu_type_get_base_type(t
);
1297 offset
= nir_intrinsic_base(instr
);
1300 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1302 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1304 bool direct
= nir_src_is_const(*src_offset
);
1307 offset
+= nir_src_as_uint(*src_offset
);
1309 /* We may need to apply a fractional offset */
1310 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1311 nir_intrinsic_component(instr
) : 0;
1312 reg
= nir_dest_index(ctx
, &instr
->dest
);
1314 if (is_uniform
&& !ctx
->is_blend
) {
1315 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1316 } else if (is_ubo
) {
1317 nir_src index
= instr
->src
[0];
1319 /* We don't yet support indirect UBOs. For indirect
1320 * block numbers (if that's possible), we don't know
1321 * enough about the hardware yet. For indirect sources,
1322 * we know what we need but we need to add some NIR
1323 * support for lowering correctly with respect to
1326 assert(nir_src_is_const(index
));
1327 assert(nir_src_is_const(*src_offset
));
1329 /* TODO: Alignment */
1330 assert((offset
& 0xF) == 0);
1332 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1333 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1334 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1335 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1336 } else if (ctx
->is_blend
) {
1337 /* For blend shaders, load the input color, which is
1338 * preloaded to r0 */
1340 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1341 emit_mir_instruction(ctx
, move
);
1342 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1343 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1344 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1345 ins
.mask
= mask_of(nr_comp
);
1347 /* Use the type appropriate load */
1351 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1354 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1356 case nir_type_float
:
1357 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1360 unreachable("Attempted to load unknown type");
1364 emit_mir_instruction(ctx
, ins
);
1366 DBG("Unknown load\n");
1373 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1375 case nir_intrinsic_load_raw_output_pan
:
1376 reg
= nir_dest_index(ctx
, &instr
->dest
);
1377 assert(ctx
->is_blend
);
1379 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1380 emit_mir_instruction(ctx
, ins
);
1383 case nir_intrinsic_load_blend_const_color_rgba
: {
1384 assert(ctx
->is_blend
);
1385 reg
= nir_dest_index(ctx
, &instr
->dest
);
1387 /* Blend constants are embedded directly in the shader and
1388 * patched in, so we use some magic routing */
1390 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1391 ins
.has_constants
= true;
1392 ins
.has_blend_constant
= true;
1393 emit_mir_instruction(ctx
, ins
);
1397 case nir_intrinsic_store_output
:
1398 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1400 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1402 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1404 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1405 /* gl_FragColor is not emitted with load/store
1406 * instructions. Instead, it gets plonked into
1407 * r0 at the end of the shader and we do the
1408 * framebuffer writeout dance. TODO: Defer
1411 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1412 emit_mir_instruction(ctx
, move
);
1414 /* Save the index we're writing to for later reference
1415 * in the epilogue */
1417 ctx
->fragment_output
= reg
;
1418 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1419 /* Varyings are written into one of two special
1420 * varying register, r26 or r27. The register itself is
1421 * selected as the register in the st_vary instruction,
1422 * minus the base of 26. E.g. write into r27 and then
1423 * call st_vary(1) */
1425 midgard_instruction ins
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1426 emit_mir_instruction(ctx
, ins
);
1428 /* We should have been vectorized, though we don't
1429 * currently check that st_vary is emitted only once
1430 * per slot (this is relevant, since there's not a mask
1431 * parameter available on the store [set to 0 by the
1432 * blob]). We do respect the component by adjusting the
1435 unsigned component
= nir_intrinsic_component(instr
);
1437 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1438 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1439 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1440 emit_mir_instruction(ctx
, st
);
1442 DBG("Unknown store\n");
1448 /* Special case of store_output for lowered blend shaders */
1449 case nir_intrinsic_store_raw_output_pan
:
1450 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1451 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1453 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1454 emit_mir_instruction(ctx
, move
);
1455 ctx
->fragment_output
= reg
;
1459 case nir_intrinsic_load_alpha_ref_float
:
1460 assert(instr
->dest
.is_ssa
);
1462 float ref_value
= ctx
->alpha_ref
;
1464 float *v
= ralloc_array(NULL
, float, 4);
1465 memcpy(v
, &ref_value
, sizeof(float));
1466 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1469 case nir_intrinsic_load_viewport_scale
:
1470 case nir_intrinsic_load_viewport_offset
:
1471 emit_sysval_read(ctx
, &instr
->instr
);
1475 printf ("Unhandled intrinsic\n");
1482 midgard_tex_format(enum glsl_sampler_dim dim
)
1485 case GLSL_SAMPLER_DIM_1D
:
1486 case GLSL_SAMPLER_DIM_BUF
:
1489 case GLSL_SAMPLER_DIM_2D
:
1490 case GLSL_SAMPLER_DIM_EXTERNAL
:
1493 case GLSL_SAMPLER_DIM_3D
:
1496 case GLSL_SAMPLER_DIM_CUBE
:
1497 return MALI_TEX_CUBE
;
1500 DBG("Unknown sampler dim type\n");
1506 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1510 pan_attach_constant_bias(
1511 compiler_context
*ctx
,
1513 midgard_texture_word
*word
)
1515 /* To attach as constant, it has to *be* constant */
1517 if (!nir_src_is_const(lod
))
1520 float f
= nir_src_as_float(lod
);
1522 /* Break into fixed-point */
1524 float lod_frac
= f
- lod_int
;
1526 /* Carry over negative fractions */
1527 if (lod_frac
< 0.0) {
1533 word
->bias
= float_to_ubyte(lod_frac
);
1534 word
->bias_int
= lod_int
;
1539 static enum mali_sampler_type
1540 midgard_sampler_type(nir_alu_type t
)
1542 switch (nir_alu_type_get_base_type(t
)) {
1543 case nir_type_float
:
1544 return MALI_SAMPLER_FLOAT
;
1546 return MALI_SAMPLER_SIGNED
;
1548 return MALI_SAMPLER_UNSIGNED
;
1550 unreachable("Unknown sampler type");
1555 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1556 unsigned midgard_texop
)
1559 //assert (!instr->sampler);
1560 //assert (!instr->texture_array_size);
1562 /* Allocate registers via a round robin scheme to alternate between the two registers */
1563 int reg
= ctx
->texture_op_count
& 1;
1564 int in_reg
= reg
, out_reg
= reg
;
1566 /* Make room for the reg */
1568 if (ctx
->texture_index
[reg
] > -1)
1569 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1571 int texture_index
= instr
->texture_index
;
1572 int sampler_index
= texture_index
;
1574 /* No helper to build texture words -- we do it all here */
1575 midgard_instruction ins
= {
1576 .type
= TAG_TEXTURE_4
,
1579 .op
= midgard_texop
,
1580 .format
= midgard_tex_format(instr
->sampler_dim
),
1581 .texture_handle
= texture_index
,
1582 .sampler_handle
= sampler_index
,
1584 /* TODO: Regalloc it in */
1585 .swizzle
= SWIZZLE_XYZW
,
1591 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1595 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1596 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1597 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1598 int nr_comp
= nir_src_num_components(instr
->src
[i
].src
);
1599 midgard_vector_alu_src alu_src
= blank_alu_src
;
1601 switch (instr
->src
[i
].src_type
) {
1602 case nir_tex_src_coord
: {
1603 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1604 /* texelFetch is undefined on samplerCube */
1605 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1607 /* For cubemaps, we need to load coords into
1608 * special r27, and then use a special ld/st op
1609 * to select the face and copy the xy into the
1610 * texture register */
1612 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1614 midgard_instruction move
= v_mov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1615 emit_mir_instruction(ctx
, move
);
1617 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1618 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1619 st
.mask
= 0x3; /* xy */
1620 st
.load_store
.swizzle
= alu_src
.swizzle
;
1621 emit_mir_instruction(ctx
, st
);
1623 ins
.texture
.in_reg_swizzle
= swizzle_of(2);
1625 ins
.texture
.in_reg_swizzle
= alu_src
.swizzle
= swizzle_of(nr_comp
);
1627 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1628 mov
.mask
= mask_of(nr_comp
);
1629 emit_mir_instruction(ctx
, mov
);
1631 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1632 /* Texel fetch opcodes care about the
1633 * values of z and w, so we actually
1634 * need to spill into a second register
1635 * for a texel fetch with register bias
1636 * (for non-2D). TODO: Implement that
1639 assert(instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
);
1641 midgard_instruction zero
= v_mov(index
, alu_src
, reg
);
1642 zero
.ssa_args
.inline_constant
= true;
1643 zero
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1644 zero
.has_constants
= true;
1645 zero
.mask
= ~mov
.mask
;
1646 emit_mir_instruction(ctx
, zero
);
1648 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1650 /* Non-texel fetch doesn't need that
1651 * nonsense. However we do use the Z
1652 * for array indexing */
1653 bool is_3d
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
;
1654 ins
.texture
.in_reg_swizzle
= is_3d
? SWIZZLE_XYZZ
: SWIZZLE_XYXZ
;
1661 case nir_tex_src_bias
:
1662 case nir_tex_src_lod
: {
1663 /* Try as a constant if we can */
1665 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1666 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1669 /* Otherwise we use a register. To keep RA simple, we
1670 * put the bias/LOD into the w component of the input
1671 * source, which is otherwise in xy */
1673 alu_src
.swizzle
= SWIZZLE_XXXX
;
1675 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1676 mov
.mask
= 1 << COMPONENT_W
;
1677 emit_mir_instruction(ctx
, mov
);
1679 ins
.texture
.lod_register
= true;
1681 midgard_tex_register_select sel
= {
1691 memcpy(&packed
, &sel
, sizeof(packed
));
1692 ins
.texture
.bias
= packed
;
1698 unreachable("Unknown texture source type\n");
1702 /* Set registers to read and write from the same place */
1703 ins
.texture
.in_reg_select
= in_reg
;
1704 ins
.texture
.out_reg_select
= out_reg
;
1706 emit_mir_instruction(ctx
, ins
);
1708 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1709 midgard_instruction ins2
= v_mov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1710 emit_mir_instruction(ctx
, ins2
);
1712 /* Used for .cont and .last hinting */
1713 ctx
->texture_op_count
++;
1717 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1719 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1720 * generic tex in some cases (which confuses the hardware) */
1722 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1724 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1725 instr
->op
= nir_texop_txl
;
1727 switch (instr
->op
) {
1730 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1733 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1736 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1739 emit_sysval_read(ctx
, &instr
->instr
);
1742 unreachable("Unhanlded texture op");
1747 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1749 switch (instr
->type
) {
1750 case nir_jump_break
: {
1751 /* Emit a branch out of the loop */
1752 struct midgard_instruction br
= v_branch(false, false);
1753 br
.branch
.target_type
= TARGET_BREAK
;
1754 br
.branch
.target_break
= ctx
->current_loop_depth
;
1755 emit_mir_instruction(ctx
, br
);
1762 DBG("Unknown jump type %d\n", instr
->type
);
1768 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1770 switch (instr
->type
) {
1771 case nir_instr_type_load_const
:
1772 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1775 case nir_instr_type_intrinsic
:
1776 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1779 case nir_instr_type_alu
:
1780 emit_alu(ctx
, nir_instr_as_alu(instr
));
1783 case nir_instr_type_tex
:
1784 emit_tex(ctx
, nir_instr_as_tex(instr
));
1787 case nir_instr_type_jump
:
1788 emit_jump(ctx
, nir_instr_as_jump(instr
));
1791 case nir_instr_type_ssa_undef
:
1796 DBG("Unhandled instruction type\n");
1802 /* ALU instructions can inline or embed constants, which decreases register
1803 * pressure and saves space. */
1805 #define CONDITIONAL_ATTACH(src) { \
1806 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1809 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1810 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1815 inline_alu_constants(compiler_context
*ctx
)
1817 mir_foreach_instr(ctx
, alu
) {
1818 /* Other instructions cannot inline constants */
1819 if (alu
->type
!= TAG_ALU_4
) continue;
1821 /* If there is already a constant here, we can do nothing */
1822 if (alu
->has_constants
) continue;
1824 /* It makes no sense to inline constants on a branch */
1825 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1827 CONDITIONAL_ATTACH(src0
);
1829 if (!alu
->has_constants
) {
1830 CONDITIONAL_ATTACH(src1
)
1831 } else if (!alu
->inline_constant
) {
1832 /* Corner case: _two_ vec4 constants, for instance with a
1833 * csel. For this case, we can only use a constant
1834 * register for one, we'll have to emit a move for the
1835 * other. Note, if both arguments are constants, then
1836 * necessarily neither argument depends on the value of
1837 * any particular register. As the destination register
1838 * will be wiped, that means we can spill the constant
1839 * to the destination register.
1842 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1843 unsigned scratch
= alu
->ssa_args
.dest
;
1846 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1847 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1849 /* Force a break XXX Defer r31 writes */
1850 ins
.unit
= UNIT_VLUT
;
1852 /* Set the source */
1853 alu
->ssa_args
.src1
= scratch
;
1855 /* Inject us -before- the last instruction which set r31 */
1856 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1862 /* Midgard supports two types of constants, embedded constants (128-bit) and
1863 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1864 * constants can be demoted to inline constants, for space savings and
1865 * sometimes a performance boost */
1868 embedded_to_inline_constant(compiler_context
*ctx
)
1870 mir_foreach_instr(ctx
, ins
) {
1871 if (!ins
->has_constants
) continue;
1873 if (ins
->ssa_args
.inline_constant
) continue;
1875 /* Blend constants must not be inlined by definition */
1876 if (ins
->has_blend_constant
) continue;
1878 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1879 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
1880 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
1882 if (!(is_16
|| is_32
))
1885 /* src1 cannot be an inline constant due to encoding
1886 * restrictions. So, if possible we try to flip the arguments
1889 int op
= ins
->alu
.op
;
1891 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1893 /* These ops require an operational change to flip
1894 * their arguments TODO */
1895 case midgard_alu_op_flt
:
1896 case midgard_alu_op_fle
:
1897 case midgard_alu_op_ilt
:
1898 case midgard_alu_op_ile
:
1899 case midgard_alu_op_fcsel
:
1900 case midgard_alu_op_icsel
:
1901 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1906 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1907 /* Flip the SSA numbers */
1908 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1909 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1911 /* And flip the modifiers */
1915 src_temp
= ins
->alu
.src2
;
1916 ins
->alu
.src2
= ins
->alu
.src1
;
1917 ins
->alu
.src1
= src_temp
;
1921 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1922 /* Extract the source information */
1924 midgard_vector_alu_src
*src
;
1925 int q
= ins
->alu
.src2
;
1926 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1929 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1930 int component
= src
->swizzle
& 3;
1932 /* Scale constant appropriately, if we can legally */
1933 uint16_t scaled_constant
= 0;
1935 if (midgard_is_integer_op(op
) || is_16
) {
1936 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1937 scaled_constant
= (uint16_t) iconstants
[component
];
1939 /* Constant overflow after resize */
1940 if (scaled_constant
!= iconstants
[component
])
1943 float original
= (float) ins
->constants
[component
];
1944 scaled_constant
= _mesa_float_to_half(original
);
1946 /* Check for loss of precision. If this is
1947 * mediump, we don't care, but for a highp
1948 * shader, we need to pay attention. NIR
1949 * doesn't yet tell us which mode we're in!
1950 * Practically this prevents most constants
1951 * from being inlined, sadly. */
1953 float fp32
= _mesa_half_to_float(scaled_constant
);
1955 if (fp32
!= original
)
1959 /* We don't know how to handle these with a constant */
1961 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
1962 DBG("Bailing inline constant...\n");
1966 /* Make sure that the constant is not itself a
1967 * vector by checking if all accessed values
1968 * (by the swizzle) are the same. */
1970 uint32_t *cons
= (uint32_t *) ins
->constants
;
1971 uint32_t value
= cons
[component
];
1973 bool is_vector
= false;
1974 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
1976 for (int c
= 1; c
< 4; ++c
) {
1977 /* We only care if this component is actually used */
1978 if (!(mask
& (1 << c
)))
1981 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1983 if (test
!= value
) {
1992 /* Get rid of the embedded constant */
1993 ins
->has_constants
= false;
1994 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1995 ins
->ssa_args
.inline_constant
= true;
1996 ins
->inline_constant
= scaled_constant
;
2001 /* Map normal SSA sources to other SSA sources / fixed registers (like
2005 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2007 /* Sign is used quite deliberately for unused */
2011 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2014 /* Remove entry in leftovers to avoid a redunant fmov */
2016 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2019 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2021 /* Assign the alias map */
2027 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
2028 * texture pipeline */
2031 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
2033 bool progress
= false;
2035 mir_foreach_instr_in_block_safe(block
, ins
) {
2036 if (ins
->type
!= TAG_ALU_4
) continue;
2037 if (ins
->compact_branch
) continue;
2039 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2040 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2042 mir_remove_instruction(ins
);
2049 /* Dead code elimination for branches at the end of a block - only one branch
2050 * per block is legal semantically */
2053 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2055 bool branched
= false;
2057 mir_foreach_instr_in_block_safe(block
, ins
) {
2058 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2060 /* We ignore prepacked branches since the fragment epilogue is
2061 * just generally special */
2062 if (ins
->prepacked_branch
) continue;
2064 /* Discards are similarly special and may not correspond to the
2067 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
2070 /* We already branched, so this is dead */
2071 mir_remove_instruction(ins
);
2079 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
2082 if (!is_int
&& src
.mod
) return true;
2084 /* Other int mods don't matter in isolation */
2085 if (is_int
&& src
.mod
== midgard_int_shift
) return true;
2087 /* size-conversion */
2088 if (src
.half
) return true;
2091 for (unsigned c
= 0; c
< 4; ++c
) {
2092 if (!(mask
& (1 << c
))) continue;
2093 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
2100 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
2102 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2104 midgard_vector_alu_src src2
=
2105 vector_alu_from_unsigned(ins
->alu
.src2
);
2107 return mir_nontrivial_mod(src2
, is_int
, ins
->mask
);
2111 mir_nontrivial_outmod(midgard_instruction
*ins
)
2113 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2114 unsigned mod
= ins
->alu
.outmod
;
2116 /* Type conversion is a sort of outmod */
2117 if (ins
->alu
.dest_override
!= midgard_dest_override_none
)
2121 return mod
!= midgard_outmod_int_wrap
;
2123 return mod
!= midgard_outmod_none
;
2127 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
2129 bool progress
= false;
2131 mir_foreach_instr_in_block_safe(block
, ins
) {
2132 if (ins
->type
!= TAG_ALU_4
) continue;
2133 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2135 unsigned from
= ins
->ssa_args
.src1
;
2136 unsigned to
= ins
->ssa_args
.dest
;
2138 /* We only work on pure SSA */
2140 if (to
>= SSA_FIXED_MINIMUM
) continue;
2141 if (from
>= SSA_FIXED_MINIMUM
) continue;
2142 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
2143 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2145 /* Constant propagation is not handled here, either */
2146 if (ins
->ssa_args
.inline_constant
) continue;
2147 if (ins
->has_constants
) continue;
2149 if (mir_nontrivial_source2_mod(ins
)) continue;
2150 if (mir_nontrivial_outmod(ins
)) continue;
2152 /* We're clear -- rewrite */
2153 mir_rewrite_index_src(ctx
, to
, from
);
2154 mir_remove_instruction(ins
);
2161 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2162 * the move can be propagated away entirely */
2165 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2168 if (comp
== midgard_outmod_none
)
2171 if (*outmod
== midgard_outmod_none
) {
2176 /* TODO: Compose rules */
2181 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2183 bool progress
= false;
2185 mir_foreach_instr_in_block_safe(block
, ins
) {
2186 if (ins
->type
!= TAG_ALU_4
) continue;
2187 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2188 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2190 /* TODO: Registers? */
2191 unsigned src
= ins
->ssa_args
.src1
;
2192 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
2193 assert(!mir_has_multiple_writes(ctx
, src
));
2195 /* There might be a source modifier, too */
2196 if (mir_nontrivial_source2_mod(ins
)) continue;
2198 /* Backpropagate the modifier */
2199 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2200 if (v
->type
!= TAG_ALU_4
) continue;
2201 if (v
->ssa_args
.dest
!= src
) continue;
2203 /* Can we even take a float outmod? */
2204 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2206 midgard_outmod_float temp
= v
->alu
.outmod
;
2207 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2209 /* Throw in the towel.. */
2210 if (!progress
) break;
2212 /* Otherwise, transfer the modifier */
2213 v
->alu
.outmod
= temp
;
2214 ins
->alu
.outmod
= midgard_outmod_none
;
2223 /* The following passes reorder MIR instructions to enable better scheduling */
2226 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2228 mir_foreach_instr_in_block_safe(block
, ins
) {
2229 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2231 /* We've found a load/store op. Check if next is also load/store. */
2232 midgard_instruction
*next_op
= mir_next_op(ins
);
2233 if (&next_op
->link
!= &block
->instructions
) {
2234 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2235 /* If so, we're done since we're a pair */
2236 ins
= mir_next_op(ins
);
2240 /* Maximum search distance to pair, to avoid register pressure disasters */
2241 int search_distance
= 8;
2243 /* Otherwise, we have an orphaned load/store -- search for another load */
2244 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2245 /* Terminate search if necessary */
2246 if (!(search_distance
--)) break;
2248 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2250 /* Stores cannot be reordered, since they have
2251 * dependencies. For the same reason, indirect
2252 * loads cannot be reordered as their index is
2253 * loaded in r27.w */
2255 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2257 /* It appears the 0x800 bit is set whenever a
2258 * load is direct, unset when it is indirect.
2259 * Skip indirect loads. */
2261 if (!(c
->load_store
.unknown
& 0x800)) continue;
2263 /* We found one! Move it up to pair and remove it from the old location */
2265 mir_insert_instruction_before(ins
, *c
);
2266 mir_remove_instruction(c
);
2274 /* If there are leftovers after the below pass, emit actual fmov
2275 * instructions for the slow-but-correct path */
2278 emit_leftover_move(compiler_context
*ctx
)
2280 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2281 int base
= ((uintptr_t) leftover
->key
) - 1;
2284 map_ssa_to_alias(ctx
, &mapped
);
2285 EMIT(mov
, mapped
, blank_alu_src
, base
);
2290 actualise_ssa_to_alias(compiler_context
*ctx
)
2292 mir_foreach_instr(ctx
, ins
) {
2293 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2294 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2297 emit_leftover_move(ctx
);
2301 emit_fragment_epilogue(compiler_context
*ctx
)
2303 /* Special case: writing out constants requires us to include the move
2304 * explicitly now, so shove it into r0 */
2306 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2308 if (constant_value
) {
2309 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2310 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2311 emit_mir_instruction(ctx
, ins
);
2314 /* Perform the actual fragment writeout. We have two writeout/branch
2315 * instructions, forming a loop until writeout is successful as per the
2316 * docs. TODO: gl_FragDepth */
2318 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2319 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2322 static midgard_block
*
2323 emit_block(compiler_context
*ctx
, nir_block
*block
)
2325 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2326 list_addtail(&this_block
->link
, &ctx
->blocks
);
2328 this_block
->is_scheduled
= false;
2331 ctx
->texture_index
[0] = -1;
2332 ctx
->texture_index
[1] = -1;
2334 /* Add us as a successor to the block we are following */
2335 if (ctx
->current_block
)
2336 midgard_block_add_successor(ctx
->current_block
, this_block
);
2338 /* Set up current block */
2339 list_inithead(&this_block
->instructions
);
2340 ctx
->current_block
= this_block
;
2342 nir_foreach_instr(instr
, block
) {
2343 emit_instr(ctx
, instr
);
2344 ++ctx
->instruction_count
;
2347 inline_alu_constants(ctx
);
2348 embedded_to_inline_constant(ctx
);
2350 /* Perform heavylifting for aliasing */
2351 actualise_ssa_to_alias(ctx
);
2353 midgard_pair_load_store(ctx
, this_block
);
2355 /* Append fragment shader epilogue (value writeout) */
2356 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2357 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2358 emit_fragment_epilogue(ctx
);
2362 if (block
== nir_start_block(ctx
->func
->impl
))
2363 ctx
->initial_block
= this_block
;
2365 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2366 ctx
->final_block
= this_block
;
2368 /* Allow the next control flow to access us retroactively, for
2370 ctx
->current_block
= this_block
;
2372 /* Document the fallthrough chain */
2373 ctx
->previous_source_block
= this_block
;
2378 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2381 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2383 /* Conditional branches expect the condition in r31.w; emit a move for
2384 * that in the _previous_ block (which is the current block). */
2385 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2387 /* Speculatively emit the branch, but we can't fill it in until later */
2388 EMIT(branch
, true, true);
2389 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2391 /* Emit the two subblocks */
2392 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2394 /* Emit a jump from the end of the then block to the end of the else */
2395 EMIT(branch
, false, false);
2396 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2398 /* Emit second block, and check if it's empty */
2400 int else_idx
= ctx
->block_count
;
2401 int count_in
= ctx
->instruction_count
;
2402 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2403 int after_else_idx
= ctx
->block_count
;
2405 /* Now that we have the subblocks emitted, fix up the branches */
2410 if (ctx
->instruction_count
== count_in
) {
2411 /* The else block is empty, so don't emit an exit jump */
2412 mir_remove_instruction(then_exit
);
2413 then_branch
->branch
.target_block
= after_else_idx
;
2415 then_branch
->branch
.target_block
= else_idx
;
2416 then_exit
->branch
.target_block
= after_else_idx
;
2421 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2423 /* Remember where we are */
2424 midgard_block
*start_block
= ctx
->current_block
;
2426 /* Allocate a loop number, growing the current inner loop depth */
2427 int loop_idx
= ++ctx
->current_loop_depth
;
2429 /* Get index from before the body so we can loop back later */
2430 int start_idx
= ctx
->block_count
;
2432 /* Emit the body itself */
2433 emit_cf_list(ctx
, &nloop
->body
);
2435 /* Branch back to loop back */
2436 struct midgard_instruction br_back
= v_branch(false, false);
2437 br_back
.branch
.target_block
= start_idx
;
2438 emit_mir_instruction(ctx
, br_back
);
2440 /* Mark down that branch in the graph. Note that we're really branching
2441 * to the block *after* we started in. TODO: Why doesn't the branch
2442 * itself have an off-by-one then...? */
2443 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2445 /* Find the index of the block about to follow us (note: we don't add
2446 * one; blocks are 0-indexed so we get a fencepost problem) */
2447 int break_block_idx
= ctx
->block_count
;
2449 /* Fix up the break statements we emitted to point to the right place,
2450 * now that we can allocate a block number for them */
2452 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2453 mir_foreach_instr_in_block(block
, ins
) {
2454 if (ins
->type
!= TAG_ALU_4
) continue;
2455 if (!ins
->compact_branch
) continue;
2456 if (ins
->prepacked_branch
) continue;
2458 /* We found a branch -- check the type to see if we need to do anything */
2459 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2461 /* It's a break! Check if it's our break */
2462 if (ins
->branch
.target_break
!= loop_idx
) continue;
2464 /* Okay, cool, we're breaking out of this loop.
2465 * Rewrite from a break to a goto */
2467 ins
->branch
.target_type
= TARGET_GOTO
;
2468 ins
->branch
.target_block
= break_block_idx
;
2472 /* Now that we've finished emitting the loop, free up the depth again
2473 * so we play nice with recursion amid nested loops */
2474 --ctx
->current_loop_depth
;
2477 static midgard_block
*
2478 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2480 midgard_block
*start_block
= NULL
;
2482 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2483 switch (node
->type
) {
2484 case nir_cf_node_block
: {
2485 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2488 start_block
= block
;
2493 case nir_cf_node_if
:
2494 emit_if(ctx
, nir_cf_node_as_if(node
));
2497 case nir_cf_node_loop
:
2498 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2501 case nir_cf_node_function
:
2510 /* Due to lookahead, we need to report the first tag executed in the command
2511 * stream and in branch targets. An initial block might be empty, so iterate
2512 * until we find one that 'works' */
2515 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2517 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2519 unsigned first_tag
= 0;
2522 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2524 if (initial_bundle
) {
2525 first_tag
= initial_bundle
->tag
;
2529 /* Initial block is empty, try the next block */
2530 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2531 } while(initial_block
!= NULL
);
2538 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2540 struct util_dynarray
*compiled
= &program
->compiled
;
2542 midgard_debug
= debug_get_option_midgard_debug();
2544 compiler_context ictx
= {
2546 .stage
= nir
->info
.stage
,
2548 .is_blend
= is_blend
,
2549 .blend_constant_offset
= 0,
2551 .alpha_ref
= program
->alpha_ref
2554 compiler_context
*ctx
= &ictx
;
2556 /* TODO: Decide this at runtime */
2557 ctx
->uniform_cutoff
= 8;
2559 /* Initialize at a global (not block) level hash tables */
2561 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2562 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
2563 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2564 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2565 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
2567 /* Record the varying mapping for the command stream's bookkeeping */
2569 struct exec_list
*varyings
=
2570 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2572 unsigned max_varying
= 0;
2573 nir_foreach_variable(var
, varyings
) {
2574 unsigned loc
= var
->data
.driver_location
;
2575 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2577 for (int c
= 0; c
< sz
; ++c
) {
2578 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2579 max_varying
= MAX2(max_varying
, loc
+ c
);
2583 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2584 * (so we don't accidentally duplicate the epilogue since mesa/st has
2585 * messed with our I/O quite a bit already) */
2587 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2589 if (ctx
->stage
== MESA_SHADER_VERTEX
)
2590 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2592 NIR_PASS_V(nir
, nir_lower_var_copies
);
2593 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2594 NIR_PASS_V(nir
, nir_split_var_copies
);
2595 NIR_PASS_V(nir
, nir_lower_var_copies
);
2596 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2597 NIR_PASS_V(nir
, nir_lower_var_copies
);
2598 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2600 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2602 /* Optimisation passes */
2606 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2607 nir_print_shader(nir
, stdout
);
2610 /* Assign sysvals and counts, now that we're sure
2611 * (post-optimisation) */
2613 midgard_nir_assign_sysvals(ctx
, nir
);
2615 program
->uniform_count
= nir
->num_uniforms
;
2616 program
->sysval_count
= ctx
->sysval_count
;
2617 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2619 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
2620 program
->varying_count
= max_varying
+ 1; /* Fencepost off-by-one */
2622 nir_foreach_function(func
, nir
) {
2626 list_inithead(&ctx
->blocks
);
2627 ctx
->block_count
= 0;
2630 emit_cf_list(ctx
, &func
->impl
->body
);
2631 emit_block(ctx
, func
->impl
->end_block
);
2633 break; /* TODO: Multi-function shaders */
2636 util_dynarray_init(compiled
, NULL
);
2638 /* MIR-level optimizations */
2640 bool progress
= false;
2645 mir_foreach_block(ctx
, block
) {
2646 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2647 progress
|= midgard_opt_copy_prop(ctx
, block
);
2648 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2652 /* Nested control-flow can result in dead branches at the end of the
2653 * block. This messes with our analysis and is just dead code, so cull
2655 mir_foreach_block(ctx
, block
) {
2656 midgard_opt_cull_dead_branch(ctx
, block
);
2660 schedule_program(ctx
);
2662 /* Now that all the bundles are scheduled and we can calculate block
2663 * sizes, emit actual branch instructions rather than placeholders */
2665 int br_block_idx
= 0;
2667 mir_foreach_block(ctx
, block
) {
2668 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2669 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2670 midgard_instruction
*ins
= bundle
->instructions
[c
];
2672 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2674 if (ins
->prepacked_branch
) continue;
2676 /* Parse some basic branch info */
2677 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2678 bool is_conditional
= ins
->branch
.conditional
;
2679 bool is_inverted
= ins
->branch
.invert_conditional
;
2680 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2682 /* Determine the block we're jumping to */
2683 int target_number
= ins
->branch
.target_block
;
2685 /* Report the destination tag */
2686 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2688 /* Count up the number of quadwords we're
2689 * jumping over = number of quadwords until
2690 * (br_block_idx, target_number) */
2692 int quadword_offset
= 0;
2695 /* Jump to the end of the shader. We
2696 * need to include not only the
2697 * following blocks, but also the
2698 * contents of our current block (since
2699 * discard can come in the middle of
2702 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2704 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2705 quadword_offset
+= quadword_size(bun
->tag
);
2708 mir_foreach_block_from(ctx
, blk
, b
) {
2709 quadword_offset
+= b
->quadword_count
;
2712 } else if (target_number
> br_block_idx
) {
2715 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2716 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2719 quadword_offset
+= blk
->quadword_count
;
2722 /* Jump backwards */
2724 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2725 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2728 quadword_offset
-= blk
->quadword_count
;
2732 /* Unconditional extended branches (far jumps)
2733 * have issues, so we always use a conditional
2734 * branch, setting the condition to always for
2735 * unconditional. For compact unconditional
2736 * branches, cond isn't used so it doesn't
2737 * matter what we pick. */
2739 midgard_condition cond
=
2740 !is_conditional
? midgard_condition_always
:
2741 is_inverted
? midgard_condition_false
:
2742 midgard_condition_true
;
2744 midgard_jmp_writeout_op op
=
2745 is_discard
? midgard_jmp_writeout_op_discard
:
2746 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2747 midgard_jmp_writeout_op_branch_cond
;
2750 midgard_branch_extended branch
=
2751 midgard_create_branch_extended(
2756 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2757 } else if (is_conditional
|| is_discard
) {
2758 midgard_branch_cond branch
= {
2760 .dest_tag
= dest_tag
,
2761 .offset
= quadword_offset
,
2765 assert(branch
.offset
== quadword_offset
);
2767 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2769 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2771 midgard_branch_uncond branch
= {
2773 .dest_tag
= dest_tag
,
2774 .offset
= quadword_offset
,
2778 assert(branch
.offset
== quadword_offset
);
2780 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2788 /* Emit flat binary from the instruction arrays. Iterate each block in
2789 * sequence. Save instruction boundaries such that lookahead tags can
2790 * be assigned easily */
2792 /* Cache _all_ bundles in source order for lookahead across failed branches */
2794 int bundle_count
= 0;
2795 mir_foreach_block(ctx
, block
) {
2796 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2798 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2800 mir_foreach_block(ctx
, block
) {
2801 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2802 source_order_bundles
[bundle_idx
++] = bundle
;
2806 int current_bundle
= 0;
2808 /* Midgard prefetches instruction types, so during emission we
2809 * need to lookahead. Unless this is the last instruction, in
2810 * which we return 1. Or if this is the second to last and the
2811 * last is an ALU, then it's also 1... */
2813 mir_foreach_block(ctx
, block
) {
2814 mir_foreach_bundle_in_block(block
, bundle
) {
2817 if (current_bundle
+ 1 < bundle_count
) {
2818 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2820 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2827 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2831 /* TODO: Free deeper */
2832 //util_dynarray_fini(&block->instructions);
2835 free(source_order_bundles
);
2837 /* Report the very first tag executed */
2838 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2840 /* Deal with off-by-one related to the fencepost problem */
2841 program
->work_register_count
= ctx
->work_registers
+ 1;
2843 program
->can_discard
= ctx
->can_discard
;
2844 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2846 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2848 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2849 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);