2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
51 #include "disassemble.h"
53 static const struct debug_named_value debug_options
[] = {
54 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
61 int midgard_debug
= 0;
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
69 midgard_is_branch_unit(unsigned unit
)
71 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
75 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
77 block
->successors
[block
->nr_successors
++] = successor
;
78 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
86 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
87 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
88 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
90 #define M_LOAD_STORE(name, rname, uname) \
91 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
92 midgard_instruction i = { \
93 .type = TAG_LOAD_STORE_4, \
100 .op = midgard_op_##name, \
102 .swizzle = SWIZZLE_XYZW, \
110 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
111 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
113 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
114 * the corresponding Midgard source */
116 static midgard_vector_alu_src
117 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
119 if (!src
) return blank_alu_src
;
121 midgard_vector_alu_src alu_src
= {
124 .half
= 0, /* TODO */
125 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
129 /* TODO: sign-extend/zero-extend */
130 alu_src
.mod
= midgard_int_normal
;
132 /* These should have been lowered away */
133 assert(!(src
->abs
|| src
->negate
));
135 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
141 /* load/store instructions have both 32-bit and 16-bit variants, depending on
142 * whether we are using vectors composed of highp or mediump. At the moment, we
143 * don't support half-floats -- this requires changes in other parts of the
144 * compiler -- therefore the 16-bit versions are commented out. */
146 //M_LOAD(ld_attr_16);
148 //M_LOAD(ld_vary_16);
150 //M_LOAD(ld_uniform_16);
151 M_LOAD(ld_uniform_32
);
152 M_LOAD(ld_color_buffer_8
);
153 //M_STORE(st_vary_16);
155 M_STORE(st_cubemap_coords
);
157 static midgard_instruction
158 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
160 midgard_branch_cond branch
= {
168 memcpy(&compact
, &branch
, sizeof(branch
));
170 midgard_instruction ins
= {
172 .unit
= ALU_ENAB_BR_COMPACT
,
173 .prepacked_branch
= true,
174 .compact_branch
= true,
175 .br_compact
= compact
178 if (op
== midgard_jmp_writeout_op_writeout
)
184 static midgard_instruction
185 v_branch(bool conditional
, bool invert
)
187 midgard_instruction ins
= {
189 .unit
= ALU_ENAB_BRANCH
,
190 .compact_branch
= true,
192 .conditional
= conditional
,
193 .invert_conditional
= invert
200 static midgard_branch_extended
201 midgard_create_branch_extended( midgard_condition cond
,
202 midgard_jmp_writeout_op op
,
204 signed quadword_offset
)
206 /* For unclear reasons, the condition code is repeated 8 times */
207 uint16_t duplicated_cond
=
217 midgard_branch_extended branch
= {
219 .dest_tag
= dest_tag
,
220 .offset
= quadword_offset
,
221 .cond
= duplicated_cond
228 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
230 ins
->has_constants
= true;
231 memcpy(&ins
->constants
, constants
, 16);
235 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
237 return glsl_count_attribute_slots(type
, false);
240 /* Lower fdot2 to a vector multiplication followed by channel addition */
242 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
244 if (alu
->op
!= nir_op_fdot2
)
247 b
->cursor
= nir_before_instr(&alu
->instr
);
249 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
250 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
252 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
254 nir_ssa_def
*sum
= nir_fadd(b
,
255 nir_channel(b
, product
, 0),
256 nir_channel(b
, product
, 1));
258 /* Replace the fdot2 with this sum */
259 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
263 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
265 switch (instr
->intrinsic
) {
266 case nir_intrinsic_load_viewport_scale
:
267 return PAN_SYSVAL_VIEWPORT_SCALE
;
268 case nir_intrinsic_load_viewport_offset
:
269 return PAN_SYSVAL_VIEWPORT_OFFSET
;
276 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
280 if (instr
->type
== nir_instr_type_intrinsic
) {
281 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
282 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
288 /* We have a sysval load; check if it's already been assigned */
290 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
293 /* It hasn't -- so assign it now! */
295 unsigned id
= ctx
->sysval_count
++;
296 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
297 ctx
->sysvals
[id
] = sysval
;
301 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
303 ctx
->sysval_count
= 0;
305 nir_foreach_function(function
, shader
) {
306 if (!function
->impl
) continue;
308 nir_foreach_block(block
, function
->impl
) {
309 nir_foreach_instr_safe(instr
, block
) {
310 midgard_nir_assign_sysval_body(ctx
, instr
);
317 midgard_nir_lower_fdot2(nir_shader
*shader
)
319 bool progress
= false;
321 nir_foreach_function(function
, shader
) {
322 if (!function
->impl
) continue;
325 nir_builder
*b
= &_b
;
326 nir_builder_init(b
, function
->impl
);
328 nir_foreach_block(block
, function
->impl
) {
329 nir_foreach_instr_safe(instr
, block
) {
330 if (instr
->type
!= nir_instr_type_alu
) continue;
332 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
333 midgard_nir_lower_fdot2_body(b
, alu
);
339 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
347 optimise_nir(nir_shader
*nir
)
350 unsigned lower_flrp
=
351 (nir
->options
->lower_flrp16
? 16 : 0) |
352 (nir
->options
->lower_flrp32
? 32 : 0) |
353 (nir
->options
->lower_flrp64
? 64 : 0);
355 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
356 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
357 NIR_PASS(progress
, nir
, nir_lower_idiv
);
359 nir_lower_tex_options lower_tex_options
= {
364 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
369 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
370 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
372 NIR_PASS(progress
, nir
, nir_copy_prop
);
373 NIR_PASS(progress
, nir
, nir_opt_dce
);
374 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
375 NIR_PASS(progress
, nir
, nir_opt_cse
);
376 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
377 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
378 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
380 if (lower_flrp
!= 0) {
381 bool lower_flrp_progress
= false;
382 NIR_PASS(lower_flrp_progress
,
386 false /* always_precise */,
387 nir
->options
->lower_ffma
);
388 if (lower_flrp_progress
) {
389 NIR_PASS(progress
, nir
,
390 nir_opt_constant_folding
);
394 /* Nothing should rematerialize any flrps, so we only
395 * need to do this lowering once.
400 NIR_PASS(progress
, nir
, nir_opt_undef
);
401 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
404 nir_var_function_temp
);
406 /* TODO: Enable vectorize when merged upstream */
407 // NIR_PASS(progress, nir, nir_opt_vectorize);
410 /* Must be run at the end to prevent creation of fsin/fcos ops */
411 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
416 NIR_PASS(progress
, nir
, nir_opt_dce
);
417 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
418 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
419 NIR_PASS(progress
, nir
, nir_copy_prop
);
422 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
424 /* We implement booleans as 32-bit 0/~0 */
425 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
427 /* Now that booleans are lowered, we can run out late opts */
428 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
430 /* Lower mods for float ops only. Integer ops don't support modifiers
431 * (saturate doesn't make sense on integers, neg/abs require dedicated
434 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
435 NIR_PASS(progress
, nir
, nir_copy_prop
);
436 NIR_PASS(progress
, nir
, nir_opt_dce
);
438 /* Take us out of SSA */
439 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
440 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
442 /* We are a vector architecture; write combine where possible */
443 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
444 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
446 NIR_PASS(progress
, nir
, nir_opt_dce
);
449 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
450 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
451 * r0. See the comments in compiler_context */
454 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
456 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
457 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
460 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
463 unalias_ssa(compiler_context
*ctx
, int dest
)
465 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
466 /* TODO: Remove from leftover or no? */
469 /* Do not actually emit a load; instead, cache the constant for inlining */
472 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
474 nir_ssa_def def
= instr
->def
;
476 float *v
= rzalloc_array(NULL
, float, 4);
477 nir_const_load_to_arr(v
, instr
, f32
);
478 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
482 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
485 return src
->ssa
->index
;
487 assert(!src
->reg
.indirect
);
488 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
493 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
496 return dst
->ssa
.index
;
498 assert(!dst
->reg
.indirect
);
499 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
504 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
506 return nir_src_index(ctx
, &src
->src
);
510 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
512 unsigned comp
= src
->swizzle
[0];
514 for (unsigned c
= 1; c
< nr_components
; ++c
) {
515 if (src
->swizzle
[c
] != comp
)
522 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
523 * output of a conditional test) into that register */
526 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
528 int condition
= nir_src_index(ctx
, src
);
530 /* Source to swizzle the desired component into w */
532 const midgard_vector_alu_src alu_src
= {
533 .swizzle
= SWIZZLE(component
, component
, component
, component
),
536 /* There is no boolean move instruction. Instead, we simulate a move by
537 * ANDing the condition with itself to get it into r31.w */
539 midgard_instruction ins
= {
542 /* We need to set the conditional as close as possible */
543 .precede_break
= true,
544 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
549 .dest
= SSA_FIXED_REGISTER(31),
553 .op
= midgard_alu_op_iand
,
554 .outmod
= midgard_outmod_int_wrap
,
555 .reg_mode
= midgard_reg_mode_32
,
556 .dest_override
= midgard_dest_override_none
,
557 .mask
= (0x3 << 6), /* w */
558 .src1
= vector_alu_srco_unsigned(alu_src
),
559 .src2
= vector_alu_srco_unsigned(alu_src
)
563 emit_mir_instruction(ctx
, ins
);
566 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
570 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
572 int condition
= nir_src_index(ctx
, &src
->src
);
574 /* Source to swizzle the desired component into w */
576 const midgard_vector_alu_src alu_src
= {
577 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
580 /* There is no boolean move instruction. Instead, we simulate a move by
581 * ANDing the condition with itself to get it into r31.w */
583 midgard_instruction ins
= {
585 .precede_break
= true,
589 .dest
= SSA_FIXED_REGISTER(31),
592 .op
= midgard_alu_op_iand
,
593 .outmod
= midgard_outmod_int_wrap
,
594 .reg_mode
= midgard_reg_mode_32
,
595 .dest_override
= midgard_dest_override_none
,
596 .mask
= expand_writemask((1 << nr_comp
) - 1),
597 .src1
= vector_alu_srco_unsigned(alu_src
),
598 .src2
= vector_alu_srco_unsigned(alu_src
)
602 emit_mir_instruction(ctx
, ins
);
607 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
608 * pinning to eliminate this move in all known cases */
611 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
613 int offset
= nir_src_index(ctx
, src
);
615 midgard_instruction ins
= {
618 .src0
= SSA_UNUSED_1
,
620 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
623 .op
= midgard_alu_op_imov
,
624 .outmod
= midgard_outmod_int_wrap
,
625 .reg_mode
= midgard_reg_mode_32
,
626 .dest_override
= midgard_dest_override_none
,
627 .mask
= (0x3 << 6), /* w */
628 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
629 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
633 emit_mir_instruction(ctx
, ins
);
636 #define ALU_CASE(nir, _op) \
638 op = midgard_alu_op_##_op; \
641 nir_is_fzero_constant(nir_src src
)
643 if (!nir_src_is_const(src
))
646 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
647 if (nir_src_comp_as_float(src
, c
) != 0.0)
655 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
657 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
659 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
660 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
661 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
663 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
664 * supported. A few do not and are commented for now. Also, there are a
665 * number of NIR ops which Midgard does not support and need to be
666 * lowered, also TODO. This switch block emits the opcode and calling
667 * convention of the Midgard instruction; actual packing is done in
673 ALU_CASE(fadd
, fadd
);
674 ALU_CASE(fmul
, fmul
);
675 ALU_CASE(fmin
, fmin
);
676 ALU_CASE(fmax
, fmax
);
677 ALU_CASE(imin
, imin
);
678 ALU_CASE(imax
, imax
);
679 ALU_CASE(umin
, umin
);
680 ALU_CASE(umax
, umax
);
681 ALU_CASE(ffloor
, ffloor
);
682 ALU_CASE(fround_even
, froundeven
);
683 ALU_CASE(ftrunc
, ftrunc
);
684 ALU_CASE(fceil
, fceil
);
685 ALU_CASE(fdot3
, fdot3
);
686 ALU_CASE(fdot4
, fdot4
);
687 ALU_CASE(iadd
, iadd
);
688 ALU_CASE(isub
, isub
);
689 ALU_CASE(imul
, imul
);
691 /* Zero shoved as second-arg */
692 ALU_CASE(iabs
, iabsdiff
);
696 ALU_CASE(feq32
, feq
);
697 ALU_CASE(fne32
, fne
);
698 ALU_CASE(flt32
, flt
);
699 ALU_CASE(ieq32
, ieq
);
700 ALU_CASE(ine32
, ine
);
701 ALU_CASE(ilt32
, ilt
);
702 ALU_CASE(ult32
, ult
);
704 /* We don't have a native b2f32 instruction. Instead, like many
705 * GPUs, we exploit booleans as 0/~0 for false/true, and
706 * correspondingly AND
707 * by 1.0 to do the type conversion. For the moment, prime us
710 * iand [whatever], #0
712 * At the end of emit_alu (as MIR), we'll fix-up the constant
715 ALU_CASE(b2f32
, iand
);
716 ALU_CASE(b2i32
, iand
);
718 /* Likewise, we don't have a dedicated f2b32 instruction, but
719 * we can do a "not equal to 0.0" test. */
721 ALU_CASE(f2b32
, fne
);
722 ALU_CASE(i2b32
, ine
);
724 ALU_CASE(frcp
, frcp
);
725 ALU_CASE(frsq
, frsqrt
);
726 ALU_CASE(fsqrt
, fsqrt
);
727 ALU_CASE(fexp2
, fexp2
);
728 ALU_CASE(flog2
, flog2
);
730 ALU_CASE(f2i32
, f2i
);
731 ALU_CASE(f2u32
, f2u
);
732 ALU_CASE(i2f32
, i2f
);
733 ALU_CASE(u2f32
, u2f
);
735 ALU_CASE(fsin
, fsin
);
736 ALU_CASE(fcos
, fcos
);
738 /* Second op implicit #0 */
739 ALU_CASE(inot
, inor
);
740 ALU_CASE(iand
, iand
);
742 ALU_CASE(ixor
, ixor
);
743 ALU_CASE(ishl
, ishl
);
744 ALU_CASE(ishr
, iasr
);
745 ALU_CASE(ushr
, ilsr
);
747 ALU_CASE(b32all_fequal2
, fball_eq
);
748 ALU_CASE(b32all_fequal3
, fball_eq
);
749 ALU_CASE(b32all_fequal4
, fball_eq
);
751 ALU_CASE(b32any_fnequal2
, fbany_neq
);
752 ALU_CASE(b32any_fnequal3
, fbany_neq
);
753 ALU_CASE(b32any_fnequal4
, fbany_neq
);
755 ALU_CASE(b32all_iequal2
, iball_eq
);
756 ALU_CASE(b32all_iequal3
, iball_eq
);
757 ALU_CASE(b32all_iequal4
, iball_eq
);
759 ALU_CASE(b32any_inequal2
, ibany_neq
);
760 ALU_CASE(b32any_inequal3
, ibany_neq
);
761 ALU_CASE(b32any_inequal4
, ibany_neq
);
763 /* Source mods will be shoved in later */
764 ALU_CASE(fabs
, fmov
);
765 ALU_CASE(fneg
, fmov
);
766 ALU_CASE(fsat
, fmov
);
768 /* For greater-or-equal, we lower to less-or-equal and flip the
776 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
777 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
778 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
779 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
782 /* Swap via temporary */
783 nir_alu_src temp
= instr
->src
[1];
784 instr
->src
[1] = instr
->src
[0];
785 instr
->src
[0] = temp
;
790 case nir_op_b32csel
: {
791 /* Midgard features both fcsel and icsel, depending on
792 * the type of the arguments/output. However, as long
793 * as we're careful we can _always_ use icsel and
794 * _never_ need fcsel, since the latter does additional
795 * floating-point-specific processing whereas the
796 * former just moves bits on the wire. It's not obvious
797 * why these are separate opcodes, save for the ability
798 * to do things like sat/pos/abs/neg for free */
800 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
801 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
803 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
806 /* Emit the condition into r31 */
809 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
811 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
813 /* The condition is the first argument; move the other
814 * arguments up one to be a binary instruction for
817 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
822 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
827 /* Midgard can perform certain modifiers on output of an ALU op */
830 if (midgard_is_integer_out_op(op
)) {
831 outmod
= midgard_outmod_int_wrap
;
833 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
834 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
837 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
839 if (instr
->op
== nir_op_fmax
) {
840 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
841 op
= midgard_alu_op_fmov
;
843 outmod
= midgard_outmod_pos
;
844 instr
->src
[0] = instr
->src
[1];
845 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
846 op
= midgard_alu_op_fmov
;
848 outmod
= midgard_outmod_pos
;
852 /* Fetch unit, quirks, etc information */
853 unsigned opcode_props
= alu_opcode_props
[op
].props
;
854 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
856 /* src0 will always exist afaik, but src1 will not for 1-argument
857 * instructions. The latter can only be fetched if the instruction
858 * needs it, or else we may segfault. */
860 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
861 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
863 /* Rather than use the instruction generation helpers, we do it
864 * ourselves here to avoid the mess */
866 midgard_instruction ins
= {
869 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
870 .src1
= quirk_flipped_r24
? src0
: src1
,
875 nir_alu_src
*nirmods
[2] = { NULL
};
877 if (nr_inputs
== 2) {
878 nirmods
[0] = &instr
->src
[0];
879 nirmods
[1] = &instr
->src
[1];
880 } else if (nr_inputs
== 1) {
881 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
886 /* These were lowered to a move, so apply the corresponding mod */
888 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
889 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
891 if (instr
->op
== nir_op_fneg
)
892 s
->negate
= !s
->negate
;
894 if (instr
->op
== nir_op_fabs
)
898 bool is_int
= midgard_is_integer_op(op
);
900 midgard_vector_alu alu
= {
902 .reg_mode
= midgard_reg_mode_32
,
903 .dest_override
= midgard_dest_override_none
,
906 /* Writemask only valid for non-SSA NIR */
907 .mask
= expand_writemask((1 << nr_components
) - 1),
909 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
910 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
913 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
916 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
920 /* Late fixup for emulated instructions */
922 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
923 /* Presently, our second argument is an inline #0 constant.
924 * Switch over to an embedded 1.0 constant (that can't fit
925 * inline, since we're 32-bit, not 16-bit like the inline
928 ins
.ssa_args
.inline_constant
= false;
929 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
930 ins
.has_constants
= true;
932 if (instr
->op
== nir_op_b2f32
) {
933 ins
.constants
[0] = 1.0f
;
935 /* Type pun it into place */
937 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
940 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
941 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
942 /* Lots of instructions need a 0 plonked in */
943 ins
.ssa_args
.inline_constant
= false;
944 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
945 ins
.has_constants
= true;
946 ins
.constants
[0] = 0.0f
;
947 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
948 } else if (instr
->op
== nir_op_inot
) {
949 /* ~b = ~(b & b), so duplicate the source */
950 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
951 ins
.alu
.src2
= ins
.alu
.src1
;
954 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
955 /* To avoid duplicating the lookup tables (probably), true LUT
956 * instructions can only operate as if they were scalars. Lower
957 * them here by changing the component. */
959 uint8_t original_swizzle
[4];
960 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
962 for (int i
= 0; i
< nr_components
; ++i
) {
963 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
965 for (int j
= 0; j
< 4; ++j
)
966 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
968 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
969 emit_mir_instruction(ctx
, ins
);
972 emit_mir_instruction(ctx
, ins
);
979 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
981 /* TODO: half-floats */
983 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
984 /* Fast path: For the first 16 uniforms, direct accesses are
985 * 0-cycle, since they're just a register fetch in the usual
986 * case. So, we alias the registers while we're still in
989 int reg_slot
= 23 - offset
;
990 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
992 /* Otherwise, read from the 'special' UBO to access
993 * higher-indexed uniforms, at a performance cost. More
994 * generally, we're emitting a UBO read instruction. */
996 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
998 /* TODO: Don't split */
999 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1000 ins
.load_store
.address
= offset
>> 3;
1002 if (indirect_offset
) {
1003 emit_indirect_offset(ctx
, indirect_offset
);
1004 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1006 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1009 emit_mir_instruction(ctx
, ins
);
1015 compiler_context
*ctx
,
1016 unsigned dest
, unsigned offset
,
1017 unsigned nr_comp
, unsigned component
,
1018 nir_src
*indirect_offset
)
1020 /* XXX: Half-floats? */
1021 /* TODO: swizzle, mask */
1023 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1024 ins
.load_store
.mask
= (1 << nr_comp
) - 1;
1025 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1027 midgard_varying_parameter p
= {
1029 .interpolation
= midgard_interp_default
,
1030 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1034 memcpy(&u
, &p
, sizeof(p
));
1035 ins
.load_store
.varying_parameters
= u
;
1037 if (indirect_offset
) {
1038 /* We need to add in the dynamic index, moved to r27.w */
1039 emit_indirect_offset(ctx
, indirect_offset
);
1040 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1042 /* Just a direct load */
1043 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1046 emit_mir_instruction(ctx
, ins
);
1050 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1052 /* First, pull out the destination */
1053 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1055 /* Now, figure out which uniform this is */
1056 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1057 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1059 /* Sysvals are prefix uniforms */
1060 unsigned uniform
= ((uintptr_t) val
) - 1;
1062 /* Emit the read itself -- this is never indirect */
1063 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1066 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1067 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1068 * generations have faster vectorized reads. This operation is for blend
1069 * shaders in particular; reading the tilebuffer from the fragment shader
1070 * remains an open problem. */
1073 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1075 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1076 ins
.load_store
.swizzle
= 0; /* xxxx */
1078 /* Read each component sequentially */
1080 for (unsigned c
= 0; c
< 4; ++c
) {
1081 ins
.load_store
.mask
= (1 << c
);
1082 ins
.load_store
.unknown
= c
;
1083 emit_mir_instruction(ctx
, ins
);
1086 /* vadd.u2f hr2, zext(hr2), #0 */
1088 midgard_vector_alu_src alu_src
= blank_alu_src
;
1089 alu_src
.mod
= midgard_int_zero_extend
;
1090 alu_src
.half
= true;
1092 midgard_instruction u2f
= {
1096 .src1
= SSA_UNUSED_0
,
1098 .inline_constant
= true
1101 .op
= midgard_alu_op_u2f
,
1102 .reg_mode
= midgard_reg_mode_16
,
1103 .dest_override
= midgard_dest_override_none
,
1105 .src1
= vector_alu_srco_unsigned(alu_src
),
1106 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1110 emit_mir_instruction(ctx
, u2f
);
1112 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1116 midgard_instruction fmul
= {
1118 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1122 .src1
= SSA_UNUSED_0
,
1123 .inline_constant
= true
1126 .op
= midgard_alu_op_fmul
,
1127 .reg_mode
= midgard_reg_mode_32
,
1128 .dest_override
= midgard_dest_override_none
,
1129 .outmod
= midgard_outmod_sat
,
1131 .src1
= vector_alu_srco_unsigned(alu_src
),
1132 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1136 emit_mir_instruction(ctx
, fmul
);
1140 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1142 unsigned offset
, reg
;
1144 switch (instr
->intrinsic
) {
1145 case nir_intrinsic_discard_if
:
1146 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1150 case nir_intrinsic_discard
: {
1151 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1152 struct midgard_instruction discard
= v_branch(conditional
, false);
1153 discard
.branch
.target_type
= TARGET_DISCARD
;
1154 emit_mir_instruction(ctx
, discard
);
1156 ctx
->can_discard
= true;
1160 case nir_intrinsic_load_uniform
:
1161 case nir_intrinsic_load_input
:
1162 offset
= nir_intrinsic_base(instr
);
1164 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1165 bool direct
= nir_src_is_const(instr
->src
[0]);
1168 offset
+= nir_src_as_uint(instr
->src
[0]);
1171 /* We may need to apply a fractional offset */
1172 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1173 nir_intrinsic_component(instr
) : 0;
1174 reg
= nir_dest_index(ctx
, &instr
->dest
);
1176 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1177 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1178 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1179 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
);
1180 } else if (ctx
->is_blend
) {
1181 /* For blend shaders, load the input color, which is
1182 * preloaded to r0 */
1184 midgard_instruction move
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1185 emit_mir_instruction(ctx
, move
);
1186 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1187 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1188 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1189 ins
.load_store
.mask
= (1 << nr_comp
) - 1;
1190 emit_mir_instruction(ctx
, ins
);
1192 DBG("Unknown load\n");
1198 case nir_intrinsic_load_output
:
1199 assert(nir_src_is_const(instr
->src
[0]));
1200 reg
= nir_dest_index(ctx
, &instr
->dest
);
1202 if (ctx
->is_blend
) {
1204 emit_fb_read_blend_scalar(ctx
, reg
);
1206 DBG("Unknown output load\n");
1212 case nir_intrinsic_load_blend_const_color_rgba
: {
1213 assert(ctx
->is_blend
);
1214 reg
= nir_dest_index(ctx
, &instr
->dest
);
1216 /* Blend constants are embedded directly in the shader and
1217 * patched in, so we use some magic routing */
1219 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1220 ins
.has_constants
= true;
1221 ins
.has_blend_constant
= true;
1222 emit_mir_instruction(ctx
, ins
);
1226 case nir_intrinsic_store_output
:
1227 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1229 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1231 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1233 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1234 /* gl_FragColor is not emitted with load/store
1235 * instructions. Instead, it gets plonked into
1236 * r0 at the end of the shader and we do the
1237 * framebuffer writeout dance. TODO: Defer
1240 midgard_instruction move
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1241 emit_mir_instruction(ctx
, move
);
1243 /* Save the index we're writing to for later reference
1244 * in the epilogue */
1246 ctx
->fragment_output
= reg
;
1247 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1248 /* Varyings are written into one of two special
1249 * varying register, r26 or r27. The register itself is
1250 * selected as the register in the st_vary instruction,
1251 * minus the base of 26. E.g. write into r27 and then
1252 * call st_vary(1) */
1254 midgard_instruction ins
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1255 emit_mir_instruction(ctx
, ins
);
1257 /* We should have been vectorized. That also lets us
1258 * ignore the mask. because the mask component on
1259 * st_vary is (as far as I can tell) ignored [the blob
1260 * sets it to zero] */
1261 assert(nir_intrinsic_component(instr
) == 0);
1263 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1264 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1265 emit_mir_instruction(ctx
, st
);
1267 DBG("Unknown store\n");
1273 case nir_intrinsic_load_alpha_ref_float
:
1274 assert(instr
->dest
.is_ssa
);
1276 float ref_value
= ctx
->alpha_ref
;
1278 float *v
= ralloc_array(NULL
, float, 4);
1279 memcpy(v
, &ref_value
, sizeof(float));
1280 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1283 case nir_intrinsic_load_viewport_scale
:
1284 case nir_intrinsic_load_viewport_offset
:
1285 emit_sysval_read(ctx
, instr
);
1289 printf ("Unhandled intrinsic\n");
1296 midgard_tex_format(enum glsl_sampler_dim dim
)
1299 case GLSL_SAMPLER_DIM_2D
:
1300 case GLSL_SAMPLER_DIM_EXTERNAL
:
1303 case GLSL_SAMPLER_DIM_3D
:
1306 case GLSL_SAMPLER_DIM_CUBE
:
1307 return TEXTURE_CUBE
;
1310 DBG("Unknown sampler dim type\n");
1317 midgard_tex_op(nir_texop op
)
1322 return TEXTURE_OP_NORMAL
;
1324 return TEXTURE_OP_LOD
;
1326 unreachable("Unhanlded texture op");
1331 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1334 //assert (!instr->sampler);
1335 //assert (!instr->texture_array_size);
1337 /* Allocate registers via a round robin scheme to alternate between the two registers */
1338 int reg
= ctx
->texture_op_count
& 1;
1339 int in_reg
= reg
, out_reg
= reg
;
1341 /* Make room for the reg */
1343 if (ctx
->texture_index
[reg
] > -1)
1344 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1346 int texture_index
= instr
->texture_index
;
1347 int sampler_index
= texture_index
;
1349 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1350 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1351 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1352 midgard_vector_alu_src alu_src
= blank_alu_src
;
1354 switch (instr
->src
[i
].src_type
) {
1355 case nir_tex_src_coord
: {
1356 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1357 /* For cubemaps, we need to load coords into
1358 * special r27, and then use a special ld/st op
1359 * to select the face and copy the xy into the
1360 * texture register */
1362 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1364 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1365 emit_mir_instruction(ctx
, move
);
1367 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1368 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1369 st
.load_store
.mask
= 0x3; /* xy */
1370 st
.load_store
.swizzle
= alu_src
.swizzle
;
1371 emit_mir_instruction(ctx
, st
);
1374 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1376 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1377 ins
.alu
.mask
= expand_writemask(0x3); /* xy */
1378 emit_mir_instruction(ctx
, ins
);
1384 case nir_tex_src_bias
:
1385 case nir_tex_src_lod
: {
1386 /* To keep RA simple, we put the bias/LOD into the w
1387 * component of the input source, which is otherwise in xy */
1389 alu_src
.swizzle
= SWIZZLE_XXXX
;
1391 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1392 ins
.alu
.mask
= expand_writemask(1 << COMPONENT_W
);
1393 emit_mir_instruction(ctx
, ins
);
1398 DBG("Unknown source type\n");
1405 /* No helper to build texture words -- we do it all here */
1406 midgard_instruction ins
= {
1407 .type
= TAG_TEXTURE_4
,
1409 .op
= midgard_tex_op(instr
->op
),
1410 .format
= midgard_tex_format(instr
->sampler_dim
),
1411 .texture_handle
= texture_index
,
1412 .sampler_handle
= sampler_index
,
1414 /* TODO: Regalloc it in */
1415 .swizzle
= SWIZZLE_XYZW
,
1420 .in_reg_swizzle
= SWIZZLE_XYXX
,
1428 /* Set registers to read and write from the same place */
1429 ins
.texture
.in_reg_select
= in_reg
;
1430 ins
.texture
.out_reg_select
= out_reg
;
1432 /* Setup bias/LOD if necessary. Only register mode support right now.
1433 * TODO: Immediate mode for performance gains */
1435 if (instr
->op
== nir_texop_txb
|| instr
->op
== nir_texop_txl
) {
1436 ins
.texture
.lod_register
= true;
1438 midgard_tex_register_select sel
= {
1448 memcpy(&packed
, &sel
, sizeof(packed
));
1449 ins
.texture
.bias
= packed
;
1452 emit_mir_instruction(ctx
, ins
);
1454 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1456 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1457 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1458 ctx
->texture_index
[reg
] = o_index
;
1460 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1461 emit_mir_instruction(ctx
, ins2
);
1463 /* Used for .cont and .last hinting */
1464 ctx
->texture_op_count
++;
1468 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1470 switch (instr
->type
) {
1471 case nir_jump_break
: {
1472 /* Emit a branch out of the loop */
1473 struct midgard_instruction br
= v_branch(false, false);
1474 br
.branch
.target_type
= TARGET_BREAK
;
1475 br
.branch
.target_break
= ctx
->current_loop_depth
;
1476 emit_mir_instruction(ctx
, br
);
1483 DBG("Unknown jump type %d\n", instr
->type
);
1489 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1491 switch (instr
->type
) {
1492 case nir_instr_type_load_const
:
1493 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1496 case nir_instr_type_intrinsic
:
1497 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1500 case nir_instr_type_alu
:
1501 emit_alu(ctx
, nir_instr_as_alu(instr
));
1504 case nir_instr_type_tex
:
1505 emit_tex(ctx
, nir_instr_as_tex(instr
));
1508 case nir_instr_type_jump
:
1509 emit_jump(ctx
, nir_instr_as_jump(instr
));
1512 case nir_instr_type_ssa_undef
:
1517 DBG("Unhandled instruction type\n");
1523 /* ALU instructions can inline or embed constants, which decreases register
1524 * pressure and saves space. */
1526 #define CONDITIONAL_ATTACH(src) { \
1527 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1530 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1531 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1536 inline_alu_constants(compiler_context
*ctx
)
1538 mir_foreach_instr(ctx
, alu
) {
1539 /* Other instructions cannot inline constants */
1540 if (alu
->type
!= TAG_ALU_4
) continue;
1542 /* If there is already a constant here, we can do nothing */
1543 if (alu
->has_constants
) continue;
1545 /* It makes no sense to inline constants on a branch */
1546 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1548 CONDITIONAL_ATTACH(src0
);
1550 if (!alu
->has_constants
) {
1551 CONDITIONAL_ATTACH(src1
)
1552 } else if (!alu
->inline_constant
) {
1553 /* Corner case: _two_ vec4 constants, for instance with a
1554 * csel. For this case, we can only use a constant
1555 * register for one, we'll have to emit a move for the
1556 * other. Note, if both arguments are constants, then
1557 * necessarily neither argument depends on the value of
1558 * any particular register. As the destination register
1559 * will be wiped, that means we can spill the constant
1560 * to the destination register.
1563 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1564 unsigned scratch
= alu
->ssa_args
.dest
;
1567 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1568 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1570 /* Force a break XXX Defer r31 writes */
1571 ins
.unit
= UNIT_VLUT
;
1573 /* Set the source */
1574 alu
->ssa_args
.src1
= scratch
;
1576 /* Inject us -before- the last instruction which set r31 */
1577 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1583 /* Midgard supports two types of constants, embedded constants (128-bit) and
1584 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1585 * constants can be demoted to inline constants, for space savings and
1586 * sometimes a performance boost */
1589 embedded_to_inline_constant(compiler_context
*ctx
)
1591 mir_foreach_instr(ctx
, ins
) {
1592 if (!ins
->has_constants
) continue;
1594 if (ins
->ssa_args
.inline_constant
) continue;
1596 /* Blend constants must not be inlined by definition */
1597 if (ins
->has_blend_constant
) continue;
1599 /* src1 cannot be an inline constant due to encoding
1600 * restrictions. So, if possible we try to flip the arguments
1603 int op
= ins
->alu
.op
;
1605 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1607 /* These ops require an operational change to flip
1608 * their arguments TODO */
1609 case midgard_alu_op_flt
:
1610 case midgard_alu_op_fle
:
1611 case midgard_alu_op_ilt
:
1612 case midgard_alu_op_ile
:
1613 case midgard_alu_op_fcsel
:
1614 case midgard_alu_op_icsel
:
1615 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1620 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1621 /* Flip the SSA numbers */
1622 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1623 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1625 /* And flip the modifiers */
1629 src_temp
= ins
->alu
.src2
;
1630 ins
->alu
.src2
= ins
->alu
.src1
;
1631 ins
->alu
.src1
= src_temp
;
1635 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1636 /* Extract the source information */
1638 midgard_vector_alu_src
*src
;
1639 int q
= ins
->alu
.src2
;
1640 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1643 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1644 int component
= src
->swizzle
& 3;
1646 /* Scale constant appropriately, if we can legally */
1647 uint16_t scaled_constant
= 0;
1649 if (midgard_is_integer_op(op
)) {
1650 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1651 scaled_constant
= (uint16_t) iconstants
[component
];
1653 /* Constant overflow after resize */
1654 if (scaled_constant
!= iconstants
[component
])
1657 float original
= (float) ins
->constants
[component
];
1658 scaled_constant
= _mesa_float_to_half(original
);
1660 /* Check for loss of precision. If this is
1661 * mediump, we don't care, but for a highp
1662 * shader, we need to pay attention. NIR
1663 * doesn't yet tell us which mode we're in!
1664 * Practically this prevents most constants
1665 * from being inlined, sadly. */
1667 float fp32
= _mesa_half_to_float(scaled_constant
);
1669 if (fp32
!= original
)
1673 /* We don't know how to handle these with a constant */
1675 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
1676 DBG("Bailing inline constant...\n");
1680 /* Make sure that the constant is not itself a
1681 * vector by checking if all accessed values
1682 * (by the swizzle) are the same. */
1684 uint32_t *cons
= (uint32_t *) ins
->constants
;
1685 uint32_t value
= cons
[component
];
1687 bool is_vector
= false;
1688 unsigned mask
= effective_writemask(&ins
->alu
);
1690 for (int c
= 1; c
< 4; ++c
) {
1691 /* We only care if this component is actually used */
1692 if (!(mask
& (1 << c
)))
1695 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1697 if (test
!= value
) {
1706 /* Get rid of the embedded constant */
1707 ins
->has_constants
= false;
1708 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1709 ins
->ssa_args
.inline_constant
= true;
1710 ins
->inline_constant
= scaled_constant
;
1715 /* Map normal SSA sources to other SSA sources / fixed registers (like
1719 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
1721 /* Sign is used quite deliberately for unused */
1725 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
1728 /* Remove entry in leftovers to avoid a redunant fmov */
1730 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
1733 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
1735 /* Assign the alias map */
1741 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1742 * texture pipeline */
1745 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
1747 bool progress
= false;
1749 mir_foreach_instr_in_block_safe(block
, ins
) {
1750 if (ins
->type
!= TAG_ALU_4
) continue;
1751 if (ins
->compact_branch
) continue;
1753 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1754 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
1756 mir_remove_instruction(ins
);
1763 /* Dead code elimination for branches at the end of a block - only one branch
1764 * per block is legal semantically */
1767 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1769 bool branched
= false;
1771 mir_foreach_instr_in_block_safe(block
, ins
) {
1772 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1774 /* We ignore prepacked branches since the fragment epilogue is
1775 * just generally special */
1776 if (ins
->prepacked_branch
) continue;
1778 /* Discards are similarly special and may not correspond to the
1781 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
1784 /* We already branched, so this is dead */
1785 mir_remove_instruction(ins
);
1793 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
1796 if (!is_int
&& src
.mod
) return true;
1799 for (unsigned c
= 0; c
< 4; ++c
) {
1800 if (!(mask
& (1 << c
))) continue;
1801 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
1808 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
1810 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
1811 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
1813 midgard_vector_alu_src src2
=
1814 vector_alu_from_unsigned(ins
->alu
.src2
);
1816 return mir_nontrivial_mod(src2
, is_int
, mask
);
1820 mir_nontrivial_outmod(midgard_instruction
*ins
)
1822 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
1823 unsigned mod
= ins
->alu
.outmod
;
1826 return mod
!= midgard_outmod_int_wrap
;
1828 return mod
!= midgard_outmod_none
;
1832 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
1834 bool progress
= false;
1836 mir_foreach_instr_in_block_safe(block
, ins
) {
1837 if (ins
->type
!= TAG_ALU_4
) continue;
1838 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
1840 unsigned from
= ins
->ssa_args
.src1
;
1841 unsigned to
= ins
->ssa_args
.dest
;
1843 /* We only work on pure SSA */
1845 if (to
>= SSA_FIXED_MINIMUM
) continue;
1846 if (from
>= SSA_FIXED_MINIMUM
) continue;
1847 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
1848 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
1850 /* Constant propagation is not handled here, either */
1851 if (ins
->ssa_args
.inline_constant
) continue;
1852 if (ins
->has_constants
) continue;
1854 if (mir_nontrivial_source2_mod(ins
)) continue;
1855 if (mir_nontrivial_outmod(ins
)) continue;
1857 /* We're clear -- rewrite */
1858 mir_rewrite_index_src(ctx
, to
, from
);
1859 mir_remove_instruction(ins
);
1866 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1867 * the move can be propagated away entirely */
1870 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
1873 if (comp
== midgard_outmod_none
)
1876 if (*outmod
== midgard_outmod_none
) {
1881 /* TODO: Compose rules */
1886 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
1888 bool progress
= false;
1890 mir_foreach_instr_in_block_safe(block
, ins
) {
1891 if (ins
->type
!= TAG_ALU_4
) continue;
1892 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
1893 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
1895 /* TODO: Registers? */
1896 unsigned src
= ins
->ssa_args
.src1
;
1897 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
1898 assert(!mir_has_multiple_writes(ctx
, src
));
1900 /* There might be a source modifier, too */
1901 if (mir_nontrivial_source2_mod(ins
)) continue;
1903 /* Backpropagate the modifier */
1904 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
1905 if (v
->type
!= TAG_ALU_4
) continue;
1906 if (v
->ssa_args
.dest
!= src
) continue;
1908 /* Can we even take a float outmod? */
1909 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
1911 midgard_outmod_float temp
= v
->alu
.outmod
;
1912 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
1914 /* Throw in the towel.. */
1915 if (!progress
) break;
1917 /* Otherwise, transfer the modifier */
1918 v
->alu
.outmod
= temp
;
1919 ins
->alu
.outmod
= midgard_outmod_none
;
1929 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
1931 bool progress
= false;
1933 mir_foreach_instr_in_block_safe(block
, ins
) {
1934 if (ins
->type
!= TAG_ALU_4
) continue;
1935 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
1937 unsigned from
= ins
->ssa_args
.src1
;
1938 unsigned to
= ins
->ssa_args
.dest
;
1940 /* Make sure it's simple enough for us to handle */
1942 if (from
>= SSA_FIXED_MINIMUM
) continue;
1943 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
1944 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
1945 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
1947 bool eliminated
= false;
1949 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
1950 /* The texture registers are not SSA so be careful.
1951 * Conservatively, just stop if we hit a texture op
1952 * (even if it may not write) to where we are */
1954 if (v
->type
!= TAG_ALU_4
)
1957 if (v
->ssa_args
.dest
== from
) {
1958 /* We don't want to track partial writes ... */
1959 if (v
->alu
.mask
== 0xF) {
1960 v
->ssa_args
.dest
= to
;
1969 mir_remove_instruction(ins
);
1971 progress
|= eliminated
;
1977 /* The following passes reorder MIR instructions to enable better scheduling */
1980 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
1982 mir_foreach_instr_in_block_safe(block
, ins
) {
1983 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
1985 /* We've found a load/store op. Check if next is also load/store. */
1986 midgard_instruction
*next_op
= mir_next_op(ins
);
1987 if (&next_op
->link
!= &block
->instructions
) {
1988 if (next_op
->type
== TAG_LOAD_STORE_4
) {
1989 /* If so, we're done since we're a pair */
1990 ins
= mir_next_op(ins
);
1994 /* Maximum search distance to pair, to avoid register pressure disasters */
1995 int search_distance
= 8;
1997 /* Otherwise, we have an orphaned load/store -- search for another load */
1998 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
1999 /* Terminate search if necessary */
2000 if (!(search_distance
--)) break;
2002 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2004 /* Stores cannot be reordered, since they have
2005 * dependencies. For the same reason, indirect
2006 * loads cannot be reordered as their index is
2007 * loaded in r27.w */
2009 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2011 /* It appears the 0x800 bit is set whenever a
2012 * load is direct, unset when it is indirect.
2013 * Skip indirect loads. */
2015 if (!(c
->load_store
.unknown
& 0x800)) continue;
2017 /* We found one! Move it up to pair and remove it from the old location */
2019 mir_insert_instruction_before(ins
, *c
);
2020 mir_remove_instruction(c
);
2028 /* If there are leftovers after the below pass, emit actual fmov
2029 * instructions for the slow-but-correct path */
2032 emit_leftover_move(compiler_context
*ctx
)
2034 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2035 int base
= ((uintptr_t) leftover
->key
) - 1;
2038 map_ssa_to_alias(ctx
, &mapped
);
2039 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2044 actualise_ssa_to_alias(compiler_context
*ctx
)
2046 mir_foreach_instr(ctx
, ins
) {
2047 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2048 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2051 emit_leftover_move(ctx
);
2055 emit_fragment_epilogue(compiler_context
*ctx
)
2057 /* Special case: writing out constants requires us to include the move
2058 * explicitly now, so shove it into r0 */
2060 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2062 if (constant_value
) {
2063 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2064 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2065 emit_mir_instruction(ctx
, ins
);
2068 /* Perform the actual fragment writeout. We have two writeout/branch
2069 * instructions, forming a loop until writeout is successful as per the
2070 * docs. TODO: gl_FragDepth */
2072 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2073 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2076 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2077 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2078 * with the int8 analogue to the fragment epilogue */
2081 emit_blend_epilogue(compiler_context
*ctx
)
2083 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2085 midgard_instruction scale
= {
2088 .inline_constant
= _mesa_float_to_half(255.0),
2090 .src0
= SSA_FIXED_REGISTER(0),
2091 .src1
= SSA_UNUSED_0
,
2092 .dest
= SSA_FIXED_REGISTER(24),
2093 .inline_constant
= true
2096 .op
= midgard_alu_op_fmul
,
2097 .reg_mode
= midgard_reg_mode_32
,
2098 .dest_override
= midgard_dest_override_lower
,
2100 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2101 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2105 emit_mir_instruction(ctx
, scale
);
2107 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2109 midgard_vector_alu_src alu_src
= blank_alu_src
;
2110 alu_src
.half
= true;
2112 midgard_instruction f2u8
= {
2115 .src0
= SSA_FIXED_REGISTER(24),
2116 .src1
= SSA_UNUSED_0
,
2117 .dest
= SSA_FIXED_REGISTER(0),
2118 .inline_constant
= true
2121 .op
= midgard_alu_op_f2u8
,
2122 .reg_mode
= midgard_reg_mode_16
,
2123 .dest_override
= midgard_dest_override_lower
,
2124 .outmod
= midgard_outmod_pos
,
2126 .src1
= vector_alu_srco_unsigned(alu_src
),
2127 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2131 emit_mir_instruction(ctx
, f2u8
);
2133 /* vmul.imov.quarter r0, r0, r0 */
2135 midgard_instruction imov_8
= {
2138 .src0
= SSA_UNUSED_1
,
2139 .src1
= SSA_FIXED_REGISTER(0),
2140 .dest
= SSA_FIXED_REGISTER(0),
2143 .op
= midgard_alu_op_imov
,
2144 .reg_mode
= midgard_reg_mode_8
,
2145 .dest_override
= midgard_dest_override_none
,
2146 .outmod
= midgard_outmod_int_wrap
,
2148 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2149 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2153 /* Emit branch epilogue with the 8-bit move as the source */
2155 emit_mir_instruction(ctx
, imov_8
);
2156 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2158 emit_mir_instruction(ctx
, imov_8
);
2159 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2162 static midgard_block
*
2163 emit_block(compiler_context
*ctx
, nir_block
*block
)
2165 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2166 list_addtail(&this_block
->link
, &ctx
->blocks
);
2168 this_block
->is_scheduled
= false;
2171 ctx
->texture_index
[0] = -1;
2172 ctx
->texture_index
[1] = -1;
2174 /* Add us as a successor to the block we are following */
2175 if (ctx
->current_block
)
2176 midgard_block_add_successor(ctx
->current_block
, this_block
);
2178 /* Set up current block */
2179 list_inithead(&this_block
->instructions
);
2180 ctx
->current_block
= this_block
;
2182 nir_foreach_instr(instr
, block
) {
2183 emit_instr(ctx
, instr
);
2184 ++ctx
->instruction_count
;
2187 inline_alu_constants(ctx
);
2188 embedded_to_inline_constant(ctx
);
2190 /* Perform heavylifting for aliasing */
2191 actualise_ssa_to_alias(ctx
);
2193 midgard_pair_load_store(ctx
, this_block
);
2195 /* Append fragment shader epilogue (value writeout) */
2196 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2197 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2199 emit_blend_epilogue(ctx
);
2201 emit_fragment_epilogue(ctx
);
2205 if (block
== nir_start_block(ctx
->func
->impl
))
2206 ctx
->initial_block
= this_block
;
2208 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2209 ctx
->final_block
= this_block
;
2211 /* Allow the next control flow to access us retroactively, for
2213 ctx
->current_block
= this_block
;
2215 /* Document the fallthrough chain */
2216 ctx
->previous_source_block
= this_block
;
2221 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2224 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2226 /* Conditional branches expect the condition in r31.w; emit a move for
2227 * that in the _previous_ block (which is the current block). */
2228 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2230 /* Speculatively emit the branch, but we can't fill it in until later */
2231 EMIT(branch
, true, true);
2232 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2234 /* Emit the two subblocks */
2235 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2237 /* Emit a jump from the end of the then block to the end of the else */
2238 EMIT(branch
, false, false);
2239 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2241 /* Emit second block, and check if it's empty */
2243 int else_idx
= ctx
->block_count
;
2244 int count_in
= ctx
->instruction_count
;
2245 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2246 int after_else_idx
= ctx
->block_count
;
2248 /* Now that we have the subblocks emitted, fix up the branches */
2253 if (ctx
->instruction_count
== count_in
) {
2254 /* The else block is empty, so don't emit an exit jump */
2255 mir_remove_instruction(then_exit
);
2256 then_branch
->branch
.target_block
= after_else_idx
;
2258 then_branch
->branch
.target_block
= else_idx
;
2259 then_exit
->branch
.target_block
= after_else_idx
;
2264 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2266 /* Remember where we are */
2267 midgard_block
*start_block
= ctx
->current_block
;
2269 /* Allocate a loop number, growing the current inner loop depth */
2270 int loop_idx
= ++ctx
->current_loop_depth
;
2272 /* Get index from before the body so we can loop back later */
2273 int start_idx
= ctx
->block_count
;
2275 /* Emit the body itself */
2276 emit_cf_list(ctx
, &nloop
->body
);
2278 /* Branch back to loop back */
2279 struct midgard_instruction br_back
= v_branch(false, false);
2280 br_back
.branch
.target_block
= start_idx
;
2281 emit_mir_instruction(ctx
, br_back
);
2283 /* Mark down that branch in the graph. Note that we're really branching
2284 * to the block *after* we started in. TODO: Why doesn't the branch
2285 * itself have an off-by-one then...? */
2286 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2288 /* Find the index of the block about to follow us (note: we don't add
2289 * one; blocks are 0-indexed so we get a fencepost problem) */
2290 int break_block_idx
= ctx
->block_count
;
2292 /* Fix up the break statements we emitted to point to the right place,
2293 * now that we can allocate a block number for them */
2295 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2296 mir_foreach_instr_in_block(block
, ins
) {
2297 if (ins
->type
!= TAG_ALU_4
) continue;
2298 if (!ins
->compact_branch
) continue;
2299 if (ins
->prepacked_branch
) continue;
2301 /* We found a branch -- check the type to see if we need to do anything */
2302 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2304 /* It's a break! Check if it's our break */
2305 if (ins
->branch
.target_break
!= loop_idx
) continue;
2307 /* Okay, cool, we're breaking out of this loop.
2308 * Rewrite from a break to a goto */
2310 ins
->branch
.target_type
= TARGET_GOTO
;
2311 ins
->branch
.target_block
= break_block_idx
;
2315 /* Now that we've finished emitting the loop, free up the depth again
2316 * so we play nice with recursion amid nested loops */
2317 --ctx
->current_loop_depth
;
2320 static midgard_block
*
2321 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2323 midgard_block
*start_block
= NULL
;
2325 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2326 switch (node
->type
) {
2327 case nir_cf_node_block
: {
2328 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2331 start_block
= block
;
2336 case nir_cf_node_if
:
2337 emit_if(ctx
, nir_cf_node_as_if(node
));
2340 case nir_cf_node_loop
:
2341 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2344 case nir_cf_node_function
:
2353 /* Due to lookahead, we need to report the first tag executed in the command
2354 * stream and in branch targets. An initial block might be empty, so iterate
2355 * until we find one that 'works' */
2358 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2360 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2362 unsigned first_tag
= 0;
2365 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2367 if (initial_bundle
) {
2368 first_tag
= initial_bundle
->tag
;
2372 /* Initial block is empty, try the next block */
2373 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2374 } while(initial_block
!= NULL
);
2381 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2383 struct util_dynarray
*compiled
= &program
->compiled
;
2385 midgard_debug
= debug_get_option_midgard_debug();
2387 compiler_context ictx
= {
2389 .stage
= nir
->info
.stage
,
2391 .is_blend
= is_blend
,
2392 .blend_constant_offset
= -1,
2394 .alpha_ref
= program
->alpha_ref
2397 compiler_context
*ctx
= &ictx
;
2399 /* TODO: Decide this at runtime */
2400 ctx
->uniform_cutoff
= 8;
2402 /* Initialize at a global (not block) level hash tables */
2404 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2405 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
2406 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2407 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2408 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
2410 /* Record the varying mapping for the command stream's bookkeeping */
2412 struct exec_list
*varyings
=
2413 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2415 unsigned max_varying
= 0;
2416 nir_foreach_variable(var
, varyings
) {
2417 unsigned loc
= var
->data
.driver_location
;
2418 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2420 for (int c
= loc
; c
< (loc
+ sz
); ++c
) {
2421 program
->varyings
[c
] = var
->data
.location
;
2422 max_varying
= MAX2(max_varying
, c
);
2426 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2427 * (so we don't accidentally duplicate the epilogue since mesa/st has
2428 * messed with our I/O quite a bit already) */
2430 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2432 if (ctx
->stage
== MESA_SHADER_VERTEX
)
2433 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2435 NIR_PASS_V(nir
, nir_lower_var_copies
);
2436 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2437 NIR_PASS_V(nir
, nir_split_var_copies
);
2438 NIR_PASS_V(nir
, nir_lower_var_copies
);
2439 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2440 NIR_PASS_V(nir
, nir_lower_var_copies
);
2441 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2443 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2445 /* Optimisation passes */
2449 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2450 nir_print_shader(nir
, stdout
);
2453 /* Assign sysvals and counts, now that we're sure
2454 * (post-optimisation) */
2456 midgard_nir_assign_sysvals(ctx
, nir
);
2458 program
->uniform_count
= nir
->num_uniforms
;
2459 program
->sysval_count
= ctx
->sysval_count
;
2460 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2462 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
2463 program
->varying_count
= max_varying
+ 1; /* Fencepost off-by-one */
2465 nir_foreach_function(func
, nir
) {
2469 list_inithead(&ctx
->blocks
);
2470 ctx
->block_count
= 0;
2473 emit_cf_list(ctx
, &func
->impl
->body
);
2474 emit_block(ctx
, func
->impl
->end_block
);
2476 break; /* TODO: Multi-function shaders */
2479 util_dynarray_init(compiled
, NULL
);
2481 /* MIR-level optimizations */
2483 bool progress
= false;
2488 mir_foreach_block(ctx
, block
) {
2489 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2490 progress
|= midgard_opt_copy_prop(ctx
, block
);
2491 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
2492 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2496 /* Nested control-flow can result in dead branches at the end of the
2497 * block. This messes with our analysis and is just dead code, so cull
2499 mir_foreach_block(ctx
, block
) {
2500 midgard_opt_cull_dead_branch(ctx
, block
);
2504 schedule_program(ctx
);
2506 /* Now that all the bundles are scheduled and we can calculate block
2507 * sizes, emit actual branch instructions rather than placeholders */
2509 int br_block_idx
= 0;
2511 mir_foreach_block(ctx
, block
) {
2512 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2513 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2514 midgard_instruction
*ins
= bundle
->instructions
[c
];
2516 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2518 if (ins
->prepacked_branch
) continue;
2520 /* Parse some basic branch info */
2521 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2522 bool is_conditional
= ins
->branch
.conditional
;
2523 bool is_inverted
= ins
->branch
.invert_conditional
;
2524 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2526 /* Determine the block we're jumping to */
2527 int target_number
= ins
->branch
.target_block
;
2529 /* Report the destination tag */
2530 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2532 /* Count up the number of quadwords we're
2533 * jumping over = number of quadwords until
2534 * (br_block_idx, target_number) */
2536 int quadword_offset
= 0;
2539 /* Jump to the end of the shader. We
2540 * need to include not only the
2541 * following blocks, but also the
2542 * contents of our current block (since
2543 * discard can come in the middle of
2546 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2548 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2549 quadword_offset
+= quadword_size(bun
->tag
);
2552 mir_foreach_block_from(ctx
, blk
, b
) {
2553 quadword_offset
+= b
->quadword_count
;
2556 } else if (target_number
> br_block_idx
) {
2559 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2560 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2563 quadword_offset
+= blk
->quadword_count
;
2566 /* Jump backwards */
2568 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2569 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2572 quadword_offset
-= blk
->quadword_count
;
2576 /* Unconditional extended branches (far jumps)
2577 * have issues, so we always use a conditional
2578 * branch, setting the condition to always for
2579 * unconditional. For compact unconditional
2580 * branches, cond isn't used so it doesn't
2581 * matter what we pick. */
2583 midgard_condition cond
=
2584 !is_conditional
? midgard_condition_always
:
2585 is_inverted
? midgard_condition_false
:
2586 midgard_condition_true
;
2588 midgard_jmp_writeout_op op
=
2589 is_discard
? midgard_jmp_writeout_op_discard
:
2590 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2591 midgard_jmp_writeout_op_branch_cond
;
2594 midgard_branch_extended branch
=
2595 midgard_create_branch_extended(
2600 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2601 } else if (is_conditional
|| is_discard
) {
2602 midgard_branch_cond branch
= {
2604 .dest_tag
= dest_tag
,
2605 .offset
= quadword_offset
,
2609 assert(branch
.offset
== quadword_offset
);
2611 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2613 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2615 midgard_branch_uncond branch
= {
2617 .dest_tag
= dest_tag
,
2618 .offset
= quadword_offset
,
2622 assert(branch
.offset
== quadword_offset
);
2624 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2632 /* Emit flat binary from the instruction arrays. Iterate each block in
2633 * sequence. Save instruction boundaries such that lookahead tags can
2634 * be assigned easily */
2636 /* Cache _all_ bundles in source order for lookahead across failed branches */
2638 int bundle_count
= 0;
2639 mir_foreach_block(ctx
, block
) {
2640 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2642 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2644 mir_foreach_block(ctx
, block
) {
2645 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2646 source_order_bundles
[bundle_idx
++] = bundle
;
2650 int current_bundle
= 0;
2652 /* Midgard prefetches instruction types, so during emission we
2653 * need to lookahead. Unless this is the last instruction, in
2654 * which we return 1. Or if this is the second to last and the
2655 * last is an ALU, then it's also 1... */
2657 mir_foreach_block(ctx
, block
) {
2658 mir_foreach_bundle_in_block(block
, bundle
) {
2661 if (current_bundle
+ 1 < bundle_count
) {
2662 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2664 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2671 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2675 /* TODO: Free deeper */
2676 //util_dynarray_fini(&block->instructions);
2679 free(source_order_bundles
);
2681 /* Report the very first tag executed */
2682 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2684 /* Deal with off-by-one related to the fencepost problem */
2685 program
->work_register_count
= ctx
->work_registers
+ 1;
2687 program
->can_discard
= ctx
->can_discard
;
2688 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2690 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2692 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2693 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);