2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/register_allocate.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
50 #include "disassemble.h"
52 static const struct debug_named_value debug_options
[] = {
53 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
54 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
58 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
60 int midgard_debug
= 0;
62 #define DBG(fmt, ...) \
63 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
64 fprintf(stderr, "%s:%d: "fmt, \
65 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
67 /* Instruction arguments represented as block-local SSA indices, rather than
68 * registers. Negative values mean unused. */
75 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
76 * in. Only valid for ALU ops. */
80 /* Forward declare so midgard_branch can reference */
83 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
84 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
85 * instruction is actually a discard op. */
88 #define TARGET_BREAK 1
89 #define TARGET_CONTINUE 2
90 #define TARGET_DISCARD 3
92 typedef struct midgard_branch
{
93 /* If conditional, the condition is specified in r31.w */
96 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
97 bool invert_conditional
;
99 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
100 unsigned target_type
;
102 /* The actual target */
111 midgard_is_branch_unit(unsigned unit
)
113 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
116 /* Generic in-memory data type repesenting a single logical instruction, rather
117 * than a single instruction group. This is the preferred form for code gen.
118 * Multiple midgard_insturctions will later be combined during scheduling,
119 * though this is not represented in this structure. Its format bridges
120 * the low-level binary representation with the higher level semantic meaning.
122 * Notably, it allows registers to be specified as block local SSA, for code
123 * emitted before the register allocation pass.
126 typedef struct midgard_instruction
{
127 /* Must be first for casting */
128 struct list_head link
;
130 unsigned type
; /* ALU, load/store, texture */
132 /* If the register allocator has not run yet... */
135 /* Special fields for an ALU instruction */
136 midgard_reg_info registers
;
138 /* I.e. (1 << alu_bit) */
141 /* When emitting bundle, should this instruction have a break forced
142 * before it? Used for r31 writes which are valid only within a single
143 * bundle and *need* to happen as early as possible... this is a hack,
144 * TODO remove when we have a scheduler */
149 uint16_t inline_constant
;
150 bool has_blend_constant
;
154 bool prepacked_branch
;
157 midgard_load_store_word load_store
;
158 midgard_vector_alu alu
;
159 midgard_texture_word texture
;
160 midgard_branch_extended branch_extended
;
163 /* General branch, rather than packed br_compact. Higher level
164 * than the other components */
165 midgard_branch branch
;
167 } midgard_instruction
;
169 typedef struct midgard_block
{
170 /* Link to next block. Must be first for mir_get_block */
171 struct list_head link
;
173 /* List of midgard_instructions emitted for the current block */
174 struct list_head instructions
;
178 /* List of midgard_bundles emitted (after the scheduler has run) */
179 struct util_dynarray bundles
;
181 /* Number of quadwords _actually_ emitted, as determined after scheduling */
182 unsigned quadword_count
;
184 /* Successors: always one forward (the block after us), maybe
185 * one backwards (for a backward branch). No need for a second
186 * forward, since graph traversal would get there eventually
188 struct midgard_block
*successors
[2];
189 unsigned nr_successors
;
191 /* The successors pointer form a graph, and in the case of
192 * complex control flow, this graph has a cycles. To aid
193 * traversal during liveness analysis, we have a visited?
194 * boolean for passes to use as they see fit, provided they
200 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
202 block
->successors
[block
->nr_successors
++] = successor
;
203 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
206 /* Helpers to generate midgard_instruction's using macro magic, since every
207 * driver seems to do it that way */
209 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
210 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
212 #define M_LOAD_STORE(name, rname, uname) \
213 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
214 midgard_instruction i = { \
215 .type = TAG_LOAD_STORE_4, \
222 .op = midgard_op_##name, \
224 .swizzle = SWIZZLE_XYZW, \
232 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
233 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
235 const midgard_vector_alu_src blank_alu_src
= {
236 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
239 const midgard_vector_alu_src blank_alu_src_xxxx
= {
240 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
243 const midgard_scalar_alu_src blank_scalar_alu_src
= {
247 /* Used for encoding the unused source of 1-op instructions */
248 const midgard_vector_alu_src zero_alu_src
= { 0 };
250 /* Coerce structs to integer */
253 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
256 memcpy(&u
, &src
, sizeof(src
));
260 static midgard_vector_alu_src
261 vector_alu_from_unsigned(unsigned u
)
263 midgard_vector_alu_src s
;
264 memcpy(&s
, &u
, sizeof(s
));
268 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
269 * the corresponding Midgard source */
271 static midgard_vector_alu_src
272 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
274 if (!src
) return blank_alu_src
;
276 midgard_vector_alu_src alu_src
= {
279 .half
= 0, /* TODO */
280 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
284 /* TODO: sign-extend/zero-extend */
285 alu_src
.mod
= midgard_int_normal
;
287 /* These should have been lowered away */
288 assert(!(src
->abs
|| src
->negate
));
290 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
296 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
298 static midgard_instruction
299 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
301 midgard_instruction ins
= {
304 .src0
= SSA_UNUSED_1
,
309 .op
= midgard_alu_op_fmov
,
310 .reg_mode
= midgard_reg_mode_32
,
311 .dest_override
= midgard_dest_override_none
,
313 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
314 .src2
= vector_alu_srco_unsigned(mod
)
321 /* load/store instructions have both 32-bit and 16-bit variants, depending on
322 * whether we are using vectors composed of highp or mediump. At the moment, we
323 * don't support half-floats -- this requires changes in other parts of the
324 * compiler -- therefore the 16-bit versions are commented out. */
326 //M_LOAD(ld_attr_16);
328 //M_LOAD(ld_vary_16);
330 //M_LOAD(ld_uniform_16);
331 M_LOAD(ld_uniform_32
);
332 M_LOAD(ld_color_buffer_8
);
333 //M_STORE(st_vary_16);
335 M_STORE(st_cubemap_coords
);
337 static midgard_instruction
338 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
340 midgard_branch_cond branch
= {
348 memcpy(&compact
, &branch
, sizeof(branch
));
350 midgard_instruction ins
= {
352 .unit
= ALU_ENAB_BR_COMPACT
,
353 .prepacked_branch
= true,
354 .compact_branch
= true,
355 .br_compact
= compact
358 if (op
== midgard_jmp_writeout_op_writeout
)
364 static midgard_instruction
365 v_branch(bool conditional
, bool invert
)
367 midgard_instruction ins
= {
369 .unit
= ALU_ENAB_BRANCH
,
370 .compact_branch
= true,
372 .conditional
= conditional
,
373 .invert_conditional
= invert
380 static midgard_branch_extended
381 midgard_create_branch_extended( midgard_condition cond
,
382 midgard_jmp_writeout_op op
,
384 signed quadword_offset
)
386 /* For unclear reasons, the condition code is repeated 8 times */
387 uint16_t duplicated_cond
=
397 midgard_branch_extended branch
= {
399 .dest_tag
= dest_tag
,
400 .offset
= quadword_offset
,
401 .cond
= duplicated_cond
407 typedef struct midgard_bundle
{
408 /* Tag for the overall bundle */
411 /* Instructions contained by the bundle */
412 int instruction_count
;
413 midgard_instruction instructions
[5];
415 /* Bundle-wide ALU configuration */
418 bool has_embedded_constants
;
420 bool has_blend_constant
;
422 uint16_t register_words
[8];
423 int register_words_count
;
425 uint64_t body_words
[8];
427 int body_words_count
;
430 typedef struct compiler_context
{
432 gl_shader_stage stage
;
434 /* Is internally a blend shader? Depends on stage == FRAGMENT */
437 /* Tracking for blend constant patching */
438 int blend_constant_number
;
439 int blend_constant_offset
;
441 /* Current NIR function */
444 /* Unordered list of midgard_blocks */
446 struct list_head blocks
;
448 midgard_block
*initial_block
;
449 midgard_block
*previous_source_block
;
450 midgard_block
*final_block
;
452 /* List of midgard_instructions emitted for the current block */
453 midgard_block
*current_block
;
455 /* The current "depth" of the loop, for disambiguating breaks/continues
456 * when using nested loops */
457 int current_loop_depth
;
459 /* Constants which have been loaded, for later inlining */
460 struct hash_table_u64
*ssa_constants
;
462 /* SSA indices to be outputted to corresponding varying offset */
463 struct hash_table_u64
*ssa_varyings
;
465 /* SSA values / registers which have been aliased. Naively, these
466 * demand a fmov output; instead, we alias them in a later pass to
467 * avoid the wasted op.
469 * A note on encoding: to avoid dynamic memory management here, rather
470 * than ampping to a pointer, we map to the source index; the key
471 * itself is just the destination index. */
473 struct hash_table_u64
*ssa_to_alias
;
474 struct set
*leftover_ssa_to_alias
;
476 /* Actual SSA-to-register for RA */
477 struct hash_table_u64
*ssa_to_register
;
479 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
480 struct hash_table_u64
*hash_to_temp
;
484 /* Just the count of the max register used. Higher count => higher
485 * register pressure */
488 /* Used for cont/last hinting. Increase when a tex op is added.
489 * Decrease when a tex op is removed. */
490 int texture_op_count
;
492 /* Mapping of texture register -> SSA index for unaliasing */
493 int texture_index
[2];
495 /* If any path hits a discard instruction */
498 /* The number of uniforms allowable for the fast path */
501 /* Count of instructions emitted from NIR overall, across all blocks */
502 int instruction_count
;
504 /* Alpha ref value passed in */
507 /* The index corresponding to the fragment output */
508 unsigned fragment_output
;
510 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
511 unsigned sysvals
[MAX_SYSVAL_COUNT
];
512 unsigned sysval_count
;
513 struct hash_table_u64
*sysval_to_id
;
516 /* Append instruction to end of current block */
518 static midgard_instruction
*
519 mir_upload_ins(struct midgard_instruction ins
)
521 midgard_instruction
*heap
= malloc(sizeof(ins
));
522 memcpy(heap
, &ins
, sizeof(ins
));
527 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
529 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
533 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
535 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
539 mir_remove_instruction(struct midgard_instruction
*ins
)
541 list_del(&ins
->link
);
544 static midgard_instruction
*
545 mir_prev_op(struct midgard_instruction
*ins
)
547 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
550 static midgard_instruction
*
551 mir_next_op(struct midgard_instruction
*ins
)
553 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
556 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
557 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
559 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
560 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
561 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
562 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
563 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
564 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
565 #define mir_foreach_instr_in_block_from_rev(block, v, from) list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
568 static midgard_instruction
*
569 mir_last_in_block(struct midgard_block
*block
)
571 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
574 static midgard_block
*
575 mir_get_block(compiler_context
*ctx
, int idx
)
577 struct list_head
*lst
= &ctx
->blocks
;
582 return (struct midgard_block
*) lst
;
585 /* Pretty printer for internal Midgard IR */
588 print_mir_source(int source
)
590 if (source
>= SSA_FIXED_MINIMUM
) {
591 /* Specific register */
592 int reg
= SSA_REG_FROM_FIXED(source
);
594 /* TODO: Moving threshold */
595 if (reg
> 16 && reg
< 24)
596 printf("u%d", 23 - reg
);
600 printf("%d", source
);
605 print_mir_instruction(midgard_instruction
*ins
)
611 midgard_alu_op op
= ins
->alu
.op
;
612 const char *name
= alu_opcode_props
[op
].name
;
615 printf("%d.", ins
->unit
);
617 printf("%s", name
? name
: "??");
621 case TAG_LOAD_STORE_4
: {
622 midgard_load_store_op op
= ins
->load_store
.op
;
623 const char *name
= load_store_opcode_names
[op
];
630 case TAG_TEXTURE_4
: {
639 ssa_args
*args
= &ins
->ssa_args
;
641 printf(" %d, ", args
->dest
);
643 print_mir_source(args
->src0
);
646 if (args
->inline_constant
)
647 printf("#%d", ins
->inline_constant
);
649 print_mir_source(args
->src1
);
651 if (ins
->has_constants
)
652 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
658 print_mir_block(midgard_block
*block
)
662 mir_foreach_instr_in_block(block
, ins
) {
663 print_mir_instruction(ins
);
670 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
672 ins
->has_constants
= true;
673 memcpy(&ins
->constants
, constants
, 16);
675 /* If this is the special blend constant, mark this instruction */
677 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
678 ins
->has_blend_constant
= true;
682 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
684 return glsl_count_attribute_slots(type
, false);
687 /* Lower fdot2 to a vector multiplication followed by channel addition */
689 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
691 if (alu
->op
!= nir_op_fdot2
)
694 b
->cursor
= nir_before_instr(&alu
->instr
);
696 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
697 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
699 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
701 nir_ssa_def
*sum
= nir_fadd(b
,
702 nir_channel(b
, product
, 0),
703 nir_channel(b
, product
, 1));
705 /* Replace the fdot2 with this sum */
706 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
710 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
712 switch (instr
->intrinsic
) {
713 case nir_intrinsic_load_viewport_scale
:
714 return PAN_SYSVAL_VIEWPORT_SCALE
;
715 case nir_intrinsic_load_viewport_offset
:
716 return PAN_SYSVAL_VIEWPORT_OFFSET
;
723 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
727 if (instr
->type
== nir_instr_type_intrinsic
) {
728 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
729 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
735 /* We have a sysval load; check if it's already been assigned */
737 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
740 /* It hasn't -- so assign it now! */
742 unsigned id
= ctx
->sysval_count
++;
743 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
744 ctx
->sysvals
[id
] = sysval
;
748 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
750 ctx
->sysval_count
= 0;
752 nir_foreach_function(function
, shader
) {
753 if (!function
->impl
) continue;
755 nir_foreach_block(block
, function
->impl
) {
756 nir_foreach_instr_safe(instr
, block
) {
757 midgard_nir_assign_sysval_body(ctx
, instr
);
764 midgard_nir_lower_fdot2(nir_shader
*shader
)
766 bool progress
= false;
768 nir_foreach_function(function
, shader
) {
769 if (!function
->impl
) continue;
772 nir_builder
*b
= &_b
;
773 nir_builder_init(b
, function
->impl
);
775 nir_foreach_block(block
, function
->impl
) {
776 nir_foreach_instr_safe(instr
, block
) {
777 if (instr
->type
!= nir_instr_type_alu
) continue;
779 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
780 midgard_nir_lower_fdot2_body(b
, alu
);
786 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
794 optimise_nir(nir_shader
*nir
)
797 unsigned lower_flrp
=
798 (nir
->options
->lower_flrp16
? 16 : 0) |
799 (nir
->options
->lower_flrp32
? 32 : 0) |
800 (nir
->options
->lower_flrp64
? 64 : 0);
802 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
803 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
805 nir_lower_tex_options lower_tex_options
= {
809 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
814 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
815 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
817 NIR_PASS(progress
, nir
, nir_copy_prop
);
818 NIR_PASS(progress
, nir
, nir_opt_dce
);
819 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
820 NIR_PASS(progress
, nir
, nir_opt_cse
);
821 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
822 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
823 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
825 if (lower_flrp
!= 0) {
826 bool lower_flrp_progress
= false;
827 NIR_PASS(lower_flrp_progress
,
831 false /* always_precise */,
832 nir
->options
->lower_ffma
);
833 if (lower_flrp_progress
) {
834 NIR_PASS(progress
, nir
,
835 nir_opt_constant_folding
);
839 /* Nothing should rematerialize any flrps, so we only
840 * need to do this lowering once.
845 NIR_PASS(progress
, nir
, nir_opt_undef
);
846 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
849 nir_var_function_temp
);
851 /* TODO: Enable vectorize when merged upstream */
852 // NIR_PASS(progress, nir, nir_opt_vectorize);
855 /* Must be run at the end to prevent creation of fsin/fcos ops */
856 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
861 NIR_PASS(progress
, nir
, nir_opt_dce
);
862 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
863 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
864 NIR_PASS(progress
, nir
, nir_copy_prop
);
867 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
869 /* We implement booleans as 32-bit 0/~0 */
870 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
872 /* Now that booleans are lowered, we can run out late opts */
873 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
875 /* Lower mods for float ops only. Integer ops don't support modifiers
876 * (saturate doesn't make sense on integers, neg/abs require dedicated
879 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
880 NIR_PASS(progress
, nir
, nir_copy_prop
);
881 NIR_PASS(progress
, nir
, nir_opt_dce
);
883 /* Take us out of SSA */
884 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
885 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
887 /* We are a vector architecture; write combine where possible */
888 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
889 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
891 NIR_PASS(progress
, nir
, nir_opt_dce
);
894 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
895 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
896 * r0. See the comments in compiler_context */
899 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
901 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
902 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
905 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
908 unalias_ssa(compiler_context
*ctx
, int dest
)
910 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
911 /* TODO: Remove from leftover or no? */
915 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
917 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
921 midgard_is_pinned(compiler_context
*ctx
, int index
)
923 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
926 /* Do not actually emit a load; instead, cache the constant for inlining */
929 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
931 nir_ssa_def def
= instr
->def
;
933 float *v
= rzalloc_array(NULL
, float, 4);
934 nir_const_load_to_arr(v
, instr
, f32
);
935 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
938 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
942 expand_writemask(unsigned mask
)
946 for (int i
= 0; i
< 4; ++i
)
954 squeeze_writemask(unsigned mask
)
958 for (int i
= 0; i
< 4; ++i
)
959 if (mask
& (3 << (2 * i
)))
966 /* Determines effective writemask, taking quirks and expansion into account */
968 effective_writemask(midgard_vector_alu
*alu
)
970 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
973 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
].props
);
975 /* If there is a fixed channel count, construct the appropriate mask */
978 return (1 << channel_count
) - 1;
980 /* Otherwise, just squeeze the existing mask */
981 return squeeze_writemask(alu
->mask
);
985 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
987 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
990 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
995 /* If no temp is find, allocate one */
996 temp
= ctx
->temp_count
++;
997 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
999 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
1005 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
1008 return src
->ssa
->index
;
1010 assert(!src
->reg
.indirect
);
1011 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
1016 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
1019 return dst
->ssa
.index
;
1021 assert(!dst
->reg
.indirect
);
1022 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
1027 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
1029 return nir_src_index(ctx
, &src
->src
);
1033 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
1035 unsigned comp
= src
->swizzle
[0];
1037 for (unsigned c
= 1; c
< nr_components
; ++c
) {
1038 if (src
->swizzle
[c
] != comp
)
1045 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
1046 * output of a conditional test) into that register */
1049 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
1051 int condition
= nir_src_index(ctx
, src
);
1053 /* Source to swizzle the desired component into w */
1055 const midgard_vector_alu_src alu_src
= {
1056 .swizzle
= SWIZZLE(component
, component
, component
, component
),
1059 /* There is no boolean move instruction. Instead, we simulate a move by
1060 * ANDing the condition with itself to get it into r31.w */
1062 midgard_instruction ins
= {
1065 /* We need to set the conditional as close as possible */
1066 .precede_break
= true,
1067 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
1073 .dest
= SSA_FIXED_REGISTER(31),
1076 .op
= midgard_alu_op_iand
,
1077 .reg_mode
= midgard_reg_mode_32
,
1078 .dest_override
= midgard_dest_override_none
,
1079 .mask
= (0x3 << 6), /* w */
1080 .src1
= vector_alu_srco_unsigned(alu_src
),
1081 .src2
= vector_alu_srco_unsigned(alu_src
)
1085 emit_mir_instruction(ctx
, ins
);
1088 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
1092 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
1094 int condition
= nir_src_index(ctx
, &src
->src
);
1096 /* Source to swizzle the desired component into w */
1098 const midgard_vector_alu_src alu_src
= {
1099 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
1102 /* There is no boolean move instruction. Instead, we simulate a move by
1103 * ANDing the condition with itself to get it into r31.w */
1105 midgard_instruction ins
= {
1107 .precede_break
= true,
1111 .dest
= SSA_FIXED_REGISTER(31),
1114 .op
= midgard_alu_op_iand
,
1115 .reg_mode
= midgard_reg_mode_32
,
1116 .dest_override
= midgard_dest_override_none
,
1117 .mask
= expand_writemask((1 << nr_comp
) - 1),
1118 .src1
= vector_alu_srco_unsigned(alu_src
),
1119 .src2
= vector_alu_srco_unsigned(alu_src
)
1123 emit_mir_instruction(ctx
, ins
);
1128 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
1129 * pinning to eliminate this move in all known cases */
1132 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
1134 int offset
= nir_src_index(ctx
, src
);
1136 midgard_instruction ins
= {
1139 .src0
= SSA_UNUSED_1
,
1141 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
1144 .op
= midgard_alu_op_imov
,
1145 .reg_mode
= midgard_reg_mode_32
,
1146 .dest_override
= midgard_dest_override_none
,
1147 .mask
= (0x3 << 6), /* w */
1148 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
1149 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
1153 emit_mir_instruction(ctx
, ins
);
1156 #define ALU_CASE(nir, _op) \
1157 case nir_op_##nir: \
1158 op = midgard_alu_op_##_op; \
1161 nir_is_fzero_constant(nir_src src
)
1163 if (!nir_src_is_const(src
))
1166 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
1167 if (nir_src_comp_as_float(src
, c
) != 0.0)
1175 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
1177 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
1179 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
1180 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
1181 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
1183 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
1184 * supported. A few do not and are commented for now. Also, there are a
1185 * number of NIR ops which Midgard does not support and need to be
1186 * lowered, also TODO. This switch block emits the opcode and calling
1187 * convention of the Midgard instruction; actual packing is done in
1192 switch (instr
->op
) {
1193 ALU_CASE(fadd
, fadd
);
1194 ALU_CASE(fmul
, fmul
);
1195 ALU_CASE(fmin
, fmin
);
1196 ALU_CASE(fmax
, fmax
);
1197 ALU_CASE(imin
, imin
);
1198 ALU_CASE(imax
, imax
);
1199 ALU_CASE(umin
, umin
);
1200 ALU_CASE(umax
, umax
);
1201 ALU_CASE(fmov
, fmov
);
1202 ALU_CASE(ffloor
, ffloor
);
1203 ALU_CASE(fround_even
, froundeven
);
1204 ALU_CASE(ftrunc
, ftrunc
);
1205 ALU_CASE(fceil
, fceil
);
1206 ALU_CASE(fdot3
, fdot3
);
1207 ALU_CASE(fdot4
, fdot4
);
1208 ALU_CASE(iadd
, iadd
);
1209 ALU_CASE(isub
, isub
);
1210 ALU_CASE(imul
, imul
);
1211 ALU_CASE(iabs
, iabs
);
1212 ALU_CASE(imov
, imov
);
1214 ALU_CASE(feq32
, feq
);
1215 ALU_CASE(fne32
, fne
);
1216 ALU_CASE(flt32
, flt
);
1217 ALU_CASE(ieq32
, ieq
);
1218 ALU_CASE(ine32
, ine
);
1219 ALU_CASE(ilt32
, ilt
);
1220 ALU_CASE(ult32
, ult
);
1222 /* We don't have a native b2f32 instruction. Instead, like many
1223 * GPUs, we exploit booleans as 0/~0 for false/true, and
1224 * correspondingly AND
1225 * by 1.0 to do the type conversion. For the moment, prime us
1228 * iand [whatever], #0
1230 * At the end of emit_alu (as MIR), we'll fix-up the constant
1233 ALU_CASE(b2f32
, iand
);
1234 ALU_CASE(b2i32
, iand
);
1236 /* Likewise, we don't have a dedicated f2b32 instruction, but
1237 * we can do a "not equal to 0.0" test. */
1239 ALU_CASE(f2b32
, fne
);
1240 ALU_CASE(i2b32
, ine
);
1242 ALU_CASE(frcp
, frcp
);
1243 ALU_CASE(frsq
, frsqrt
);
1244 ALU_CASE(fsqrt
, fsqrt
);
1245 ALU_CASE(fexp2
, fexp2
);
1246 ALU_CASE(flog2
, flog2
);
1248 ALU_CASE(f2i32
, f2i
);
1249 ALU_CASE(f2u32
, f2u
);
1250 ALU_CASE(i2f32
, i2f
);
1251 ALU_CASE(u2f32
, u2f
);
1253 ALU_CASE(fsin
, fsin
);
1254 ALU_CASE(fcos
, fcos
);
1256 ALU_CASE(iand
, iand
);
1258 ALU_CASE(ixor
, ixor
);
1259 ALU_CASE(inot
, inand
);
1260 ALU_CASE(ishl
, ishl
);
1261 ALU_CASE(ishr
, iasr
);
1262 ALU_CASE(ushr
, ilsr
);
1264 ALU_CASE(b32all_fequal2
, fball_eq
);
1265 ALU_CASE(b32all_fequal3
, fball_eq
);
1266 ALU_CASE(b32all_fequal4
, fball_eq
);
1268 ALU_CASE(b32any_fnequal2
, fbany_neq
);
1269 ALU_CASE(b32any_fnequal3
, fbany_neq
);
1270 ALU_CASE(b32any_fnequal4
, fbany_neq
);
1272 ALU_CASE(b32all_iequal2
, iball_eq
);
1273 ALU_CASE(b32all_iequal3
, iball_eq
);
1274 ALU_CASE(b32all_iequal4
, iball_eq
);
1276 ALU_CASE(b32any_inequal2
, ibany_neq
);
1277 ALU_CASE(b32any_inequal3
, ibany_neq
);
1278 ALU_CASE(b32any_inequal4
, ibany_neq
);
1280 /* For greater-or-equal, we lower to less-or-equal and flip the
1286 case nir_op_uge32
: {
1288 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
1289 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
1290 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
1291 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
1294 /* Swap via temporary */
1295 nir_alu_src temp
= instr
->src
[1];
1296 instr
->src
[1] = instr
->src
[0];
1297 instr
->src
[0] = temp
;
1302 case nir_op_b32csel
: {
1303 /* Midgard features both fcsel and icsel, depending on
1304 * the type of the arguments/output. However, as long
1305 * as we're careful we can _always_ use icsel and
1306 * _never_ need fcsel, since the latter does additional
1307 * floating-point-specific processing whereas the
1308 * former just moves bits on the wire. It's not obvious
1309 * why these are separate opcodes, save for the ability
1310 * to do things like sat/pos/abs/neg for free */
1312 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
1313 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
1315 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
1318 /* Emit the condition into r31 */
1321 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
1323 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
1325 /* The condition is the first argument; move the other
1326 * arguments up one to be a binary instruction for
1329 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
1334 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1339 /* Midgard can perform certain modifiers on output of an ALU op */
1340 midgard_outmod outmod
=
1341 midgard_is_integer_out_op(op
) ? midgard_outmod_int
:
1342 instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1344 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1346 if (instr
->op
== nir_op_fmax
) {
1347 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1348 op
= midgard_alu_op_fmov
;
1350 outmod
= midgard_outmod_pos
;
1351 instr
->src
[0] = instr
->src
[1];
1352 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1353 op
= midgard_alu_op_fmov
;
1355 outmod
= midgard_outmod_pos
;
1359 /* Fetch unit, quirks, etc information */
1360 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1361 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1363 /* src0 will always exist afaik, but src1 will not for 1-argument
1364 * instructions. The latter can only be fetched if the instruction
1365 * needs it, or else we may segfault. */
1367 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1368 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1370 /* Rather than use the instruction generation helpers, we do it
1371 * ourselves here to avoid the mess */
1373 midgard_instruction ins
= {
1376 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1377 .src1
= quirk_flipped_r24
? src0
: src1
,
1382 nir_alu_src
*nirmods
[2] = { NULL
};
1384 if (nr_inputs
== 2) {
1385 nirmods
[0] = &instr
->src
[0];
1386 nirmods
[1] = &instr
->src
[1];
1387 } else if (nr_inputs
== 1) {
1388 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1393 bool is_int
= midgard_is_integer_op(op
);
1395 midgard_vector_alu alu
= {
1397 .reg_mode
= midgard_reg_mode_32
,
1398 .dest_override
= midgard_dest_override_none
,
1401 /* Writemask only valid for non-SSA NIR */
1402 .mask
= expand_writemask((1 << nr_components
) - 1),
1404 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
1405 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
1408 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1411 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1415 /* Late fixup for emulated instructions */
1417 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1418 /* Presently, our second argument is an inline #0 constant.
1419 * Switch over to an embedded 1.0 constant (that can't fit
1420 * inline, since we're 32-bit, not 16-bit like the inline
1423 ins
.ssa_args
.inline_constant
= false;
1424 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1425 ins
.has_constants
= true;
1427 if (instr
->op
== nir_op_b2f32
) {
1428 ins
.constants
[0] = 1.0f
;
1430 /* Type pun it into place */
1432 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1435 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1436 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
1437 ins
.ssa_args
.inline_constant
= false;
1438 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1439 ins
.has_constants
= true;
1440 ins
.constants
[0] = 0.0f
;
1441 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1442 } else if (instr
->op
== nir_op_inot
) {
1443 /* ~b = ~(b & b), so duplicate the source */
1444 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1445 ins
.alu
.src2
= ins
.alu
.src1
;
1448 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1449 /* To avoid duplicating the lookup tables (probably), true LUT
1450 * instructions can only operate as if they were scalars. Lower
1451 * them here by changing the component. */
1453 uint8_t original_swizzle
[4];
1454 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1456 for (int i
= 0; i
< nr_components
; ++i
) {
1457 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1459 for (int j
= 0; j
< 4; ++j
)
1460 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1462 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
1463 emit_mir_instruction(ctx
, ins
);
1466 emit_mir_instruction(ctx
, ins
);
1473 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1475 /* TODO: half-floats */
1477 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1478 /* Fast path: For the first 16 uniforms, direct accesses are
1479 * 0-cycle, since they're just a register fetch in the usual
1480 * case. So, we alias the registers while we're still in
1483 int reg_slot
= 23 - offset
;
1484 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1486 /* Otherwise, read from the 'special' UBO to access
1487 * higher-indexed uniforms, at a performance cost. More
1488 * generally, we're emitting a UBO read instruction. */
1490 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1492 /* TODO: Don't split */
1493 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1494 ins
.load_store
.address
= offset
>> 3;
1496 if (indirect_offset
) {
1497 emit_indirect_offset(ctx
, indirect_offset
);
1498 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1500 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1503 emit_mir_instruction(ctx
, ins
);
1508 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1510 /* First, pull out the destination */
1511 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1513 /* Now, figure out which uniform this is */
1514 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1515 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1517 /* Sysvals are prefix uniforms */
1518 unsigned uniform
= ((uintptr_t) val
) - 1;
1520 /* Emit the read itself -- this is never indirect */
1521 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1525 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1527 unsigned offset
, reg
;
1529 switch (instr
->intrinsic
) {
1530 case nir_intrinsic_discard_if
:
1531 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1535 case nir_intrinsic_discard
: {
1536 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1537 struct midgard_instruction discard
= v_branch(conditional
, false);
1538 discard
.branch
.target_type
= TARGET_DISCARD
;
1539 emit_mir_instruction(ctx
, discard
);
1541 ctx
->can_discard
= true;
1545 case nir_intrinsic_load_uniform
:
1546 case nir_intrinsic_load_input
:
1547 offset
= nir_intrinsic_base(instr
);
1549 bool direct
= nir_src_is_const(instr
->src
[0]);
1552 offset
+= nir_src_as_uint(instr
->src
[0]);
1555 reg
= nir_dest_index(ctx
, &instr
->dest
);
1557 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1558 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1559 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1560 /* XXX: Half-floats? */
1561 /* TODO: swizzle, mask */
1563 midgard_instruction ins
= m_ld_vary_32(reg
, offset
);
1565 midgard_varying_parameter p
= {
1567 .interpolation
= midgard_interp_default
,
1568 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1572 memcpy(&u
, &p
, sizeof(p
));
1573 ins
.load_store
.varying_parameters
= u
;
1576 /* We have the offset totally ready */
1577 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1579 /* We have it partially ready, but we need to
1580 * add in the dynamic index, moved to r27.w */
1581 emit_indirect_offset(ctx
, &instr
->src
[0]);
1582 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1585 emit_mir_instruction(ctx
, ins
);
1586 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1587 /* Constant encoded as a pinned constant */
1589 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1590 ins
.has_constants
= true;
1591 ins
.has_blend_constant
= true;
1592 emit_mir_instruction(ctx
, ins
);
1593 } else if (ctx
->is_blend
) {
1594 /* For blend shaders, a load might be
1595 * translated various ways depending on what
1596 * we're loading. Figure out how this is used */
1598 nir_variable
*out
= NULL
;
1600 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1601 int drvloc
= var
->data
.driver_location
;
1603 if (nir_intrinsic_base(instr
) == drvloc
) {
1611 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1612 /* Source color preloaded to r0 */
1614 midgard_pin_output(ctx
, reg
, 0);
1615 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1616 /* Destination color must be read from framebuffer */
1618 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1619 ins
.load_store
.swizzle
= 0; /* xxxx */
1621 /* Read each component sequentially */
1623 for (int c
= 0; c
< 4; ++c
) {
1624 ins
.load_store
.mask
= (1 << c
);
1625 ins
.load_store
.unknown
= c
;
1626 emit_mir_instruction(ctx
, ins
);
1629 /* vadd.u2f hr2, zext(hr2), #0 */
1631 midgard_vector_alu_src alu_src
= blank_alu_src
;
1632 alu_src
.mod
= midgard_int_zero_extend
;
1633 alu_src
.half
= true;
1635 midgard_instruction u2f
= {
1639 .src1
= SSA_UNUSED_0
,
1641 .inline_constant
= true
1644 .op
= midgard_alu_op_u2f
,
1645 .reg_mode
= midgard_reg_mode_16
,
1646 .dest_override
= midgard_dest_override_none
,
1648 .src1
= vector_alu_srco_unsigned(alu_src
),
1649 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1653 emit_mir_instruction(ctx
, u2f
);
1655 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1659 midgard_instruction fmul
= {
1661 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1665 .src1
= SSA_UNUSED_0
,
1666 .inline_constant
= true
1669 .op
= midgard_alu_op_fmul
,
1670 .reg_mode
= midgard_reg_mode_32
,
1671 .dest_override
= midgard_dest_override_none
,
1672 .outmod
= midgard_outmod_sat
,
1674 .src1
= vector_alu_srco_unsigned(alu_src
),
1675 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1679 emit_mir_instruction(ctx
, fmul
);
1681 DBG("Unknown input in blend shader\n");
1684 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1685 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1686 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1687 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1688 emit_mir_instruction(ctx
, ins
);
1690 DBG("Unknown load\n");
1696 case nir_intrinsic_store_output
:
1697 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1699 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1701 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1703 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1704 /* gl_FragColor is not emitted with load/store
1705 * instructions. Instead, it gets plonked into
1706 * r0 at the end of the shader and we do the
1707 * framebuffer writeout dance. TODO: Defer
1710 midgard_pin_output(ctx
, reg
, 0);
1712 /* Save the index we're writing to for later reference
1713 * in the epilogue */
1715 ctx
->fragment_output
= reg
;
1716 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1717 /* Varyings are written into one of two special
1718 * varying register, r26 or r27. The register itself is selected as the register
1719 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1721 * Normally emitting fmov's is frowned upon,
1722 * but due to unique constraints of
1723 * REGISTER_VARYING, fmov emission + a
1724 * dedicated cleanup pass is the only way to
1725 * guarantee correctness when considering some
1726 * (common) edge cases XXX: FIXME */
1728 /* If this varying corresponds to a constant (why?!),
1729 * emit that now since it won't get picked up by
1730 * hoisting (since there is no corresponding move
1731 * emitted otherwise) */
1733 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1735 if (constant_value
) {
1736 /* Special case: emit the varying write
1737 * directly to r26 (looks funny in asm but it's
1738 * fine) and emit the store _now_. Possibly
1739 * slightly slower, but this is a really stupid
1740 * special case anyway (why on earth would you
1741 * have a constant varying? Your own fault for
1742 * slightly worse perf :P) */
1744 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1745 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1746 emit_mir_instruction(ctx
, ins
);
1748 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1749 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1750 emit_mir_instruction(ctx
, st
);
1752 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1754 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1757 DBG("Unknown store\n");
1763 case nir_intrinsic_load_alpha_ref_float
:
1764 assert(instr
->dest
.is_ssa
);
1766 float ref_value
= ctx
->alpha_ref
;
1768 float *v
= ralloc_array(NULL
, float, 4);
1769 memcpy(v
, &ref_value
, sizeof(float));
1770 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1773 case nir_intrinsic_load_viewport_scale
:
1774 case nir_intrinsic_load_viewport_offset
:
1775 emit_sysval_read(ctx
, instr
);
1779 printf ("Unhandled intrinsic\n");
1786 midgard_tex_format(enum glsl_sampler_dim dim
)
1789 case GLSL_SAMPLER_DIM_2D
:
1790 case GLSL_SAMPLER_DIM_EXTERNAL
:
1793 case GLSL_SAMPLER_DIM_3D
:
1796 case GLSL_SAMPLER_DIM_CUBE
:
1797 return TEXTURE_CUBE
;
1800 DBG("Unknown sampler dim type\n");
1807 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1810 //assert (!instr->sampler);
1811 //assert (!instr->texture_array_size);
1812 assert (instr
->op
== nir_texop_tex
);
1814 /* Allocate registers via a round robin scheme to alternate between the two registers */
1815 int reg
= ctx
->texture_op_count
& 1;
1816 int in_reg
= reg
, out_reg
= reg
;
1818 /* Make room for the reg */
1820 if (ctx
->texture_index
[reg
] > -1)
1821 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1823 int texture_index
= instr
->texture_index
;
1824 int sampler_index
= texture_index
;
1826 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1827 switch (instr
->src
[i
].src_type
) {
1828 case nir_tex_src_coord
: {
1829 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1831 midgard_vector_alu_src alu_src
= blank_alu_src
;
1833 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1835 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1836 /* For cubemaps, we need to load coords into
1837 * special r27, and then use a special ld/st op
1838 * to copy into the texture register */
1840 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1842 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1843 emit_mir_instruction(ctx
, move
);
1845 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1846 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1847 st
.load_store
.mask
= 0x3; /* xy? */
1848 st
.load_store
.swizzle
= alu_src
.swizzle
;
1849 emit_mir_instruction(ctx
, st
);
1852 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1854 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1855 emit_mir_instruction(ctx
, ins
);
1862 DBG("Unknown source type\n");
1869 /* No helper to build texture words -- we do it all here */
1870 midgard_instruction ins
= {
1871 .type
= TAG_TEXTURE_4
,
1873 .op
= TEXTURE_OP_NORMAL
,
1874 .format
= midgard_tex_format(instr
->sampler_dim
),
1875 .texture_handle
= texture_index
,
1876 .sampler_handle
= sampler_index
,
1878 /* TODO: Don't force xyzw */
1879 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1891 /* Assume we can continue; hint it out later */
1896 /* Set registers to read and write from the same place */
1897 ins
.texture
.in_reg_select
= in_reg
;
1898 ins
.texture
.out_reg_select
= out_reg
;
1900 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1901 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1902 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1903 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1904 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1906 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1907 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1908 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1911 emit_mir_instruction(ctx
, ins
);
1913 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1915 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1916 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1917 ctx
->texture_index
[reg
] = o_index
;
1919 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1920 emit_mir_instruction(ctx
, ins2
);
1922 /* Used for .cont and .last hinting */
1923 ctx
->texture_op_count
++;
1927 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1929 switch (instr
->type
) {
1930 case nir_jump_break
: {
1931 /* Emit a branch out of the loop */
1932 struct midgard_instruction br
= v_branch(false, false);
1933 br
.branch
.target_type
= TARGET_BREAK
;
1934 br
.branch
.target_break
= ctx
->current_loop_depth
;
1935 emit_mir_instruction(ctx
, br
);
1942 DBG("Unknown jump type %d\n", instr
->type
);
1948 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1950 switch (instr
->type
) {
1951 case nir_instr_type_load_const
:
1952 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1955 case nir_instr_type_intrinsic
:
1956 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1959 case nir_instr_type_alu
:
1960 emit_alu(ctx
, nir_instr_as_alu(instr
));
1963 case nir_instr_type_tex
:
1964 emit_tex(ctx
, nir_instr_as_tex(instr
));
1967 case nir_instr_type_jump
:
1968 emit_jump(ctx
, nir_instr_as_jump(instr
));
1971 case nir_instr_type_ssa_undef
:
1976 DBG("Unhandled instruction type\n");
1981 /* Determine the actual hardware from the index based on the RA results or special values */
1984 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1986 if (reg
>= SSA_FIXED_MINIMUM
)
1987 return SSA_REG_FROM_FIXED(reg
);
1990 assert(reg
< maxreg
);
1992 int r
= ra_get_node_reg(g
, reg
);
1993 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1998 /* fmov style unused */
2000 return REGISTER_UNUSED
;
2002 /* lut style unused */
2004 return REGISTER_UNUSED
;
2007 DBG("Unknown SSA register alias %d\n", reg
);
2014 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
2016 /* Choose the first available register to minimise reported register pressure */
2018 for (int i
= 0; i
< 16; ++i
) {
2019 if (BITSET_TEST(regs
, i
)) {
2029 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
2031 if (ins
->ssa_args
.src0
== src
) return true;
2032 if (ins
->ssa_args
.src1
== src
) return true;
2037 /* Determine if a variable is live in the successors of a block */
2039 is_live_after_successors(compiler_context
*ctx
, midgard_block
*bl
, int src
)
2041 for (unsigned i
= 0; i
< bl
->nr_successors
; ++i
) {
2042 midgard_block
*succ
= bl
->successors
[i
];
2044 /* If we already visited, the value we're seeking
2045 * isn't down this path (or we would have short
2048 if (succ
->visited
) continue;
2050 /* Otherwise (it's visited *now*), check the block */
2052 succ
->visited
= true;
2054 mir_foreach_instr_in_block(succ
, ins
) {
2055 if (midgard_is_live_in_instr(ins
, src
))
2059 /* ...and also, check *its* successors */
2060 if (is_live_after_successors(ctx
, succ
, src
))
2065 /* Welp. We're really not live. */
2071 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
2073 /* Check the rest of the block for liveness */
2075 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
2076 if (midgard_is_live_in_instr(ins
, src
))
2080 /* Check the rest of the blocks for liveness recursively */
2082 bool succ
= is_live_after_successors(ctx
, block
, src
);
2084 mir_foreach_block(ctx
, block
) {
2085 block
->visited
= false;
2091 /* Once registers have been decided via register allocation
2092 * (allocate_registers), we need to rewrite the MIR to use registers instead of
2096 install_registers(compiler_context
*ctx
, struct ra_graph
*g
)
2098 mir_foreach_block(ctx
, block
) {
2099 mir_foreach_instr_in_block(block
, ins
) {
2100 if (ins
->compact_branch
) continue;
2102 ssa_args args
= ins
->ssa_args
;
2104 switch (ins
->type
) {
2106 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, ctx
->temp_count
);
2108 ins
->registers
.src2_imm
= args
.inline_constant
;
2110 if (args
.inline_constant
) {
2111 /* Encode inline 16-bit constant as a vector by default */
2113 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
2115 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2117 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
2118 ins
->alu
.src2
= imm
<< 2;
2120 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, ctx
->temp_count
);
2123 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, ctx
->temp_count
);
2127 case TAG_LOAD_STORE_4
: {
2128 if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
2129 /* TODO: use ssa_args for st_vary */
2130 ins
->load_store
.reg
= 0;
2132 bool has_dest
= args
.dest
>= 0;
2133 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
2135 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, ctx
->temp_count
);
2149 /* This routine performs the actual register allocation. It should be succeeded
2150 * by install_registers */
2152 static struct ra_graph
*
2153 allocate_registers(compiler_context
*ctx
)
2155 /* First, initialize the RA */
2156 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
2158 /* Create a primary (general purpose) class, as well as special purpose
2159 * pipeline register classes */
2161 int primary_class
= ra_alloc_reg_class(regs
);
2162 int varying_class
= ra_alloc_reg_class(regs
);
2164 /* Add the full set of work registers */
2165 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
2166 for (int i
= 0; i
< work_count
; ++i
)
2167 ra_class_add_reg(regs
, primary_class
, i
);
2169 /* Add special registers */
2170 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
2171 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
2173 /* We're done setting up */
2174 ra_set_finalize(regs
, NULL
);
2176 /* Transform the MIR into squeezed index form */
2177 mir_foreach_block(ctx
, block
) {
2178 mir_foreach_instr_in_block(block
, ins
) {
2179 if (ins
->compact_branch
) continue;
2181 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
2182 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
2183 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
2185 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2186 print_mir_block(block
);
2189 /* No register allocation to do with no SSA */
2191 if (!ctx
->temp_count
)
2194 /* Let's actually do register allocation */
2195 int nodes
= ctx
->temp_count
;
2196 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
2198 /* Set everything to the work register class, unless it has somewhere
2201 mir_foreach_block(ctx
, block
) {
2202 mir_foreach_instr_in_block(block
, ins
) {
2203 if (ins
->compact_branch
) continue;
2205 if (ins
->ssa_args
.dest
< 0) continue;
2207 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2209 int class = primary_class
;
2211 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
2215 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
2216 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
2219 unsigned reg
= temp
- 1;
2220 int t
= find_or_allocate_temp(ctx
, index
);
2221 ra_set_node_reg(g
, t
, reg
);
2225 /* Determine liveness */
2227 int *live_start
= malloc(nodes
* sizeof(int));
2228 int *live_end
= malloc(nodes
* sizeof(int));
2230 /* Initialize as non-existent */
2232 for (int i
= 0; i
< nodes
; ++i
) {
2233 live_start
[i
] = live_end
[i
] = -1;
2238 mir_foreach_block(ctx
, block
) {
2239 mir_foreach_instr_in_block(block
, ins
) {
2240 if (ins
->compact_branch
) continue;
2242 /* Dest is < 0 for st_vary instructions, which break
2243 * the usual SSA conventions. Liveness analysis doesn't
2244 * make sense on these instructions, so skip them to
2245 * avoid memory corruption */
2247 if (ins
->ssa_args
.dest
< 0) continue;
2249 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
2250 /* If this destination is not yet live, it is now since we just wrote it */
2252 int dest
= ins
->ssa_args
.dest
;
2254 if (live_start
[dest
] == -1)
2255 live_start
[dest
] = d
;
2258 /* Since we just used a source, the source might be
2259 * dead now. Scan the rest of the block for
2260 * invocations, and if there are none, the source dies
2263 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
2265 for (int src
= 0; src
< 2; ++src
) {
2266 int s
= sources
[src
];
2268 if (s
< 0) continue;
2270 if (s
>= SSA_FIXED_MINIMUM
) continue;
2272 if (!is_live_after(ctx
, block
, ins
, s
)) {
2281 /* If a node still hasn't been killed, kill it now */
2283 for (int i
= 0; i
< nodes
; ++i
) {
2284 /* live_start == -1 most likely indicates a pinned output */
2286 if (live_end
[i
] == -1)
2290 /* Setup interference between nodes that are live at the same time */
2292 for (int i
= 0; i
< nodes
; ++i
) {
2293 for (int j
= i
+ 1; j
< nodes
; ++j
) {
2294 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
2295 ra_add_node_interference(g
, i
, j
);
2299 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
2301 if (!ra_allocate(g
)) {
2302 DBG("Error allocating registers\n");
2313 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
2314 * use scalar ALU instructions, for functional or performance reasons. To do
2315 * this, we just demote vector ALU payloads to scalar. */
2318 component_from_mask(unsigned mask
)
2320 for (int c
= 0; c
< 4; ++c
) {
2321 if (mask
& (3 << (2 * c
)))
2330 is_single_component_mask(unsigned mask
)
2334 for (int c
= 0; c
< 4; ++c
)
2335 if (mask
& (3 << (2 * c
)))
2338 return components
== 1;
2341 /* Create a mask of accessed components from a swizzle to figure out vector
2345 swizzle_to_access_mask(unsigned swizzle
)
2347 unsigned component_mask
= 0;
2349 for (int i
= 0; i
< 4; ++i
) {
2350 unsigned c
= (swizzle
>> (2 * i
)) & 3;
2351 component_mask
|= (1 << c
);
2354 return component_mask
;
2358 vector_to_scalar_source(unsigned u
, bool is_int
)
2360 midgard_vector_alu_src v
;
2361 memcpy(&v
, &u
, sizeof(v
));
2363 /* TODO: Integers */
2365 midgard_scalar_alu_src s
= {
2367 .component
= (v
.swizzle
& 3) << 1
2373 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
2374 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
2378 memcpy(&o
, &s
, sizeof(s
));
2380 return o
& ((1 << 6) - 1);
2383 static midgard_scalar_alu
2384 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
2386 bool is_int
= midgard_is_integer_op(v
.op
);
2388 /* The output component is from the mask */
2389 midgard_scalar_alu s
= {
2391 .src1
= vector_to_scalar_source(v
.src1
, is_int
),
2392 .src2
= vector_to_scalar_source(v
.src2
, is_int
),
2395 .output_full
= 1, /* TODO: Half */
2396 .output_component
= component_from_mask(v
.mask
) << 1,
2399 /* Inline constant is passed along rather than trying to extract it
2402 if (ins
->ssa_args
.inline_constant
) {
2404 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
2405 imm
|= (lower_11
>> 9) & 3;
2406 imm
|= (lower_11
>> 6) & 4;
2407 imm
|= (lower_11
>> 2) & 0x38;
2408 imm
|= (lower_11
& 63) << 6;
2416 /* Midgard prefetches instruction types, so during emission we need to
2417 * lookahead too. Unless this is the last instruction, in which we return 1. Or
2418 * if this is the second to last and the last is an ALU, then it's also 1... */
2420 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
2421 tag == TAG_ALU_12 || tag == TAG_ALU_16)
2423 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
2424 bytes_emitted += sizeof(type)
2427 emit_binary_vector_instruction(midgard_instruction
*ains
,
2428 uint16_t *register_words
, int *register_words_count
,
2429 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
2430 size_t *bytes_emitted
)
2432 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
2433 *bytes_emitted
+= sizeof(midgard_reg_info
);
2435 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
2436 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
2437 *bytes_emitted
+= sizeof(midgard_vector_alu
);
2440 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
2441 * mind that we are a vector architecture and we can write to different
2442 * components simultaneously */
2445 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
2447 /* Each instruction reads some registers and writes to a register. See
2448 * where the first writes */
2450 /* Figure out where exactly we wrote to */
2451 int source
= first
->ssa_args
.dest
;
2452 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
2454 /* As long as the second doesn't read from the first, we're okay */
2455 if (second
->ssa_args
.src0
== source
) {
2456 if (first
->type
== TAG_ALU_4
) {
2457 /* Figure out which components we just read from */
2459 int q
= second
->alu
.src1
;
2460 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2462 /* Check if there are components in common, and fail if so */
2463 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2470 if (second
->ssa_args
.src1
== source
)
2473 /* Otherwise, it's safe in that regard. Another data hazard is both
2474 * writing to the same place, of course */
2476 if (second
->ssa_args
.dest
== source
) {
2477 /* ...but only if the components overlap */
2478 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2480 if (dest_mask
& source_mask
)
2490 midgard_instruction
**segment
, unsigned segment_size
,
2491 midgard_instruction
*ains
)
2493 for (int s
= 0; s
< segment_size
; ++s
)
2494 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2502 /* Schedules, but does not emit, a single basic block. After scheduling, the
2503 * final tag and size of the block are known, which are necessary for branching
2506 static midgard_bundle
2507 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2509 int instructions_emitted
= 0, instructions_consumed
= -1;
2510 midgard_bundle bundle
= { 0 };
2512 uint8_t tag
= ins
->type
;
2514 /* Default to the instruction's tag */
2517 switch (ins
->type
) {
2519 uint32_t control
= 0;
2520 size_t bytes_emitted
= sizeof(control
);
2522 /* TODO: Constant combining */
2523 int index
= 0, last_unit
= 0;
2525 /* Previous instructions, for the purpose of parallelism */
2526 midgard_instruction
*segment
[4] = {0};
2527 int segment_size
= 0;
2529 instructions_emitted
= -1;
2530 midgard_instruction
*pins
= ins
;
2533 midgard_instruction
*ains
= pins
;
2535 /* Advance instruction pointer */
2537 ains
= mir_next_op(pins
);
2541 /* Out-of-work condition */
2542 if ((struct list_head
*) ains
== &block
->instructions
)
2545 /* Ensure that the chain can continue */
2546 if (ains
->type
!= TAG_ALU_4
) break;
2548 /* If there's already something in the bundle and we
2549 * have weird scheduler constraints, break now */
2550 if (ains
->precede_break
&& index
) break;
2552 /* According to the presentation "The ARM
2553 * Mali-T880 Mobile GPU" from HotChips 27,
2554 * there are two pipeline stages. Branching
2555 * position determined experimentally. Lines
2556 * are executed in parallel:
2559 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2561 * Verify that there are no ordering dependencies here.
2563 * TODO: Allow for parallelism!!!
2566 /* Pick a unit for it if it doesn't force a particular unit */
2568 int unit
= ains
->unit
;
2571 int op
= ains
->alu
.op
;
2572 int units
= alu_opcode_props
[op
].props
;
2574 /* TODO: Promotion of scalars to vectors */
2575 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2578 assert(units
& UNITS_SCALAR
);
2581 if (last_unit
>= UNIT_VADD
) {
2582 if (units
& UNIT_VLUT
)
2587 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2589 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2591 else if (units
& UNIT_VLUT
)
2597 if (last_unit
>= UNIT_VADD
) {
2598 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2600 else if (units
& UNIT_VLUT
)
2605 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
2607 else if (units
& UNIT_SMUL
)
2608 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
2609 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2616 assert(unit
& units
);
2619 /* Late unit check, this time for encoding (not parallelism) */
2620 if (unit
<= last_unit
) break;
2622 /* Clear the segment */
2623 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2626 if (midgard_has_hazard(segment
, segment_size
, ains
))
2629 /* We're good to go -- emit the instruction */
2632 segment
[segment_size
++] = ains
;
2634 /* Only one set of embedded constants per
2635 * bundle possible; if we have more, we must
2636 * break the chain early, unfortunately */
2638 if (ains
->has_constants
) {
2639 if (bundle
.has_embedded_constants
) {
2640 /* ...but if there are already
2641 * constants but these are the
2642 * *same* constants, we let it
2645 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2648 bundle
.has_embedded_constants
= true;
2649 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2651 /* If this is a blend shader special constant, track it for patching */
2652 if (ains
->has_blend_constant
)
2653 bundle
.has_blend_constant
= true;
2657 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2658 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2659 &bundle
.register_words_count
, bundle
.body_words
,
2660 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2661 } else if (ains
->compact_branch
) {
2662 /* All of r0 has to be written out
2663 * along with the branch writeout.
2666 if (ains
->writeout
) {
2668 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2669 ins
.unit
= UNIT_VMUL
;
2671 control
|= ins
.unit
;
2673 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2674 &bundle
.register_words_count
, bundle
.body_words
,
2675 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2677 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2678 bool written_late
= false;
2679 bool components
[4] = { 0 };
2680 uint16_t register_dep_mask
= 0;
2681 uint16_t written_mask
= 0;
2683 midgard_instruction
*qins
= ins
;
2684 for (int t
= 0; t
< index
; ++t
) {
2685 if (qins
->registers
.out_reg
!= 0) {
2686 /* Mark down writes */
2688 written_mask
|= (1 << qins
->registers
.out_reg
);
2690 /* Mark down the register dependencies for errata check */
2692 if (qins
->registers
.src1_reg
< 16)
2693 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2695 if (qins
->registers
.src2_reg
< 16)
2696 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2698 int mask
= qins
->alu
.mask
;
2700 for (int c
= 0; c
< 4; ++c
)
2701 if (mask
& (0x3 << (2 * c
)))
2702 components
[c
] = true;
2704 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2706 if (qins
->unit
== UNIT_VLUT
)
2707 written_late
= true;
2710 /* Advance instruction pointer */
2711 qins
= mir_next_op(qins
);
2715 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2716 if (register_dep_mask
& written_mask
) {
2717 DBG("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2724 /* If even a single component is not written, break it up (conservative check). */
2725 bool breakup
= false;
2727 for (int c
= 0; c
< 4; ++c
)
2734 /* Otherwise, we're free to proceed */
2738 if (ains
->unit
== ALU_ENAB_BRANCH
) {
2739 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
2740 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
2741 bytes_emitted
+= sizeof(midgard_branch_extended
);
2743 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2744 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2745 bytes_emitted
+= sizeof(ains
->br_compact
);
2748 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2749 bytes_emitted
+= sizeof(midgard_reg_info
);
2751 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2752 bundle
.body_words_count
++;
2753 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2756 /* Defer marking until after writing to allow for break */
2757 control
|= ains
->unit
;
2758 last_unit
= ains
->unit
;
2759 ++instructions_emitted
;
2763 /* Bubble up the number of instructions for skipping */
2764 instructions_consumed
= index
- 1;
2768 /* Pad ALU op to nearest word */
2770 if (bytes_emitted
& 15) {
2771 padding
= 16 - (bytes_emitted
& 15);
2772 bytes_emitted
+= padding
;
2775 /* Constants must always be quadwords */
2776 if (bundle
.has_embedded_constants
)
2777 bytes_emitted
+= 16;
2779 /* Size ALU instruction for tag */
2780 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2781 bundle
.padding
= padding
;
2782 bundle
.control
= bundle
.tag
| control
;
2787 case TAG_LOAD_STORE_4
: {
2788 /* Load store instructions have two words at once. If
2789 * we only have one queued up, we need to NOP pad.
2790 * Otherwise, we store both in succession to save space
2791 * and cycles -- letting them go in parallel -- skip
2792 * the next. The usefulness of this optimisation is
2793 * greatly dependent on the quality of the instruction
2797 midgard_instruction
*next_op
= mir_next_op(ins
);
2799 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2800 /* As the two operate concurrently, make sure
2801 * they are not dependent */
2803 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2804 /* Skip ahead, since it's redundant with the pair */
2805 instructions_consumed
= 1 + (instructions_emitted
++);
2813 /* Texture ops default to single-op-per-bundle scheduling */
2817 /* Copy the instructions into the bundle */
2818 bundle
.instruction_count
= instructions_emitted
+ 1;
2822 midgard_instruction
*uins
= ins
;
2823 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2824 bundle
.instructions
[used_idx
++] = *uins
;
2825 uins
= mir_next_op(uins
);
2828 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2834 quadword_size(int tag
)
2849 case TAG_LOAD_STORE_4
:
2861 /* Schedule a single block by iterating its instruction to create bundles.
2862 * While we go, tally about the bundle sizes to compute the block size. */
2865 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2867 util_dynarray_init(&block
->bundles
, NULL
);
2869 block
->quadword_count
= 0;
2871 mir_foreach_instr_in_block(block
, ins
) {
2873 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2874 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2876 if (bundle
.has_blend_constant
) {
2877 /* TODO: Multiblock? */
2878 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2879 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2883 ins
= mir_next_op(ins
);
2885 block
->quadword_count
+= quadword_size(bundle
.tag
);
2888 block
->is_scheduled
= true;
2892 schedule_program(compiler_context
*ctx
)
2894 /* We run RA prior to scheduling */
2895 struct ra_graph
*g
= allocate_registers(ctx
);
2896 install_registers(ctx
, g
);
2898 mir_foreach_block(ctx
, block
) {
2899 schedule_block(ctx
, block
);
2903 /* After everything is scheduled, emit whole bundles at a time */
2906 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2908 int lookahead
= next_tag
<< 4;
2910 switch (bundle
->tag
) {
2915 /* Actually emit each component */
2916 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2918 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2919 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2921 /* Emit body words based on the instructions bundled */
2922 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2923 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2925 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2926 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2927 } else if (ins
->compact_branch
) {
2928 /* Dummy move, XXX DRY */
2929 if ((i
== 0) && ins
->writeout
) {
2930 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2931 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2934 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2935 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2937 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2941 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2942 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2946 /* Emit padding (all zero) */
2947 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2949 /* Tack on constants */
2951 if (bundle
->has_embedded_constants
) {
2952 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2953 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2954 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2955 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2961 case TAG_LOAD_STORE_4
: {
2962 /* One or two composing instructions */
2964 uint64_t current64
, next64
= LDST_NOP
;
2966 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2968 if (bundle
->instruction_count
== 2)
2969 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2971 midgard_load_store instruction
= {
2972 .type
= bundle
->tag
,
2973 .next_type
= next_tag
,
2978 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2983 case TAG_TEXTURE_4
: {
2984 /* Texture instructions are easy, since there is no
2985 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2987 midgard_instruction
*ins
= &bundle
->instructions
[0];
2989 ins
->texture
.type
= TAG_TEXTURE_4
;
2990 ins
->texture
.next_type
= next_tag
;
2992 ctx
->texture_op_count
--;
2994 if (!ctx
->texture_op_count
) {
2995 ins
->texture
.cont
= 0;
2996 ins
->texture
.last
= 1;
2999 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
3004 DBG("Unknown midgard instruction type\n");
3011 /* ALU instructions can inline or embed constants, which decreases register
3012 * pressure and saves space. */
3014 #define CONDITIONAL_ATTACH(src) { \
3015 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
3018 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
3019 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
3024 inline_alu_constants(compiler_context
*ctx
)
3026 mir_foreach_instr(ctx
, alu
) {
3027 /* Other instructions cannot inline constants */
3028 if (alu
->type
!= TAG_ALU_4
) continue;
3030 /* If there is already a constant here, we can do nothing */
3031 if (alu
->has_constants
) continue;
3033 /* It makes no sense to inline constants on a branch */
3034 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
3036 CONDITIONAL_ATTACH(src0
);
3038 if (!alu
->has_constants
) {
3039 CONDITIONAL_ATTACH(src1
)
3040 } else if (!alu
->inline_constant
) {
3041 /* Corner case: _two_ vec4 constants, for instance with a
3042 * csel. For this case, we can only use a constant
3043 * register for one, we'll have to emit a move for the
3044 * other. Note, if both arguments are constants, then
3045 * necessarily neither argument depends on the value of
3046 * any particular register. As the destination register
3047 * will be wiped, that means we can spill the constant
3048 * to the destination register.
3051 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
3052 unsigned scratch
= alu
->ssa_args
.dest
;
3055 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
3056 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
3058 /* Force a break XXX Defer r31 writes */
3059 ins
.unit
= UNIT_VLUT
;
3061 /* Set the source */
3062 alu
->ssa_args
.src1
= scratch
;
3064 /* Inject us -before- the last instruction which set r31 */
3065 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
3071 /* Midgard supports two types of constants, embedded constants (128-bit) and
3072 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
3073 * constants can be demoted to inline constants, for space savings and
3074 * sometimes a performance boost */
3077 embedded_to_inline_constant(compiler_context
*ctx
)
3079 mir_foreach_instr(ctx
, ins
) {
3080 if (!ins
->has_constants
) continue;
3082 if (ins
->ssa_args
.inline_constant
) continue;
3084 /* Blend constants must not be inlined by definition */
3085 if (ins
->has_blend_constant
) continue;
3087 /* src1 cannot be an inline constant due to encoding
3088 * restrictions. So, if possible we try to flip the arguments
3091 int op
= ins
->alu
.op
;
3093 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
3095 /* These ops require an operational change to flip
3096 * their arguments TODO */
3097 case midgard_alu_op_flt
:
3098 case midgard_alu_op_fle
:
3099 case midgard_alu_op_ilt
:
3100 case midgard_alu_op_ile
:
3101 case midgard_alu_op_fcsel
:
3102 case midgard_alu_op_icsel
:
3103 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
3108 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
3109 /* Flip the SSA numbers */
3110 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
3111 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
3113 /* And flip the modifiers */
3117 src_temp
= ins
->alu
.src2
;
3118 ins
->alu
.src2
= ins
->alu
.src1
;
3119 ins
->alu
.src1
= src_temp
;
3123 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
3124 /* Extract the source information */
3126 midgard_vector_alu_src
*src
;
3127 int q
= ins
->alu
.src2
;
3128 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
3131 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
3132 int component
= src
->swizzle
& 3;
3134 /* Scale constant appropriately, if we can legally */
3135 uint16_t scaled_constant
= 0;
3137 if (midgard_is_integer_op(op
)) {
3138 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
3139 scaled_constant
= (uint16_t) iconstants
[component
];
3141 /* Constant overflow after resize */
3142 if (scaled_constant
!= iconstants
[component
])
3145 float original
= (float) ins
->constants
[component
];
3146 scaled_constant
= _mesa_float_to_half(original
);
3148 /* Check for loss of precision. If this is
3149 * mediump, we don't care, but for a highp
3150 * shader, we need to pay attention. NIR
3151 * doesn't yet tell us which mode we're in!
3152 * Practically this prevents most constants
3153 * from being inlined, sadly. */
3155 float fp32
= _mesa_half_to_float(scaled_constant
);
3157 if (fp32
!= original
)
3161 /* We don't know how to handle these with a constant */
3163 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
3164 DBG("Bailing inline constant...\n");
3168 /* Make sure that the constant is not itself a
3169 * vector by checking if all accessed values
3170 * (by the swizzle) are the same. */
3172 uint32_t *cons
= (uint32_t *) ins
->constants
;
3173 uint32_t value
= cons
[component
];
3175 bool is_vector
= false;
3176 unsigned mask
= effective_writemask(&ins
->alu
);
3178 for (int c
= 1; c
< 4; ++c
) {
3179 /* We only care if this component is actually used */
3180 if (!(mask
& (1 << c
)))
3183 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
3185 if (test
!= value
) {
3194 /* Get rid of the embedded constant */
3195 ins
->has_constants
= false;
3196 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
3197 ins
->ssa_args
.inline_constant
= true;
3198 ins
->inline_constant
= scaled_constant
;
3203 /* Map normal SSA sources to other SSA sources / fixed registers (like
3207 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
3209 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
3212 /* Remove entry in leftovers to avoid a redunant fmov */
3214 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
3217 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
3219 /* Assign the alias map */
3225 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
3226 * texture pipeline */
3229 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
3231 bool progress
= false;
3233 mir_foreach_instr_in_block_safe(block
, ins
) {
3234 if (ins
->type
!= TAG_ALU_4
) continue;
3235 if (ins
->compact_branch
) continue;
3237 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
3238 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
3239 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
3241 mir_remove_instruction(ins
);
3249 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
3252 if (!is_int
&& src
.mod
) return true;
3255 for (unsigned c
= 0; c
< 4; ++c
) {
3256 if (!(mask
& (1 << c
))) continue;
3257 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
3264 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
3266 bool progress
= false;
3268 mir_foreach_instr_in_block_safe(block
, ins
) {
3269 if (ins
->type
!= TAG_ALU_4
) continue;
3270 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3272 unsigned from
= ins
->ssa_args
.src1
;
3273 unsigned to
= ins
->ssa_args
.dest
;
3275 /* We only work on pure SSA */
3277 if (to
>= SSA_FIXED_MINIMUM
) continue;
3278 if (from
>= SSA_FIXED_MINIMUM
) continue;
3279 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
3280 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
3282 /* Constant propagation is not handled here, either */
3283 if (ins
->ssa_args
.inline_constant
) continue;
3284 if (ins
->has_constants
) continue;
3286 /* Also, if the move has side effects, we're helpless */
3288 midgard_vector_alu_src src
=
3289 vector_alu_from_unsigned(ins
->alu
.src2
);
3290 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
3291 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
3293 if (mir_nontrivial_mod(src
, is_int
, mask
)) continue;
3294 if (ins
->alu
.outmod
!= midgard_outmod_none
) continue;
3296 mir_foreach_instr_in_block_from(block
, v
, mir_next_op(ins
)) {
3297 if (v
->ssa_args
.src0
== to
) {
3298 v
->ssa_args
.src0
= from
;
3302 if (v
->ssa_args
.src1
== to
&& !v
->ssa_args
.inline_constant
) {
3303 v
->ssa_args
.src1
= from
;
3313 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
3315 bool progress
= false;
3317 mir_foreach_instr_in_block_safe(block
, ins
) {
3318 if (ins
->type
!= TAG_ALU_4
) continue;
3319 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
3321 unsigned from
= ins
->ssa_args
.src1
;
3322 unsigned to
= ins
->ssa_args
.dest
;
3324 /* Make sure it's simple enough for us to handle */
3326 if (from
>= SSA_FIXED_MINIMUM
) continue;
3327 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
3328 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
3329 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
3331 bool eliminated
= false;
3333 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
3334 /* The texture registers are not SSA so be careful.
3335 * Conservatively, just stop if we hit a texture op
3336 * (even if it may not write) to where we are */
3338 if (v
->type
!= TAG_ALU_4
)
3341 if (v
->ssa_args
.dest
== from
) {
3342 /* We don't want to track partial writes ... */
3343 if (v
->alu
.mask
== 0xF) {
3344 v
->ssa_args
.dest
= to
;
3353 mir_remove_instruction(ins
);
3355 progress
|= eliminated
;
3361 /* The following passes reorder MIR instructions to enable better scheduling */
3364 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
3366 mir_foreach_instr_in_block_safe(block
, ins
) {
3367 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
3369 /* We've found a load/store op. Check if next is also load/store. */
3370 midgard_instruction
*next_op
= mir_next_op(ins
);
3371 if (&next_op
->link
!= &block
->instructions
) {
3372 if (next_op
->type
== TAG_LOAD_STORE_4
) {
3373 /* If so, we're done since we're a pair */
3374 ins
= mir_next_op(ins
);
3378 /* Maximum search distance to pair, to avoid register pressure disasters */
3379 int search_distance
= 8;
3381 /* Otherwise, we have an orphaned load/store -- search for another load */
3382 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
3383 /* Terminate search if necessary */
3384 if (!(search_distance
--)) break;
3386 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
3388 /* Stores cannot be reordered, since they have
3389 * dependencies. For the same reason, indirect
3390 * loads cannot be reordered as their index is
3391 * loaded in r27.w */
3393 if (OP_IS_STORE(c
->load_store
.op
)) continue;
3395 /* It appears the 0x800 bit is set whenever a
3396 * load is direct, unset when it is indirect.
3397 * Skip indirect loads. */
3399 if (!(c
->load_store
.unknown
& 0x800)) continue;
3401 /* We found one! Move it up to pair and remove it from the old location */
3403 mir_insert_instruction_before(ins
, *c
);
3404 mir_remove_instruction(c
);
3412 /* Emit varying stores late */
3415 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
3416 /* Iterate in reverse to get the final write, rather than the first */
3418 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
3419 /* Check if what we just wrote needs a store */
3420 int idx
= ins
->ssa_args
.dest
;
3421 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
3423 if (!varying
) continue;
3427 /* We need to store to the appropriate varying, so emit the
3430 /* TODO: Integrate with special purpose RA (and scheduler?) */
3431 bool high_varying_register
= false;
3433 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
3435 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
3436 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
3438 mir_insert_instruction_before(mir_next_op(ins
), st
);
3439 mir_insert_instruction_before(mir_next_op(ins
), mov
);
3441 /* We no longer need to store this varying */
3442 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
3446 /* If there are leftovers after the below pass, emit actual fmov
3447 * instructions for the slow-but-correct path */
3450 emit_leftover_move(compiler_context
*ctx
)
3452 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
3453 int base
= ((uintptr_t) leftover
->key
) - 1;
3456 map_ssa_to_alias(ctx
, &mapped
);
3457 EMIT(fmov
, mapped
, blank_alu_src
, base
);
3462 actualise_ssa_to_alias(compiler_context
*ctx
)
3464 mir_foreach_instr(ctx
, ins
) {
3465 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
3466 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
3469 emit_leftover_move(ctx
);
3473 emit_fragment_epilogue(compiler_context
*ctx
)
3475 /* Special case: writing out constants requires us to include the move
3476 * explicitly now, so shove it into r0 */
3478 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
3480 if (constant_value
) {
3481 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3482 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3483 emit_mir_instruction(ctx
, ins
);
3486 /* Perform the actual fragment writeout. We have two writeout/branch
3487 * instructions, forming a loop until writeout is successful as per the
3488 * docs. TODO: gl_FragDepth */
3490 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3491 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3494 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3495 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3496 * with the int8 analogue to the fragment epilogue */
3499 emit_blend_epilogue(compiler_context
*ctx
)
3501 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3503 midgard_instruction scale
= {
3506 .inline_constant
= _mesa_float_to_half(255.0),
3508 .src0
= SSA_FIXED_REGISTER(0),
3509 .src1
= SSA_UNUSED_0
,
3510 .dest
= SSA_FIXED_REGISTER(24),
3511 .inline_constant
= true
3514 .op
= midgard_alu_op_fmul
,
3515 .reg_mode
= midgard_reg_mode_32
,
3516 .dest_override
= midgard_dest_override_lower
,
3518 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3519 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3523 emit_mir_instruction(ctx
, scale
);
3525 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3527 midgard_vector_alu_src alu_src
= blank_alu_src
;
3528 alu_src
.half
= true;
3530 midgard_instruction f2u8
= {
3533 .src0
= SSA_FIXED_REGISTER(24),
3534 .src1
= SSA_UNUSED_0
,
3535 .dest
= SSA_FIXED_REGISTER(0),
3536 .inline_constant
= true
3539 .op
= midgard_alu_op_f2u8
,
3540 .reg_mode
= midgard_reg_mode_16
,
3541 .dest_override
= midgard_dest_override_lower
,
3542 .outmod
= midgard_outmod_pos
,
3544 .src1
= vector_alu_srco_unsigned(alu_src
),
3545 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3549 emit_mir_instruction(ctx
, f2u8
);
3551 /* vmul.imov.quarter r0, r0, r0 */
3553 midgard_instruction imov_8
= {
3556 .src0
= SSA_UNUSED_1
,
3557 .src1
= SSA_FIXED_REGISTER(0),
3558 .dest
= SSA_FIXED_REGISTER(0),
3561 .op
= midgard_alu_op_imov
,
3562 .reg_mode
= midgard_reg_mode_8
,
3563 .dest_override
= midgard_dest_override_none
,
3565 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3566 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3570 /* Emit branch epilogue with the 8-bit move as the source */
3572 emit_mir_instruction(ctx
, imov_8
);
3573 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3575 emit_mir_instruction(ctx
, imov_8
);
3576 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3579 static midgard_block
*
3580 emit_block(compiler_context
*ctx
, nir_block
*block
)
3582 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
3583 list_addtail(&this_block
->link
, &ctx
->blocks
);
3585 this_block
->is_scheduled
= false;
3588 ctx
->texture_index
[0] = -1;
3589 ctx
->texture_index
[1] = -1;
3591 /* Add us as a successor to the block we are following */
3592 if (ctx
->current_block
)
3593 midgard_block_add_successor(ctx
->current_block
, this_block
);
3595 /* Set up current block */
3596 list_inithead(&this_block
->instructions
);
3597 ctx
->current_block
= this_block
;
3599 nir_foreach_instr(instr
, block
) {
3600 emit_instr(ctx
, instr
);
3601 ++ctx
->instruction_count
;
3604 inline_alu_constants(ctx
);
3605 embedded_to_inline_constant(ctx
);
3607 /* Perform heavylifting for aliasing */
3608 actualise_ssa_to_alias(ctx
);
3610 midgard_emit_store(ctx
, this_block
);
3611 midgard_pair_load_store(ctx
, this_block
);
3613 /* Append fragment shader epilogue (value writeout) */
3614 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3615 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3617 emit_blend_epilogue(ctx
);
3619 emit_fragment_epilogue(ctx
);
3623 if (block
== nir_start_block(ctx
->func
->impl
))
3624 ctx
->initial_block
= this_block
;
3626 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3627 ctx
->final_block
= this_block
;
3629 /* Allow the next control flow to access us retroactively, for
3631 ctx
->current_block
= this_block
;
3633 /* Document the fallthrough chain */
3634 ctx
->previous_source_block
= this_block
;
3639 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3642 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3644 /* Conditional branches expect the condition in r31.w; emit a move for
3645 * that in the _previous_ block (which is the current block). */
3646 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
3648 /* Speculatively emit the branch, but we can't fill it in until later */
3649 EMIT(branch
, true, true);
3650 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3652 /* Emit the two subblocks */
3653 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3655 /* Emit a jump from the end of the then block to the end of the else */
3656 EMIT(branch
, false, false);
3657 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3659 /* Emit second block, and check if it's empty */
3661 int else_idx
= ctx
->block_count
;
3662 int count_in
= ctx
->instruction_count
;
3663 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3664 int after_else_idx
= ctx
->block_count
;
3666 /* Now that we have the subblocks emitted, fix up the branches */
3671 if (ctx
->instruction_count
== count_in
) {
3672 /* The else block is empty, so don't emit an exit jump */
3673 mir_remove_instruction(then_exit
);
3674 then_branch
->branch
.target_block
= after_else_idx
;
3676 then_branch
->branch
.target_block
= else_idx
;
3677 then_exit
->branch
.target_block
= after_else_idx
;
3682 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3684 /* Remember where we are */
3685 midgard_block
*start_block
= ctx
->current_block
;
3687 /* Allocate a loop number, growing the current inner loop depth */
3688 int loop_idx
= ++ctx
->current_loop_depth
;
3690 /* Get index from before the body so we can loop back later */
3691 int start_idx
= ctx
->block_count
;
3693 /* Emit the body itself */
3694 emit_cf_list(ctx
, &nloop
->body
);
3696 /* Branch back to loop back */
3697 struct midgard_instruction br_back
= v_branch(false, false);
3698 br_back
.branch
.target_block
= start_idx
;
3699 emit_mir_instruction(ctx
, br_back
);
3701 /* Mark down that branch in the graph. Note that we're really branching
3702 * to the block *after* we started in. TODO: Why doesn't the branch
3703 * itself have an off-by-one then...? */
3704 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
3706 /* Find the index of the block about to follow us (note: we don't add
3707 * one; blocks are 0-indexed so we get a fencepost problem) */
3708 int break_block_idx
= ctx
->block_count
;
3710 /* Fix up the break statements we emitted to point to the right place,
3711 * now that we can allocate a block number for them */
3713 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3714 mir_foreach_instr_in_block(block
, ins
) {
3715 if (ins
->type
!= TAG_ALU_4
) continue;
3716 if (!ins
->compact_branch
) continue;
3717 if (ins
->prepacked_branch
) continue;
3719 /* We found a branch -- check the type to see if we need to do anything */
3720 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3722 /* It's a break! Check if it's our break */
3723 if (ins
->branch
.target_break
!= loop_idx
) continue;
3725 /* Okay, cool, we're breaking out of this loop.
3726 * Rewrite from a break to a goto */
3728 ins
->branch
.target_type
= TARGET_GOTO
;
3729 ins
->branch
.target_block
= break_block_idx
;
3733 /* Now that we've finished emitting the loop, free up the depth again
3734 * so we play nice with recursion amid nested loops */
3735 --ctx
->current_loop_depth
;
3738 static midgard_block
*
3739 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3741 midgard_block
*start_block
= NULL
;
3743 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3744 switch (node
->type
) {
3745 case nir_cf_node_block
: {
3746 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3749 start_block
= block
;
3754 case nir_cf_node_if
:
3755 emit_if(ctx
, nir_cf_node_as_if(node
));
3758 case nir_cf_node_loop
:
3759 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3762 case nir_cf_node_function
:
3771 /* Due to lookahead, we need to report the first tag executed in the command
3772 * stream and in branch targets. An initial block might be empty, so iterate
3773 * until we find one that 'works' */
3776 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
3778 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
3780 unsigned first_tag
= 0;
3783 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3785 if (initial_bundle
) {
3786 first_tag
= initial_bundle
->tag
;
3790 /* Initial block is empty, try the next block */
3791 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3792 } while(initial_block
!= NULL
);
3799 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3801 struct util_dynarray
*compiled
= &program
->compiled
;
3803 midgard_debug
= debug_get_option_midgard_debug();
3805 compiler_context ictx
= {
3807 .stage
= nir
->info
.stage
,
3809 .is_blend
= is_blend
,
3810 .blend_constant_offset
= -1,
3812 .alpha_ref
= program
->alpha_ref
3815 compiler_context
*ctx
= &ictx
;
3817 /* TODO: Decide this at runtime */
3818 ctx
->uniform_cutoff
= 8;
3820 /* Assign var locations early, so the epilogue can use them if necessary */
3822 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3823 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3824 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3826 /* Initialize at a global (not block) level hash tables */
3828 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3829 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3830 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3831 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3832 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3833 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3834 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3836 /* Record the varying mapping for the command stream's bookkeeping */
3838 struct exec_list
*varyings
=
3839 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3841 nir_foreach_variable(var
, varyings
) {
3842 unsigned loc
= var
->data
.driver_location
;
3843 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3845 for (int c
= 0; c
< sz
; ++c
) {
3846 program
->varyings
[loc
+ c
] = var
->data
.location
;
3850 /* Lower gl_Position pre-optimisation */
3852 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3853 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3855 NIR_PASS_V(nir
, nir_lower_var_copies
);
3856 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3857 NIR_PASS_V(nir
, nir_split_var_copies
);
3858 NIR_PASS_V(nir
, nir_lower_var_copies
);
3859 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3860 NIR_PASS_V(nir
, nir_lower_var_copies
);
3861 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3863 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3865 /* Optimisation passes */
3869 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3870 nir_print_shader(nir
, stdout
);
3873 /* Assign sysvals and counts, now that we're sure
3874 * (post-optimisation) */
3876 midgard_nir_assign_sysvals(ctx
, nir
);
3878 program
->uniform_count
= nir
->num_uniforms
;
3879 program
->sysval_count
= ctx
->sysval_count
;
3880 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3882 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3883 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3885 nir_foreach_function(func
, nir
) {
3889 list_inithead(&ctx
->blocks
);
3890 ctx
->block_count
= 0;
3893 emit_cf_list(ctx
, &func
->impl
->body
);
3894 emit_block(ctx
, func
->impl
->end_block
);
3896 break; /* TODO: Multi-function shaders */
3899 util_dynarray_init(compiled
, NULL
);
3901 /* MIR-level optimizations */
3903 bool progress
= false;
3908 mir_foreach_block(ctx
, block
) {
3909 progress
|= midgard_opt_copy_prop(ctx
, block
);
3910 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
3911 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
3916 schedule_program(ctx
);
3918 /* Now that all the bundles are scheduled and we can calculate block
3919 * sizes, emit actual branch instructions rather than placeholders */
3921 int br_block_idx
= 0;
3923 mir_foreach_block(ctx
, block
) {
3924 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3925 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3926 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3928 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3930 if (ins
->prepacked_branch
) continue;
3932 /* Parse some basic branch info */
3933 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3934 bool is_conditional
= ins
->branch
.conditional
;
3935 bool is_inverted
= ins
->branch
.invert_conditional
;
3936 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3938 /* Determine the block we're jumping to */
3939 int target_number
= ins
->branch
.target_block
;
3941 /* Report the destination tag. Discards don't need this */
3942 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3944 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3945 int quadword_offset
= 0;
3948 /* Jump to the end of the shader. We
3949 * need to include not only the
3950 * following blocks, but also the
3951 * contents of our current block (since
3952 * discard can come in the middle of
3955 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3957 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3958 quadword_offset
+= quadword_size(bun
->tag
);
3961 mir_foreach_block_from(ctx
, blk
, b
) {
3962 quadword_offset
+= b
->quadword_count
;
3965 } else if (target_number
> br_block_idx
) {
3968 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3969 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3972 quadword_offset
+= blk
->quadword_count
;
3975 /* Jump backwards */
3977 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3978 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3981 quadword_offset
-= blk
->quadword_count
;
3985 /* Unconditional extended branches (far jumps)
3986 * have issues, so we always use a conditional
3987 * branch, setting the condition to always for
3988 * unconditional. For compact unconditional
3989 * branches, cond isn't used so it doesn't
3990 * matter what we pick. */
3992 midgard_condition cond
=
3993 !is_conditional
? midgard_condition_always
:
3994 is_inverted
? midgard_condition_false
:
3995 midgard_condition_true
;
3997 midgard_jmp_writeout_op op
=
3998 is_discard
? midgard_jmp_writeout_op_discard
:
3999 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
4000 midgard_jmp_writeout_op_branch_cond
;
4003 midgard_branch_extended branch
=
4004 midgard_create_branch_extended(
4009 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
4010 } else if (is_conditional
|| is_discard
) {
4011 midgard_branch_cond branch
= {
4013 .dest_tag
= dest_tag
,
4014 .offset
= quadword_offset
,
4018 assert(branch
.offset
== quadword_offset
);
4020 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
4022 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
4024 midgard_branch_uncond branch
= {
4026 .dest_tag
= dest_tag
,
4027 .offset
= quadword_offset
,
4031 assert(branch
.offset
== quadword_offset
);
4033 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
4041 /* Emit flat binary from the instruction arrays. Iterate each block in
4042 * sequence. Save instruction boundaries such that lookahead tags can
4043 * be assigned easily */
4045 /* Cache _all_ bundles in source order for lookahead across failed branches */
4047 int bundle_count
= 0;
4048 mir_foreach_block(ctx
, block
) {
4049 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
4051 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
4053 mir_foreach_block(ctx
, block
) {
4054 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
4055 source_order_bundles
[bundle_idx
++] = bundle
;
4059 int current_bundle
= 0;
4061 mir_foreach_block(ctx
, block
) {
4062 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
4065 if (current_bundle
+ 1 < bundle_count
) {
4066 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
4068 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
4075 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
4079 /* TODO: Free deeper */
4080 //util_dynarray_fini(&block->instructions);
4083 free(source_order_bundles
);
4085 /* Report the very first tag executed */
4086 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
4088 /* Deal with off-by-one related to the fencepost problem */
4089 program
->work_register_count
= ctx
->work_registers
+ 1;
4091 program
->can_discard
= ctx
->can_discard
;
4092 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
4094 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
4096 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
4097 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);