2 * Copyright (C) 2018 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "compiler/glsl/glsl_to_nir.h"
34 #include "compiler/nir_types.h"
35 #include "main/imports.h"
36 #include "compiler/nir/nir_builder.h"
37 #include "util/half_float.h"
38 #include "util/register_allocate.h"
39 #include "util/u_dynarray.h"
40 #include "util/list.h"
41 #include "main/mtypes.h"
44 #include "midgard_nir.h"
45 #include "midgard_compile.h"
48 #include "disassemble.h"
50 /* Instruction arguments represented as block-local SSA indices, rather than
51 * registers. Negative values mean unused. */
58 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
59 * in. Only valid for ALU ops. */
63 /* Forward declare so midgard_branch can reference */
66 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
67 * the hardware), hence why that must be zero */
70 #define TARGET_BREAK 1
71 #define TARGET_CONTINUE 2
73 typedef struct midgard_branch
{
74 /* If conditional, the condition is specified in r31.w */
77 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
78 bool invert_conditional
;
80 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
83 /* The actual target */
91 /* Generic in-memory data type repesenting a single logical instruction, rather
92 * than a single instruction group. This is the preferred form for code gen.
93 * Multiple midgard_insturctions will later be combined during scheduling,
94 * though this is not represented in this structure. Its format bridges
95 * the low-level binary representation with the higher level semantic meaning.
97 * Notably, it allows registers to be specified as block local SSA, for code
98 * emitted before the register allocation pass.
101 typedef struct midgard_instruction
{
102 /* Must be first for casting */
103 struct list_head link
;
105 unsigned type
; /* ALU, load/store, texture */
107 /* If the register allocator has not run yet... */
110 /* Special fields for an ALU instruction */
111 midgard_reg_info registers
;
113 /* I.e. (1 << alu_bit) */
118 uint16_t inline_constant
;
119 bool has_blend_constant
;
123 bool prepacked_branch
;
126 midgard_load_store_word load_store
;
127 midgard_vector_alu alu
;
128 midgard_texture_word texture
;
131 /* General branch, rather than packed br_compact. Higher level
132 * than the other components */
133 midgard_branch branch
;
135 } midgard_instruction
;
137 typedef struct midgard_block
{
138 /* Link to next block. Must be first for mir_get_block */
139 struct list_head link
;
141 /* List of midgard_instructions emitted for the current block */
142 struct list_head instructions
;
146 /* List of midgard_bundles emitted (after the scheduler has run) */
147 struct util_dynarray bundles
;
149 /* Number of quadwords _actually_ emitted, as determined after scheduling */
150 unsigned quadword_count
;
152 struct midgard_block
*next_fallthrough
;
155 /* Helpers to generate midgard_instruction's using macro magic, since every
156 * driver seems to do it that way */
158 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
160 #define M_LOAD_STORE(name, rname, uname) \
161 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
162 midgard_instruction i = { \
163 .type = TAG_LOAD_STORE_4, \
170 .op = midgard_op_##name, \
172 .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W), \
180 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
181 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
183 const midgard_vector_alu_src blank_alu_src
= {
184 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
187 const midgard_scalar_alu_src blank_scalar_alu_src
= {
191 /* Used for encoding the unused source of 1-op instructions */
192 const midgard_vector_alu_src zero_alu_src
= { 0 };
194 /* Coerce structs to integer */
197 vector_alu_srco_unsigned(midgard_vector_alu_src src
)
200 memcpy(&u
, &src
, sizeof(src
));
204 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
205 * the corresponding Midgard source */
207 static midgard_vector_alu_src
208 vector_alu_modifiers(nir_alu_src
*src
)
210 if (!src
) return blank_alu_src
;
212 midgard_vector_alu_src alu_src
= {
214 .negate
= src
->negate
,
217 .half
= 0, /* TODO */
218 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
224 /* 'Intrinsic' move for misc aliasing uses independent of actual NIR ALU code */
226 static midgard_instruction
227 v_fmov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
229 midgard_instruction ins
= {
232 .src0
= SSA_UNUSED_1
,
237 .op
= midgard_alu_op_fmov
,
238 .reg_mode
= midgard_reg_mode_full
,
239 .dest_override
= midgard_dest_override_none
,
241 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
242 .src2
= vector_alu_srco_unsigned(mod
)
249 /* load/store instructions have both 32-bit and 16-bit variants, depending on
250 * whether we are using vectors composed of highp or mediump. At the moment, we
251 * don't support half-floats -- this requires changes in other parts of the
252 * compiler -- therefore the 16-bit versions are commented out. */
254 //M_LOAD(load_attr_16);
255 M_LOAD(load_attr_32
);
256 //M_LOAD(load_vary_16);
257 M_LOAD(load_vary_32
);
258 //M_LOAD(load_uniform_16);
259 M_LOAD(load_uniform_32
);
260 M_LOAD(load_color_buffer_8
);
261 //M_STORE(store_vary_16);
262 M_STORE(store_vary_32
);
264 static midgard_instruction
265 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
267 midgard_branch_cond branch
= {
275 memcpy(&compact
, &branch
, sizeof(branch
));
277 midgard_instruction ins
= {
279 .unit
= ALU_ENAB_BR_COMPACT
,
280 .prepacked_branch
= true,
281 .compact_branch
= true,
282 .br_compact
= compact
285 if (op
== midgard_jmp_writeout_op_writeout
)
291 static midgard_instruction
292 v_branch(bool conditional
, bool invert
)
294 midgard_instruction ins
= {
296 .unit
= ALU_ENAB_BR_COMPACT
,
297 .compact_branch
= true,
299 .conditional
= conditional
,
300 .invert_conditional
= invert
307 typedef struct midgard_bundle
{
308 /* Tag for the overall bundle */
311 /* Instructions contained by the bundle */
312 int instruction_count
;
313 midgard_instruction instructions
[5];
315 /* Bundle-wide ALU configuration */
318 bool has_embedded_constants
;
320 bool has_blend_constant
;
322 uint16_t register_words
[8];
323 int register_words_count
;
325 uint64_t body_words
[8];
327 int body_words_count
;
330 typedef struct compiler_context
{
332 gl_shader_stage stage
;
334 /* Is internally a blend shader? Depends on stage == FRAGMENT */
337 /* Tracking for blend constant patching */
338 int blend_constant_number
;
339 int blend_constant_offset
;
341 /* Current NIR function */
344 /* Unordered list of midgard_blocks */
346 struct list_head blocks
;
348 midgard_block
*initial_block
;
349 midgard_block
*previous_source_block
;
350 midgard_block
*final_block
;
352 /* List of midgard_instructions emitted for the current block */
353 midgard_block
*current_block
;
355 /* The index corresponding to the current loop, e.g. for breaks/contineus */
358 /* Constants which have been loaded, for later inlining */
359 struct hash_table_u64
*ssa_constants
;
361 /* SSA indices to be outputted to corresponding varying offset */
362 struct hash_table_u64
*ssa_varyings
;
364 /* SSA values / registers which have been aliased. Naively, these
365 * demand a fmov output; instead, we alias them in a later pass to
366 * avoid the wasted op.
368 * A note on encoding: to avoid dynamic memory management here, rather
369 * than ampping to a pointer, we map to the source index; the key
370 * itself is just the destination index. */
372 struct hash_table_u64
*ssa_to_alias
;
373 struct set
*leftover_ssa_to_alias
;
375 /* Actual SSA-to-register for RA */
376 struct hash_table_u64
*ssa_to_register
;
378 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
379 struct hash_table_u64
*hash_to_temp
;
383 /* Uniform IDs for mdg */
384 struct hash_table_u64
*uniform_nir_to_mdg
;
387 struct hash_table_u64
*varying_nir_to_mdg
;
390 /* Just the count of the max register used. Higher count => higher
391 * register pressure */
394 /* Used for cont/last hinting. Increase when a tex op is added.
395 * Decrease when a tex op is removed. */
396 int texture_op_count
;
398 /* Mapping of texture register -> SSA index for unaliasing */
399 int texture_index
[2];
401 /* Count of special uniforms (viewport, etc) in vec4 units */
402 int special_uniforms
;
404 /* If any path hits a discard instruction */
407 /* The number of uniforms allowable for the fast path */
410 /* Count of instructions emitted from NIR overall, across all blocks */
411 int instruction_count
;
413 /* Alpha ref value passed in */
416 /* The index corresponding to the fragment output */
417 unsigned fragment_output
;
420 /* Append instruction to end of current block */
422 static midgard_instruction
*
423 mir_upload_ins(struct midgard_instruction ins
)
425 midgard_instruction
*heap
= malloc(sizeof(ins
));
426 memcpy(heap
, &ins
, sizeof(ins
));
431 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
433 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
437 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
439 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
443 mir_remove_instruction(struct midgard_instruction
*ins
)
445 list_del(&ins
->link
);
448 static midgard_instruction
*
449 mir_prev_op(struct midgard_instruction
*ins
)
451 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
454 static midgard_instruction
*
455 mir_next_op(struct midgard_instruction
*ins
)
457 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
460 static midgard_block
*
461 mir_next_block(struct midgard_block
*blk
)
463 return list_first_entry(&(blk
->link
), midgard_block
, link
);
467 #define mir_foreach_block(ctx, v) list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
468 #define mir_foreach_block_from(ctx, from, v) list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
470 #define mir_foreach_instr(ctx, v) list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
471 #define mir_foreach_instr_safe(ctx, v) list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
472 #define mir_foreach_instr_in_block(block, v) list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
473 #define mir_foreach_instr_in_block_safe(block, v) list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
474 #define mir_foreach_instr_in_block_safe_rev(block, v) list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
475 #define mir_foreach_instr_in_block_from(block, v, from) list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
478 static midgard_instruction
*
479 mir_last_in_block(struct midgard_block
*block
)
481 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
484 static midgard_block
*
485 mir_get_block(compiler_context
*ctx
, int idx
)
487 struct list_head
*lst
= &ctx
->blocks
;
492 return (struct midgard_block
*) lst
;
495 /* Pretty printer for internal Midgard IR */
498 print_mir_source(int source
)
500 if (source
>= SSA_FIXED_MINIMUM
) {
501 /* Specific register */
502 int reg
= SSA_REG_FROM_FIXED(source
);
504 /* TODO: Moving threshold */
505 if (reg
> 16 && reg
< 24)
506 printf("u%d", 23 - reg
);
510 printf("%d", source
);
515 print_mir_instruction(midgard_instruction
*ins
)
521 midgard_alu_op op
= ins
->alu
.op
;
522 const char *name
= alu_opcode_names
[op
];
525 printf("%d.", ins
->unit
);
527 printf("%s", name
? name
: "??");
531 case TAG_LOAD_STORE_4
: {
532 midgard_load_store_op op
= ins
->load_store
.op
;
533 const char *name
= load_store_opcode_names
[op
];
540 case TAG_TEXTURE_4
: {
549 ssa_args
*args
= &ins
->ssa_args
;
551 printf(" %d, ", args
->dest
);
553 print_mir_source(args
->src0
);
556 if (args
->inline_constant
)
557 printf("#%d", ins
->inline_constant
);
559 print_mir_source(args
->src1
);
561 if (ins
->has_constants
)
562 printf(" <%f, %f, %f, %f>", ins
->constants
[0], ins
->constants
[1], ins
->constants
[2], ins
->constants
[3]);
568 print_mir_block(midgard_block
*block
)
572 mir_foreach_instr_in_block(block
, ins
) {
573 print_mir_instruction(ins
);
582 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
584 ins
->has_constants
= true;
585 memcpy(&ins
->constants
, constants
, 16);
587 /* If this is the special blend constant, mark this instruction */
589 if (ctx
->is_blend
&& ctx
->blend_constant_number
== name
)
590 ins
->has_blend_constant
= true;
594 glsl_type_size(const struct glsl_type
*type
)
596 return glsl_count_attribute_slots(type
, false);
599 /* Lower fdot2 to a vector multiplication followed by channel addition */
601 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
603 if (alu
->op
!= nir_op_fdot2
)
606 b
->cursor
= nir_before_instr(&alu
->instr
);
608 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
609 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
611 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
613 nir_ssa_def
*sum
= nir_fadd(b
,
614 nir_channel(b
, product
, 0),
615 nir_channel(b
, product
, 1));
617 /* Replace the fdot2 with this sum */
618 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
622 midgard_nir_lower_fdot2(nir_shader
*shader
)
624 bool progress
= false;
626 nir_foreach_function(function
, shader
) {
627 if (!function
->impl
) continue;
630 nir_builder
*b
= &_b
;
631 nir_builder_init(b
, function
->impl
);
633 nir_foreach_block(block
, function
->impl
) {
634 nir_foreach_instr_safe(instr
, block
) {
635 if (instr
->type
!= nir_instr_type_alu
) continue;
637 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
638 midgard_nir_lower_fdot2_body(b
, alu
);
644 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
652 optimise_nir(nir_shader
*nir
)
656 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
657 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
659 nir_lower_tex_options lower_tex_options
= {
663 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
668 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic
);
669 NIR_PASS(progress
, nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
670 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
671 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
673 NIR_PASS(progress
, nir
, nir_copy_prop
);
674 NIR_PASS(progress
, nir
, nir_opt_dce
);
675 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
676 NIR_PASS(progress
, nir
, nir_opt_cse
);
677 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
678 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
679 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
680 NIR_PASS(progress
, nir
, nir_opt_undef
);
681 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
684 nir_var_function_temp
);
686 /* TODO: Enable vectorize when merged upstream */
687 // NIR_PASS(progress, nir, nir_opt_vectorize);
690 /* Must be run at the end to prevent creation of fsin/fcos ops */
691 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
696 NIR_PASS(progress
, nir
, nir_opt_dce
);
697 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
698 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
699 NIR_PASS(progress
, nir
, nir_copy_prop
);
702 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
705 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_all_source_mods
);
706 NIR_PASS(progress
, nir
, nir_copy_prop
);
707 NIR_PASS(progress
, nir
, nir_opt_dce
);
709 /* Take us out of SSA */
710 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
711 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
713 /* We are a vector architecture; write combine where possible */
714 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
715 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
717 NIR_PASS(progress
, nir
, nir_opt_dce
);
720 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
721 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
722 * r0. See the comments in compiler_context */
725 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
727 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
728 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
731 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
734 unalias_ssa(compiler_context
*ctx
, int dest
)
736 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
737 /* TODO: Remove from leftover or no? */
741 midgard_pin_output(compiler_context
*ctx
, int index
, int reg
)
743 _mesa_hash_table_u64_insert(ctx
->ssa_to_register
, index
+ 1, (void *) ((uintptr_t) reg
+ 1));
747 midgard_is_pinned(compiler_context
*ctx
, int index
)
749 return _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1) != NULL
;
752 /* Do not actually emit a load; instead, cache the constant for inlining */
755 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
757 nir_ssa_def def
= instr
->def
;
759 float *v
= ralloc_array(NULL
, float, 4);
760 memcpy(v
, &instr
->value
.f32
, 4 * sizeof(float));
761 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
764 /* Duplicate bits to convert sane 4-bit writemask to obscure 8-bit format (or
768 expand_writemask(unsigned mask
)
772 for (int i
= 0; i
< 4; ++i
)
780 squeeze_writemask(unsigned mask
)
784 for (int i
= 0; i
< 4; ++i
)
785 if (mask
& (3 << (2 * i
)))
792 /* Determines effective writemask, taking quirks and expansion into account */
794 effective_writemask(midgard_vector_alu
*alu
)
796 /* Channel count is off-by-one to fit in two-bits (0 channel makes no
799 unsigned channel_count
= GET_CHANNEL_COUNT(alu_opcode_props
[alu
->op
]);
801 /* If there is a fixed channel count, construct the appropriate mask */
804 return (1 << channel_count
) - 1;
806 /* Otherwise, just squeeze the existing mask */
807 return squeeze_writemask(alu
->mask
);
811 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
813 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
816 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->hash_to_temp
, hash
+ 1);
821 /* If no temp is find, allocate one */
822 temp
= ctx
->temp_count
++;
823 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
825 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
, hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
831 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
834 return src
->ssa
->index
;
836 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
840 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
843 return dst
->ssa
.index
;
845 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
849 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
851 return nir_src_index(ctx
, &src
->src
);
854 /* Midgard puts conditionals in r31.w; move an arbitrary source (the output of
855 * a conditional test) into that register */
858 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
)
860 /* XXX: Force component correct */
861 int condition
= nir_src_index(ctx
, src
);
863 const midgard_vector_alu_src alu_src
= {
864 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
867 /* There is no boolean move instruction. Instead, we simulate a move by
868 * ANDing the condition with itself to get it into r31.w */
870 midgard_instruction ins
= {
872 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
, /* TODO: DEDUCE THIS */
876 .dest
= SSA_FIXED_REGISTER(31),
879 .op
= midgard_alu_op_iand
,
880 .reg_mode
= midgard_reg_mode_full
,
881 .dest_override
= midgard_dest_override_none
,
882 .mask
= (0x3 << 6), /* w */
883 .src1
= vector_alu_srco_unsigned(alu_src
),
884 .src2
= vector_alu_srco_unsigned(alu_src
)
888 emit_mir_instruction(ctx
, ins
);
891 #define ALU_CASE(nir, _op) \
893 op = midgard_alu_op_##_op; \
897 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
899 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
901 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
902 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
903 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
905 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
906 * supported. A few do not and are commented for now. Also, there are a
907 * number of NIR ops which Midgard does not support and need to be
908 * lowered, also TODO. This switch block emits the opcode and calling
909 * convention of the Midgard instruction; actual packing is done in
915 ALU_CASE(fadd
, fadd
);
916 ALU_CASE(fmul
, fmul
);
917 ALU_CASE(fmin
, fmin
);
918 ALU_CASE(fmax
, fmax
);
919 ALU_CASE(imin
, imin
);
920 ALU_CASE(imax
, imax
);
921 ALU_CASE(fmov
, fmov
);
922 ALU_CASE(ffloor
, ffloor
);
923 ALU_CASE(fceil
, fceil
);
924 ALU_CASE(fdot3
, fdot3
);
925 ALU_CASE(fdot4
, fdot4
);
926 ALU_CASE(iadd
, iadd
);
927 ALU_CASE(isub
, isub
);
928 ALU_CASE(imul
, imul
);
930 /* XXX: Use fmov, not imov, since imov was causing major
931 * issues with texture precision? XXX research */
932 ALU_CASE(imov
, fmov
);
941 ALU_CASE(frcp
, frcp
);
942 ALU_CASE(frsq
, frsqrt
);
943 ALU_CASE(fsqrt
, fsqrt
);
944 ALU_CASE(fexp2
, fexp2
);
945 ALU_CASE(flog2
, flog2
);
947 ALU_CASE(f2i32
, f2i
);
948 ALU_CASE(f2u32
, f2u
);
949 ALU_CASE(i2f32
, i2f
);
950 ALU_CASE(u2f32
, u2f
);
952 ALU_CASE(fsin
, fsin
);
953 ALU_CASE(fcos
, fcos
);
955 ALU_CASE(iand
, iand
);
957 ALU_CASE(ixor
, ixor
);
958 ALU_CASE(inot
, inot
);
959 ALU_CASE(ishl
, ishl
);
960 ALU_CASE(ishr
, iasr
);
961 ALU_CASE(ushr
, ilsr
);
963 ALU_CASE(ball_fequal4
, fball_eq
);
964 ALU_CASE(bany_fnequal4
, fbany_neq
);
965 ALU_CASE(ball_iequal4
, iball_eq
);
966 ALU_CASE(bany_inequal4
, ibany_neq
);
968 /* For greater-or-equal, we use less-or-equal and flip the
972 op
= midgard_alu_op_ile
;
974 /* Swap via temporary */
975 nir_alu_src temp
= instr
->src
[1];
976 instr
->src
[1] = instr
->src
[0];
977 instr
->src
[0] = temp
;
983 op
= midgard_alu_op_fcsel
;
985 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
988 emit_condition(ctx
, &instr
->src
[0].src
, false);
990 /* The condition is the first argument; move the other
991 * arguments up one to be a binary instruction for
994 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
998 /* We don't have a native b2f32 instruction. Instead, like many GPUs,
999 * we exploit booleans as 0/~0 for false/true, and correspondingly AND
1000 * by 1.0 to do the type conversion. For the moment, prime us to emit:
1002 * iand [whatever], #0
1004 * At the end of emit_alu (as MIR), we'll fix-up the constant */
1006 case nir_op_b2f32
: {
1007 op
= midgard_alu_op_iand
;
1012 printf("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
1017 /* Fetch unit, quirks, etc information */
1018 unsigned opcode_props
= alu_opcode_props
[op
];
1019 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1021 /* Initialise fields common between scalar/vector instructions */
1022 midgard_outmod outmod
= instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
1024 /* src0 will always exist afaik, but src1 will not for 1-argument
1025 * instructions. The latter can only be fetched if the instruction
1026 * needs it, or else we may segfault. */
1028 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1029 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1031 /* Rather than use the instruction generation helpers, we do it
1032 * ourselves here to avoid the mess */
1034 midgard_instruction ins
= {
1037 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1038 .src1
= quirk_flipped_r24
? src0
: src1
,
1040 .inline_constant
= (nr_inputs
== 1) && !quirk_flipped_r24
1044 nir_alu_src
*nirmods
[2] = { NULL
};
1046 if (nr_inputs
== 2) {
1047 nirmods
[0] = &instr
->src
[0];
1048 nirmods
[1] = &instr
->src
[1];
1049 } else if (nr_inputs
== 1) {
1050 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1055 midgard_vector_alu alu
= {
1057 .reg_mode
= midgard_reg_mode_full
,
1058 .dest_override
= midgard_dest_override_none
,
1061 /* Writemask only valid for non-SSA NIR */
1062 .mask
= expand_writemask((1 << nr_components
) - 1),
1064 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0])),
1065 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1])),
1068 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1071 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1075 /* Late fixup for emulated instructions */
1077 if (instr
->op
== nir_op_b2f32
) {
1078 /* Presently, our second argument is an inline #0 constant.
1079 * Switch over to an embedded 1.0 constant (that can't fit
1080 * inline, since we're 32-bit, not 16-bit like the inline
1083 ins
.ssa_args
.inline_constant
= false;
1084 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1085 ins
.has_constants
= true;
1086 ins
.constants
[0] = 1.0;
1089 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1090 /* To avoid duplicating the lookup tables (probably), true LUT
1091 * instructions can only operate as if they were scalars. Lower
1092 * them here by changing the component. */
1094 uint8_t original_swizzle
[4];
1095 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1097 for (int i
= 0; i
< nr_components
; ++i
) {
1098 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
1100 for (int j
= 0; j
< 4; ++j
)
1101 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1103 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0]));
1104 emit_mir_instruction(ctx
, ins
);
1107 emit_mir_instruction(ctx
, ins
);
1114 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1116 nir_const_value
*const_offset
;
1117 unsigned offset
, reg
;
1119 switch (instr
->intrinsic
) {
1120 case nir_intrinsic_discard_if
:
1121 emit_condition(ctx
, &instr
->src
[0], true);
1125 case nir_intrinsic_discard
: {
1126 midgard_condition cond
= instr
->intrinsic
== nir_intrinsic_discard_if
?
1127 midgard_condition_true
: midgard_condition_always
;
1129 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_discard
, 0, 2, cond
);
1130 ctx
->can_discard
= true;
1134 case nir_intrinsic_load_uniform
:
1135 case nir_intrinsic_load_input
:
1136 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1137 assert (const_offset
&& "no indirect inputs");
1139 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1141 reg
= nir_dest_index(ctx
, &instr
->dest
);
1143 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1144 /* TODO: half-floats */
1146 int uniform_offset
= 0;
1148 if (offset
>= SPECIAL_UNIFORM_BASE
) {
1149 /* XXX: Resolve which uniform */
1152 /* Offset away from the special
1155 void *entry
= _mesa_hash_table_u64_search(ctx
->uniform_nir_to_mdg
, offset
+ 1);
1159 printf("WARNING: Unknown uniform %d\n", offset
);
1163 uniform_offset
= (uintptr_t) (entry
) - 1;
1164 uniform_offset
+= ctx
->special_uniforms
;
1167 if (uniform_offset
< ctx
->uniform_cutoff
) {
1168 /* Fast path: For the first 16 uniform,
1169 * accesses are 0-cycle, since they're
1170 * just a register fetch in the usual
1171 * case. So, we alias the registers
1172 * while we're still in SSA-space */
1174 int reg_slot
= 23 - uniform_offset
;
1175 alias_ssa(ctx
, reg
, SSA_FIXED_REGISTER(reg_slot
));
1177 /* Otherwise, read from the 'special'
1178 * UBO to access higher-indexed
1179 * uniforms, at a performance cost */
1181 midgard_instruction ins
= m_load_uniform_32(reg
, uniform_offset
);
1183 /* TODO: Don't split */
1184 ins
.load_store
.varying_parameters
= (uniform_offset
& 7) << 7;
1185 ins
.load_store
.address
= uniform_offset
>> 3;
1187 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1188 emit_mir_instruction(ctx
, ins
);
1190 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1191 /* XXX: Half-floats? */
1192 /* TODO: swizzle, mask */
1194 midgard_instruction ins
= m_load_vary_32(reg
, offset
);
1196 midgard_varying_parameter p
= {
1198 .interpolation
= midgard_interp_default
,
1199 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1203 memcpy(&u
, &p
, sizeof(p
));
1204 ins
.load_store
.varying_parameters
= u
;
1206 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1207 emit_mir_instruction(ctx
, ins
);
1208 } else if (ctx
->is_blend
&& instr
->intrinsic
== nir_intrinsic_load_uniform
) {
1209 /* Constant encoded as a pinned constant */
1211 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1212 ins
.has_constants
= true;
1213 ins
.has_blend_constant
= true;
1214 emit_mir_instruction(ctx
, ins
);
1215 } else if (ctx
->is_blend
) {
1216 /* For blend shaders, a load might be
1217 * translated various ways depending on what
1218 * we're loading. Figure out how this is used */
1220 nir_variable
*out
= NULL
;
1222 nir_foreach_variable(var
, &ctx
->nir
->inputs
) {
1223 int drvloc
= var
->data
.driver_location
;
1225 if (nir_intrinsic_base(instr
) == drvloc
) {
1233 if (out
->data
.location
== VARYING_SLOT_COL0
) {
1234 /* Source color preloaded to r0 */
1236 midgard_pin_output(ctx
, reg
, 0);
1237 } else if (out
->data
.location
== VARYING_SLOT_COL1
) {
1238 /* Destination color must be read from framebuffer */
1240 midgard_instruction ins
= m_load_color_buffer_8(reg
, 0);
1241 ins
.load_store
.swizzle
= 0; /* xxxx */
1243 /* Read each component sequentially */
1245 for (int c
= 0; c
< 4; ++c
) {
1246 ins
.load_store
.mask
= (1 << c
);
1247 ins
.load_store
.unknown
= c
;
1248 emit_mir_instruction(ctx
, ins
);
1251 /* vadd.u2f hr2, abs(hr2), #0 */
1253 midgard_vector_alu_src alu_src
= blank_alu_src
;
1255 alu_src
.half
= true;
1257 midgard_instruction u2f
= {
1261 .src1
= SSA_UNUSED_0
,
1263 .inline_constant
= true
1266 .op
= midgard_alu_op_u2f
,
1267 .reg_mode
= midgard_reg_mode_half
,
1268 .dest_override
= midgard_dest_override_none
,
1270 .src1
= vector_alu_srco_unsigned(alu_src
),
1271 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1275 emit_mir_instruction(ctx
, u2f
);
1277 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1279 alu_src
.abs
= false;
1281 midgard_instruction fmul
= {
1283 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1287 .src1
= SSA_UNUSED_0
,
1288 .inline_constant
= true
1291 .op
= midgard_alu_op_fmul
,
1292 .reg_mode
= midgard_reg_mode_full
,
1293 .dest_override
= midgard_dest_override_none
,
1294 .outmod
= midgard_outmod_sat
,
1296 .src1
= vector_alu_srco_unsigned(alu_src
),
1297 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1301 emit_mir_instruction(ctx
, fmul
);
1303 printf("Unknown input in blend shader\n");
1306 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1307 midgard_instruction ins
= m_load_attr_32(reg
, offset
);
1308 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1309 ins
.load_store
.mask
= (1 << instr
->num_components
) - 1;
1310 emit_mir_instruction(ctx
, ins
);
1312 printf("Unknown load\n");
1318 case nir_intrinsic_store_output
:
1319 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1320 assert(const_offset
&& "no indirect outputs");
1322 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1324 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1326 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1327 /* gl_FragColor is not emitted with load/store
1328 * instructions. Instead, it gets plonked into
1329 * r0 at the end of the shader and we do the
1330 * framebuffer writeout dance. TODO: Defer
1333 midgard_pin_output(ctx
, reg
, 0);
1335 /* Save the index we're writing to for later reference
1336 * in the epilogue */
1338 ctx
->fragment_output
= reg
;
1339 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1340 /* Varyings are written into one of two special
1341 * varying register, r26 or r27. The register itself is selected as the register
1342 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1344 * Normally emitting fmov's is frowned upon,
1345 * but due to unique constraints of
1346 * REGISTER_VARYING, fmov emission + a
1347 * dedicated cleanup pass is the only way to
1348 * guarantee correctness when considering some
1349 * (common) edge cases XXX: FIXME */
1351 /* Look up how it was actually laid out */
1353 void *entry
= _mesa_hash_table_u64_search(ctx
->varying_nir_to_mdg
, offset
+ 1);
1356 printf("WARNING: skipping varying\n");
1360 offset
= (uintptr_t) (entry
) - 1;
1362 /* If this varying corresponds to a constant (why?!),
1363 * emit that now since it won't get picked up by
1364 * hoisting (since there is no corresponding move
1365 * emitted otherwise) */
1367 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1369 if (constant_value
) {
1370 /* Special case: emit the varying write
1371 * directly to r26 (looks funny in asm but it's
1372 * fine) and emit the store _now_. Possibly
1373 * slightly slower, but this is a really stupid
1374 * special case anyway (why on earth would you
1375 * have a constant varying? Your own fault for
1376 * slightly worse perf :P) */
1378 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1379 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1380 emit_mir_instruction(ctx
, ins
);
1382 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(0), offset
);
1383 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1384 emit_mir_instruction(ctx
, st
);
1386 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1388 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1391 printf("Unknown store\n");
1397 case nir_intrinsic_load_alpha_ref_float
:
1398 assert(instr
->dest
.is_ssa
);
1400 float ref_value
= ctx
->alpha_ref
;
1402 float *v
= ralloc_array(NULL
, float, 4);
1403 memcpy(v
, &ref_value
, sizeof(float));
1404 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1409 printf ("Unhandled intrinsic\n");
1416 midgard_tex_format(enum glsl_sampler_dim dim
)
1419 case GLSL_SAMPLER_DIM_2D
:
1420 case GLSL_SAMPLER_DIM_EXTERNAL
:
1423 case GLSL_SAMPLER_DIM_3D
:
1426 case GLSL_SAMPLER_DIM_CUBE
:
1427 return TEXTURE_CUBE
;
1430 printf("Unknown sampler dim type\n");
1437 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1440 //assert (!instr->sampler);
1441 //assert (!instr->texture_array_size);
1442 assert (instr
->op
== nir_texop_tex
);
1444 /* Allocate registers via a round robin scheme to alternate between the two registers */
1445 int reg
= ctx
->texture_op_count
& 1;
1446 int in_reg
= reg
, out_reg
= reg
;
1448 /* Make room for the reg */
1450 if (ctx
->texture_index
[reg
] > -1)
1451 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1453 int texture_index
= instr
->texture_index
;
1454 int sampler_index
= texture_index
;
1456 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1457 switch (instr
->src
[i
].src_type
) {
1458 case nir_tex_src_coord
: {
1459 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1461 midgard_vector_alu_src alu_src
= blank_alu_src
;
1462 alu_src
.swizzle
= (COMPONENT_Y
<< 2);
1464 midgard_instruction ins
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
));
1465 emit_mir_instruction(ctx
, ins
);
1467 //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg);
1473 printf("Unknown source type\n");
1480 /* No helper to build texture words -- we do it all here */
1481 midgard_instruction ins
= {
1482 .type
= TAG_TEXTURE_4
,
1484 .op
= TEXTURE_OP_NORMAL
,
1485 .format
= midgard_tex_format(instr
->sampler_dim
),
1486 .texture_handle
= texture_index
,
1487 .sampler_handle
= sampler_index
,
1489 /* TODO: Don't force xyzw */
1490 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1502 /* Assume we can continue; hint it out later */
1507 /* Set registers to read and write from the same place */
1508 ins
.texture
.in_reg_select
= in_reg
;
1509 ins
.texture
.out_reg_select
= out_reg
;
1511 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1512 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1513 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1514 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1515 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1517 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1518 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1519 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1522 emit_mir_instruction(ctx
, ins
);
1524 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1526 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1527 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1528 ctx
->texture_index
[reg
] = o_index
;
1530 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1531 emit_mir_instruction(ctx
, ins2
);
1533 /* Used for .cont and .last hinting */
1534 ctx
->texture_op_count
++;
1538 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1540 switch (instr
->type
) {
1541 case nir_jump_break
: {
1542 /* Emit a branch out of the loop */
1543 struct midgard_instruction br
= v_branch(false, false);
1544 br
.branch
.target_type
= TARGET_BREAK
;
1545 br
.branch
.target_break
= ctx
->current_loop
;
1546 emit_mir_instruction(ctx
, br
);
1548 printf("break..\n");
1553 printf("Unknown jump type %d\n", instr
->type
);
1559 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1561 switch (instr
->type
) {
1562 case nir_instr_type_load_const
:
1563 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1566 case nir_instr_type_intrinsic
:
1567 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1570 case nir_instr_type_alu
:
1571 emit_alu(ctx
, nir_instr_as_alu(instr
));
1574 case nir_instr_type_tex
:
1575 emit_tex(ctx
, nir_instr_as_tex(instr
));
1578 case nir_instr_type_jump
:
1579 emit_jump(ctx
, nir_instr_as_jump(instr
));
1582 case nir_instr_type_ssa_undef
:
1587 printf("Unhandled instruction type\n");
1592 /* Determine the actual hardware from the index based on the RA results or special values */
1595 dealias_register(compiler_context
*ctx
, struct ra_graph
*g
, int reg
, int maxreg
)
1597 if (reg
>= SSA_FIXED_MINIMUM
)
1598 return SSA_REG_FROM_FIXED(reg
);
1601 assert(reg
< maxreg
);
1602 int r
= ra_get_node_reg(g
, reg
);
1603 ctx
->work_registers
= MAX2(ctx
->work_registers
, r
);
1608 /* fmov style unused */
1610 return REGISTER_UNUSED
;
1612 /* lut style unused */
1614 return REGISTER_UNUSED
;
1617 printf("Unknown SSA register alias %d\n", reg
);
1624 midgard_ra_select_callback(struct ra_graph
*g
, BITSET_WORD
*regs
, void *data
)
1626 /* Choose the first available register to minimise reported register pressure */
1628 for (int i
= 0; i
< 16; ++i
) {
1629 if (BITSET_TEST(regs
, i
)) {
1639 midgard_is_live_in_instr(midgard_instruction
*ins
, int src
)
1641 if (ins
->ssa_args
.src0
== src
) return true;
1642 if (ins
->ssa_args
.src1
== src
) return true;
1648 is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
)
1650 /* Check the rest of the block for liveness */
1651 mir_foreach_instr_in_block_from(block
, ins
, mir_next_op(start
)) {
1652 if (midgard_is_live_in_instr(ins
, src
))
1656 /* Check the rest of the blocks for liveness */
1657 mir_foreach_block_from(ctx
, mir_next_block(block
), b
) {
1658 mir_foreach_instr_in_block(b
, ins
) {
1659 if (midgard_is_live_in_instr(ins
, src
))
1664 /* TODO: How does control flow interact in complex shaders? */
1670 allocate_registers(compiler_context
*ctx
)
1672 /* First, initialize the RA */
1673 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, 32, true);
1675 /* Create a primary (general purpose) class, as well as special purpose
1676 * pipeline register classes */
1678 int primary_class
= ra_alloc_reg_class(regs
);
1679 int varying_class
= ra_alloc_reg_class(regs
);
1681 /* Add the full set of work registers */
1682 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
1683 for (int i
= 0; i
< work_count
; ++i
)
1684 ra_class_add_reg(regs
, primary_class
, i
);
1686 /* Add special registers */
1687 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
);
1688 ra_class_add_reg(regs
, varying_class
, REGISTER_VARYING_BASE
+ 1);
1690 /* We're done setting up */
1691 ra_set_finalize(regs
, NULL
);
1693 /* Transform the MIR into squeezed index form */
1694 mir_foreach_block(ctx
, block
) {
1695 mir_foreach_instr_in_block(block
, ins
) {
1696 if (ins
->compact_branch
) continue;
1698 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
1699 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
1700 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
1703 print_mir_block(block
);
1706 /* Let's actually do register allocation */
1707 int nodes
= ctx
->temp_count
;
1708 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
1710 /* Set everything to the work register class, unless it has somewhere
1713 mir_foreach_block(ctx
, block
) {
1714 mir_foreach_instr_in_block(block
, ins
) {
1715 if (ins
->compact_branch
) continue;
1717 if (ins
->ssa_args
.dest
< 0) continue;
1719 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1721 int class = primary_class
;
1723 ra_set_node_class(g
, ins
->ssa_args
.dest
, class);
1727 for (int index
= 0; index
<= ctx
->max_hash
; ++index
) {
1728 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_register
, index
+ 1);
1731 unsigned reg
= temp
- 1;
1732 int t
= find_or_allocate_temp(ctx
, index
);
1733 ra_set_node_reg(g
, t
, reg
);
1737 /* Determine liveness */
1739 int *live_start
= malloc(nodes
* sizeof(int));
1740 int *live_end
= malloc(nodes
* sizeof(int));
1742 /* Initialize as non-existent */
1744 for (int i
= 0; i
< nodes
; ++i
) {
1745 live_start
[i
] = live_end
[i
] = -1;
1750 mir_foreach_block(ctx
, block
) {
1751 mir_foreach_instr_in_block(block
, ins
) {
1752 if (ins
->compact_branch
) continue;
1754 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
1755 /* If this destination is not yet live, it is now since we just wrote it */
1757 int dest
= ins
->ssa_args
.dest
;
1759 if (live_start
[dest
] == -1)
1760 live_start
[dest
] = d
;
1763 /* Since we just used a source, the source might be
1764 * dead now. Scan the rest of the block for
1765 * invocations, and if there are none, the source dies
1768 int sources
[2] = { ins
->ssa_args
.src0
, ins
->ssa_args
.src1
};
1770 for (int src
= 0; src
< 2; ++src
) {
1771 int s
= sources
[src
];
1773 if (s
< 0) continue;
1775 if (s
>= SSA_FIXED_MINIMUM
) continue;
1777 if (!is_live_after(ctx
, block
, ins
, s
)) {
1786 /* If a node still hasn't been killed, kill it now */
1788 for (int i
= 0; i
< nodes
; ++i
) {
1789 /* live_start == -1 most likely indicates a pinned output */
1791 if (live_end
[i
] == -1)
1795 /* Setup interference between nodes that are live at the same time */
1797 for (int i
= 0; i
< nodes
; ++i
) {
1798 for (int j
= i
+ 1; j
< nodes
; ++j
) {
1799 if (!(live_start
[i
] >= live_end
[j
] || live_start
[j
] >= live_end
[i
]))
1800 ra_add_node_interference(g
, i
, j
);
1804 ra_set_select_reg_callback(g
, midgard_ra_select_callback
, NULL
);
1806 if (!ra_allocate(g
)) {
1807 printf("Error allocating registers\n");
1815 mir_foreach_block(ctx
, block
) {
1816 mir_foreach_instr_in_block(block
, ins
) {
1817 if (ins
->compact_branch
) continue;
1819 ssa_args args
= ins
->ssa_args
;
1821 switch (ins
->type
) {
1823 ins
->registers
.src1_reg
= dealias_register(ctx
, g
, args
.src0
, nodes
);
1825 ins
->registers
.src2_imm
= args
.inline_constant
;
1827 if (args
.inline_constant
) {
1828 /* Encode inline 16-bit constant as a vector by default */
1830 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
1832 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1834 uint16_t imm
= ((lower_11
>> 8) & 0x7) | ((lower_11
& 0xFF) << 3);
1835 ins
->alu
.src2
= imm
<< 2;
1837 ins
->registers
.src2_reg
= dealias_register(ctx
, g
, args
.src1
, nodes
);
1840 ins
->registers
.out_reg
= dealias_register(ctx
, g
, args
.dest
, nodes
);
1844 case TAG_LOAD_STORE_4
: {
1845 if (OP_IS_STORE(ins
->load_store
.op
)) {
1846 /* TODO: use ssa_args for store_vary */
1847 ins
->load_store
.reg
= 0;
1849 bool has_dest
= args
.dest
>= 0;
1850 int ssa_arg
= has_dest
? args
.dest
: args
.src0
;
1852 ins
->load_store
.reg
= dealias_register(ctx
, g
, ssa_arg
, nodes
);
1865 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1866 * use scalar ALU instructions, for functional or performance reasons. To do
1867 * this, we just demote vector ALU payloads to scalar. */
1870 component_from_mask(unsigned mask
)
1872 for (int c
= 0; c
< 4; ++c
) {
1873 if (mask
& (3 << (2 * c
)))
1882 is_single_component_mask(unsigned mask
)
1886 for (int c
= 0; c
< 4; ++c
)
1887 if (mask
& (3 << (2 * c
)))
1890 return components
== 1;
1893 /* Create a mask of accessed components from a swizzle to figure out vector
1897 swizzle_to_access_mask(unsigned swizzle
)
1899 unsigned component_mask
= 0;
1901 for (int i
= 0; i
< 4; ++i
) {
1902 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1903 component_mask
|= (1 << c
);
1906 return component_mask
;
1910 vector_to_scalar_source(unsigned u
)
1912 midgard_vector_alu_src v
;
1913 memcpy(&v
, &u
, sizeof(v
));
1915 midgard_scalar_alu_src s
= {
1919 .component
= (v
.swizzle
& 3) << 1
1923 memcpy(&o
, &s
, sizeof(s
));
1925 return o
& ((1 << 6) - 1);
1928 static midgard_scalar_alu
1929 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
1931 /* The output component is from the mask */
1932 midgard_scalar_alu s
= {
1934 .src1
= vector_to_scalar_source(v
.src1
),
1935 .src2
= vector_to_scalar_source(v
.src2
),
1938 .output_full
= 1, /* TODO: Half */
1939 .output_component
= component_from_mask(v
.mask
) << 1,
1942 /* Inline constant is passed along rather than trying to extract it
1945 if (ins
->ssa_args
.inline_constant
) {
1947 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1948 imm
|= (lower_11
>> 9) & 3;
1949 imm
|= (lower_11
>> 6) & 4;
1950 imm
|= (lower_11
>> 2) & 0x38;
1951 imm
|= (lower_11
& 63) << 6;
1959 /* Midgard prefetches instruction types, so during emission we need to
1960 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1961 * if this is the second to last and the last is an ALU, then it's also 1... */
1963 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
1964 tag == TAG_ALU_12 || tag == TAG_ALU_16)
1966 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
1967 bytes_emitted += sizeof(type)
1970 emit_binary_vector_instruction(midgard_instruction
*ains
,
1971 uint16_t *register_words
, int *register_words_count
,
1972 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
1973 size_t *bytes_emitted
)
1975 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
1976 *bytes_emitted
+= sizeof(midgard_reg_info
);
1978 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
1979 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
1980 *bytes_emitted
+= sizeof(midgard_vector_alu
);
1983 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
1984 * mind that we are a vector architecture and we can write to different
1985 * components simultaneously */
1988 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
1990 /* Each instruction reads some registers and writes to a register. See
1991 * where the first writes */
1993 /* Figure out where exactly we wrote to */
1994 int source
= first
->ssa_args
.dest
;
1995 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
1997 /* As long as the second doesn't read from the first, we're okay */
1998 if (second
->ssa_args
.src0
== source
) {
1999 if (first
->type
== TAG_ALU_4
) {
2000 /* Figure out which components we just read from */
2002 int q
= second
->alu
.src1
;
2003 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2005 /* Check if there are components in common, and fail if so */
2006 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
2013 if (second
->ssa_args
.src1
== source
)
2016 /* Otherwise, it's safe in that regard. Another data hazard is both
2017 * writing to the same place, of course */
2019 if (second
->ssa_args
.dest
== source
) {
2020 /* ...but only if the components overlap */
2021 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
2023 if (dest_mask
& source_mask
)
2031 /* Schedules, but does not emit, a single basic block. After scheduling, the
2032 * final tag and size of the block are known, which are necessary for branching
2035 static midgard_bundle
2036 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
2038 int instructions_emitted
= 0, instructions_consumed
= -1;
2039 midgard_bundle bundle
= { 0 };
2041 uint8_t tag
= ins
->type
;
2043 /* Default to the instruction's tag */
2046 switch (ins
->type
) {
2048 uint32_t control
= 0;
2049 size_t bytes_emitted
= sizeof(control
);
2051 /* TODO: Constant combining */
2052 int index
= 0, last_unit
= 0;
2054 /* Previous instructions, for the purpose of parallelism */
2055 midgard_instruction
*segment
[4] = {0};
2056 int segment_size
= 0;
2058 instructions_emitted
= -1;
2059 midgard_instruction
*pins
= ins
;
2062 midgard_instruction
*ains
= pins
;
2064 /* Advance instruction pointer */
2066 ains
= mir_next_op(pins
);
2070 /* Out-of-work condition */
2071 if ((struct list_head
*) ains
== &block
->instructions
)
2074 /* Ensure that the chain can continue */
2075 if (ains
->type
!= TAG_ALU_4
) break;
2077 /* According to the presentation "The ARM
2078 * Mali-T880 Mobile GPU" from HotChips 27,
2079 * there are two pipeline stages. Branching
2080 * position determined experimentally. Lines
2081 * are executed in parallel:
2084 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
2086 * Verify that there are no ordering dependencies here.
2088 * TODO: Allow for parallelism!!!
2091 /* Pick a unit for it if it doesn't force a particular unit */
2093 int unit
= ains
->unit
;
2096 int op
= ains
->alu
.op
;
2097 int units
= alu_opcode_props
[op
];
2099 /* TODO: Promotion of scalars to vectors */
2100 int vector
= ((!is_single_component_mask(ains
->alu
.mask
)) || ((units
& UNITS_SCALAR
) == 0)) && (units
& UNITS_ANY_VECTOR
);
2103 assert(units
& UNITS_SCALAR
);
2106 if (last_unit
>= UNIT_VADD
) {
2107 if (units
& UNIT_VLUT
)
2112 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
2114 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2116 else if (units
& UNIT_VLUT
)
2122 if (last_unit
>= UNIT_VADD
) {
2123 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
2125 else if (units
& UNIT_VLUT
)
2130 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
))
2132 else if (units
& UNIT_SMUL
)
2134 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
2141 assert(unit
& units
);
2144 /* Late unit check, this time for encoding (not parallelism) */
2145 if (unit
<= last_unit
) break;
2147 /* Clear the segment */
2148 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
2151 /* Check for data hazards */
2152 int has_hazard
= false;
2154 for (int s
= 0; s
< segment_size
; ++s
)
2155 if (!can_run_concurrent_ssa(segment
[s
], ains
))
2161 /* We're good to go -- emit the instruction */
2164 segment
[segment_size
++] = ains
;
2166 /* Only one set of embedded constants per
2167 * bundle possible; if we have more, we must
2168 * break the chain early, unfortunately */
2170 if (ains
->has_constants
) {
2171 if (bundle
.has_embedded_constants
) {
2172 /* ...but if there are already
2173 * constants but these are the
2174 * *same* constants, we let it
2177 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
2180 bundle
.has_embedded_constants
= true;
2181 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
2183 /* If this is a blend shader special constant, track it for patching */
2184 if (ains
->has_blend_constant
)
2185 bundle
.has_blend_constant
= true;
2189 if (ains
->unit
& UNITS_ANY_VECTOR
) {
2190 emit_binary_vector_instruction(ains
, bundle
.register_words
,
2191 &bundle
.register_words_count
, bundle
.body_words
,
2192 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2193 } else if (ains
->compact_branch
) {
2194 /* All of r0 has to be written out
2195 * along with the branch writeout.
2198 if (ains
->writeout
) {
2200 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2201 ins
.unit
= UNIT_VMUL
;
2203 control
|= ins
.unit
;
2205 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
2206 &bundle
.register_words_count
, bundle
.body_words
,
2207 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
2209 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
2210 bool written_late
= false;
2211 bool components
[4] = { 0 };
2212 uint16_t register_dep_mask
= 0;
2213 uint16_t written_mask
= 0;
2215 midgard_instruction
*qins
= ins
;
2216 for (int t
= 0; t
< index
; ++t
) {
2217 if (qins
->registers
.out_reg
!= 0) {
2218 /* Mark down writes */
2220 written_mask
|= (1 << qins
->registers
.out_reg
);
2222 /* Mark down the register dependencies for errata check */
2224 if (qins
->registers
.src1_reg
< 16)
2225 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
2227 if (qins
->registers
.src2_reg
< 16)
2228 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
2230 int mask
= qins
->alu
.mask
;
2232 for (int c
= 0; c
< 4; ++c
)
2233 if (mask
& (0x3 << (2 * c
)))
2234 components
[c
] = true;
2236 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
2238 if (qins
->unit
== UNIT_VLUT
)
2239 written_late
= true;
2242 /* Advance instruction pointer */
2243 qins
= mir_next_op(qins
);
2247 /* ERRATA (?): In a bundle ending in a fragment writeout, the register dependencies of r0 cannot be written within this bundle (discovered in -bshading:shading=phong) */
2248 if (register_dep_mask
& written_mask
) {
2249 printf("ERRATA WORKAROUND: Breakup for writeout dependency masks %X vs %X (common %X)\n", register_dep_mask
, written_mask
, register_dep_mask
& written_mask
);
2256 /* If even a single component is not written, break it up (conservative check). */
2257 bool breakup
= false;
2259 for (int c
= 0; c
< 4; ++c
)
2266 /* Otherwise, we're free to proceed */
2270 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
2271 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
2272 bytes_emitted
+= sizeof(ains
->br_compact
);
2274 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
2275 bytes_emitted
+= sizeof(midgard_reg_info
);
2277 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
2278 bundle
.body_words_count
++;
2279 bytes_emitted
+= sizeof(midgard_scalar_alu
);
2282 /* Defer marking until after writing to allow for break */
2283 control
|= ains
->unit
;
2284 last_unit
= ains
->unit
;
2285 ++instructions_emitted
;
2289 /* Bubble up the number of instructions for skipping */
2290 instructions_consumed
= index
- 1;
2294 /* Pad ALU op to nearest word */
2296 if (bytes_emitted
& 15) {
2297 padding
= 16 - (bytes_emitted
& 15);
2298 bytes_emitted
+= padding
;
2301 /* Constants must always be quadwords */
2302 if (bundle
.has_embedded_constants
)
2303 bytes_emitted
+= 16;
2305 /* Size ALU instruction for tag */
2306 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
2307 bundle
.padding
= padding
;
2308 bundle
.control
= bundle
.tag
| control
;
2313 case TAG_LOAD_STORE_4
: {
2314 /* Load store instructions have two words at once. If
2315 * we only have one queued up, we need to NOP pad.
2316 * Otherwise, we store both in succession to save space
2317 * and cycles -- letting them go in parallel -- skip
2318 * the next. The usefulness of this optimisation is
2319 * greatly dependent on the quality of the instruction
2323 midgard_instruction
*next_op
= mir_next_op(ins
);
2325 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
2326 /* As the two operate concurrently, make sure
2327 * they are not dependent */
2329 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
2330 /* Skip ahead, since it's redundant with the pair */
2331 instructions_consumed
= 1 + (instructions_emitted
++);
2339 /* Texture ops default to single-op-per-bundle scheduling */
2343 /* Copy the instructions into the bundle */
2344 bundle
.instruction_count
= instructions_emitted
+ 1;
2348 midgard_instruction
*uins
= ins
;
2349 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2350 bundle
.instructions
[used_idx
++] = *uins
;
2351 uins
= mir_next_op(uins
);
2354 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2360 quadword_size(int tag
)
2375 case TAG_LOAD_STORE_4
:
2387 /* Schedule a single block by iterating its instruction to create bundles.
2388 * While we go, tally about the bundle sizes to compute the block size. */
2391 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2393 util_dynarray_init(&block
->bundles
, NULL
);
2395 block
->quadword_count
= 0;
2397 mir_foreach_instr_in_block(block
, ins
) {
2399 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2400 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2402 if (bundle
.has_blend_constant
) {
2403 /* TODO: Multiblock? */
2404 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2405 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2409 ins
= mir_next_op(ins
);
2411 block
->quadword_count
+= quadword_size(bundle
.tag
);
2414 block
->is_scheduled
= true;
2418 schedule_program(compiler_context
*ctx
)
2420 allocate_registers(ctx
);
2422 mir_foreach_block(ctx
, block
) {
2423 schedule_block(ctx
, block
);
2427 /* After everything is scheduled, emit whole bundles at a time */
2430 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2432 int lookahead
= next_tag
<< 4;
2434 switch (bundle
->tag
) {
2439 /* Actually emit each component */
2440 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2442 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2443 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2445 /* Emit body words based on the instructions bundled */
2446 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2447 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2449 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2450 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2451 } else if (ins
->compact_branch
) {
2452 /* Dummy move, XXX DRY */
2453 if ((i
== 0) && ins
->writeout
) {
2454 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2455 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2458 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2461 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2462 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2466 /* Emit padding (all zero) */
2467 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2469 /* Tack on constants */
2471 if (bundle
->has_embedded_constants
) {
2472 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2473 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2474 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2475 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2481 case TAG_LOAD_STORE_4
: {
2482 /* One or two composing instructions */
2484 uint64_t current64
, next64
= LDST_NOP
;
2486 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2488 if (bundle
->instruction_count
== 2)
2489 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2491 midgard_load_store instruction
= {
2492 .type
= bundle
->tag
,
2493 .next_type
= next_tag
,
2498 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2503 case TAG_TEXTURE_4
: {
2504 /* Texture instructions are easy, since there is no
2505 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2507 midgard_instruction
*ins
= &bundle
->instructions
[0];
2509 ins
->texture
.type
= TAG_TEXTURE_4
;
2510 ins
->texture
.next_type
= next_tag
;
2512 ctx
->texture_op_count
--;
2514 if (!ctx
->texture_op_count
) {
2515 ins
->texture
.cont
= 0;
2516 ins
->texture
.last
= 1;
2519 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2524 printf("Unknown midgard instruction type\n");
2531 /* ALU instructions can inline or embed constants, which decreases register
2532 * pressure and saves space. */
2534 #define CONDITIONAL_ATTACH(src) { \
2535 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2538 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2539 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2544 inline_alu_constants(compiler_context
*ctx
)
2546 mir_foreach_instr(ctx
, alu
) {
2547 /* Other instructions cannot inline constants */
2548 if (alu
->type
!= TAG_ALU_4
) continue;
2550 /* If there is already a constant here, we can do nothing */
2551 if (alu
->has_constants
) continue;
2553 CONDITIONAL_ATTACH(src0
);
2555 if (!alu
->has_constants
) {
2556 CONDITIONAL_ATTACH(src1
)
2557 } else if (!alu
->inline_constant
) {
2558 /* Corner case: _two_ vec4 constants, for instance with a
2559 * csel. For this case, we can only use a constant
2560 * register for one, we'll have to emit a move for the
2561 * other. Note, if both arguments are constants, then
2562 * necessarily neither argument depends on the value of
2563 * any particular register. As the destination register
2564 * will be wiped, that means we can spill the constant
2565 * to the destination register.
2568 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2569 unsigned scratch
= alu
->ssa_args
.dest
;
2572 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2573 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2575 /* Force a break XXX Defer r31 writes */
2576 ins
.unit
= UNIT_VLUT
;
2578 /* Set the source */
2579 alu
->ssa_args
.src1
= scratch
;
2581 /* Inject us -before- the last instruction which set r31 */
2582 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2588 /* Midgard supports two types of constants, embedded constants (128-bit) and
2589 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2590 * constants can be demoted to inline constants, for space savings and
2591 * sometimes a performance boost */
2594 embedded_to_inline_constant(compiler_context
*ctx
)
2596 mir_foreach_instr(ctx
, ins
) {
2597 if (!ins
->has_constants
) continue;
2599 if (ins
->ssa_args
.inline_constant
) continue;
2601 /* Blend constants must not be inlined by definition */
2602 if (ins
->has_blend_constant
) continue;
2604 /* src1 cannot be an inline constant due to encoding
2605 * restrictions. So, if possible we try to flip the arguments
2608 int op
= ins
->alu
.op
;
2610 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2611 /* Flip based on op. Fallthrough intentional */
2614 /* These ops require an operational change to flip their arguments TODO */
2615 case midgard_alu_op_flt
:
2616 case midgard_alu_op_fle
:
2617 case midgard_alu_op_ilt
:
2618 case midgard_alu_op_ile
:
2619 case midgard_alu_op_fcsel
:
2620 case midgard_alu_op_icsel
:
2621 case midgard_alu_op_isub
:
2622 printf("Missed non-commutative flip (%s)\n", alu_opcode_names
[op
]);
2625 /* These ops are commutative and Just Flip */
2626 case midgard_alu_op_fne
:
2627 case midgard_alu_op_fadd
:
2628 case midgard_alu_op_fmul
:
2629 case midgard_alu_op_fmin
:
2630 case midgard_alu_op_fmax
:
2631 case midgard_alu_op_iadd
:
2632 case midgard_alu_op_imul
:
2633 case midgard_alu_op_feq
:
2634 case midgard_alu_op_ieq
:
2635 case midgard_alu_op_ine
:
2636 case midgard_alu_op_iand
:
2637 case midgard_alu_op_ior
:
2638 case midgard_alu_op_ixor
:
2639 /* Flip the SSA numbers */
2640 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2641 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2643 /* And flip the modifiers */
2647 src_temp
= ins
->alu
.src2
;
2648 ins
->alu
.src2
= ins
->alu
.src1
;
2649 ins
->alu
.src1
= src_temp
;
2656 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2657 /* Extract the source information */
2659 midgard_vector_alu_src
*src
;
2660 int q
= ins
->alu
.src2
;
2661 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2664 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2665 int component
= src
->swizzle
& 3;
2667 /* Scale constant appropriately, if we can legally */
2668 uint16_t scaled_constant
= 0;
2670 /* XXX: Check legality */
2671 if (midgard_is_integer_op(op
)) {
2672 /* TODO: Inline integer */
2675 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2676 scaled_constant
= (uint16_t) iconstants
[component
];
2678 /* Constant overflow after resize */
2679 if (scaled_constant
!= iconstants
[component
])
2682 scaled_constant
= _mesa_float_to_half((float) ins
->constants
[component
]);
2685 /* We don't know how to handle these with a constant */
2687 if (src
->abs
|| src
->negate
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2688 printf("Bailing inline constant...\n");
2692 /* Make sure that the constant is not itself a
2693 * vector by checking if all accessed values
2694 * (by the swizzle) are the same. */
2696 uint32_t *cons
= (uint32_t *) ins
->constants
;
2697 uint32_t value
= cons
[component
];
2699 bool is_vector
= false;
2700 unsigned mask
= effective_writemask(&ins
->alu
);
2702 for (int c
= 1; c
< 4; ++c
) {
2703 /* We only care if this component is actually used */
2704 if (!(mask
& (1 << c
)))
2707 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2709 if (test
!= value
) {
2718 /* Get rid of the embedded constant */
2719 ins
->has_constants
= false;
2720 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2721 ins
->ssa_args
.inline_constant
= true;
2722 ins
->inline_constant
= scaled_constant
;
2727 /* Map normal SSA sources to other SSA sources / fixed registers (like
2731 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2733 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2736 /* Remove entry in leftovers to avoid a redunant fmov */
2738 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2741 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2743 /* Assign the alias map */
2749 #define AS_SRC(to, u) \
2750 int q##to = ins->alu.src2; \
2751 midgard_vector_alu_src *to = (midgard_vector_alu_src *) &q##to;
2753 /* Removing unused moves is necessary to clean up the texture pipeline results.
2755 * To do so, we find moves in the MIR. We check if their destination is live later. If it's not, the move is redundant. */
2758 midgard_eliminate_orphan_moves(compiler_context
*ctx
, midgard_block
*block
)
2760 mir_foreach_instr_in_block_safe(block
, ins
) {
2761 if (ins
->type
!= TAG_ALU_4
) continue;
2763 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2765 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2767 if (midgard_is_pinned(ctx
, ins
->ssa_args
.dest
)) continue;
2769 if (is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2771 mir_remove_instruction(ins
);
2775 /* The following passes reorder MIR instructions to enable better scheduling */
2778 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2780 mir_foreach_instr_in_block_safe(block
, ins
) {
2781 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2783 /* We've found a load/store op. Check if next is also load/store. */
2784 midgard_instruction
*next_op
= mir_next_op(ins
);
2785 if (&next_op
->link
!= &block
->instructions
) {
2786 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2787 /* If so, we're done since we're a pair */
2788 ins
= mir_next_op(ins
);
2792 /* Maximum search distance to pair, to avoid register pressure disasters */
2793 int search_distance
= 8;
2795 /* Otherwise, we have an orphaned load/store -- search for another load */
2796 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2797 /* Terminate search if necessary */
2798 if (!(search_distance
--)) break;
2800 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2802 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2804 /* We found one! Move it up to pair and remove it from the old location */
2806 mir_insert_instruction_before(ins
, *c
);
2807 mir_remove_instruction(c
);
2815 /* Emit varying stores late */
2818 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2819 /* Iterate in reverse to get the final write, rather than the first */
2821 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2822 /* Check if what we just wrote needs a store */
2823 int idx
= ins
->ssa_args
.dest
;
2824 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2826 if (!varying
) continue;
2830 /* We need to store to the appropriate varying, so emit the
2833 /* TODO: Integrate with special purpose RA (and scheduler?) */
2834 bool high_varying_register
= false;
2836 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2838 midgard_instruction st
= m_store_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2839 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2841 mir_insert_instruction_before(mir_next_op(ins
), st
);
2842 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2844 /* We no longer need to store this varying */
2845 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2849 /* If there are leftovers after the below pass, emit actual fmov
2850 * instructions for the slow-but-correct path */
2853 emit_leftover_move(compiler_context
*ctx
)
2855 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2856 int base
= ((uintptr_t) leftover
->key
) - 1;
2859 map_ssa_to_alias(ctx
, &mapped
);
2860 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2865 actualise_ssa_to_alias(compiler_context
*ctx
)
2867 mir_foreach_instr(ctx
, ins
) {
2868 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2869 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2872 emit_leftover_move(ctx
);
2875 /* Vertex shaders do not write gl_Position as is; instead, they write a
2876 * transformed screen space position as a varying. See section 12.5 "Coordinate
2877 * Transformation" of the ES 3.2 full specification for details.
2879 * This transformation occurs early on, as NIR and prior to optimisation, in
2880 * order to take advantage of NIR optimisation passes of the transform itself.
2884 write_transformed_position(nir_builder
*b
, nir_src input_point_src
, int uniform_no
)
2886 nir_ssa_def
*input_point
= nir_ssa_for_src(b
, input_point_src
, 4);
2888 /* Get viewport from the uniforms */
2889 nir_intrinsic_instr
*load
;
2890 load
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_uniform
);
2891 load
->num_components
= 4;
2892 load
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, uniform_no
));
2893 nir_ssa_dest_init(&load
->instr
, &load
->dest
, 4, 32, NULL
);
2894 nir_builder_instr_insert(b
, &load
->instr
);
2896 /* Formatted as <width, height, centerx, centery> */
2897 nir_ssa_def
*viewport_vec4
= &load
->dest
.ssa
;
2898 nir_ssa_def
*viewport_width_2
= nir_channel(b
, viewport_vec4
, 0);
2899 nir_ssa_def
*viewport_height_2
= nir_channel(b
, viewport_vec4
, 1);
2900 nir_ssa_def
*viewport_offset
= nir_channels(b
, viewport_vec4
, 0x8 | 0x4);
2902 /* XXX: From uniforms? */
2903 nir_ssa_def
*depth_near
= nir_imm_float(b
, 0.0);
2904 nir_ssa_def
*depth_far
= nir_imm_float(b
, 1.0);
2906 /* World space to normalised device coordinates */
2908 nir_ssa_def
*w_recip
= nir_frcp(b
, nir_channel(b
, input_point
, 3));
2909 nir_ssa_def
*ndc_point
= nir_fmul(b
, nir_channels(b
, input_point
, 0x7), w_recip
);
2911 /* Normalised device coordinates to screen space */
2913 nir_ssa_def
*viewport_multiplier
= nir_vec2(b
, viewport_width_2
, viewport_height_2
);
2914 nir_ssa_def
*viewport_xy
= nir_fadd(b
, nir_fmul(b
, nir_channels(b
, ndc_point
, 0x3), viewport_multiplier
), viewport_offset
);
2916 nir_ssa_def
*depth_multiplier
= nir_fmul(b
, nir_fsub(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2917 nir_ssa_def
*depth_offset
= nir_fmul(b
, nir_fadd(b
, depth_far
, depth_near
), nir_imm_float(b
, 0.5f
));
2918 nir_ssa_def
*screen_depth
= nir_fadd(b
, nir_fmul(b
, nir_channel(b
, ndc_point
, 2), depth_multiplier
), depth_offset
);
2920 /* gl_Position will be written out in screenspace xyz, with w set to
2921 * the reciprocal we computed earlier. The transformed w component is
2922 * then used for perspective-correct varying interpolation */
2924 nir_ssa_def
*screen_space
= nir_vec4(b
,
2925 nir_channel(b
, viewport_xy
, 0),
2926 nir_channel(b
, viewport_xy
, 1),
2928 nir_fabs(b
, w_recip
));
2930 /* Finally, write out the transformed values to the varying */
2932 nir_intrinsic_instr
*store
;
2933 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
2934 store
->num_components
= 4;
2935 nir_intrinsic_set_base(store
, 0);
2936 nir_intrinsic_set_write_mask(store
, 0xf);
2937 store
->src
[0].ssa
= screen_space
;
2938 store
->src
[0].is_ssa
= true;
2939 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
2940 nir_builder_instr_insert(b
, &store
->instr
);
2944 transform_position_writes(nir_shader
*shader
)
2946 nir_foreach_function(func
, shader
) {
2947 nir_foreach_block(block
, func
->impl
) {
2948 nir_foreach_instr_safe(instr
, block
) {
2949 if (instr
->type
!= nir_instr_type_intrinsic
) continue;
2951 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
2952 nir_variable
*out
= NULL
;
2954 switch (intr
->intrinsic
) {
2955 case nir_intrinsic_store_output
:
2956 /* already had i/o lowered.. lookup the matching output var: */
2957 nir_foreach_variable(var
, &shader
->outputs
) {
2958 int drvloc
= var
->data
.driver_location
;
2960 if (nir_intrinsic_base(intr
) == drvloc
) {
2974 if (out
->data
.mode
!= nir_var_shader_out
)
2977 if (out
->data
.location
!= VARYING_SLOT_POS
)
2981 nir_builder_init(&b
, func
->impl
);
2982 b
.cursor
= nir_before_instr(instr
);
2984 write_transformed_position(&b
, intr
->src
[0], UNIFORM_VIEWPORT
);
2985 nir_instr_remove(instr
);
2992 emit_fragment_epilogue(compiler_context
*ctx
)
2994 /* Special case: writing out constants requires us to include the move
2995 * explicitly now, so shove it into r0 */
2997 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2999 if (constant_value
) {
3000 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
3001 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
3002 emit_mir_instruction(ctx
, ins
);
3005 /* Perform the actual fragment writeout. We have two writeout/branch
3006 * instructions, forming a loop until writeout is successful as per the
3007 * docs. TODO: gl_FragDepth */
3009 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3010 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3013 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
3014 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
3015 * with the int8 analogue to the fragment epilogue */
3018 emit_blend_epilogue(compiler_context
*ctx
)
3020 /* vmul.fmul.none.fulllow hr48, r0, #255 */
3022 midgard_instruction scale
= {
3025 .inline_constant
= _mesa_float_to_half(255.0),
3027 .src0
= SSA_FIXED_REGISTER(0),
3028 .src1
= SSA_UNUSED_0
,
3029 .dest
= SSA_FIXED_REGISTER(24),
3030 .inline_constant
= true
3033 .op
= midgard_alu_op_fmul
,
3034 .reg_mode
= midgard_reg_mode_full
,
3035 .dest_override
= midgard_dest_override_lower
,
3037 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3038 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3042 emit_mir_instruction(ctx
, scale
);
3044 /* vadd.f2u8.pos.low hr0, hr48, #0 */
3046 midgard_vector_alu_src alu_src
= blank_alu_src
;
3047 alu_src
.half
= true;
3049 midgard_instruction f2u8
= {
3052 .src0
= SSA_FIXED_REGISTER(24),
3053 .src1
= SSA_UNUSED_0
,
3054 .dest
= SSA_FIXED_REGISTER(0),
3055 .inline_constant
= true
3058 .op
= midgard_alu_op_f2u8
,
3059 .reg_mode
= midgard_reg_mode_half
,
3060 .dest_override
= midgard_dest_override_lower
,
3061 .outmod
= midgard_outmod_pos
,
3063 .src1
= vector_alu_srco_unsigned(alu_src
),
3064 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3068 emit_mir_instruction(ctx
, f2u8
);
3070 /* vmul.imov.quarter r0, r0, r0 */
3072 midgard_instruction imov_8
= {
3075 .src0
= SSA_UNUSED_1
,
3076 .src1
= SSA_FIXED_REGISTER(0),
3077 .dest
= SSA_FIXED_REGISTER(0),
3080 .op
= midgard_alu_op_imov
,
3081 .reg_mode
= midgard_reg_mode_quarter
,
3082 .dest_override
= midgard_dest_override_none
,
3084 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
3085 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
3089 /* Emit branch epilogue with the 8-bit move as the source */
3091 emit_mir_instruction(ctx
, imov_8
);
3092 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
3094 emit_mir_instruction(ctx
, imov_8
);
3095 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
3098 static midgard_block
*
3099 emit_block(compiler_context
*ctx
, nir_block
*block
)
3101 midgard_block
*this_block
= malloc(sizeof(midgard_block
));
3102 list_addtail(&this_block
->link
, &ctx
->blocks
);
3104 this_block
->is_scheduled
= false;
3107 ctx
->texture_index
[0] = -1;
3108 ctx
->texture_index
[1] = -1;
3110 /* Set up current block */
3111 list_inithead(&this_block
->instructions
);
3112 ctx
->current_block
= this_block
;
3114 nir_foreach_instr(instr
, block
) {
3115 emit_instr(ctx
, instr
);
3116 ++ctx
->instruction_count
;
3119 inline_alu_constants(ctx
);
3120 embedded_to_inline_constant(ctx
);
3122 /* Perform heavylifting for aliasing */
3123 actualise_ssa_to_alias(ctx
);
3125 midgard_emit_store(ctx
, this_block
);
3126 midgard_eliminate_orphan_moves(ctx
, this_block
);
3127 midgard_pair_load_store(ctx
, this_block
);
3129 /* Append fragment shader epilogue (value writeout) */
3130 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
3131 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
3133 emit_blend_epilogue(ctx
);
3135 emit_fragment_epilogue(ctx
);
3139 /* Fallthrough save */
3140 this_block
->next_fallthrough
= ctx
->previous_source_block
;
3142 if (block
== nir_start_block(ctx
->func
->impl
))
3143 ctx
->initial_block
= this_block
;
3145 if (block
== nir_impl_last_block(ctx
->func
->impl
))
3146 ctx
->final_block
= this_block
;
3148 /* Allow the next control flow to access us retroactively, for
3150 ctx
->current_block
= this_block
;
3152 /* Document the fallthrough chain */
3153 ctx
->previous_source_block
= this_block
;
3158 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
3161 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
3163 /* Conditional branches expect the condition in r31.w; emit a move for
3164 * that in the _previous_ block (which is the current block). */
3165 emit_condition(ctx
, &nif
->condition
, true);
3167 /* Speculatively emit the branch, but we can't fill it in until later */
3168 EMIT(branch
, true, true);
3169 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
3171 /* Emit the two subblocks */
3172 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
3174 /* Emit a jump from the end of the then block to the end of the else */
3175 EMIT(branch
, false, false);
3176 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
3178 /* Emit second block, and check if it's empty */
3180 int else_idx
= ctx
->block_count
;
3181 int count_in
= ctx
->instruction_count
;
3182 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
3184 /* Now that we have the subblocks emitted, fix up the branches */
3190 if (ctx
->instruction_count
== count_in
) {
3191 /* The else block is empty, so don't emit an exit jump */
3192 mir_remove_instruction(then_exit
);
3193 then_branch
->branch
.target_block
= else_idx
+ 1;
3195 then_branch
->branch
.target_block
= else_idx
;
3196 then_exit
->branch
.target_block
= else_idx
+ 1;
3201 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
3203 /* Remember where we are */
3204 midgard_block
*start_block
= ctx
->current_block
;
3206 /* Allocate a loop number for this. TODO: Nested loops. Instead of a
3207 * single current_loop variable, maybe we need a stack */
3209 int loop_idx
= ++ctx
->current_loop
;
3211 /* Get index from before the body so we can loop back later */
3212 int start_idx
= ctx
->block_count
;
3214 /* Emit the body itself */
3215 emit_cf_list(ctx
, &nloop
->body
);
3217 /* Branch back to loop back */
3218 struct midgard_instruction br_back
= v_branch(false, false);
3219 br_back
.branch
.target_block
= start_idx
;
3220 emit_mir_instruction(ctx
, br_back
);
3222 /* Find the index of the block about to follow us (note: we don't add
3223 * one; blocks are 0-indexed so we get a fencepost problem) */
3224 int break_block_idx
= ctx
->block_count
;
3226 /* Fix up the break statements we emitted to point to the right place,
3227 * now that we can allocate a block number for them */
3229 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
3230 print_mir_block(block
);
3231 mir_foreach_instr_in_block(block
, ins
) {
3232 if (ins
->type
!= TAG_ALU_4
) continue;
3233 if (!ins
->compact_branch
) continue;
3234 if (ins
->prepacked_branch
) continue;
3236 /* We found a branch -- check the type to see if we need to do anything */
3237 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
3239 /* It's a break! Check if it's our break */
3240 if (ins
->branch
.target_break
!= loop_idx
) continue;
3242 /* Okay, cool, we're breaking out of this loop.
3243 * Rewrite from a break to a goto */
3245 ins
->branch
.target_type
= TARGET_GOTO
;
3246 ins
->branch
.target_block
= break_block_idx
;
3251 static midgard_block
*
3252 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
3254 midgard_block
*start_block
= NULL
;
3256 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
3257 switch (node
->type
) {
3258 case nir_cf_node_block
: {
3259 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
3262 start_block
= block
;
3267 case nir_cf_node_if
:
3268 emit_if(ctx
, nir_cf_node_as_if(node
));
3271 case nir_cf_node_loop
:
3272 emit_loop(ctx
, nir_cf_node_as_loop(node
));
3275 case nir_cf_node_function
:
3285 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
3287 struct util_dynarray
*compiled
= &program
->compiled
;
3289 compiler_context ictx
= {
3291 .stage
= nir
->info
.stage
,
3293 .is_blend
= is_blend
,
3294 .blend_constant_offset
= -1,
3296 .alpha_ref
= program
->alpha_ref
3299 compiler_context
*ctx
= &ictx
;
3301 /* TODO: Decide this at runtime */
3302 ctx
->uniform_cutoff
= 8;
3304 switch (ctx
->stage
) {
3305 case MESA_SHADER_VERTEX
:
3306 ctx
->special_uniforms
= 1;
3310 ctx
->special_uniforms
= 0;
3314 /* Append epilogue uniforms if necessary. The cmdstream depends on
3315 * these being at the -end-; see assign_var_locations. */
3317 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3318 nir_variable_create(nir
, nir_var_uniform
, glsl_vec4_type(), "viewport");
3321 /* Assign var locations early, so the epilogue can use them if necessary */
3323 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3324 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3325 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3327 /* Initialize at a global (not block) level hash tables */
3329 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3330 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3331 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3332 ctx
->ssa_to_register
= _mesa_hash_table_u64_create(NULL
);
3333 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3334 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3336 /* Assign actual uniform location, skipping over samplers */
3338 ctx
->uniform_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3340 nir_foreach_variable(var
, &nir
->uniforms
) {
3341 if (glsl_get_base_type(var
->type
) == GLSL_TYPE_SAMPLER
) continue;
3343 unsigned length
= glsl_get_aoa_size(var
->type
);
3346 length
= glsl_get_length(var
->type
);
3350 length
= glsl_get_matrix_columns(var
->type
);
3353 for (int col
= 0; col
< length
; ++col
) {
3354 int id
= ctx
->uniform_count
++;
3355 _mesa_hash_table_u64_insert(ctx
->uniform_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3359 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3360 ctx
->varying_nir_to_mdg
= _mesa_hash_table_u64_create(NULL
);
3362 /* First, collect the special varyings */
3363 nir_foreach_variable(var
, &nir
->outputs
) {
3364 if (var
->data
.location
== VARYING_SLOT_POS
) {
3365 /* Set position first, always. It takes up two
3366 * spots, the latter one is de facto unused (at
3367 * least from the shader's perspective), we
3368 * just need to skip over the spot*/
3370 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (0 + 1)));
3371 ctx
->varying_count
= MAX2(ctx
->varying_count
, 2);
3372 } else if (var
->data
.location
== VARYING_SLOT_PSIZ
) {
3373 /* Set point size second (third, see above) */
3374 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ 1, (void *) ((uintptr_t) (2 + 1)));
3375 ctx
->varying_count
= MAX2(ctx
->varying_count
, 3);
3377 program
->writes_point_size
= true;
3381 /* Now, collect normal varyings */
3383 nir_foreach_variable(var
, &nir
->outputs
) {
3384 if (var
->data
.location
== VARYING_SLOT_POS
|| var
->data
.location
== VARYING_SLOT_PSIZ
) continue;
3386 for (int col
= 0; col
< glsl_get_matrix_columns(var
->type
); ++col
) {
3387 int id
= ctx
->varying_count
++;
3388 _mesa_hash_table_u64_insert(ctx
->varying_nir_to_mdg
, var
->data
.driver_location
+ col
+ 1, (void *) ((uintptr_t) (id
+ 1)));
3395 /* Lower vars -- not I/O -- before epilogue */
3397 NIR_PASS_V(nir
, nir_lower_var_copies
);
3398 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3399 NIR_PASS_V(nir
, nir_split_var_copies
);
3400 NIR_PASS_V(nir
, nir_lower_var_copies
);
3401 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3402 NIR_PASS_V(nir
, nir_lower_var_copies
);
3403 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3404 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3406 /* Append vertex epilogue before optimisation, so the epilogue itself
3409 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3410 transform_position_writes(nir
);
3412 /* Optimisation passes */
3416 nir_print_shader(nir
, stdout
);
3418 /* Assign counts, now that we're sure (post-optimisation) */
3419 program
->uniform_count
= nir
->num_uniforms
;
3421 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3422 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3425 nir_foreach_function(func
, nir
) {
3429 list_inithead(&ctx
->blocks
);
3430 ctx
->block_count
= 0;
3433 emit_cf_list(ctx
, &func
->impl
->body
);
3434 emit_block(ctx
, func
->impl
->end_block
);
3436 break; /* TODO: Multi-function shaders */
3439 util_dynarray_init(compiled
, NULL
);
3442 schedule_program(ctx
);
3444 /* Now that all the bundles are scheduled and we can calculate block
3445 * sizes, emit actual branch instructions rather than placeholders */
3447 int br_block_idx
= 0;
3449 mir_foreach_block(ctx
, block
) {
3450 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3451 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3452 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3454 if (ins
->unit
!= ALU_ENAB_BR_COMPACT
) continue;
3456 if (ins
->prepacked_branch
) continue;
3460 /* Determine the block we're jumping to */
3461 int target_number
= ins
->branch
.target_block
;
3463 midgard_block
*target
= mir_get_block(ctx
, target_number
);
3466 /* Determine the destination tag */
3467 midgard_bundle
*first
= util_dynarray_element(&target
->bundles
, midgard_bundle
, 0);
3470 int dest_tag
= first
->tag
;
3472 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3473 int quadword_offset
= 0;
3475 if (target_number
> br_block_idx
) {
3478 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3479 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3482 quadword_offset
+= blk
->quadword_count
;
3485 /* Jump backwards */
3487 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3488 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3491 quadword_offset
-= blk
->quadword_count
;
3495 if (ins
->branch
.conditional
) {
3496 midgard_branch_cond branch
= {
3497 .op
= midgard_jmp_writeout_op_branch_cond
,
3498 .dest_tag
= dest_tag
,
3499 .offset
= quadword_offset
,
3500 .cond
= ins
->branch
.invert_conditional
? midgard_condition_false
: midgard_condition_true
3503 memcpy(&compact
, &branch
, sizeof(branch
));
3505 midgard_branch_uncond branch
= {
3506 .op
= midgard_jmp_writeout_op_branch_uncond
,
3507 .dest_tag
= dest_tag
,
3508 .offset
= quadword_offset
,
3512 memcpy(&compact
, &branch
, sizeof(branch
));
3515 /* Swap in the generic branch for our actual branch */
3516 ins
->unit
= ALU_ENAB_BR_COMPACT
;
3517 ins
->br_compact
= compact
;
3525 /* Emit flat binary from the instruction arrays. Iterate each block in
3526 * sequence. Save instruction boundaries such that lookahead tags can
3527 * be assigned easily */
3529 /* Cache _all_ bundles in source order for lookahead across failed branches */
3531 int bundle_count
= 0;
3532 mir_foreach_block(ctx
, block
) {
3533 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3535 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3537 mir_foreach_block(ctx
, block
) {
3538 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3539 source_order_bundles
[bundle_idx
++] = bundle
;
3543 int current_bundle
= 0;
3545 mir_foreach_block(ctx
, block
) {
3546 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3549 if (current_bundle
+ 1 < bundle_count
) {
3550 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3552 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3559 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3563 /* TODO: Free deeper */
3564 //util_dynarray_fini(&block->instructions);
3567 free(source_order_bundles
);
3569 /* Due to lookahead, we need to report in the command stream the first
3570 * tag executed. An initial block might be empty, so iterate until we
3571 * find one that 'works' */
3573 midgard_block
*initial_block
= list_first_entry(&ctx
->blocks
, midgard_block
, link
);
3575 program
->first_tag
= 0;
3578 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
3580 if (initial_bundle
) {
3581 program
->first_tag
= initial_bundle
->tag
;
3585 /* Initial block is empty, try the next block */
3586 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
3587 } while(initial_block
!= NULL
);
3589 /* Make sure we actually set the tag */
3590 assert(program
->first_tag
);
3592 /* Deal with off-by-one related to the fencepost problem */
3593 program
->work_register_count
= ctx
->work_registers
+ 1;
3595 program
->can_discard
= ctx
->can_discard
;
3596 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3598 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3600 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);