2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
51 #include "disassemble.h"
53 static const struct debug_named_value debug_options
[] = {
54 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
61 int midgard_debug
= 0;
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
69 midgard_is_branch_unit(unsigned unit
)
71 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
75 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
77 block
->successors
[block
->nr_successors
++] = successor
;
78 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
97 .op = midgard_op_##name, \
99 .swizzle = SWIZZLE_XYZW, \
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
116 if (!src
) return blank_alu_src
;
118 midgard_vector_alu_src alu_src
= {
121 .half
= 0, /* TODO */
122 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
126 /* TODO: sign-extend/zero-extend */
127 alu_src
.mod
= midgard_int_normal
;
129 /* These should have been lowered away */
130 assert(!(src
->abs
|| src
->negate
));
132 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
138 /* load/store instructions have both 32-bit and 16-bit variants, depending on
139 * whether we are using vectors composed of highp or mediump. At the moment, we
140 * don't support half-floats -- this requires changes in other parts of the
141 * compiler -- therefore the 16-bit versions are commented out. */
143 //M_LOAD(ld_attr_16);
145 //M_LOAD(ld_vary_16);
147 //M_LOAD(ld_uniform_16);
148 M_LOAD(ld_uniform_32
);
149 M_LOAD(ld_color_buffer_8
);
150 //M_STORE(st_vary_16);
152 M_STORE(st_cubemap_coords
);
154 static midgard_instruction
155 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
157 midgard_branch_cond branch
= {
165 memcpy(&compact
, &branch
, sizeof(branch
));
167 midgard_instruction ins
= {
169 .unit
= ALU_ENAB_BR_COMPACT
,
170 .prepacked_branch
= true,
171 .compact_branch
= true,
172 .br_compact
= compact
175 if (op
== midgard_jmp_writeout_op_writeout
)
181 static midgard_instruction
182 v_branch(bool conditional
, bool invert
)
184 midgard_instruction ins
= {
186 .unit
= ALU_ENAB_BRANCH
,
187 .compact_branch
= true,
189 .conditional
= conditional
,
190 .invert_conditional
= invert
197 static midgard_branch_extended
198 midgard_create_branch_extended( midgard_condition cond
,
199 midgard_jmp_writeout_op op
,
201 signed quadword_offset
)
203 /* For unclear reasons, the condition code is repeated 8 times */
204 uint16_t duplicated_cond
=
214 midgard_branch_extended branch
= {
216 .dest_tag
= dest_tag
,
217 .offset
= quadword_offset
,
218 .cond
= duplicated_cond
225 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
227 ins
->has_constants
= true;
228 memcpy(&ins
->constants
, constants
, 16);
232 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
234 return glsl_count_attribute_slots(type
, false);
237 /* Lower fdot2 to a vector multiplication followed by channel addition */
239 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
241 if (alu
->op
!= nir_op_fdot2
)
244 b
->cursor
= nir_before_instr(&alu
->instr
);
246 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
247 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
249 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
251 nir_ssa_def
*sum
= nir_fadd(b
,
252 nir_channel(b
, product
, 0),
253 nir_channel(b
, product
, 1));
255 /* Replace the fdot2 with this sum */
256 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
260 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
262 switch (instr
->intrinsic
) {
263 case nir_intrinsic_load_viewport_scale
:
264 return PAN_SYSVAL_VIEWPORT_SCALE
;
265 case nir_intrinsic_load_viewport_offset
:
266 return PAN_SYSVAL_VIEWPORT_OFFSET
;
273 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
277 if (instr
->type
== nir_instr_type_intrinsic
) {
278 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
279 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
285 /* We have a sysval load; check if it's already been assigned */
287 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
290 /* It hasn't -- so assign it now! */
292 unsigned id
= ctx
->sysval_count
++;
293 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
294 ctx
->sysvals
[id
] = sysval
;
298 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
300 ctx
->sysval_count
= 0;
302 nir_foreach_function(function
, shader
) {
303 if (!function
->impl
) continue;
305 nir_foreach_block(block
, function
->impl
) {
306 nir_foreach_instr_safe(instr
, block
) {
307 midgard_nir_assign_sysval_body(ctx
, instr
);
314 midgard_nir_lower_fdot2(nir_shader
*shader
)
316 bool progress
= false;
318 nir_foreach_function(function
, shader
) {
319 if (!function
->impl
) continue;
322 nir_builder
*b
= &_b
;
323 nir_builder_init(b
, function
->impl
);
325 nir_foreach_block(block
, function
->impl
) {
326 nir_foreach_instr_safe(instr
, block
) {
327 if (instr
->type
!= nir_instr_type_alu
) continue;
329 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
330 midgard_nir_lower_fdot2_body(b
, alu
);
336 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
344 optimise_nir(nir_shader
*nir
)
347 unsigned lower_flrp
=
348 (nir
->options
->lower_flrp16
? 16 : 0) |
349 (nir
->options
->lower_flrp32
? 32 : 0) |
350 (nir
->options
->lower_flrp64
? 64 : 0);
352 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
353 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
355 nir_lower_tex_options lower_tex_options
= {
359 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
364 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
365 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
367 NIR_PASS(progress
, nir
, nir_copy_prop
);
368 NIR_PASS(progress
, nir
, nir_opt_dce
);
369 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
370 NIR_PASS(progress
, nir
, nir_opt_cse
);
371 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
372 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
373 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
375 if (lower_flrp
!= 0) {
376 bool lower_flrp_progress
= false;
377 NIR_PASS(lower_flrp_progress
,
381 false /* always_precise */,
382 nir
->options
->lower_ffma
);
383 if (lower_flrp_progress
) {
384 NIR_PASS(progress
, nir
,
385 nir_opt_constant_folding
);
389 /* Nothing should rematerialize any flrps, so we only
390 * need to do this lowering once.
395 NIR_PASS(progress
, nir
, nir_opt_undef
);
396 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
399 nir_var_function_temp
);
401 /* TODO: Enable vectorize when merged upstream */
402 // NIR_PASS(progress, nir, nir_opt_vectorize);
405 /* Must be run at the end to prevent creation of fsin/fcos ops */
406 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
411 NIR_PASS(progress
, nir
, nir_opt_dce
);
412 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
413 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
414 NIR_PASS(progress
, nir
, nir_copy_prop
);
417 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
419 /* We implement booleans as 32-bit 0/~0 */
420 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
422 /* Now that booleans are lowered, we can run out late opts */
423 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
425 /* Lower mods for float ops only. Integer ops don't support modifiers
426 * (saturate doesn't make sense on integers, neg/abs require dedicated
429 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
430 NIR_PASS(progress
, nir
, nir_copy_prop
);
431 NIR_PASS(progress
, nir
, nir_opt_dce
);
433 /* Take us out of SSA */
434 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
435 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
437 /* We are a vector architecture; write combine where possible */
438 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
439 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
441 NIR_PASS(progress
, nir
, nir_opt_dce
);
444 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
445 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
446 * r0. See the comments in compiler_context */
449 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
451 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
452 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
455 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
458 unalias_ssa(compiler_context
*ctx
, int dest
)
460 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
461 /* TODO: Remove from leftover or no? */
464 /* Do not actually emit a load; instead, cache the constant for inlining */
467 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
469 nir_ssa_def def
= instr
->def
;
471 float *v
= rzalloc_array(NULL
, float, 4);
472 nir_const_load_to_arr(v
, instr
, f32
);
473 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
477 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
480 return src
->ssa
->index
;
482 assert(!src
->reg
.indirect
);
483 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
488 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
491 return dst
->ssa
.index
;
493 assert(!dst
->reg
.indirect
);
494 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
499 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
501 return nir_src_index(ctx
, &src
->src
);
505 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
507 unsigned comp
= src
->swizzle
[0];
509 for (unsigned c
= 1; c
< nr_components
; ++c
) {
510 if (src
->swizzle
[c
] != comp
)
517 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
518 * output of a conditional test) into that register */
521 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
523 int condition
= nir_src_index(ctx
, src
);
525 /* Source to swizzle the desired component into w */
527 const midgard_vector_alu_src alu_src
= {
528 .swizzle
= SWIZZLE(component
, component
, component
, component
),
531 /* There is no boolean move instruction. Instead, we simulate a move by
532 * ANDing the condition with itself to get it into r31.w */
534 midgard_instruction ins
= {
537 /* We need to set the conditional as close as possible */
538 .precede_break
= true,
539 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
545 .dest
= SSA_FIXED_REGISTER(31),
548 .op
= midgard_alu_op_iand
,
549 .outmod
= midgard_outmod_int
,
550 .reg_mode
= midgard_reg_mode_32
,
551 .dest_override
= midgard_dest_override_none
,
552 .mask
= (0x3 << 6), /* w */
553 .src1
= vector_alu_srco_unsigned(alu_src
),
554 .src2
= vector_alu_srco_unsigned(alu_src
)
558 emit_mir_instruction(ctx
, ins
);
561 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
565 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
567 int condition
= nir_src_index(ctx
, &src
->src
);
569 /* Source to swizzle the desired component into w */
571 const midgard_vector_alu_src alu_src
= {
572 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
575 /* There is no boolean move instruction. Instead, we simulate a move by
576 * ANDing the condition with itself to get it into r31.w */
578 midgard_instruction ins
= {
580 .precede_break
= true,
584 .dest
= SSA_FIXED_REGISTER(31),
587 .op
= midgard_alu_op_iand
,
588 .outmod
= midgard_outmod_int
,
589 .reg_mode
= midgard_reg_mode_32
,
590 .dest_override
= midgard_dest_override_none
,
591 .mask
= expand_writemask((1 << nr_comp
) - 1),
592 .src1
= vector_alu_srco_unsigned(alu_src
),
593 .src2
= vector_alu_srco_unsigned(alu_src
)
597 emit_mir_instruction(ctx
, ins
);
602 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
603 * pinning to eliminate this move in all known cases */
606 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
608 int offset
= nir_src_index(ctx
, src
);
610 midgard_instruction ins
= {
613 .src0
= SSA_UNUSED_1
,
615 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
618 .op
= midgard_alu_op_imov
,
619 .outmod
= midgard_outmod_int
,
620 .reg_mode
= midgard_reg_mode_32
,
621 .dest_override
= midgard_dest_override_none
,
622 .mask
= (0x3 << 6), /* w */
623 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
624 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
628 emit_mir_instruction(ctx
, ins
);
631 #define ALU_CASE(nir, _op) \
633 op = midgard_alu_op_##_op; \
636 nir_is_fzero_constant(nir_src src
)
638 if (!nir_src_is_const(src
))
641 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
642 if (nir_src_comp_as_float(src
, c
) != 0.0)
650 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
652 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
654 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
655 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
656 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
658 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
659 * supported. A few do not and are commented for now. Also, there are a
660 * number of NIR ops which Midgard does not support and need to be
661 * lowered, also TODO. This switch block emits the opcode and calling
662 * convention of the Midgard instruction; actual packing is done in
668 ALU_CASE(fadd
, fadd
);
669 ALU_CASE(fmul
, fmul
);
670 ALU_CASE(fmin
, fmin
);
671 ALU_CASE(fmax
, fmax
);
672 ALU_CASE(imin
, imin
);
673 ALU_CASE(imax
, imax
);
674 ALU_CASE(umin
, umin
);
675 ALU_CASE(umax
, umax
);
676 ALU_CASE(ffloor
, ffloor
);
677 ALU_CASE(fround_even
, froundeven
);
678 ALU_CASE(ftrunc
, ftrunc
);
679 ALU_CASE(fceil
, fceil
);
680 ALU_CASE(fdot3
, fdot3
);
681 ALU_CASE(fdot4
, fdot4
);
682 ALU_CASE(iadd
, iadd
);
683 ALU_CASE(isub
, isub
);
684 ALU_CASE(imul
, imul
);
685 ALU_CASE(iabs
, iabs
);
688 ALU_CASE(feq32
, feq
);
689 ALU_CASE(fne32
, fne
);
690 ALU_CASE(flt32
, flt
);
691 ALU_CASE(ieq32
, ieq
);
692 ALU_CASE(ine32
, ine
);
693 ALU_CASE(ilt32
, ilt
);
694 ALU_CASE(ult32
, ult
);
696 /* We don't have a native b2f32 instruction. Instead, like many
697 * GPUs, we exploit booleans as 0/~0 for false/true, and
698 * correspondingly AND
699 * by 1.0 to do the type conversion. For the moment, prime us
702 * iand [whatever], #0
704 * At the end of emit_alu (as MIR), we'll fix-up the constant
707 ALU_CASE(b2f32
, iand
);
708 ALU_CASE(b2i32
, iand
);
710 /* Likewise, we don't have a dedicated f2b32 instruction, but
711 * we can do a "not equal to 0.0" test. */
713 ALU_CASE(f2b32
, fne
);
714 ALU_CASE(i2b32
, ine
);
716 ALU_CASE(frcp
, frcp
);
717 ALU_CASE(frsq
, frsqrt
);
718 ALU_CASE(fsqrt
, fsqrt
);
719 ALU_CASE(fexp2
, fexp2
);
720 ALU_CASE(flog2
, flog2
);
722 ALU_CASE(f2i32
, f2i
);
723 ALU_CASE(f2u32
, f2u
);
724 ALU_CASE(i2f32
, i2f
);
725 ALU_CASE(u2f32
, u2f
);
727 ALU_CASE(fsin
, fsin
);
728 ALU_CASE(fcos
, fcos
);
730 ALU_CASE(iand
, iand
);
732 ALU_CASE(ixor
, ixor
);
733 ALU_CASE(inot
, inand
);
734 ALU_CASE(ishl
, ishl
);
735 ALU_CASE(ishr
, iasr
);
736 ALU_CASE(ushr
, ilsr
);
738 ALU_CASE(b32all_fequal2
, fball_eq
);
739 ALU_CASE(b32all_fequal3
, fball_eq
);
740 ALU_CASE(b32all_fequal4
, fball_eq
);
742 ALU_CASE(b32any_fnequal2
, fbany_neq
);
743 ALU_CASE(b32any_fnequal3
, fbany_neq
);
744 ALU_CASE(b32any_fnequal4
, fbany_neq
);
746 ALU_CASE(b32all_iequal2
, iball_eq
);
747 ALU_CASE(b32all_iequal3
, iball_eq
);
748 ALU_CASE(b32all_iequal4
, iball_eq
);
750 ALU_CASE(b32any_inequal2
, ibany_neq
);
751 ALU_CASE(b32any_inequal3
, ibany_neq
);
752 ALU_CASE(b32any_inequal4
, ibany_neq
);
754 /* Source mods will be shoved in later */
755 ALU_CASE(fabs
, fmov
);
756 ALU_CASE(fneg
, fmov
);
757 ALU_CASE(fsat
, fmov
);
759 /* For greater-or-equal, we lower to less-or-equal and flip the
767 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
768 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
769 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
770 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
773 /* Swap via temporary */
774 nir_alu_src temp
= instr
->src
[1];
775 instr
->src
[1] = instr
->src
[0];
776 instr
->src
[0] = temp
;
781 case nir_op_b32csel
: {
782 /* Midgard features both fcsel and icsel, depending on
783 * the type of the arguments/output. However, as long
784 * as we're careful we can _always_ use icsel and
785 * _never_ need fcsel, since the latter does additional
786 * floating-point-specific processing whereas the
787 * former just moves bits on the wire. It's not obvious
788 * why these are separate opcodes, save for the ability
789 * to do things like sat/pos/abs/neg for free */
791 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
792 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
794 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
797 /* Emit the condition into r31 */
800 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
802 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
804 /* The condition is the first argument; move the other
805 * arguments up one to be a binary instruction for
808 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
813 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
818 /* Midgard can perform certain modifiers on output of an ALU op */
819 midgard_outmod outmod
=
820 midgard_is_integer_out_op(op
) ? midgard_outmod_int
:
821 instr
->dest
.saturate
? midgard_outmod_sat
: midgard_outmod_none
;
823 if (instr
->op
== nir_op_fsat
)
824 outmod
= midgard_outmod_sat
;
826 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
828 if (instr
->op
== nir_op_fmax
) {
829 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
830 op
= midgard_alu_op_fmov
;
832 outmod
= midgard_outmod_pos
;
833 instr
->src
[0] = instr
->src
[1];
834 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
835 op
= midgard_alu_op_fmov
;
837 outmod
= midgard_outmod_pos
;
841 /* Fetch unit, quirks, etc information */
842 unsigned opcode_props
= alu_opcode_props
[op
].props
;
843 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
845 /* src0 will always exist afaik, but src1 will not for 1-argument
846 * instructions. The latter can only be fetched if the instruction
847 * needs it, or else we may segfault. */
849 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
850 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
852 /* Rather than use the instruction generation helpers, we do it
853 * ourselves here to avoid the mess */
855 midgard_instruction ins
= {
858 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
859 .src1
= quirk_flipped_r24
? src0
: src1
,
864 nir_alu_src
*nirmods
[2] = { NULL
};
866 if (nr_inputs
== 2) {
867 nirmods
[0] = &instr
->src
[0];
868 nirmods
[1] = &instr
->src
[1];
869 } else if (nr_inputs
== 1) {
870 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
875 /* These were lowered to a move, so apply the corresponding mod */
877 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
878 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
880 if (instr
->op
== nir_op_fneg
)
881 s
->negate
= !s
->negate
;
883 if (instr
->op
== nir_op_fabs
)
887 bool is_int
= midgard_is_integer_op(op
);
889 midgard_vector_alu alu
= {
891 .reg_mode
= midgard_reg_mode_32
,
892 .dest_override
= midgard_dest_override_none
,
895 /* Writemask only valid for non-SSA NIR */
896 .mask
= expand_writemask((1 << nr_components
) - 1),
898 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
899 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
902 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
905 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
909 /* Late fixup for emulated instructions */
911 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
912 /* Presently, our second argument is an inline #0 constant.
913 * Switch over to an embedded 1.0 constant (that can't fit
914 * inline, since we're 32-bit, not 16-bit like the inline
917 ins
.ssa_args
.inline_constant
= false;
918 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
919 ins
.has_constants
= true;
921 if (instr
->op
== nir_op_b2f32
) {
922 ins
.constants
[0] = 1.0f
;
924 /* Type pun it into place */
926 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
929 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
930 } else if (instr
->op
== nir_op_f2b32
|| instr
->op
== nir_op_i2b32
) {
931 ins
.ssa_args
.inline_constant
= false;
932 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
933 ins
.has_constants
= true;
934 ins
.constants
[0] = 0.0f
;
935 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
936 } else if (instr
->op
== nir_op_inot
) {
937 /* ~b = ~(b & b), so duplicate the source */
938 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
939 ins
.alu
.src2
= ins
.alu
.src1
;
942 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
943 /* To avoid duplicating the lookup tables (probably), true LUT
944 * instructions can only operate as if they were scalars. Lower
945 * them here by changing the component. */
947 uint8_t original_swizzle
[4];
948 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
950 for (int i
= 0; i
< nr_components
; ++i
) {
951 ins
.alu
.mask
= (0x3) << (2 * i
); /* Mask the associated component */
953 for (int j
= 0; j
< 4; ++j
)
954 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
956 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
957 emit_mir_instruction(ctx
, ins
);
960 emit_mir_instruction(ctx
, ins
);
967 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
969 /* TODO: half-floats */
971 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
972 /* Fast path: For the first 16 uniforms, direct accesses are
973 * 0-cycle, since they're just a register fetch in the usual
974 * case. So, we alias the registers while we're still in
977 int reg_slot
= 23 - offset
;
978 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
980 /* Otherwise, read from the 'special' UBO to access
981 * higher-indexed uniforms, at a performance cost. More
982 * generally, we're emitting a UBO read instruction. */
984 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
986 /* TODO: Don't split */
987 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
988 ins
.load_store
.address
= offset
>> 3;
990 if (indirect_offset
) {
991 emit_indirect_offset(ctx
, indirect_offset
);
992 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
994 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
997 emit_mir_instruction(ctx
, ins
);
1002 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1004 /* First, pull out the destination */
1005 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1007 /* Now, figure out which uniform this is */
1008 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1009 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1011 /* Sysvals are prefix uniforms */
1012 unsigned uniform
= ((uintptr_t) val
) - 1;
1014 /* Emit the read itself -- this is never indirect */
1015 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1018 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1019 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1020 * generations have faster vectorized reads. This operation is for blend
1021 * shaders in particular; reading the tilebuffer from the fragment shader
1022 * remains an open problem. */
1025 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1027 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1028 ins
.load_store
.swizzle
= 0; /* xxxx */
1030 /* Read each component sequentially */
1032 for (unsigned c
= 0; c
< 4; ++c
) {
1033 ins
.load_store
.mask
= (1 << c
);
1034 ins
.load_store
.unknown
= c
;
1035 emit_mir_instruction(ctx
, ins
);
1038 /* vadd.u2f hr2, zext(hr2), #0 */
1040 midgard_vector_alu_src alu_src
= blank_alu_src
;
1041 alu_src
.mod
= midgard_int_zero_extend
;
1042 alu_src
.half
= true;
1044 midgard_instruction u2f
= {
1048 .src1
= SSA_UNUSED_0
,
1050 .inline_constant
= true
1053 .op
= midgard_alu_op_u2f
,
1054 .reg_mode
= midgard_reg_mode_16
,
1055 .dest_override
= midgard_dest_override_none
,
1057 .src1
= vector_alu_srco_unsigned(alu_src
),
1058 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1062 emit_mir_instruction(ctx
, u2f
);
1064 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1068 midgard_instruction fmul
= {
1070 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1074 .src1
= SSA_UNUSED_0
,
1075 .inline_constant
= true
1078 .op
= midgard_alu_op_fmul
,
1079 .reg_mode
= midgard_reg_mode_32
,
1080 .dest_override
= midgard_dest_override_none
,
1081 .outmod
= midgard_outmod_sat
,
1083 .src1
= vector_alu_srco_unsigned(alu_src
),
1084 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1088 emit_mir_instruction(ctx
, fmul
);
1092 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1094 unsigned offset
, reg
;
1096 switch (instr
->intrinsic
) {
1097 case nir_intrinsic_discard_if
:
1098 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1102 case nir_intrinsic_discard
: {
1103 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1104 struct midgard_instruction discard
= v_branch(conditional
, false);
1105 discard
.branch
.target_type
= TARGET_DISCARD
;
1106 emit_mir_instruction(ctx
, discard
);
1108 ctx
->can_discard
= true;
1112 case nir_intrinsic_load_uniform
:
1113 case nir_intrinsic_load_input
:
1114 offset
= nir_intrinsic_base(instr
);
1116 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1117 bool direct
= nir_src_is_const(instr
->src
[0]);
1120 offset
+= nir_src_as_uint(instr
->src
[0]);
1123 reg
= nir_dest_index(ctx
, &instr
->dest
);
1125 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1126 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1127 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1128 /* XXX: Half-floats? */
1129 /* TODO: swizzle, mask */
1131 midgard_instruction ins
= m_ld_vary_32(reg
, offset
);
1132 ins
.load_store
.mask
= (1 << nr_comp
) - 1;
1134 midgard_varying_parameter p
= {
1136 .interpolation
= midgard_interp_default
,
1137 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1141 memcpy(&u
, &p
, sizeof(p
));
1142 ins
.load_store
.varying_parameters
= u
;
1145 /* We have the offset totally ready */
1146 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1148 /* We have it partially ready, but we need to
1149 * add in the dynamic index, moved to r27.w */
1150 emit_indirect_offset(ctx
, &instr
->src
[0]);
1151 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1154 emit_mir_instruction(ctx
, ins
);
1155 } else if (ctx
->is_blend
) {
1156 /* For blend shaders, load the input color, which is
1157 * preloaded to r0 */
1159 midgard_instruction move
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1160 emit_mir_instruction(ctx
, move
);
1161 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1162 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1163 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1164 ins
.load_store
.mask
= (1 << nr_comp
) - 1;
1165 emit_mir_instruction(ctx
, ins
);
1167 DBG("Unknown load\n");
1173 case nir_intrinsic_load_output
:
1174 assert(nir_src_is_const(instr
->src
[0]));
1175 reg
= nir_dest_index(ctx
, &instr
->dest
);
1177 if (ctx
->is_blend
) {
1179 emit_fb_read_blend_scalar(ctx
, reg
);
1181 DBG("Unknown output load\n");
1187 case nir_intrinsic_load_blend_const_color_rgba
: {
1188 assert(ctx
->is_blend
);
1189 reg
= nir_dest_index(ctx
, &instr
->dest
);
1191 /* Blend constants are embedded directly in the shader and
1192 * patched in, so we use some magic routing */
1194 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1195 ins
.has_constants
= true;
1196 ins
.has_blend_constant
= true;
1197 emit_mir_instruction(ctx
, ins
);
1201 case nir_intrinsic_store_output
:
1202 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1204 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1206 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1208 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1209 /* gl_FragColor is not emitted with load/store
1210 * instructions. Instead, it gets plonked into
1211 * r0 at the end of the shader and we do the
1212 * framebuffer writeout dance. TODO: Defer
1215 midgard_instruction move
= v_fmov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1216 emit_mir_instruction(ctx
, move
);
1218 /* Save the index we're writing to for later reference
1219 * in the epilogue */
1221 ctx
->fragment_output
= reg
;
1222 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1223 /* Varyings are written into one of two special
1224 * varying register, r26 or r27. The register itself is selected as the register
1225 * in the st_vary instruction, minus the base of 26. E.g. write into r27 and then call st_vary(1)
1227 * Normally emitting fmov's is frowned upon,
1228 * but due to unique constraints of
1229 * REGISTER_VARYING, fmov emission + a
1230 * dedicated cleanup pass is the only way to
1231 * guarantee correctness when considering some
1232 * (common) edge cases XXX: FIXME */
1234 /* If this varying corresponds to a constant (why?!),
1235 * emit that now since it won't get picked up by
1236 * hoisting (since there is no corresponding move
1237 * emitted otherwise) */
1239 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, reg
+ 1);
1241 if (constant_value
) {
1242 /* Special case: emit the varying write
1243 * directly to r26 (looks funny in asm but it's
1244 * fine) and emit the store _now_. Possibly
1245 * slightly slower, but this is a really stupid
1246 * special case anyway (why on earth would you
1247 * have a constant varying? Your own fault for
1248 * slightly worse perf :P) */
1250 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(26));
1251 attach_constants(ctx
, &ins
, constant_value
, reg
+ 1);
1252 emit_mir_instruction(ctx
, ins
);
1254 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1255 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1256 emit_mir_instruction(ctx
, st
);
1258 /* Do not emit the varying yet -- instead, just mark down that we need to later */
1260 _mesa_hash_table_u64_insert(ctx
->ssa_varyings
, reg
+ 1, (void *) ((uintptr_t) (offset
+ 1)));
1263 DBG("Unknown store\n");
1269 case nir_intrinsic_load_alpha_ref_float
:
1270 assert(instr
->dest
.is_ssa
);
1272 float ref_value
= ctx
->alpha_ref
;
1274 float *v
= ralloc_array(NULL
, float, 4);
1275 memcpy(v
, &ref_value
, sizeof(float));
1276 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1279 case nir_intrinsic_load_viewport_scale
:
1280 case nir_intrinsic_load_viewport_offset
:
1281 emit_sysval_read(ctx
, instr
);
1285 printf ("Unhandled intrinsic\n");
1292 midgard_tex_format(enum glsl_sampler_dim dim
)
1295 case GLSL_SAMPLER_DIM_2D
:
1296 case GLSL_SAMPLER_DIM_EXTERNAL
:
1299 case GLSL_SAMPLER_DIM_3D
:
1302 case GLSL_SAMPLER_DIM_CUBE
:
1303 return TEXTURE_CUBE
;
1306 DBG("Unknown sampler dim type\n");
1313 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1316 //assert (!instr->sampler);
1317 //assert (!instr->texture_array_size);
1318 assert (instr
->op
== nir_texop_tex
);
1320 /* Allocate registers via a round robin scheme to alternate between the two registers */
1321 int reg
= ctx
->texture_op_count
& 1;
1322 int in_reg
= reg
, out_reg
= reg
;
1324 /* Make room for the reg */
1326 if (ctx
->texture_index
[reg
] > -1)
1327 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1329 int texture_index
= instr
->texture_index
;
1330 int sampler_index
= texture_index
;
1332 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1333 switch (instr
->src
[i
].src_type
) {
1334 case nir_tex_src_coord
: {
1335 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1337 midgard_vector_alu_src alu_src
= blank_alu_src
;
1339 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1341 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1342 /* For cubemaps, we need to load coords into
1343 * special r27, and then use a special ld/st op
1344 * to copy into the texture register */
1346 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1348 midgard_instruction move
= v_fmov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1349 emit_mir_instruction(ctx
, move
);
1351 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1352 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1353 st
.load_store
.mask
= 0x3; /* xy? */
1354 st
.load_store
.swizzle
= alu_src
.swizzle
;
1355 emit_mir_instruction(ctx
, st
);
1358 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_X
, COMPONENT_X
);
1360 midgard_instruction ins
= v_fmov(index
, alu_src
, reg
);
1361 emit_mir_instruction(ctx
, ins
);
1368 DBG("Unknown source type\n");
1375 /* No helper to build texture words -- we do it all here */
1376 midgard_instruction ins
= {
1377 .type
= TAG_TEXTURE_4
,
1379 .op
= TEXTURE_OP_NORMAL
,
1380 .format
= midgard_tex_format(instr
->sampler_dim
),
1381 .texture_handle
= texture_index
,
1382 .sampler_handle
= sampler_index
,
1384 /* TODO: Don't force xyzw */
1385 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
1397 /* Assume we can continue; hint it out later */
1402 /* Set registers to read and write from the same place */
1403 ins
.texture
.in_reg_select
= in_reg
;
1404 ins
.texture
.out_reg_select
= out_reg
;
1406 /* TODO: Dynamic swizzle input selection, half-swizzles? */
1407 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
) {
1408 ins
.texture
.in_reg_swizzle_right
= COMPONENT_X
;
1409 ins
.texture
.in_reg_swizzle_left
= COMPONENT_Y
;
1410 //ins.texture.in_reg_swizzle_third = COMPONENT_Z;
1412 ins
.texture
.in_reg_swizzle_left
= COMPONENT_X
;
1413 ins
.texture
.in_reg_swizzle_right
= COMPONENT_Y
;
1414 //ins.texture.in_reg_swizzle_third = COMPONENT_X;
1417 emit_mir_instruction(ctx
, ins
);
1419 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1421 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1422 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1423 ctx
->texture_index
[reg
] = o_index
;
1425 midgard_instruction ins2
= v_fmov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1426 emit_mir_instruction(ctx
, ins2
);
1428 /* Used for .cont and .last hinting */
1429 ctx
->texture_op_count
++;
1433 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1435 switch (instr
->type
) {
1436 case nir_jump_break
: {
1437 /* Emit a branch out of the loop */
1438 struct midgard_instruction br
= v_branch(false, false);
1439 br
.branch
.target_type
= TARGET_BREAK
;
1440 br
.branch
.target_break
= ctx
->current_loop_depth
;
1441 emit_mir_instruction(ctx
, br
);
1448 DBG("Unknown jump type %d\n", instr
->type
);
1454 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1456 switch (instr
->type
) {
1457 case nir_instr_type_load_const
:
1458 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1461 case nir_instr_type_intrinsic
:
1462 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1465 case nir_instr_type_alu
:
1466 emit_alu(ctx
, nir_instr_as_alu(instr
));
1469 case nir_instr_type_tex
:
1470 emit_tex(ctx
, nir_instr_as_tex(instr
));
1473 case nir_instr_type_jump
:
1474 emit_jump(ctx
, nir_instr_as_jump(instr
));
1477 case nir_instr_type_ssa_undef
:
1482 DBG("Unhandled instruction type\n");
1487 /* Midgard IR only knows vector ALU types, but we sometimes need to actually
1488 * use scalar ALU instructions, for functional or performance reasons. To do
1489 * this, we just demote vector ALU payloads to scalar. */
1492 component_from_mask(unsigned mask
)
1494 for (int c
= 0; c
< 4; ++c
) {
1495 if (mask
& (3 << (2 * c
)))
1504 is_single_component_mask(unsigned mask
)
1508 for (int c
= 0; c
< 4; ++c
)
1509 if (mask
& (3 << (2 * c
)))
1512 return components
== 1;
1515 /* Create a mask of accessed components from a swizzle to figure out vector
1519 swizzle_to_access_mask(unsigned swizzle
)
1521 unsigned component_mask
= 0;
1523 for (int i
= 0; i
< 4; ++i
) {
1524 unsigned c
= (swizzle
>> (2 * i
)) & 3;
1525 component_mask
|= (1 << c
);
1528 return component_mask
;
1532 vector_to_scalar_source(unsigned u
, bool is_int
)
1534 midgard_vector_alu_src v
;
1535 memcpy(&v
, &u
, sizeof(v
));
1537 /* TODO: Integers */
1539 midgard_scalar_alu_src s
= {
1541 .component
= (v
.swizzle
& 3) << 1
1547 s
.abs
= v
.mod
& MIDGARD_FLOAT_MOD_ABS
;
1548 s
.negate
= v
.mod
& MIDGARD_FLOAT_MOD_NEG
;
1552 memcpy(&o
, &s
, sizeof(s
));
1554 return o
& ((1 << 6) - 1);
1557 static midgard_scalar_alu
1558 vector_to_scalar_alu(midgard_vector_alu v
, midgard_instruction
*ins
)
1560 bool is_int
= midgard_is_integer_op(v
.op
);
1562 /* The output component is from the mask */
1563 midgard_scalar_alu s
= {
1565 .src1
= vector_to_scalar_source(v
.src1
, is_int
),
1566 .src2
= vector_to_scalar_source(v
.src2
, is_int
),
1569 .output_full
= 1, /* TODO: Half */
1570 .output_component
= component_from_mask(v
.mask
) << 1,
1573 /* Inline constant is passed along rather than trying to extract it
1576 if (ins
->ssa_args
.inline_constant
) {
1578 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
1579 imm
|= (lower_11
>> 9) & 3;
1580 imm
|= (lower_11
>> 6) & 4;
1581 imm
|= (lower_11
>> 2) & 0x38;
1582 imm
|= (lower_11
& 63) << 6;
1590 /* Midgard prefetches instruction types, so during emission we need to
1591 * lookahead too. Unless this is the last instruction, in which we return 1. Or
1592 * if this is the second to last and the last is an ALU, then it's also 1... */
1594 #define IS_ALU(tag) (tag == TAG_ALU_4 || tag == TAG_ALU_8 || \
1595 tag == TAG_ALU_12 || tag == TAG_ALU_16)
1597 #define EMIT_AND_COUNT(type, val) util_dynarray_append(emission, type, val); \
1598 bytes_emitted += sizeof(type)
1601 emit_binary_vector_instruction(midgard_instruction
*ains
,
1602 uint16_t *register_words
, int *register_words_count
,
1603 uint64_t *body_words
, size_t *body_size
, int *body_words_count
,
1604 size_t *bytes_emitted
)
1606 memcpy(®ister_words
[(*register_words_count
)++], &ains
->registers
, sizeof(ains
->registers
));
1607 *bytes_emitted
+= sizeof(midgard_reg_info
);
1609 body_size
[*body_words_count
] = sizeof(midgard_vector_alu
);
1610 memcpy(&body_words
[(*body_words_count
)++], &ains
->alu
, sizeof(ains
->alu
));
1611 *bytes_emitted
+= sizeof(midgard_vector_alu
);
1614 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
1615 * mind that we are a vector architecture and we can write to different
1616 * components simultaneously */
1619 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
1621 /* Each instruction reads some registers and writes to a register. See
1622 * where the first writes */
1624 /* Figure out where exactly we wrote to */
1625 int source
= first
->ssa_args
.dest
;
1626 int source_mask
= first
->type
== TAG_ALU_4
? squeeze_writemask(first
->alu
.mask
) : 0xF;
1628 /* As long as the second doesn't read from the first, we're okay */
1629 if (second
->ssa_args
.src0
== source
) {
1630 if (first
->type
== TAG_ALU_4
) {
1631 /* Figure out which components we just read from */
1633 int q
= second
->alu
.src1
;
1634 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1636 /* Check if there are components in common, and fail if so */
1637 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
1644 if (second
->ssa_args
.src1
== source
)
1647 /* Otherwise, it's safe in that regard. Another data hazard is both
1648 * writing to the same place, of course */
1650 if (second
->ssa_args
.dest
== source
) {
1651 /* ...but only if the components overlap */
1652 int dest_mask
= second
->type
== TAG_ALU_4
? squeeze_writemask(second
->alu
.mask
) : 0xF;
1654 if (dest_mask
& source_mask
)
1664 midgard_instruction
**segment
, unsigned segment_size
,
1665 midgard_instruction
*ains
)
1667 for (int s
= 0; s
< segment_size
; ++s
)
1668 if (!can_run_concurrent_ssa(segment
[s
], ains
))
1676 /* Schedules, but does not emit, a single basic block. After scheduling, the
1677 * final tag and size of the block are known, which are necessary for branching
1680 static midgard_bundle
1681 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
1683 int instructions_emitted
= 0, instructions_consumed
= -1;
1684 midgard_bundle bundle
= { 0 };
1686 uint8_t tag
= ins
->type
;
1688 /* Default to the instruction's tag */
1691 switch (ins
->type
) {
1693 uint32_t control
= 0;
1694 size_t bytes_emitted
= sizeof(control
);
1696 /* TODO: Constant combining */
1697 int index
= 0, last_unit
= 0;
1699 /* Previous instructions, for the purpose of parallelism */
1700 midgard_instruction
*segment
[4] = {0};
1701 int segment_size
= 0;
1703 instructions_emitted
= -1;
1704 midgard_instruction
*pins
= ins
;
1707 midgard_instruction
*ains
= pins
;
1709 /* Advance instruction pointer */
1711 ains
= mir_next_op(pins
);
1715 /* Out-of-work condition */
1716 if ((struct list_head
*) ains
== &block
->instructions
)
1719 /* Ensure that the chain can continue */
1720 if (ains
->type
!= TAG_ALU_4
) break;
1722 /* If there's already something in the bundle and we
1723 * have weird scheduler constraints, break now */
1724 if (ains
->precede_break
&& index
) break;
1726 /* According to the presentation "The ARM
1727 * Mali-T880 Mobile GPU" from HotChips 27,
1728 * there are two pipeline stages. Branching
1729 * position determined experimentally. Lines
1730 * are executed in parallel:
1733 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
1735 * Verify that there are no ordering dependencies here.
1737 * TODO: Allow for parallelism!!!
1740 /* Pick a unit for it if it doesn't force a particular unit */
1742 int unit
= ains
->unit
;
1745 int op
= ains
->alu
.op
;
1746 int units
= alu_opcode_props
[op
].props
;
1748 bool vectorable
= units
& UNITS_ANY_VECTOR
;
1749 bool scalarable
= units
& UNITS_SCALAR
;
1750 bool could_scalar
= is_single_component_mask(ains
->alu
.mask
);
1751 bool vector
= vectorable
&& !(could_scalar
&& scalarable
);
1754 assert(units
& UNITS_SCALAR
);
1757 if (last_unit
>= UNIT_VADD
) {
1758 if (units
& UNIT_VLUT
)
1763 if ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
))
1765 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
1767 else if (units
& UNIT_VLUT
)
1773 if (last_unit
>= UNIT_VADD
) {
1774 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
1776 else if (units
& UNIT_VLUT
)
1781 if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
1783 else if (units
& UNIT_SMUL
)
1784 unit
= ((units
& UNIT_VMUL
) && !(control
& UNIT_VMUL
)) ? UNIT_VMUL
: UNIT_SMUL
;
1785 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
1792 assert(unit
& units
);
1795 /* Late unit check, this time for encoding (not parallelism) */
1796 if (unit
<= last_unit
) break;
1798 /* Clear the segment */
1799 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
1802 if (midgard_has_hazard(segment
, segment_size
, ains
))
1805 /* We're good to go -- emit the instruction */
1808 segment
[segment_size
++] = ains
;
1810 /* Only one set of embedded constants per
1811 * bundle possible; if we have more, we must
1812 * break the chain early, unfortunately */
1814 if (ains
->has_constants
) {
1815 if (bundle
.has_embedded_constants
) {
1816 /* The blend constant needs to be
1817 * alone, since it conflicts with
1818 * everything by definition*/
1820 if (ains
->has_blend_constant
|| bundle
.has_blend_constant
)
1823 /* ...but if there are already
1824 * constants but these are the
1825 * *same* constants, we let it
1828 if (memcmp(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
)))
1831 bundle
.has_embedded_constants
= true;
1832 memcpy(bundle
.constants
, ains
->constants
, sizeof(bundle
.constants
));
1834 /* If this is a blend shader special constant, track it for patching */
1835 bundle
.has_blend_constant
|= ains
->has_blend_constant
;
1839 if (ains
->unit
& UNITS_ANY_VECTOR
) {
1840 emit_binary_vector_instruction(ains
, bundle
.register_words
,
1841 &bundle
.register_words_count
, bundle
.body_words
,
1842 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
1843 } else if (ains
->compact_branch
) {
1844 /* All of r0 has to be written out
1845 * along with the branch writeout.
1848 if (ains
->writeout
) {
1850 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
1851 ins
.unit
= UNIT_VMUL
;
1853 control
|= ins
.unit
;
1855 emit_binary_vector_instruction(&ins
, bundle
.register_words
,
1856 &bundle
.register_words_count
, bundle
.body_words
,
1857 bundle
.body_size
, &bundle
.body_words_count
, &bytes_emitted
);
1859 /* Analyse the group to see if r0 is written in full, on-time, without hanging dependencies*/
1860 bool written_late
= false;
1861 bool components
[4] = { 0 };
1862 uint16_t register_dep_mask
= 0;
1863 uint16_t written_mask
= 0;
1865 midgard_instruction
*qins
= ins
;
1866 for (int t
= 0; t
< index
; ++t
) {
1867 if (qins
->registers
.out_reg
!= 0) {
1868 /* Mark down writes */
1870 written_mask
|= (1 << qins
->registers
.out_reg
);
1872 /* Mark down the register dependencies for errata check */
1874 if (qins
->registers
.src1_reg
< 16)
1875 register_dep_mask
|= (1 << qins
->registers
.src1_reg
);
1877 if (qins
->registers
.src2_reg
< 16)
1878 register_dep_mask
|= (1 << qins
->registers
.src2_reg
);
1880 int mask
= qins
->alu
.mask
;
1882 for (int c
= 0; c
< 4; ++c
)
1883 if (mask
& (0x3 << (2 * c
)))
1884 components
[c
] = true;
1886 /* ..but if the writeout is too late, we have to break up anyway... for some reason */
1888 if (qins
->unit
== UNIT_VLUT
)
1889 written_late
= true;
1892 /* Advance instruction pointer */
1893 qins
= mir_next_op(qins
);
1897 /* Register dependencies of r0 must be out of fragment writeout bundle */
1898 if (register_dep_mask
& written_mask
)
1904 /* If even a single component is not written, break it up (conservative check). */
1905 bool breakup
= false;
1907 for (int c
= 0; c
< 4; ++c
)
1914 /* Otherwise, we're free to proceed */
1918 if (ains
->unit
== ALU_ENAB_BRANCH
) {
1919 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_branch_extended
);
1920 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->branch_extended
, sizeof(midgard_branch_extended
));
1921 bytes_emitted
+= sizeof(midgard_branch_extended
);
1923 bundle
.body_size
[bundle
.body_words_count
] = sizeof(ains
->br_compact
);
1924 memcpy(&bundle
.body_words
[bundle
.body_words_count
++], &ains
->br_compact
, sizeof(ains
->br_compact
));
1925 bytes_emitted
+= sizeof(ains
->br_compact
);
1928 memcpy(&bundle
.register_words
[bundle
.register_words_count
++], &ains
->registers
, sizeof(ains
->registers
));
1929 bytes_emitted
+= sizeof(midgard_reg_info
);
1931 bundle
.body_size
[bundle
.body_words_count
] = sizeof(midgard_scalar_alu
);
1932 bundle
.body_words_count
++;
1933 bytes_emitted
+= sizeof(midgard_scalar_alu
);
1936 /* Defer marking until after writing to allow for break */
1937 control
|= ains
->unit
;
1938 last_unit
= ains
->unit
;
1939 ++instructions_emitted
;
1943 /* Bubble up the number of instructions for skipping */
1944 instructions_consumed
= index
- 1;
1948 /* Pad ALU op to nearest word */
1950 if (bytes_emitted
& 15) {
1951 padding
= 16 - (bytes_emitted
& 15);
1952 bytes_emitted
+= padding
;
1955 /* Constants must always be quadwords */
1956 if (bundle
.has_embedded_constants
)
1957 bytes_emitted
+= 16;
1959 /* Size ALU instruction for tag */
1960 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
1961 bundle
.padding
= padding
;
1962 bundle
.control
= bundle
.tag
| control
;
1967 case TAG_LOAD_STORE_4
: {
1968 /* Load store instructions have two words at once. If
1969 * we only have one queued up, we need to NOP pad.
1970 * Otherwise, we store both in succession to save space
1971 * and cycles -- letting them go in parallel -- skip
1972 * the next. The usefulness of this optimisation is
1973 * greatly dependent on the quality of the instruction
1977 midgard_instruction
*next_op
= mir_next_op(ins
);
1979 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
1980 /* As the two operate concurrently, make sure
1981 * they are not dependent */
1983 if (can_run_concurrent_ssa(ins
, next_op
) || true) {
1984 /* Skip ahead, since it's redundant with the pair */
1985 instructions_consumed
= 1 + (instructions_emitted
++);
1993 /* Texture ops default to single-op-per-bundle scheduling */
1997 /* Copy the instructions into the bundle */
1998 bundle
.instruction_count
= instructions_emitted
+ 1;
2002 midgard_instruction
*uins
= ins
;
2003 for (int i
= 0; used_idx
< bundle
.instruction_count
; ++i
) {
2004 bundle
.instructions
[used_idx
++] = *uins
;
2005 uins
= mir_next_op(uins
);
2008 *skip
= (instructions_consumed
== -1) ? instructions_emitted
: instructions_consumed
;
2014 quadword_size(int tag
)
2029 case TAG_LOAD_STORE_4
:
2041 /* Schedule a single block by iterating its instruction to create bundles.
2042 * While we go, tally about the bundle sizes to compute the block size. */
2045 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
2047 util_dynarray_init(&block
->bundles
, NULL
);
2049 block
->quadword_count
= 0;
2051 mir_foreach_instr_in_block(block
, ins
) {
2053 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
2054 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
2056 if (bundle
.has_blend_constant
) {
2057 /* TODO: Multiblock? */
2058 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
2059 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
2063 ins
= mir_next_op(ins
);
2065 block
->quadword_count
+= quadword_size(bundle
.tag
);
2068 block
->is_scheduled
= true;
2072 schedule_program(compiler_context
*ctx
)
2074 /* We run RA prior to scheduling */
2075 struct ra_graph
*g
= allocate_registers(ctx
);
2076 install_registers(ctx
, g
);
2078 mir_foreach_block(ctx
, block
) {
2079 schedule_block(ctx
, block
);
2083 /* After everything is scheduled, emit whole bundles at a time */
2086 emit_binary_bundle(compiler_context
*ctx
, midgard_bundle
*bundle
, struct util_dynarray
*emission
, int next_tag
)
2088 int lookahead
= next_tag
<< 4;
2090 switch (bundle
->tag
) {
2095 /* Actually emit each component */
2096 util_dynarray_append(emission
, uint32_t, bundle
->control
| lookahead
);
2098 for (int i
= 0; i
< bundle
->register_words_count
; ++i
)
2099 util_dynarray_append(emission
, uint16_t, bundle
->register_words
[i
]);
2101 /* Emit body words based on the instructions bundled */
2102 for (int i
= 0; i
< bundle
->instruction_count
; ++i
) {
2103 midgard_instruction
*ins
= &bundle
->instructions
[i
];
2105 if (ins
->unit
& UNITS_ANY_VECTOR
) {
2106 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
->alu
, sizeof(midgard_vector_alu
));
2107 } else if (ins
->compact_branch
) {
2108 /* Dummy move, XXX DRY */
2109 if ((i
== 0) && ins
->writeout
) {
2110 midgard_instruction ins
= v_fmov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
2111 memcpy(util_dynarray_grow(emission
, sizeof(midgard_vector_alu
)), &ins
.alu
, sizeof(midgard_vector_alu
));
2114 if (ins
->unit
== ALU_ENAB_BR_COMPACT
) {
2115 memcpy(util_dynarray_grow(emission
, sizeof(ins
->br_compact
)), &ins
->br_compact
, sizeof(ins
->br_compact
));
2117 memcpy(util_dynarray_grow(emission
, sizeof(ins
->branch_extended
)), &ins
->branch_extended
, sizeof(ins
->branch_extended
));
2121 midgard_scalar_alu scalarised
= vector_to_scalar_alu(ins
->alu
, ins
);
2122 memcpy(util_dynarray_grow(emission
, sizeof(scalarised
)), &scalarised
, sizeof(scalarised
));
2126 /* Emit padding (all zero) */
2127 memset(util_dynarray_grow(emission
, bundle
->padding
), 0, bundle
->padding
);
2129 /* Tack on constants */
2131 if (bundle
->has_embedded_constants
) {
2132 util_dynarray_append(emission
, float, bundle
->constants
[0]);
2133 util_dynarray_append(emission
, float, bundle
->constants
[1]);
2134 util_dynarray_append(emission
, float, bundle
->constants
[2]);
2135 util_dynarray_append(emission
, float, bundle
->constants
[3]);
2141 case TAG_LOAD_STORE_4
: {
2142 /* One or two composing instructions */
2144 uint64_t current64
, next64
= LDST_NOP
;
2146 memcpy(¤t64
, &bundle
->instructions
[0].load_store
, sizeof(current64
));
2148 if (bundle
->instruction_count
== 2)
2149 memcpy(&next64
, &bundle
->instructions
[1].load_store
, sizeof(next64
));
2151 midgard_load_store instruction
= {
2152 .type
= bundle
->tag
,
2153 .next_type
= next_tag
,
2158 util_dynarray_append(emission
, midgard_load_store
, instruction
);
2163 case TAG_TEXTURE_4
: {
2164 /* Texture instructions are easy, since there is no
2165 * pipelining nor VLIW to worry about. We may need to set the .last flag */
2167 midgard_instruction
*ins
= &bundle
->instructions
[0];
2169 ins
->texture
.type
= TAG_TEXTURE_4
;
2170 ins
->texture
.next_type
= next_tag
;
2172 ctx
->texture_op_count
--;
2174 if (!ctx
->texture_op_count
) {
2175 ins
->texture
.cont
= 0;
2176 ins
->texture
.last
= 1;
2179 util_dynarray_append(emission
, midgard_texture_word
, ins
->texture
);
2184 DBG("Unknown midgard instruction type\n");
2191 /* ALU instructions can inline or embed constants, which decreases register
2192 * pressure and saves space. */
2194 #define CONDITIONAL_ATTACH(src) { \
2195 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
2198 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
2199 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
2204 inline_alu_constants(compiler_context
*ctx
)
2206 mir_foreach_instr(ctx
, alu
) {
2207 /* Other instructions cannot inline constants */
2208 if (alu
->type
!= TAG_ALU_4
) continue;
2210 /* If there is already a constant here, we can do nothing */
2211 if (alu
->has_constants
) continue;
2213 /* It makes no sense to inline constants on a branch */
2214 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
2216 CONDITIONAL_ATTACH(src0
);
2218 if (!alu
->has_constants
) {
2219 CONDITIONAL_ATTACH(src1
)
2220 } else if (!alu
->inline_constant
) {
2221 /* Corner case: _two_ vec4 constants, for instance with a
2222 * csel. For this case, we can only use a constant
2223 * register for one, we'll have to emit a move for the
2224 * other. Note, if both arguments are constants, then
2225 * necessarily neither argument depends on the value of
2226 * any particular register. As the destination register
2227 * will be wiped, that means we can spill the constant
2228 * to the destination register.
2231 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
2232 unsigned scratch
= alu
->ssa_args
.dest
;
2235 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
2236 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
2238 /* Force a break XXX Defer r31 writes */
2239 ins
.unit
= UNIT_VLUT
;
2241 /* Set the source */
2242 alu
->ssa_args
.src1
= scratch
;
2244 /* Inject us -before- the last instruction which set r31 */
2245 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
2251 /* Midgard supports two types of constants, embedded constants (128-bit) and
2252 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
2253 * constants can be demoted to inline constants, for space savings and
2254 * sometimes a performance boost */
2257 embedded_to_inline_constant(compiler_context
*ctx
)
2259 mir_foreach_instr(ctx
, ins
) {
2260 if (!ins
->has_constants
) continue;
2262 if (ins
->ssa_args
.inline_constant
) continue;
2264 /* Blend constants must not be inlined by definition */
2265 if (ins
->has_blend_constant
) continue;
2267 /* src1 cannot be an inline constant due to encoding
2268 * restrictions. So, if possible we try to flip the arguments
2271 int op
= ins
->alu
.op
;
2273 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2275 /* These ops require an operational change to flip
2276 * their arguments TODO */
2277 case midgard_alu_op_flt
:
2278 case midgard_alu_op_fle
:
2279 case midgard_alu_op_ilt
:
2280 case midgard_alu_op_ile
:
2281 case midgard_alu_op_fcsel
:
2282 case midgard_alu_op_icsel
:
2283 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
2288 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
2289 /* Flip the SSA numbers */
2290 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
2291 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
2293 /* And flip the modifiers */
2297 src_temp
= ins
->alu
.src2
;
2298 ins
->alu
.src2
= ins
->alu
.src1
;
2299 ins
->alu
.src1
= src_temp
;
2303 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
2304 /* Extract the source information */
2306 midgard_vector_alu_src
*src
;
2307 int q
= ins
->alu
.src2
;
2308 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
2311 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
2312 int component
= src
->swizzle
& 3;
2314 /* Scale constant appropriately, if we can legally */
2315 uint16_t scaled_constant
= 0;
2317 if (midgard_is_integer_op(op
)) {
2318 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
2319 scaled_constant
= (uint16_t) iconstants
[component
];
2321 /* Constant overflow after resize */
2322 if (scaled_constant
!= iconstants
[component
])
2325 float original
= (float) ins
->constants
[component
];
2326 scaled_constant
= _mesa_float_to_half(original
);
2328 /* Check for loss of precision. If this is
2329 * mediump, we don't care, but for a highp
2330 * shader, we need to pay attention. NIR
2331 * doesn't yet tell us which mode we're in!
2332 * Practically this prevents most constants
2333 * from being inlined, sadly. */
2335 float fp32
= _mesa_half_to_float(scaled_constant
);
2337 if (fp32
!= original
)
2341 /* We don't know how to handle these with a constant */
2343 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2344 DBG("Bailing inline constant...\n");
2348 /* Make sure that the constant is not itself a
2349 * vector by checking if all accessed values
2350 * (by the swizzle) are the same. */
2352 uint32_t *cons
= (uint32_t *) ins
->constants
;
2353 uint32_t value
= cons
[component
];
2355 bool is_vector
= false;
2356 unsigned mask
= effective_writemask(&ins
->alu
);
2358 for (int c
= 1; c
< 4; ++c
) {
2359 /* We only care if this component is actually used */
2360 if (!(mask
& (1 << c
)))
2363 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2365 if (test
!= value
) {
2374 /* Get rid of the embedded constant */
2375 ins
->has_constants
= false;
2376 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2377 ins
->ssa_args
.inline_constant
= true;
2378 ins
->inline_constant
= scaled_constant
;
2383 /* Map normal SSA sources to other SSA sources / fixed registers (like
2387 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2389 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2392 /* Remove entry in leftovers to avoid a redunant fmov */
2394 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2397 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2399 /* Assign the alias map */
2405 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
2406 * texture pipeline */
2409 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
2411 bool progress
= false;
2413 mir_foreach_instr_in_block_safe(block
, ins
) {
2414 if (ins
->type
!= TAG_ALU_4
) continue;
2415 if (ins
->compact_branch
) continue;
2417 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2418 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2420 mir_remove_instruction(ins
);
2428 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
2431 if (!is_int
&& src
.mod
) return true;
2434 for (unsigned c
= 0; c
< 4; ++c
) {
2435 if (!(mask
& (1 << c
))) continue;
2436 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
2443 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
2445 bool progress
= false;
2447 mir_foreach_instr_in_block_safe(block
, ins
) {
2448 if (ins
->type
!= TAG_ALU_4
) continue;
2449 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2451 unsigned from
= ins
->ssa_args
.src1
;
2452 unsigned to
= ins
->ssa_args
.dest
;
2454 /* We only work on pure SSA */
2456 if (to
>= SSA_FIXED_MINIMUM
) continue;
2457 if (from
>= SSA_FIXED_MINIMUM
) continue;
2458 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
2459 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2461 /* Constant propagation is not handled here, either */
2462 if (ins
->ssa_args
.inline_constant
) continue;
2463 if (ins
->has_constants
) continue;
2465 /* Also, if the move has side effects, we're helpless */
2467 midgard_vector_alu_src src
=
2468 vector_alu_from_unsigned(ins
->alu
.src2
);
2469 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
2470 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2472 if (mir_nontrivial_mod(src
, is_int
, mask
)) continue;
2473 if (ins
->alu
.outmod
!= midgard_outmod_none
) continue;
2475 mir_foreach_instr_in_block_from(block
, v
, mir_next_op(ins
)) {
2476 if (v
->ssa_args
.src0
== to
) {
2477 v
->ssa_args
.src0
= from
;
2481 if (v
->ssa_args
.src1
== to
&& !v
->ssa_args
.inline_constant
) {
2482 v
->ssa_args
.src1
= from
;
2492 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
2494 bool progress
= false;
2496 mir_foreach_instr_in_block_safe(block
, ins
) {
2497 if (ins
->type
!= TAG_ALU_4
) continue;
2498 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2500 unsigned from
= ins
->ssa_args
.src1
;
2501 unsigned to
= ins
->ssa_args
.dest
;
2503 /* Make sure it's simple enough for us to handle */
2505 if (from
>= SSA_FIXED_MINIMUM
) continue;
2506 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2507 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
2508 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
2510 bool eliminated
= false;
2512 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2513 /* The texture registers are not SSA so be careful.
2514 * Conservatively, just stop if we hit a texture op
2515 * (even if it may not write) to where we are */
2517 if (v
->type
!= TAG_ALU_4
)
2520 if (v
->ssa_args
.dest
== from
) {
2521 /* We don't want to track partial writes ... */
2522 if (v
->alu
.mask
== 0xF) {
2523 v
->ssa_args
.dest
= to
;
2532 mir_remove_instruction(ins
);
2534 progress
|= eliminated
;
2540 /* The following passes reorder MIR instructions to enable better scheduling */
2543 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2545 mir_foreach_instr_in_block_safe(block
, ins
) {
2546 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2548 /* We've found a load/store op. Check if next is also load/store. */
2549 midgard_instruction
*next_op
= mir_next_op(ins
);
2550 if (&next_op
->link
!= &block
->instructions
) {
2551 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2552 /* If so, we're done since we're a pair */
2553 ins
= mir_next_op(ins
);
2557 /* Maximum search distance to pair, to avoid register pressure disasters */
2558 int search_distance
= 8;
2560 /* Otherwise, we have an orphaned load/store -- search for another load */
2561 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2562 /* Terminate search if necessary */
2563 if (!(search_distance
--)) break;
2565 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2567 /* Stores cannot be reordered, since they have
2568 * dependencies. For the same reason, indirect
2569 * loads cannot be reordered as their index is
2570 * loaded in r27.w */
2572 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2574 /* It appears the 0x800 bit is set whenever a
2575 * load is direct, unset when it is indirect.
2576 * Skip indirect loads. */
2578 if (!(c
->load_store
.unknown
& 0x800)) continue;
2580 /* We found one! Move it up to pair and remove it from the old location */
2582 mir_insert_instruction_before(ins
, *c
);
2583 mir_remove_instruction(c
);
2591 /* Emit varying stores late */
2594 midgard_emit_store(compiler_context
*ctx
, midgard_block
*block
) {
2595 /* Iterate in reverse to get the final write, rather than the first */
2597 mir_foreach_instr_in_block_safe_rev(block
, ins
) {
2598 /* Check if what we just wrote needs a store */
2599 int idx
= ins
->ssa_args
.dest
;
2600 uintptr_t varying
= ((uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_varyings
, idx
+ 1));
2602 if (!varying
) continue;
2606 /* We need to store to the appropriate varying, so emit the
2609 /* TODO: Integrate with special purpose RA (and scheduler?) */
2610 bool high_varying_register
= false;
2612 midgard_instruction mov
= v_fmov(idx
, blank_alu_src
, SSA_FIXED_REGISTER(REGISTER_VARYING_BASE
+ high_varying_register
));
2614 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(high_varying_register
), varying
);
2615 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
2617 mir_insert_instruction_before(mir_next_op(ins
), st
);
2618 mir_insert_instruction_before(mir_next_op(ins
), mov
);
2620 /* We no longer need to store this varying */
2621 _mesa_hash_table_u64_remove(ctx
->ssa_varyings
, idx
+ 1);
2625 /* If there are leftovers after the below pass, emit actual fmov
2626 * instructions for the slow-but-correct path */
2629 emit_leftover_move(compiler_context
*ctx
)
2631 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2632 int base
= ((uintptr_t) leftover
->key
) - 1;
2635 map_ssa_to_alias(ctx
, &mapped
);
2636 EMIT(fmov
, mapped
, blank_alu_src
, base
);
2641 actualise_ssa_to_alias(compiler_context
*ctx
)
2643 mir_foreach_instr(ctx
, ins
) {
2644 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2645 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2648 emit_leftover_move(ctx
);
2652 emit_fragment_epilogue(compiler_context
*ctx
)
2654 /* Special case: writing out constants requires us to include the move
2655 * explicitly now, so shove it into r0 */
2657 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2659 if (constant_value
) {
2660 midgard_instruction ins
= v_fmov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2661 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2662 emit_mir_instruction(ctx
, ins
);
2665 /* Perform the actual fragment writeout. We have two writeout/branch
2666 * instructions, forming a loop until writeout is successful as per the
2667 * docs. TODO: gl_FragDepth */
2669 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2670 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2673 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2674 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2675 * with the int8 analogue to the fragment epilogue */
2678 emit_blend_epilogue(compiler_context
*ctx
)
2680 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2682 midgard_instruction scale
= {
2685 .inline_constant
= _mesa_float_to_half(255.0),
2687 .src0
= SSA_FIXED_REGISTER(0),
2688 .src1
= SSA_UNUSED_0
,
2689 .dest
= SSA_FIXED_REGISTER(24),
2690 .inline_constant
= true
2693 .op
= midgard_alu_op_fmul
,
2694 .reg_mode
= midgard_reg_mode_32
,
2695 .dest_override
= midgard_dest_override_lower
,
2697 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2698 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2702 emit_mir_instruction(ctx
, scale
);
2704 /* vadd.f2u8.pos.low hr0, hr48, #0 */
2706 midgard_vector_alu_src alu_src
= blank_alu_src
;
2707 alu_src
.half
= true;
2709 midgard_instruction f2u8
= {
2712 .src0
= SSA_FIXED_REGISTER(24),
2713 .src1
= SSA_UNUSED_0
,
2714 .dest
= SSA_FIXED_REGISTER(0),
2715 .inline_constant
= true
2718 .op
= midgard_alu_op_f2u8
,
2719 .reg_mode
= midgard_reg_mode_16
,
2720 .dest_override
= midgard_dest_override_lower
,
2721 .outmod
= midgard_outmod_pos
,
2723 .src1
= vector_alu_srco_unsigned(alu_src
),
2724 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2728 emit_mir_instruction(ctx
, f2u8
);
2730 /* vmul.imov.quarter r0, r0, r0 */
2732 midgard_instruction imov_8
= {
2735 .src0
= SSA_UNUSED_1
,
2736 .src1
= SSA_FIXED_REGISTER(0),
2737 .dest
= SSA_FIXED_REGISTER(0),
2740 .op
= midgard_alu_op_imov
,
2741 .reg_mode
= midgard_reg_mode_8
,
2742 .dest_override
= midgard_dest_override_none
,
2743 .outmod
= midgard_outmod_int
,
2745 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2746 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2750 /* Emit branch epilogue with the 8-bit move as the source */
2752 emit_mir_instruction(ctx
, imov_8
);
2753 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2755 emit_mir_instruction(ctx
, imov_8
);
2756 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2759 static midgard_block
*
2760 emit_block(compiler_context
*ctx
, nir_block
*block
)
2762 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2763 list_addtail(&this_block
->link
, &ctx
->blocks
);
2765 this_block
->is_scheduled
= false;
2768 ctx
->texture_index
[0] = -1;
2769 ctx
->texture_index
[1] = -1;
2771 /* Add us as a successor to the block we are following */
2772 if (ctx
->current_block
)
2773 midgard_block_add_successor(ctx
->current_block
, this_block
);
2775 /* Set up current block */
2776 list_inithead(&this_block
->instructions
);
2777 ctx
->current_block
= this_block
;
2779 nir_foreach_instr(instr
, block
) {
2780 emit_instr(ctx
, instr
);
2781 ++ctx
->instruction_count
;
2784 inline_alu_constants(ctx
);
2785 embedded_to_inline_constant(ctx
);
2787 /* Perform heavylifting for aliasing */
2788 actualise_ssa_to_alias(ctx
);
2790 midgard_emit_store(ctx
, this_block
);
2791 midgard_pair_load_store(ctx
, this_block
);
2793 /* Append fragment shader epilogue (value writeout) */
2794 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2795 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2797 emit_blend_epilogue(ctx
);
2799 emit_fragment_epilogue(ctx
);
2803 if (block
== nir_start_block(ctx
->func
->impl
))
2804 ctx
->initial_block
= this_block
;
2806 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2807 ctx
->final_block
= this_block
;
2809 /* Allow the next control flow to access us retroactively, for
2811 ctx
->current_block
= this_block
;
2813 /* Document the fallthrough chain */
2814 ctx
->previous_source_block
= this_block
;
2819 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2822 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2824 /* Conditional branches expect the condition in r31.w; emit a move for
2825 * that in the _previous_ block (which is the current block). */
2826 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2828 /* Speculatively emit the branch, but we can't fill it in until later */
2829 EMIT(branch
, true, true);
2830 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2832 /* Emit the two subblocks */
2833 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2835 /* Emit a jump from the end of the then block to the end of the else */
2836 EMIT(branch
, false, false);
2837 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2839 /* Emit second block, and check if it's empty */
2841 int else_idx
= ctx
->block_count
;
2842 int count_in
= ctx
->instruction_count
;
2843 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2844 int after_else_idx
= ctx
->block_count
;
2846 /* Now that we have the subblocks emitted, fix up the branches */
2851 if (ctx
->instruction_count
== count_in
) {
2852 /* The else block is empty, so don't emit an exit jump */
2853 mir_remove_instruction(then_exit
);
2854 then_branch
->branch
.target_block
= after_else_idx
;
2856 then_branch
->branch
.target_block
= else_idx
;
2857 then_exit
->branch
.target_block
= after_else_idx
;
2862 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2864 /* Remember where we are */
2865 midgard_block
*start_block
= ctx
->current_block
;
2867 /* Allocate a loop number, growing the current inner loop depth */
2868 int loop_idx
= ++ctx
->current_loop_depth
;
2870 /* Get index from before the body so we can loop back later */
2871 int start_idx
= ctx
->block_count
;
2873 /* Emit the body itself */
2874 emit_cf_list(ctx
, &nloop
->body
);
2876 /* Branch back to loop back */
2877 struct midgard_instruction br_back
= v_branch(false, false);
2878 br_back
.branch
.target_block
= start_idx
;
2879 emit_mir_instruction(ctx
, br_back
);
2881 /* Mark down that branch in the graph. Note that we're really branching
2882 * to the block *after* we started in. TODO: Why doesn't the branch
2883 * itself have an off-by-one then...? */
2884 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2886 /* Find the index of the block about to follow us (note: we don't add
2887 * one; blocks are 0-indexed so we get a fencepost problem) */
2888 int break_block_idx
= ctx
->block_count
;
2890 /* Fix up the break statements we emitted to point to the right place,
2891 * now that we can allocate a block number for them */
2893 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2894 mir_foreach_instr_in_block(block
, ins
) {
2895 if (ins
->type
!= TAG_ALU_4
) continue;
2896 if (!ins
->compact_branch
) continue;
2897 if (ins
->prepacked_branch
) continue;
2899 /* We found a branch -- check the type to see if we need to do anything */
2900 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2902 /* It's a break! Check if it's our break */
2903 if (ins
->branch
.target_break
!= loop_idx
) continue;
2905 /* Okay, cool, we're breaking out of this loop.
2906 * Rewrite from a break to a goto */
2908 ins
->branch
.target_type
= TARGET_GOTO
;
2909 ins
->branch
.target_block
= break_block_idx
;
2913 /* Now that we've finished emitting the loop, free up the depth again
2914 * so we play nice with recursion amid nested loops */
2915 --ctx
->current_loop_depth
;
2918 static midgard_block
*
2919 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2921 midgard_block
*start_block
= NULL
;
2923 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2924 switch (node
->type
) {
2925 case nir_cf_node_block
: {
2926 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2929 start_block
= block
;
2934 case nir_cf_node_if
:
2935 emit_if(ctx
, nir_cf_node_as_if(node
));
2938 case nir_cf_node_loop
:
2939 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2942 case nir_cf_node_function
:
2951 /* Due to lookahead, we need to report the first tag executed in the command
2952 * stream and in branch targets. An initial block might be empty, so iterate
2953 * until we find one that 'works' */
2956 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2958 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2960 unsigned first_tag
= 0;
2963 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2965 if (initial_bundle
) {
2966 first_tag
= initial_bundle
->tag
;
2970 /* Initial block is empty, try the next block */
2971 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2972 } while(initial_block
!= NULL
);
2979 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2981 struct util_dynarray
*compiled
= &program
->compiled
;
2983 midgard_debug
= debug_get_option_midgard_debug();
2985 compiler_context ictx
= {
2987 .stage
= nir
->info
.stage
,
2989 .is_blend
= is_blend
,
2990 .blend_constant_offset
= -1,
2992 .alpha_ref
= program
->alpha_ref
2995 compiler_context
*ctx
= &ictx
;
2997 /* TODO: Decide this at runtime */
2998 ctx
->uniform_cutoff
= 8;
3000 /* Assign var locations early, so the epilogue can use them if necessary */
3002 nir_assign_var_locations(&nir
->outputs
, &nir
->num_outputs
, glsl_type_size
);
3003 nir_assign_var_locations(&nir
->inputs
, &nir
->num_inputs
, glsl_type_size
);
3004 nir_assign_var_locations(&nir
->uniforms
, &nir
->num_uniforms
, glsl_type_size
);
3006 /* Initialize at a global (not block) level hash tables */
3008 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
3009 ctx
->ssa_varyings
= _mesa_hash_table_u64_create(NULL
);
3010 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
3011 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
3012 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
3013 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
3015 /* Record the varying mapping for the command stream's bookkeeping */
3017 struct exec_list
*varyings
=
3018 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
3020 nir_foreach_variable(var
, varyings
) {
3021 unsigned loc
= var
->data
.driver_location
;
3022 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
3024 for (int c
= 0; c
< sz
; ++c
) {
3025 program
->varyings
[loc
+ c
] = var
->data
.location
;
3029 /* Lower gl_Position pre-optimisation */
3031 if (ctx
->stage
== MESA_SHADER_VERTEX
)
3032 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
3034 NIR_PASS_V(nir
, nir_lower_var_copies
);
3035 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3036 NIR_PASS_V(nir
, nir_split_var_copies
);
3037 NIR_PASS_V(nir
, nir_lower_var_copies
);
3038 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
3039 NIR_PASS_V(nir
, nir_lower_var_copies
);
3040 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
3042 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
3044 /* Optimisation passes */
3048 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
3049 nir_print_shader(nir
, stdout
);
3052 /* Assign sysvals and counts, now that we're sure
3053 * (post-optimisation) */
3055 midgard_nir_assign_sysvals(ctx
, nir
);
3057 program
->uniform_count
= nir
->num_uniforms
;
3058 program
->sysval_count
= ctx
->sysval_count
;
3059 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
3061 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
3062 program
->varying_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_outputs
: ((ctx
->stage
== MESA_SHADER_FRAGMENT
) ? nir
->num_inputs
: 0);
3064 nir_foreach_function(func
, nir
) {
3068 list_inithead(&ctx
->blocks
);
3069 ctx
->block_count
= 0;
3072 emit_cf_list(ctx
, &func
->impl
->body
);
3073 emit_block(ctx
, func
->impl
->end_block
);
3075 break; /* TODO: Multi-function shaders */
3078 util_dynarray_init(compiled
, NULL
);
3080 /* MIR-level optimizations */
3082 bool progress
= false;
3087 mir_foreach_block(ctx
, block
) {
3088 progress
|= midgard_opt_copy_prop(ctx
, block
);
3089 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
3090 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
3095 schedule_program(ctx
);
3097 /* Now that all the bundles are scheduled and we can calculate block
3098 * sizes, emit actual branch instructions rather than placeholders */
3100 int br_block_idx
= 0;
3102 mir_foreach_block(ctx
, block
) {
3103 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3104 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
3105 midgard_instruction
*ins
= &bundle
->instructions
[c
];
3107 if (!midgard_is_branch_unit(ins
->unit
)) continue;
3109 if (ins
->prepacked_branch
) continue;
3111 /* Parse some basic branch info */
3112 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
3113 bool is_conditional
= ins
->branch
.conditional
;
3114 bool is_inverted
= ins
->branch
.invert_conditional
;
3115 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
3117 /* Determine the block we're jumping to */
3118 int target_number
= ins
->branch
.target_block
;
3120 /* Report the destination tag. Discards don't need this */
3121 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
3123 /* Count up the number of quadwords we're jumping over. That is, the number of quadwords in each of the blocks between (br_block_idx, target_number) */
3124 int quadword_offset
= 0;
3127 /* Jump to the end of the shader. We
3128 * need to include not only the
3129 * following blocks, but also the
3130 * contents of our current block (since
3131 * discard can come in the middle of
3134 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
3136 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
3137 quadword_offset
+= quadword_size(bun
->tag
);
3140 mir_foreach_block_from(ctx
, blk
, b
) {
3141 quadword_offset
+= b
->quadword_count
;
3144 } else if (target_number
> br_block_idx
) {
3147 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
3148 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3151 quadword_offset
+= blk
->quadword_count
;
3154 /* Jump backwards */
3156 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
3157 midgard_block
*blk
= mir_get_block(ctx
, idx
);
3160 quadword_offset
-= blk
->quadword_count
;
3164 /* Unconditional extended branches (far jumps)
3165 * have issues, so we always use a conditional
3166 * branch, setting the condition to always for
3167 * unconditional. For compact unconditional
3168 * branches, cond isn't used so it doesn't
3169 * matter what we pick. */
3171 midgard_condition cond
=
3172 !is_conditional
? midgard_condition_always
:
3173 is_inverted
? midgard_condition_false
:
3174 midgard_condition_true
;
3176 midgard_jmp_writeout_op op
=
3177 is_discard
? midgard_jmp_writeout_op_discard
:
3178 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
3179 midgard_jmp_writeout_op_branch_cond
;
3182 midgard_branch_extended branch
=
3183 midgard_create_branch_extended(
3188 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
3189 } else if (is_conditional
|| is_discard
) {
3190 midgard_branch_cond branch
= {
3192 .dest_tag
= dest_tag
,
3193 .offset
= quadword_offset
,
3197 assert(branch
.offset
== quadword_offset
);
3199 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3201 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
3203 midgard_branch_uncond branch
= {
3205 .dest_tag
= dest_tag
,
3206 .offset
= quadword_offset
,
3210 assert(branch
.offset
== quadword_offset
);
3212 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
3220 /* Emit flat binary from the instruction arrays. Iterate each block in
3221 * sequence. Save instruction boundaries such that lookahead tags can
3222 * be assigned easily */
3224 /* Cache _all_ bundles in source order for lookahead across failed branches */
3226 int bundle_count
= 0;
3227 mir_foreach_block(ctx
, block
) {
3228 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
3230 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
3232 mir_foreach_block(ctx
, block
) {
3233 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3234 source_order_bundles
[bundle_idx
++] = bundle
;
3238 int current_bundle
= 0;
3240 mir_foreach_block(ctx
, block
) {
3241 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
3244 if (current_bundle
+ 1 < bundle_count
) {
3245 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
3247 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
3254 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
3258 /* TODO: Free deeper */
3259 //util_dynarray_fini(&block->instructions);
3262 free(source_order_bundles
);
3264 /* Report the very first tag executed */
3265 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
3267 /* Deal with off-by-one related to the fencepost problem */
3268 program
->work_register_count
= ctx
->work_registers
+ 1;
3270 program
->can_discard
= ctx
->can_discard
;
3271 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
3273 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
3275 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
3276 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);