2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
60 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
62 int midgard_debug
= 0;
64 #define DBG(fmt, ...) \
65 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
66 fprintf(stderr, "%s:%d: "fmt, \
67 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
70 midgard_is_branch_unit(unsigned unit
)
72 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
76 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
78 block
->successors
[block
->nr_successors
++] = successor
;
79 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
82 /* Helpers to generate midgard_instruction's using macro magic, since every
83 * driver seems to do it that way */
85 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
98 .op = midgard_op_##name, \
99 .swizzle = SWIZZLE_XYZW, \
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
115 bool half
, bool sext
)
117 if (!src
) return blank_alu_src
;
119 /* Figure out how many components there are so we can adjust the
120 * swizzle. Specifically we want to broadcast the last channel so
121 * things like ball2/3 work
124 if (broadcast_count
) {
125 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
127 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
128 src
->swizzle
[c
] = last_component
;
132 midgard_vector_alu_src alu_src
= {
136 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
140 alu_src
.mod
= midgard_int_normal
;
142 /* Sign/zero-extend if needed */
146 midgard_int_sign_extend
147 : midgard_int_zero_extend
;
150 /* These should have been lowered away */
151 assert(!(src
->abs
|| src
->negate
));
153 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
159 /* load/store instructions have both 32-bit and 16-bit variants, depending on
160 * whether we are using vectors composed of highp or mediump. At the moment, we
161 * don't support half-floats -- this requires changes in other parts of the
162 * compiler -- therefore the 16-bit versions are commented out. */
164 //M_LOAD(ld_attr_16);
166 //M_LOAD(ld_vary_16);
168 //M_LOAD(ld_uniform_16);
169 M_LOAD(ld_uniform_32
);
170 M_LOAD(ld_color_buffer_8
);
171 //M_STORE(st_vary_16);
173 M_STORE(st_cubemap_coords
);
175 static midgard_instruction
176 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
178 midgard_branch_cond branch
= {
186 memcpy(&compact
, &branch
, sizeof(branch
));
188 midgard_instruction ins
= {
190 .unit
= ALU_ENAB_BR_COMPACT
,
191 .prepacked_branch
= true,
192 .compact_branch
= true,
193 .br_compact
= compact
196 if (op
== midgard_jmp_writeout_op_writeout
)
202 static midgard_instruction
203 v_branch(bool conditional
, bool invert
)
205 midgard_instruction ins
= {
207 .unit
= ALU_ENAB_BRANCH
,
208 .compact_branch
= true,
210 .conditional
= conditional
,
211 .invert_conditional
= invert
218 static midgard_branch_extended
219 midgard_create_branch_extended( midgard_condition cond
,
220 midgard_jmp_writeout_op op
,
222 signed quadword_offset
)
224 /* For unclear reasons, the condition code is repeated 8 times */
225 uint16_t duplicated_cond
=
235 midgard_branch_extended branch
= {
237 .dest_tag
= dest_tag
,
238 .offset
= quadword_offset
,
239 .cond
= duplicated_cond
246 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
248 ins
->has_constants
= true;
249 memcpy(&ins
->constants
, constants
, 16);
253 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
255 return glsl_count_attribute_slots(type
, false);
258 /* Lower fdot2 to a vector multiplication followed by channel addition */
260 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
262 if (alu
->op
!= nir_op_fdot2
)
265 b
->cursor
= nir_before_instr(&alu
->instr
);
267 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
268 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
270 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
272 nir_ssa_def
*sum
= nir_fadd(b
,
273 nir_channel(b
, product
, 0),
274 nir_channel(b
, product
, 1));
276 /* Replace the fdot2 with this sum */
277 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
281 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
283 switch (instr
->intrinsic
) {
284 case nir_intrinsic_load_viewport_scale
:
285 return PAN_SYSVAL_VIEWPORT_SCALE
;
286 case nir_intrinsic_load_viewport_offset
:
287 return PAN_SYSVAL_VIEWPORT_OFFSET
;
294 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
297 return dst
->ssa
.index
;
299 assert(!dst
->reg
.indirect
);
300 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
304 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
307 nir_intrinsic_instr
*intr
;
308 nir_dest
*dst
= NULL
;
312 switch (instr
->type
) {
313 case nir_instr_type_intrinsic
:
314 intr
= nir_instr_as_intrinsic(instr
);
315 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
318 case nir_instr_type_tex
:
319 tex
= nir_instr_as_tex(instr
);
320 if (tex
->op
!= nir_texop_txs
)
323 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
324 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
325 nir_tex_instr_dest_size(tex
) -
326 (tex
->is_array
? 1 : 0),
335 *dest
= nir_dest_index(ctx
, dst
);
341 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
345 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
349 /* We have a sysval load; check if it's already been assigned */
351 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
354 /* It hasn't -- so assign it now! */
356 unsigned id
= ctx
->sysval_count
++;
357 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
358 ctx
->sysvals
[id
] = sysval
;
362 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
364 ctx
->sysval_count
= 0;
366 nir_foreach_function(function
, shader
) {
367 if (!function
->impl
) continue;
369 nir_foreach_block(block
, function
->impl
) {
370 nir_foreach_instr_safe(instr
, block
) {
371 midgard_nir_assign_sysval_body(ctx
, instr
);
378 midgard_nir_lower_fdot2(nir_shader
*shader
)
380 bool progress
= false;
382 nir_foreach_function(function
, shader
) {
383 if (!function
->impl
) continue;
386 nir_builder
*b
= &_b
;
387 nir_builder_init(b
, function
->impl
);
389 nir_foreach_block(block
, function
->impl
) {
390 nir_foreach_instr_safe(instr
, block
) {
391 if (instr
->type
!= nir_instr_type_alu
) continue;
393 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
394 midgard_nir_lower_fdot2_body(b
, alu
);
400 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
407 /* Flushes undefined values to zero */
410 optimise_nir(nir_shader
*nir
)
413 unsigned lower_flrp
=
414 (nir
->options
->lower_flrp16
? 16 : 0) |
415 (nir
->options
->lower_flrp32
? 32 : 0) |
416 (nir
->options
->lower_flrp64
? 64 : 0);
418 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
419 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
420 NIR_PASS(progress
, nir
, nir_lower_idiv
);
422 nir_lower_tex_options lower_tex_1st_pass_options
= {
427 nir_lower_tex_options lower_tex_2nd_pass_options
= {
428 .lower_txs_lod
= true,
431 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
432 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
437 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
438 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
440 NIR_PASS(progress
, nir
, nir_copy_prop
);
441 NIR_PASS(progress
, nir
, nir_opt_dce
);
442 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
443 NIR_PASS(progress
, nir
, nir_opt_cse
);
444 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
445 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
446 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
448 if (lower_flrp
!= 0) {
449 bool lower_flrp_progress
= false;
450 NIR_PASS(lower_flrp_progress
,
454 false /* always_precise */,
455 nir
->options
->lower_ffma
);
456 if (lower_flrp_progress
) {
457 NIR_PASS(progress
, nir
,
458 nir_opt_constant_folding
);
462 /* Nothing should rematerialize any flrps, so we only
463 * need to do this lowering once.
468 NIR_PASS(progress
, nir
, nir_opt_undef
);
469 NIR_PASS(progress
, nir
, nir_undef_to_zero
);
471 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
474 nir_var_function_temp
);
476 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
479 /* Must be run at the end to prevent creation of fsin/fcos ops */
480 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
485 NIR_PASS(progress
, nir
, nir_opt_dce
);
486 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
487 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
488 NIR_PASS(progress
, nir
, nir_copy_prop
);
491 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
493 /* We implement booleans as 32-bit 0/~0 */
494 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
496 /* Now that booleans are lowered, we can run out late opts */
497 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
499 /* Lower mods for float ops only. Integer ops don't support modifiers
500 * (saturate doesn't make sense on integers, neg/abs require dedicated
503 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
504 NIR_PASS(progress
, nir
, nir_copy_prop
);
505 NIR_PASS(progress
, nir
, nir_opt_dce
);
507 /* Take us out of SSA */
508 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
509 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
511 /* We are a vector architecture; write combine where possible */
512 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
513 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
515 NIR_PASS(progress
, nir
, nir_opt_dce
);
518 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
519 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
520 * r0. See the comments in compiler_context */
523 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
525 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
526 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
529 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
532 unalias_ssa(compiler_context
*ctx
, int dest
)
534 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
535 /* TODO: Remove from leftover or no? */
538 /* Do not actually emit a load; instead, cache the constant for inlining */
541 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
543 nir_ssa_def def
= instr
->def
;
545 float *v
= rzalloc_array(NULL
, float, 4);
546 nir_const_load_to_arr(v
, instr
, f32
);
547 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
551 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
554 return src
->ssa
->index
;
556 assert(!src
->reg
.indirect
);
557 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
562 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
564 return nir_src_index(ctx
, &src
->src
);
568 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
570 unsigned comp
= src
->swizzle
[0];
572 for (unsigned c
= 1; c
< nr_components
; ++c
) {
573 if (src
->swizzle
[c
] != comp
)
580 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
581 * output of a conditional test) into that register */
584 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
586 int condition
= nir_src_index(ctx
, src
);
588 /* Source to swizzle the desired component into w */
590 const midgard_vector_alu_src alu_src
= {
591 .swizzle
= SWIZZLE(component
, component
, component
, component
),
594 /* There is no boolean move instruction. Instead, we simulate a move by
595 * ANDing the condition with itself to get it into r31.w */
597 midgard_instruction ins
= {
600 /* We need to set the conditional as close as possible */
601 .precede_break
= true,
602 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
603 .mask
= 1 << COMPONENT_W
,
608 .dest
= SSA_FIXED_REGISTER(31),
612 .op
= midgard_alu_op_iand
,
613 .outmod
= midgard_outmod_int_wrap
,
614 .reg_mode
= midgard_reg_mode_32
,
615 .dest_override
= midgard_dest_override_none
,
616 .src1
= vector_alu_srco_unsigned(alu_src
),
617 .src2
= vector_alu_srco_unsigned(alu_src
)
621 emit_mir_instruction(ctx
, ins
);
624 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
628 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
630 int condition
= nir_src_index(ctx
, &src
->src
);
632 /* Source to swizzle the desired component into w */
634 const midgard_vector_alu_src alu_src
= {
635 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
638 /* There is no boolean move instruction. Instead, we simulate a move by
639 * ANDing the condition with itself to get it into r31.w */
641 midgard_instruction ins
= {
643 .precede_break
= true,
644 .mask
= mask_of(nr_comp
),
648 .dest
= SSA_FIXED_REGISTER(31),
651 .op
= midgard_alu_op_iand
,
652 .outmod
= midgard_outmod_int_wrap
,
653 .reg_mode
= midgard_reg_mode_32
,
654 .dest_override
= midgard_dest_override_none
,
655 .src1
= vector_alu_srco_unsigned(alu_src
),
656 .src2
= vector_alu_srco_unsigned(alu_src
)
660 emit_mir_instruction(ctx
, ins
);
665 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
666 * pinning to eliminate this move in all known cases */
669 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
671 int offset
= nir_src_index(ctx
, src
);
673 midgard_instruction ins
= {
675 .mask
= 1 << COMPONENT_W
,
677 .src0
= SSA_UNUSED_1
,
679 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
682 .op
= midgard_alu_op_imov
,
683 .outmod
= midgard_outmod_int_wrap
,
684 .reg_mode
= midgard_reg_mode_32
,
685 .dest_override
= midgard_dest_override_none
,
686 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
687 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
691 emit_mir_instruction(ctx
, ins
);
694 #define ALU_CASE(nir, _op) \
696 op = midgard_alu_op_##_op; \
697 assert(src_bitsize == dst_bitsize); \
700 #define ALU_CASE_BCAST(nir, _op, count) \
702 op = midgard_alu_op_##_op; \
703 broadcast_swizzle = count; \
704 assert(src_bitsize == dst_bitsize); \
707 nir_is_fzero_constant(nir_src src
)
709 if (!nir_src_is_const(src
))
712 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
713 if (nir_src_comp_as_float(src
, c
) != 0.0)
720 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
721 * special treatment override this anyway. */
723 static midgard_reg_mode
724 reg_mode_for_nir(nir_alu_instr
*instr
)
726 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
728 switch (src_bitsize
) {
730 return midgard_reg_mode_8
;
732 return midgard_reg_mode_16
;
734 return midgard_reg_mode_32
;
736 return midgard_reg_mode_64
;
738 unreachable("Invalid bit size");
743 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
745 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
747 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
748 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
749 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
751 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
752 * supported. A few do not and are commented for now. Also, there are a
753 * number of NIR ops which Midgard does not support and need to be
754 * lowered, also TODO. This switch block emits the opcode and calling
755 * convention of the Midgard instruction; actual packing is done in
760 /* Number of components valid to check for the instruction (the rest
761 * will be forced to the last), or 0 to use as-is. Relevant as
762 * ball-type instructions have a channel count in NIR but are all vec4
765 unsigned broadcast_swizzle
= 0;
767 /* What register mode should we operate in? */
768 midgard_reg_mode reg_mode
=
769 reg_mode_for_nir(instr
);
771 /* Do we need a destination override? Used for inline
774 midgard_dest_override dest_override
=
775 midgard_dest_override_none
;
777 /* Should we use a smaller respective source and sign-extend? */
779 bool half_1
= false, sext_1
= false;
780 bool half_2
= false, sext_2
= false;
782 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
783 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
786 ALU_CASE(fadd
, fadd
);
787 ALU_CASE(fmul
, fmul
);
788 ALU_CASE(fmin
, fmin
);
789 ALU_CASE(fmax
, fmax
);
790 ALU_CASE(imin
, imin
);
791 ALU_CASE(imax
, imax
);
792 ALU_CASE(umin
, umin
);
793 ALU_CASE(umax
, umax
);
794 ALU_CASE(ffloor
, ffloor
);
795 ALU_CASE(fround_even
, froundeven
);
796 ALU_CASE(ftrunc
, ftrunc
);
797 ALU_CASE(fceil
, fceil
);
798 ALU_CASE(fdot3
, fdot3
);
799 ALU_CASE(fdot4
, fdot4
);
800 ALU_CASE(iadd
, iadd
);
801 ALU_CASE(isub
, isub
);
802 ALU_CASE(imul
, imul
);
804 /* Zero shoved as second-arg */
805 ALU_CASE(iabs
, iabsdiff
);
809 ALU_CASE(feq32
, feq
);
810 ALU_CASE(fne32
, fne
);
811 ALU_CASE(flt32
, flt
);
812 ALU_CASE(ieq32
, ieq
);
813 ALU_CASE(ine32
, ine
);
814 ALU_CASE(ilt32
, ilt
);
815 ALU_CASE(ult32
, ult
);
817 /* We don't have a native b2f32 instruction. Instead, like many
818 * GPUs, we exploit booleans as 0/~0 for false/true, and
819 * correspondingly AND
820 * by 1.0 to do the type conversion. For the moment, prime us
823 * iand [whatever], #0
825 * At the end of emit_alu (as MIR), we'll fix-up the constant
828 ALU_CASE(b2f32
, iand
);
829 ALU_CASE(b2i32
, iand
);
831 /* Likewise, we don't have a dedicated f2b32 instruction, but
832 * we can do a "not equal to 0.0" test. */
834 ALU_CASE(f2b32
, fne
);
835 ALU_CASE(i2b32
, ine
);
837 ALU_CASE(frcp
, frcp
);
838 ALU_CASE(frsq
, frsqrt
);
839 ALU_CASE(fsqrt
, fsqrt
);
840 ALU_CASE(fexp2
, fexp2
);
841 ALU_CASE(flog2
, flog2
);
843 ALU_CASE(f2i32
, f2i_rtz
);
844 ALU_CASE(f2u32
, f2u_rtz
);
845 ALU_CASE(i2f32
, i2f_rtz
);
846 ALU_CASE(u2f32
, u2f_rtz
);
848 ALU_CASE(f2i16
, f2i_rtz
);
849 ALU_CASE(f2u16
, f2u_rtz
);
850 ALU_CASE(i2f16
, i2f_rtz
);
851 ALU_CASE(u2f16
, u2f_rtz
);
853 ALU_CASE(fsin
, fsin
);
854 ALU_CASE(fcos
, fcos
);
856 /* Second op implicit #0 */
857 ALU_CASE(inot
, inor
);
858 ALU_CASE(iand
, iand
);
860 ALU_CASE(ixor
, ixor
);
861 ALU_CASE(ishl
, ishl
);
862 ALU_CASE(ishr
, iasr
);
863 ALU_CASE(ushr
, ilsr
);
865 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
866 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
867 ALU_CASE(b32all_fequal4
, fball_eq
);
869 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
870 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
871 ALU_CASE(b32any_fnequal4
, fbany_neq
);
873 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
874 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
875 ALU_CASE(b32all_iequal4
, iball_eq
);
877 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
878 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
879 ALU_CASE(b32any_inequal4
, ibany_neq
);
881 /* Source mods will be shoved in later */
882 ALU_CASE(fabs
, fmov
);
883 ALU_CASE(fneg
, fmov
);
884 ALU_CASE(fsat
, fmov
);
886 /* For size conversion, we use a move. Ideally though we would squash
887 * these ops together; maybe that has to happen after in NIR as part of
888 * propagation...? An earlier algebraic pass ensured we step down by
889 * only / exactly one size. If stepping down, we use a dest override to
890 * reduce the size; if stepping up, we use a larger-sized move with a
891 * half source and a sign/zero-extension modifier */
896 /* If we end up upscale, we'll need a sign-extend on the
897 * operand (the second argument) */
903 op
= midgard_alu_op_imov
;
905 if (dst_bitsize
== (src_bitsize
* 2)) {
909 /* Use a greater register mode */
911 } else if (src_bitsize
== (dst_bitsize
* 2)) {
912 /* Converting down */
913 dest_override
= midgard_dest_override_lower
;
920 assert(src_bitsize
== 32);
922 op
= midgard_alu_op_fmov
;
923 dest_override
= midgard_dest_override_lower
;
928 assert(src_bitsize
== 16);
930 op
= midgard_alu_op_fmov
;
937 /* For greater-or-equal, we lower to less-or-equal and flip the
945 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
946 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
947 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
948 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
951 /* Swap via temporary */
952 nir_alu_src temp
= instr
->src
[1];
953 instr
->src
[1] = instr
->src
[0];
954 instr
->src
[0] = temp
;
959 case nir_op_b32csel
: {
960 /* Midgard features both fcsel and icsel, depending on
961 * the type of the arguments/output. However, as long
962 * as we're careful we can _always_ use icsel and
963 * _never_ need fcsel, since the latter does additional
964 * floating-point-specific processing whereas the
965 * former just moves bits on the wire. It's not obvious
966 * why these are separate opcodes, save for the ability
967 * to do things like sat/pos/abs/neg for free */
969 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
970 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
972 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
975 /* Emit the condition into r31 */
978 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
980 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
982 /* The condition is the first argument; move the other
983 * arguments up one to be a binary instruction for
986 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
991 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
996 /* Midgard can perform certain modifiers on output of an ALU op */
999 if (midgard_is_integer_out_op(op
)) {
1000 outmod
= midgard_outmod_int_wrap
;
1002 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
1003 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
1006 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
1008 if (instr
->op
== nir_op_fmax
) {
1009 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
1010 op
= midgard_alu_op_fmov
;
1012 outmod
= midgard_outmod_pos
;
1013 instr
->src
[0] = instr
->src
[1];
1014 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
1015 op
= midgard_alu_op_fmov
;
1017 outmod
= midgard_outmod_pos
;
1021 /* Fetch unit, quirks, etc information */
1022 unsigned opcode_props
= alu_opcode_props
[op
].props
;
1023 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
1025 /* src0 will always exist afaik, but src1 will not for 1-argument
1026 * instructions. The latter can only be fetched if the instruction
1027 * needs it, or else we may segfault. */
1029 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1030 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1032 /* Rather than use the instruction generation helpers, we do it
1033 * ourselves here to avoid the mess */
1035 midgard_instruction ins
= {
1038 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1039 .src1
= quirk_flipped_r24
? src0
: src1
,
1044 nir_alu_src
*nirmods
[2] = { NULL
};
1046 if (nr_inputs
== 2) {
1047 nirmods
[0] = &instr
->src
[0];
1048 nirmods
[1] = &instr
->src
[1];
1049 } else if (nr_inputs
== 1) {
1050 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1055 /* These were lowered to a move, so apply the corresponding mod */
1057 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1058 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1060 if (instr
->op
== nir_op_fneg
)
1061 s
->negate
= !s
->negate
;
1063 if (instr
->op
== nir_op_fabs
)
1067 bool is_int
= midgard_is_integer_op(op
);
1069 ins
.mask
= mask_of(nr_components
);
1071 midgard_vector_alu alu
= {
1073 .reg_mode
= reg_mode
,
1074 .dest_override
= dest_override
,
1077 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1078 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1081 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1084 ins
.mask
&= instr
->dest
.write_mask
;
1088 /* Late fixup for emulated instructions */
1090 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1091 /* Presently, our second argument is an inline #0 constant.
1092 * Switch over to an embedded 1.0 constant (that can't fit
1093 * inline, since we're 32-bit, not 16-bit like the inline
1096 ins
.ssa_args
.inline_constant
= false;
1097 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1098 ins
.has_constants
= true;
1100 if (instr
->op
== nir_op_b2f32
) {
1101 ins
.constants
[0] = 1.0f
;
1103 /* Type pun it into place */
1105 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1108 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1109 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1110 /* Lots of instructions need a 0 plonked in */
1111 ins
.ssa_args
.inline_constant
= false;
1112 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1113 ins
.has_constants
= true;
1114 ins
.constants
[0] = 0.0f
;
1115 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1116 } else if (instr
->op
== nir_op_inot
) {
1117 /* ~b = ~(b & b), so duplicate the source */
1118 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1119 ins
.alu
.src2
= ins
.alu
.src1
;
1122 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1123 /* To avoid duplicating the lookup tables (probably), true LUT
1124 * instructions can only operate as if they were scalars. Lower
1125 * them here by changing the component. */
1127 uint8_t original_swizzle
[4];
1128 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1129 unsigned orig_mask
= ins
.mask
;
1131 for (int i
= 0; i
< nr_components
; ++i
) {
1132 /* Mask the associated component, dropping the
1133 * instruction if needed */
1136 ins
.mask
&= orig_mask
;
1141 for (int j
= 0; j
< 4; ++j
)
1142 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1144 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1145 emit_mir_instruction(ctx
, ins
);
1148 emit_mir_instruction(ctx
, ins
);
1154 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1155 * optimized) versions of UBO #0 */
1159 compiler_context
*ctx
,
1162 nir_src
*indirect_offset
,
1165 /* TODO: half-floats */
1167 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
&& index
== 0) {
1168 /* Fast path: For the first 16 uniforms, direct accesses are
1169 * 0-cycle, since they're just a register fetch in the usual
1170 * case. So, we alias the registers while we're still in
1173 int reg_slot
= 23 - offset
;
1174 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1176 /* Otherwise, read from the 'special' UBO to access
1177 * higher-indexed uniforms, at a performance cost. More
1178 * generally, we're emitting a UBO read instruction. */
1180 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1182 /* TODO: Don't split */
1183 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1184 ins
.load_store
.address
= offset
>> 3;
1186 if (indirect_offset
) {
1187 emit_indirect_offset(ctx
, indirect_offset
);
1188 ins
.load_store
.unknown
= 0x8700 | index
; /* xxx: what is this? */
1190 ins
.load_store
.unknown
= 0x1E00 | index
; /* xxx: what is this? */
1193 /* TODO respect index */
1195 emit_mir_instruction(ctx
, ins
);
1201 compiler_context
*ctx
,
1202 unsigned dest
, unsigned offset
,
1203 unsigned nr_comp
, unsigned component
,
1204 nir_src
*indirect_offset
, nir_alu_type type
)
1206 /* XXX: Half-floats? */
1207 /* TODO: swizzle, mask */
1209 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1210 ins
.mask
= mask_of(nr_comp
);
1211 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1213 midgard_varying_parameter p
= {
1215 .interpolation
= midgard_interp_default
,
1216 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1220 memcpy(&u
, &p
, sizeof(p
));
1221 ins
.load_store
.varying_parameters
= u
;
1223 if (indirect_offset
) {
1224 /* We need to add in the dynamic index, moved to r27.w */
1225 emit_indirect_offset(ctx
, indirect_offset
);
1226 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1228 /* Just a direct load */
1229 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1232 /* Use the type appropriate load */
1236 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1239 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1241 case nir_type_float
:
1242 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1245 unreachable("Attempted to load unknown type");
1249 emit_mir_instruction(ctx
, ins
);
1253 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1256 /* Figure out which uniform this is */
1257 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1258 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1260 /* Sysvals are prefix uniforms */
1261 unsigned uniform
= ((uintptr_t) val
) - 1;
1263 /* Emit the read itself -- this is never indirect */
1264 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1268 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1270 unsigned offset
= 0, reg
;
1272 switch (instr
->intrinsic
) {
1273 case nir_intrinsic_discard_if
:
1274 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1278 case nir_intrinsic_discard
: {
1279 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1280 struct midgard_instruction discard
= v_branch(conditional
, false);
1281 discard
.branch
.target_type
= TARGET_DISCARD
;
1282 emit_mir_instruction(ctx
, discard
);
1284 ctx
->can_discard
= true;
1288 case nir_intrinsic_load_uniform
:
1289 case nir_intrinsic_load_ubo
:
1290 case nir_intrinsic_load_input
: {
1291 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1292 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1294 /* Get the base type of the intrinsic */
1295 /* TODO: Infer type? Does it matter? */
1297 is_ubo
? nir_type_uint
: nir_intrinsic_type(instr
);
1298 t
= nir_alu_type_get_base_type(t
);
1301 offset
= nir_intrinsic_base(instr
);
1304 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1306 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1308 bool direct
= nir_src_is_const(*src_offset
);
1311 offset
+= nir_src_as_uint(*src_offset
);
1313 /* We may need to apply a fractional offset */
1314 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1315 nir_intrinsic_component(instr
) : 0;
1316 reg
= nir_dest_index(ctx
, &instr
->dest
);
1318 if (is_uniform
&& !ctx
->is_blend
) {
1319 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1320 } else if (is_ubo
) {
1321 nir_src index
= instr
->src
[0];
1323 /* We don't yet support indirect UBOs. For indirect
1324 * block numbers (if that's possible), we don't know
1325 * enough about the hardware yet. For indirect sources,
1326 * we know what we need but we need to add some NIR
1327 * support for lowering correctly with respect to
1330 assert(nir_src_is_const(index
));
1331 assert(nir_src_is_const(*src_offset
));
1333 /* TODO: Alignment */
1334 assert((offset
& 0xF) == 0);
1336 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1337 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1338 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1339 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1340 } else if (ctx
->is_blend
) {
1341 /* For blend shaders, load the input color, which is
1342 * preloaded to r0 */
1344 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1345 emit_mir_instruction(ctx
, move
);
1346 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1347 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1348 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1349 ins
.mask
= mask_of(nr_comp
);
1351 /* Use the type appropriate load */
1355 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1358 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1360 case nir_type_float
:
1361 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1364 unreachable("Attempted to load unknown type");
1368 emit_mir_instruction(ctx
, ins
);
1370 DBG("Unknown load\n");
1377 /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
1379 case nir_intrinsic_load_raw_output_pan
:
1380 reg
= nir_dest_index(ctx
, &instr
->dest
);
1381 assert(ctx
->is_blend
);
1383 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1384 emit_mir_instruction(ctx
, ins
);
1387 case nir_intrinsic_load_blend_const_color_rgba
: {
1388 assert(ctx
->is_blend
);
1389 reg
= nir_dest_index(ctx
, &instr
->dest
);
1391 /* Blend constants are embedded directly in the shader and
1392 * patched in, so we use some magic routing */
1394 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1395 ins
.has_constants
= true;
1396 ins
.has_blend_constant
= true;
1397 emit_mir_instruction(ctx
, ins
);
1401 case nir_intrinsic_store_output
:
1402 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1404 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1406 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1408 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1409 /* gl_FragColor is not emitted with load/store
1410 * instructions. Instead, it gets plonked into
1411 * r0 at the end of the shader and we do the
1412 * framebuffer writeout dance. TODO: Defer
1415 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1416 emit_mir_instruction(ctx
, move
);
1418 /* Save the index we're writing to for later reference
1419 * in the epilogue */
1421 ctx
->fragment_output
= reg
;
1422 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1423 /* Varyings are written into one of two special
1424 * varying register, r26 or r27. The register itself is
1425 * selected as the register in the st_vary instruction,
1426 * minus the base of 26. E.g. write into r27 and then
1427 * call st_vary(1) */
1429 midgard_instruction ins
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1430 emit_mir_instruction(ctx
, ins
);
1432 /* We should have been vectorized, though we don't
1433 * currently check that st_vary is emitted only once
1434 * per slot (this is relevant, since there's not a mask
1435 * parameter available on the store [set to 0 by the
1436 * blob]). We do respect the component by adjusting the
1439 unsigned component
= nir_intrinsic_component(instr
);
1441 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1442 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1443 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1444 emit_mir_instruction(ctx
, st
);
1446 DBG("Unknown store\n");
1452 /* Special case of store_output for lowered blend shaders */
1453 case nir_intrinsic_store_raw_output_pan
:
1454 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1455 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1457 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1458 emit_mir_instruction(ctx
, move
);
1459 ctx
->fragment_output
= reg
;
1463 case nir_intrinsic_load_alpha_ref_float
:
1464 assert(instr
->dest
.is_ssa
);
1466 float ref_value
= ctx
->alpha_ref
;
1468 float *v
= ralloc_array(NULL
, float, 4);
1469 memcpy(v
, &ref_value
, sizeof(float));
1470 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1473 case nir_intrinsic_load_viewport_scale
:
1474 case nir_intrinsic_load_viewport_offset
:
1475 emit_sysval_read(ctx
, &instr
->instr
);
1479 printf ("Unhandled intrinsic\n");
1486 midgard_tex_format(enum glsl_sampler_dim dim
)
1489 case GLSL_SAMPLER_DIM_1D
:
1490 case GLSL_SAMPLER_DIM_BUF
:
1493 case GLSL_SAMPLER_DIM_2D
:
1494 case GLSL_SAMPLER_DIM_EXTERNAL
:
1497 case GLSL_SAMPLER_DIM_3D
:
1500 case GLSL_SAMPLER_DIM_CUBE
:
1501 return MALI_TEX_CUBE
;
1504 DBG("Unknown sampler dim type\n");
1510 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1514 pan_attach_constant_bias(
1515 compiler_context
*ctx
,
1517 midgard_texture_word
*word
)
1519 /* To attach as constant, it has to *be* constant */
1521 if (!nir_src_is_const(lod
))
1524 float f
= nir_src_as_float(lod
);
1526 /* Break into fixed-point */
1528 float lod_frac
= f
- lod_int
;
1530 /* Carry over negative fractions */
1531 if (lod_frac
< 0.0) {
1537 word
->bias
= float_to_ubyte(lod_frac
);
1538 word
->bias_int
= lod_int
;
1543 static enum mali_sampler_type
1544 midgard_sampler_type(nir_alu_type t
)
1546 switch (nir_alu_type_get_base_type(t
)) {
1547 case nir_type_float
:
1548 return MALI_SAMPLER_FLOAT
;
1550 return MALI_SAMPLER_SIGNED
;
1552 return MALI_SAMPLER_UNSIGNED
;
1554 unreachable("Unknown sampler type");
1559 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1560 unsigned midgard_texop
)
1563 //assert (!instr->sampler);
1564 //assert (!instr->texture_array_size);
1566 /* Allocate registers via a round robin scheme to alternate between the two registers */
1567 int reg
= ctx
->texture_op_count
& 1;
1568 int in_reg
= reg
, out_reg
= reg
;
1570 /* Make room for the reg */
1572 if (ctx
->texture_index
[reg
] > -1)
1573 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1575 int texture_index
= instr
->texture_index
;
1576 int sampler_index
= texture_index
;
1578 /* No helper to build texture words -- we do it all here */
1579 midgard_instruction ins
= {
1580 .type
= TAG_TEXTURE_4
,
1583 .op
= midgard_texop
,
1584 .format
= midgard_tex_format(instr
->sampler_dim
),
1585 .texture_handle
= texture_index
,
1586 .sampler_handle
= sampler_index
,
1588 /* TODO: Regalloc it in */
1589 .swizzle
= SWIZZLE_XYZW
,
1595 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1599 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1600 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1601 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1602 int nr_comp
= nir_src_num_components(instr
->src
[i
].src
);
1603 midgard_vector_alu_src alu_src
= blank_alu_src
;
1605 switch (instr
->src
[i
].src_type
) {
1606 case nir_tex_src_coord
: {
1607 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1608 /* texelFetch is undefined on samplerCube */
1609 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1611 /* For cubemaps, we need to load coords into
1612 * special r27, and then use a special ld/st op
1613 * to select the face and copy the xy into the
1614 * texture register */
1616 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1618 midgard_instruction move
= v_mov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1619 emit_mir_instruction(ctx
, move
);
1621 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1622 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1623 st
.mask
= 0x3; /* xy */
1624 st
.load_store
.swizzle
= alu_src
.swizzle
;
1625 emit_mir_instruction(ctx
, st
);
1627 ins
.texture
.in_reg_swizzle
= swizzle_of(2);
1629 ins
.texture
.in_reg_swizzle
= alu_src
.swizzle
= swizzle_of(nr_comp
);
1631 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1632 mov
.mask
= mask_of(nr_comp
);
1633 emit_mir_instruction(ctx
, mov
);
1635 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1636 /* Texel fetch opcodes care about the
1637 * values of z and w, so we actually
1638 * need to spill into a second register
1639 * for a texel fetch with register bias
1640 * (for non-2D). TODO: Implement that
1643 assert(instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
);
1645 midgard_instruction zero
= v_mov(index
, alu_src
, reg
);
1646 zero
.ssa_args
.inline_constant
= true;
1647 zero
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1648 zero
.has_constants
= true;
1649 zero
.mask
= ~mov
.mask
;
1650 emit_mir_instruction(ctx
, zero
);
1652 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1654 /* Non-texel fetch doesn't need that
1655 * nonsense. However we do use the Z
1656 * for array indexing */
1657 bool is_3d
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
;
1658 ins
.texture
.in_reg_swizzle
= is_3d
? SWIZZLE_XYZZ
: SWIZZLE_XYXZ
;
1665 case nir_tex_src_bias
:
1666 case nir_tex_src_lod
: {
1667 /* Try as a constant if we can */
1669 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1670 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1673 /* Otherwise we use a register. To keep RA simple, we
1674 * put the bias/LOD into the w component of the input
1675 * source, which is otherwise in xy */
1677 alu_src
.swizzle
= SWIZZLE_XXXX
;
1679 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1680 mov
.mask
= 1 << COMPONENT_W
;
1681 emit_mir_instruction(ctx
, mov
);
1683 ins
.texture
.lod_register
= true;
1685 midgard_tex_register_select sel
= {
1695 memcpy(&packed
, &sel
, sizeof(packed
));
1696 ins
.texture
.bias
= packed
;
1702 unreachable("Unknown texture source type\n");
1706 /* Set registers to read and write from the same place */
1707 ins
.texture
.in_reg_select
= in_reg
;
1708 ins
.texture
.out_reg_select
= out_reg
;
1710 emit_mir_instruction(ctx
, ins
);
1712 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1713 midgard_instruction ins2
= v_mov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1714 emit_mir_instruction(ctx
, ins2
);
1716 /* Used for .cont and .last hinting */
1717 ctx
->texture_op_count
++;
1721 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1723 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1724 * generic tex in some cases (which confuses the hardware) */
1726 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1728 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1729 instr
->op
= nir_texop_txl
;
1731 switch (instr
->op
) {
1734 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1737 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1740 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1743 emit_sysval_read(ctx
, &instr
->instr
);
1746 unreachable("Unhanlded texture op");
1751 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1753 switch (instr
->type
) {
1754 case nir_jump_break
: {
1755 /* Emit a branch out of the loop */
1756 struct midgard_instruction br
= v_branch(false, false);
1757 br
.branch
.target_type
= TARGET_BREAK
;
1758 br
.branch
.target_break
= ctx
->current_loop_depth
;
1759 emit_mir_instruction(ctx
, br
);
1766 DBG("Unknown jump type %d\n", instr
->type
);
1772 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1774 switch (instr
->type
) {
1775 case nir_instr_type_load_const
:
1776 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1779 case nir_instr_type_intrinsic
:
1780 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1783 case nir_instr_type_alu
:
1784 emit_alu(ctx
, nir_instr_as_alu(instr
));
1787 case nir_instr_type_tex
:
1788 emit_tex(ctx
, nir_instr_as_tex(instr
));
1791 case nir_instr_type_jump
:
1792 emit_jump(ctx
, nir_instr_as_jump(instr
));
1795 case nir_instr_type_ssa_undef
:
1800 DBG("Unhandled instruction type\n");
1806 /* ALU instructions can inline or embed constants, which decreases register
1807 * pressure and saves space. */
1809 #define CONDITIONAL_ATTACH(src) { \
1810 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1813 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1814 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1819 inline_alu_constants(compiler_context
*ctx
)
1821 mir_foreach_instr(ctx
, alu
) {
1822 /* Other instructions cannot inline constants */
1823 if (alu
->type
!= TAG_ALU_4
) continue;
1825 /* If there is already a constant here, we can do nothing */
1826 if (alu
->has_constants
) continue;
1828 /* It makes no sense to inline constants on a branch */
1829 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1831 CONDITIONAL_ATTACH(src0
);
1833 if (!alu
->has_constants
) {
1834 CONDITIONAL_ATTACH(src1
)
1835 } else if (!alu
->inline_constant
) {
1836 /* Corner case: _two_ vec4 constants, for instance with a
1837 * csel. For this case, we can only use a constant
1838 * register for one, we'll have to emit a move for the
1839 * other. Note, if both arguments are constants, then
1840 * necessarily neither argument depends on the value of
1841 * any particular register. As the destination register
1842 * will be wiped, that means we can spill the constant
1843 * to the destination register.
1846 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1847 unsigned scratch
= alu
->ssa_args
.dest
;
1850 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1851 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1853 /* Force a break XXX Defer r31 writes */
1854 ins
.unit
= UNIT_VLUT
;
1856 /* Set the source */
1857 alu
->ssa_args
.src1
= scratch
;
1859 /* Inject us -before- the last instruction which set r31 */
1860 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1866 /* Midgard supports two types of constants, embedded constants (128-bit) and
1867 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1868 * constants can be demoted to inline constants, for space savings and
1869 * sometimes a performance boost */
1872 embedded_to_inline_constant(compiler_context
*ctx
)
1874 mir_foreach_instr(ctx
, ins
) {
1875 if (!ins
->has_constants
) continue;
1877 if (ins
->ssa_args
.inline_constant
) continue;
1879 /* Blend constants must not be inlined by definition */
1880 if (ins
->has_blend_constant
) continue;
1882 /* We can inline 32-bit (sometimes) or 16-bit (usually) */
1883 bool is_16
= ins
->alu
.reg_mode
== midgard_reg_mode_16
;
1884 bool is_32
= ins
->alu
.reg_mode
== midgard_reg_mode_32
;
1886 if (!(is_16
|| is_32
))
1889 /* src1 cannot be an inline constant due to encoding
1890 * restrictions. So, if possible we try to flip the arguments
1893 int op
= ins
->alu
.op
;
1895 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1897 /* These ops require an operational change to flip
1898 * their arguments TODO */
1899 case midgard_alu_op_flt
:
1900 case midgard_alu_op_fle
:
1901 case midgard_alu_op_ilt
:
1902 case midgard_alu_op_ile
:
1903 case midgard_alu_op_fcsel
:
1904 case midgard_alu_op_icsel
:
1905 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1910 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1911 /* Flip the SSA numbers */
1912 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1913 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1915 /* And flip the modifiers */
1919 src_temp
= ins
->alu
.src2
;
1920 ins
->alu
.src2
= ins
->alu
.src1
;
1921 ins
->alu
.src1
= src_temp
;
1925 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1926 /* Extract the source information */
1928 midgard_vector_alu_src
*src
;
1929 int q
= ins
->alu
.src2
;
1930 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1933 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1934 int component
= src
->swizzle
& 3;
1936 /* Scale constant appropriately, if we can legally */
1937 uint16_t scaled_constant
= 0;
1939 if (midgard_is_integer_op(op
) || is_16
) {
1940 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1941 scaled_constant
= (uint16_t) iconstants
[component
];
1943 /* Constant overflow after resize */
1944 if (scaled_constant
!= iconstants
[component
])
1947 float original
= (float) ins
->constants
[component
];
1948 scaled_constant
= _mesa_float_to_half(original
);
1950 /* Check for loss of precision. If this is
1951 * mediump, we don't care, but for a highp
1952 * shader, we need to pay attention. NIR
1953 * doesn't yet tell us which mode we're in!
1954 * Practically this prevents most constants
1955 * from being inlined, sadly. */
1957 float fp32
= _mesa_half_to_float(scaled_constant
);
1959 if (fp32
!= original
)
1963 /* We don't know how to handle these with a constant */
1965 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
1966 DBG("Bailing inline constant...\n");
1970 /* Make sure that the constant is not itself a
1971 * vector by checking if all accessed values
1972 * (by the swizzle) are the same. */
1974 uint32_t *cons
= (uint32_t *) ins
->constants
;
1975 uint32_t value
= cons
[component
];
1977 bool is_vector
= false;
1978 unsigned mask
= effective_writemask(&ins
->alu
, ins
->mask
);
1980 for (int c
= 1; c
< 4; ++c
) {
1981 /* We only care if this component is actually used */
1982 if (!(mask
& (1 << c
)))
1985 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1987 if (test
!= value
) {
1996 /* Get rid of the embedded constant */
1997 ins
->has_constants
= false;
1998 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1999 ins
->ssa_args
.inline_constant
= true;
2000 ins
->inline_constant
= scaled_constant
;
2005 /* Map normal SSA sources to other SSA sources / fixed registers (like
2009 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2011 /* Sign is used quite deliberately for unused */
2015 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2018 /* Remove entry in leftovers to avoid a redunant fmov */
2020 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2023 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2025 /* Assign the alias map */
2031 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
2032 * texture pipeline */
2035 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
2037 bool progress
= false;
2039 mir_foreach_instr_in_block_safe(block
, ins
) {
2040 if (ins
->type
!= TAG_ALU_4
) continue;
2041 if (ins
->compact_branch
) continue;
2043 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2044 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2046 mir_remove_instruction(ins
);
2053 /* Dead code elimination for branches at the end of a block - only one branch
2054 * per block is legal semantically */
2057 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2059 bool branched
= false;
2061 mir_foreach_instr_in_block_safe(block
, ins
) {
2062 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2064 /* We ignore prepacked branches since the fragment epilogue is
2065 * just generally special */
2066 if (ins
->prepacked_branch
) continue;
2068 /* Discards are similarly special and may not correspond to the
2071 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
2074 /* We already branched, so this is dead */
2075 mir_remove_instruction(ins
);
2083 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
2086 if (!is_int
&& src
.mod
) return true;
2088 /* Other int mods don't matter in isolation */
2089 if (is_int
&& src
.mod
== midgard_int_shift
) return true;
2091 /* size-conversion */
2092 if (src
.half
) return true;
2095 for (unsigned c
= 0; c
< 4; ++c
) {
2096 if (!(mask
& (1 << c
))) continue;
2097 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
2104 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
2106 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2108 midgard_vector_alu_src src2
=
2109 vector_alu_from_unsigned(ins
->alu
.src2
);
2111 return mir_nontrivial_mod(src2
, is_int
, ins
->mask
);
2115 mir_nontrivial_outmod(midgard_instruction
*ins
)
2117 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2118 unsigned mod
= ins
->alu
.outmod
;
2120 /* Type conversion is a sort of outmod */
2121 if (ins
->alu
.dest_override
!= midgard_dest_override_none
)
2125 return mod
!= midgard_outmod_int_wrap
;
2127 return mod
!= midgard_outmod_none
;
2131 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
2133 bool progress
= false;
2135 mir_foreach_instr_in_block_safe(block
, ins
) {
2136 if (ins
->type
!= TAG_ALU_4
) continue;
2137 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2139 unsigned from
= ins
->ssa_args
.src1
;
2140 unsigned to
= ins
->ssa_args
.dest
;
2142 /* We only work on pure SSA */
2144 if (to
>= SSA_FIXED_MINIMUM
) continue;
2145 if (from
>= SSA_FIXED_MINIMUM
) continue;
2146 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
2147 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2149 /* Constant propagation is not handled here, either */
2150 if (ins
->ssa_args
.inline_constant
) continue;
2151 if (ins
->has_constants
) continue;
2153 if (mir_nontrivial_source2_mod(ins
)) continue;
2154 if (mir_nontrivial_outmod(ins
)) continue;
2156 /* We're clear -- rewrite */
2157 mir_rewrite_index_src(ctx
, to
, from
);
2158 mir_remove_instruction(ins
);
2165 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2166 * the move can be propagated away entirely */
2169 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2172 if (comp
== midgard_outmod_none
)
2175 if (*outmod
== midgard_outmod_none
) {
2180 /* TODO: Compose rules */
2185 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2187 bool progress
= false;
2189 mir_foreach_instr_in_block_safe(block
, ins
) {
2190 if (ins
->type
!= TAG_ALU_4
) continue;
2191 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2192 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2194 /* TODO: Registers? */
2195 unsigned src
= ins
->ssa_args
.src1
;
2196 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
2197 assert(!mir_has_multiple_writes(ctx
, src
));
2199 /* There might be a source modifier, too */
2200 if (mir_nontrivial_source2_mod(ins
)) continue;
2202 /* Backpropagate the modifier */
2203 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2204 if (v
->type
!= TAG_ALU_4
) continue;
2205 if (v
->ssa_args
.dest
!= src
) continue;
2207 /* Can we even take a float outmod? */
2208 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2210 midgard_outmod_float temp
= v
->alu
.outmod
;
2211 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2213 /* Throw in the towel.. */
2214 if (!progress
) break;
2216 /* Otherwise, transfer the modifier */
2217 v
->alu
.outmod
= temp
;
2218 ins
->alu
.outmod
= midgard_outmod_none
;
2227 /* The following passes reorder MIR instructions to enable better scheduling */
2230 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2232 mir_foreach_instr_in_block_safe(block
, ins
) {
2233 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2235 /* We've found a load/store op. Check if next is also load/store. */
2236 midgard_instruction
*next_op
= mir_next_op(ins
);
2237 if (&next_op
->link
!= &block
->instructions
) {
2238 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2239 /* If so, we're done since we're a pair */
2240 ins
= mir_next_op(ins
);
2244 /* Maximum search distance to pair, to avoid register pressure disasters */
2245 int search_distance
= 8;
2247 /* Otherwise, we have an orphaned load/store -- search for another load */
2248 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2249 /* Terminate search if necessary */
2250 if (!(search_distance
--)) break;
2252 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2254 /* Stores cannot be reordered, since they have
2255 * dependencies. For the same reason, indirect
2256 * loads cannot be reordered as their index is
2257 * loaded in r27.w */
2259 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2261 /* It appears the 0x800 bit is set whenever a
2262 * load is direct, unset when it is indirect.
2263 * Skip indirect loads. */
2265 if (!(c
->load_store
.unknown
& 0x800)) continue;
2267 /* We found one! Move it up to pair and remove it from the old location */
2269 mir_insert_instruction_before(ins
, *c
);
2270 mir_remove_instruction(c
);
2278 /* If there are leftovers after the below pass, emit actual fmov
2279 * instructions for the slow-but-correct path */
2282 emit_leftover_move(compiler_context
*ctx
)
2284 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2285 int base
= ((uintptr_t) leftover
->key
) - 1;
2288 map_ssa_to_alias(ctx
, &mapped
);
2289 EMIT(mov
, mapped
, blank_alu_src
, base
);
2294 actualise_ssa_to_alias(compiler_context
*ctx
)
2296 mir_foreach_instr(ctx
, ins
) {
2297 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2298 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2301 emit_leftover_move(ctx
);
2305 emit_fragment_epilogue(compiler_context
*ctx
)
2307 /* Special case: writing out constants requires us to include the move
2308 * explicitly now, so shove it into r0 */
2310 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2312 if (constant_value
) {
2313 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2314 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2315 emit_mir_instruction(ctx
, ins
);
2318 /* Perform the actual fragment writeout. We have two writeout/branch
2319 * instructions, forming a loop until writeout is successful as per the
2320 * docs. TODO: gl_FragDepth */
2322 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2323 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2326 static midgard_block
*
2327 emit_block(compiler_context
*ctx
, nir_block
*block
)
2329 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2330 list_addtail(&this_block
->link
, &ctx
->blocks
);
2332 this_block
->is_scheduled
= false;
2335 ctx
->texture_index
[0] = -1;
2336 ctx
->texture_index
[1] = -1;
2338 /* Add us as a successor to the block we are following */
2339 if (ctx
->current_block
)
2340 midgard_block_add_successor(ctx
->current_block
, this_block
);
2342 /* Set up current block */
2343 list_inithead(&this_block
->instructions
);
2344 ctx
->current_block
= this_block
;
2346 nir_foreach_instr(instr
, block
) {
2347 emit_instr(ctx
, instr
);
2348 ++ctx
->instruction_count
;
2351 inline_alu_constants(ctx
);
2352 embedded_to_inline_constant(ctx
);
2354 /* Perform heavylifting for aliasing */
2355 actualise_ssa_to_alias(ctx
);
2357 midgard_pair_load_store(ctx
, this_block
);
2359 /* Append fragment shader epilogue (value writeout) */
2360 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2361 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2362 emit_fragment_epilogue(ctx
);
2366 if (block
== nir_start_block(ctx
->func
->impl
))
2367 ctx
->initial_block
= this_block
;
2369 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2370 ctx
->final_block
= this_block
;
2372 /* Allow the next control flow to access us retroactively, for
2374 ctx
->current_block
= this_block
;
2376 /* Document the fallthrough chain */
2377 ctx
->previous_source_block
= this_block
;
2382 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2385 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2387 /* Conditional branches expect the condition in r31.w; emit a move for
2388 * that in the _previous_ block (which is the current block). */
2389 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2391 /* Speculatively emit the branch, but we can't fill it in until later */
2392 EMIT(branch
, true, true);
2393 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2395 /* Emit the two subblocks */
2396 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2398 /* Emit a jump from the end of the then block to the end of the else */
2399 EMIT(branch
, false, false);
2400 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2402 /* Emit second block, and check if it's empty */
2404 int else_idx
= ctx
->block_count
;
2405 int count_in
= ctx
->instruction_count
;
2406 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2407 int after_else_idx
= ctx
->block_count
;
2409 /* Now that we have the subblocks emitted, fix up the branches */
2414 if (ctx
->instruction_count
== count_in
) {
2415 /* The else block is empty, so don't emit an exit jump */
2416 mir_remove_instruction(then_exit
);
2417 then_branch
->branch
.target_block
= after_else_idx
;
2419 then_branch
->branch
.target_block
= else_idx
;
2420 then_exit
->branch
.target_block
= after_else_idx
;
2425 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2427 /* Remember where we are */
2428 midgard_block
*start_block
= ctx
->current_block
;
2430 /* Allocate a loop number, growing the current inner loop depth */
2431 int loop_idx
= ++ctx
->current_loop_depth
;
2433 /* Get index from before the body so we can loop back later */
2434 int start_idx
= ctx
->block_count
;
2436 /* Emit the body itself */
2437 emit_cf_list(ctx
, &nloop
->body
);
2439 /* Branch back to loop back */
2440 struct midgard_instruction br_back
= v_branch(false, false);
2441 br_back
.branch
.target_block
= start_idx
;
2442 emit_mir_instruction(ctx
, br_back
);
2444 /* Mark down that branch in the graph. Note that we're really branching
2445 * to the block *after* we started in. TODO: Why doesn't the branch
2446 * itself have an off-by-one then...? */
2447 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2449 /* Find the index of the block about to follow us (note: we don't add
2450 * one; blocks are 0-indexed so we get a fencepost problem) */
2451 int break_block_idx
= ctx
->block_count
;
2453 /* Fix up the break statements we emitted to point to the right place,
2454 * now that we can allocate a block number for them */
2456 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2457 mir_foreach_instr_in_block(block
, ins
) {
2458 if (ins
->type
!= TAG_ALU_4
) continue;
2459 if (!ins
->compact_branch
) continue;
2460 if (ins
->prepacked_branch
) continue;
2462 /* We found a branch -- check the type to see if we need to do anything */
2463 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2465 /* It's a break! Check if it's our break */
2466 if (ins
->branch
.target_break
!= loop_idx
) continue;
2468 /* Okay, cool, we're breaking out of this loop.
2469 * Rewrite from a break to a goto */
2471 ins
->branch
.target_type
= TARGET_GOTO
;
2472 ins
->branch
.target_block
= break_block_idx
;
2476 /* Now that we've finished emitting the loop, free up the depth again
2477 * so we play nice with recursion amid nested loops */
2478 --ctx
->current_loop_depth
;
2481 static midgard_block
*
2482 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2484 midgard_block
*start_block
= NULL
;
2486 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2487 switch (node
->type
) {
2488 case nir_cf_node_block
: {
2489 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2492 start_block
= block
;
2497 case nir_cf_node_if
:
2498 emit_if(ctx
, nir_cf_node_as_if(node
));
2501 case nir_cf_node_loop
:
2502 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2505 case nir_cf_node_function
:
2514 /* Due to lookahead, we need to report the first tag executed in the command
2515 * stream and in branch targets. An initial block might be empty, so iterate
2516 * until we find one that 'works' */
2519 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2521 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2523 unsigned first_tag
= 0;
2526 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2528 if (initial_bundle
) {
2529 first_tag
= initial_bundle
->tag
;
2533 /* Initial block is empty, try the next block */
2534 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2535 } while(initial_block
!= NULL
);
2542 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2544 struct util_dynarray
*compiled
= &program
->compiled
;
2546 midgard_debug
= debug_get_option_midgard_debug();
2548 compiler_context ictx
= {
2550 .stage
= nir
->info
.stage
,
2552 .is_blend
= is_blend
,
2553 .blend_constant_offset
= 0,
2555 .alpha_ref
= program
->alpha_ref
2558 compiler_context
*ctx
= &ictx
;
2560 /* TODO: Decide this at runtime */
2561 ctx
->uniform_cutoff
= 8;
2563 /* Initialize at a global (not block) level hash tables */
2565 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2566 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
2567 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2568 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2569 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
2571 /* Record the varying mapping for the command stream's bookkeeping */
2573 struct exec_list
*varyings
=
2574 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2576 unsigned max_varying
= 0;
2577 nir_foreach_variable(var
, varyings
) {
2578 unsigned loc
= var
->data
.driver_location
;
2579 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2581 for (int c
= 0; c
< sz
; ++c
) {
2582 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2583 max_varying
= MAX2(max_varying
, loc
+ c
);
2587 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2588 * (so we don't accidentally duplicate the epilogue since mesa/st has
2589 * messed with our I/O quite a bit already) */
2591 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2593 if (ctx
->stage
== MESA_SHADER_VERTEX
)
2594 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2596 NIR_PASS_V(nir
, nir_lower_var_copies
);
2597 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2598 NIR_PASS_V(nir
, nir_split_var_copies
);
2599 NIR_PASS_V(nir
, nir_lower_var_copies
);
2600 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2601 NIR_PASS_V(nir
, nir_lower_var_copies
);
2602 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2604 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2606 /* Optimisation passes */
2610 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2611 nir_print_shader(nir
, stdout
);
2614 /* Assign sysvals and counts, now that we're sure
2615 * (post-optimisation) */
2617 midgard_nir_assign_sysvals(ctx
, nir
);
2619 program
->uniform_count
= nir
->num_uniforms
;
2620 program
->sysval_count
= ctx
->sysval_count
;
2621 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2623 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
2624 program
->varying_count
= max_varying
+ 1; /* Fencepost off-by-one */
2626 nir_foreach_function(func
, nir
) {
2630 list_inithead(&ctx
->blocks
);
2631 ctx
->block_count
= 0;
2634 emit_cf_list(ctx
, &func
->impl
->body
);
2635 emit_block(ctx
, func
->impl
->end_block
);
2637 break; /* TODO: Multi-function shaders */
2640 util_dynarray_init(compiled
, NULL
);
2642 /* MIR-level optimizations */
2644 bool progress
= false;
2649 mir_foreach_block(ctx
, block
) {
2650 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2651 progress
|= midgard_opt_copy_prop(ctx
, block
);
2652 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2656 /* Nested control-flow can result in dead branches at the end of the
2657 * block. This messes with our analysis and is just dead code, so cull
2659 mir_foreach_block(ctx
, block
) {
2660 midgard_opt_cull_dead_branch(ctx
, block
);
2664 schedule_program(ctx
);
2666 /* Now that all the bundles are scheduled and we can calculate block
2667 * sizes, emit actual branch instructions rather than placeholders */
2669 int br_block_idx
= 0;
2671 mir_foreach_block(ctx
, block
) {
2672 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2673 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2674 midgard_instruction
*ins
= bundle
->instructions
[c
];
2676 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2678 if (ins
->prepacked_branch
) continue;
2680 /* Parse some basic branch info */
2681 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2682 bool is_conditional
= ins
->branch
.conditional
;
2683 bool is_inverted
= ins
->branch
.invert_conditional
;
2684 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2686 /* Determine the block we're jumping to */
2687 int target_number
= ins
->branch
.target_block
;
2689 /* Report the destination tag */
2690 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2692 /* Count up the number of quadwords we're
2693 * jumping over = number of quadwords until
2694 * (br_block_idx, target_number) */
2696 int quadword_offset
= 0;
2699 /* Jump to the end of the shader. We
2700 * need to include not only the
2701 * following blocks, but also the
2702 * contents of our current block (since
2703 * discard can come in the middle of
2706 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2708 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2709 quadword_offset
+= quadword_size(bun
->tag
);
2712 mir_foreach_block_from(ctx
, blk
, b
) {
2713 quadword_offset
+= b
->quadword_count
;
2716 } else if (target_number
> br_block_idx
) {
2719 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2720 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2723 quadword_offset
+= blk
->quadword_count
;
2726 /* Jump backwards */
2728 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2729 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2732 quadword_offset
-= blk
->quadword_count
;
2736 /* Unconditional extended branches (far jumps)
2737 * have issues, so we always use a conditional
2738 * branch, setting the condition to always for
2739 * unconditional. For compact unconditional
2740 * branches, cond isn't used so it doesn't
2741 * matter what we pick. */
2743 midgard_condition cond
=
2744 !is_conditional
? midgard_condition_always
:
2745 is_inverted
? midgard_condition_false
:
2746 midgard_condition_true
;
2748 midgard_jmp_writeout_op op
=
2749 is_discard
? midgard_jmp_writeout_op_discard
:
2750 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2751 midgard_jmp_writeout_op_branch_cond
;
2754 midgard_branch_extended branch
=
2755 midgard_create_branch_extended(
2760 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2761 } else if (is_conditional
|| is_discard
) {
2762 midgard_branch_cond branch
= {
2764 .dest_tag
= dest_tag
,
2765 .offset
= quadword_offset
,
2769 assert(branch
.offset
== quadword_offset
);
2771 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2773 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2775 midgard_branch_uncond branch
= {
2777 .dest_tag
= dest_tag
,
2778 .offset
= quadword_offset
,
2782 assert(branch
.offset
== quadword_offset
);
2784 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2792 /* Emit flat binary from the instruction arrays. Iterate each block in
2793 * sequence. Save instruction boundaries such that lookahead tags can
2794 * be assigned easily */
2796 /* Cache _all_ bundles in source order for lookahead across failed branches */
2798 int bundle_count
= 0;
2799 mir_foreach_block(ctx
, block
) {
2800 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2802 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2804 mir_foreach_block(ctx
, block
) {
2805 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2806 source_order_bundles
[bundle_idx
++] = bundle
;
2810 int current_bundle
= 0;
2812 /* Midgard prefetches instruction types, so during emission we
2813 * need to lookahead. Unless this is the last instruction, in
2814 * which we return 1. Or if this is the second to last and the
2815 * last is an ALU, then it's also 1... */
2817 mir_foreach_block(ctx
, block
) {
2818 mir_foreach_bundle_in_block(block
, bundle
) {
2821 if (current_bundle
+ 1 < bundle_count
) {
2822 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2824 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2831 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2835 /* TODO: Free deeper */
2836 //util_dynarray_fini(&block->instructions);
2839 free(source_order_bundles
);
2841 /* Report the very first tag executed */
2842 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2844 /* Deal with off-by-one related to the fencepost problem */
2845 program
->work_register_count
= ctx
->work_registers
+ 1;
2847 program
->can_discard
= ctx
->can_discard
;
2848 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2850 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2852 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2853 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);