2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_math.h"
40 #include "util/u_debug.h"
41 #include "util/u_dynarray.h"
42 #include "util/list.h"
43 #include "main/mtypes.h"
46 #include "midgard_nir.h"
47 #include "midgard_compile.h"
48 #include "midgard_ops.h"
52 #include "disassemble.h"
54 static const struct debug_named_value debug_options
[] = {
55 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
56 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
60 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
62 int midgard_debug
= 0;
64 #define DBG(fmt, ...) \
65 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
66 fprintf(stderr, "%s:%d: "fmt, \
67 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
70 midgard_is_branch_unit(unsigned unit
)
72 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
76 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
78 block
->successors
[block
->nr_successors
++] = successor
;
79 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
82 /* Helpers to generate midgard_instruction's using macro magic, since every
83 * driver seems to do it that way */
85 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
87 #define M_LOAD_STORE(name, rname, uname) \
88 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
89 midgard_instruction i = { \
90 .type = TAG_LOAD_STORE_4, \
97 .op = midgard_op_##name, \
99 .swizzle = SWIZZLE_XYZW, \
107 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
108 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
110 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
111 * the corresponding Midgard source */
113 static midgard_vector_alu_src
114 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
, unsigned broadcast_count
,
115 bool half
, bool sext
)
117 if (!src
) return blank_alu_src
;
119 /* Figure out how many components there are so we can adjust the
120 * swizzle. Specifically we want to broadcast the last channel so
121 * things like ball2/3 work
124 if (broadcast_count
) {
125 uint8_t last_component
= src
->swizzle
[broadcast_count
- 1];
127 for (unsigned c
= broadcast_count
; c
< NIR_MAX_VEC_COMPONENTS
; ++c
) {
128 src
->swizzle
[c
] = last_component
;
132 midgard_vector_alu_src alu_src
= {
136 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
140 alu_src
.mod
= midgard_int_normal
;
142 /* Sign/zero-extend if needed */
146 midgard_int_sign_extend
147 : midgard_int_zero_extend
;
150 /* These should have been lowered away */
151 assert(!(src
->abs
|| src
->negate
));
153 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
159 /* load/store instructions have both 32-bit and 16-bit variants, depending on
160 * whether we are using vectors composed of highp or mediump. At the moment, we
161 * don't support half-floats -- this requires changes in other parts of the
162 * compiler -- therefore the 16-bit versions are commented out. */
164 //M_LOAD(ld_attr_16);
166 //M_LOAD(ld_vary_16);
168 //M_LOAD(ld_uniform_16);
169 M_LOAD(ld_uniform_32
);
170 M_LOAD(ld_color_buffer_8
);
171 //M_STORE(st_vary_16);
173 M_STORE(st_cubemap_coords
);
175 static midgard_instruction
176 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
178 midgard_branch_cond branch
= {
186 memcpy(&compact
, &branch
, sizeof(branch
));
188 midgard_instruction ins
= {
190 .unit
= ALU_ENAB_BR_COMPACT
,
191 .prepacked_branch
= true,
192 .compact_branch
= true,
193 .br_compact
= compact
196 if (op
== midgard_jmp_writeout_op_writeout
)
202 static midgard_instruction
203 v_branch(bool conditional
, bool invert
)
205 midgard_instruction ins
= {
207 .unit
= ALU_ENAB_BRANCH
,
208 .compact_branch
= true,
210 .conditional
= conditional
,
211 .invert_conditional
= invert
218 static midgard_branch_extended
219 midgard_create_branch_extended( midgard_condition cond
,
220 midgard_jmp_writeout_op op
,
222 signed quadword_offset
)
224 /* For unclear reasons, the condition code is repeated 8 times */
225 uint16_t duplicated_cond
=
235 midgard_branch_extended branch
= {
237 .dest_tag
= dest_tag
,
238 .offset
= quadword_offset
,
239 .cond
= duplicated_cond
246 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
248 ins
->has_constants
= true;
249 memcpy(&ins
->constants
, constants
, 16);
253 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
255 return glsl_count_attribute_slots(type
, false);
258 /* Lower fdot2 to a vector multiplication followed by channel addition */
260 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
262 if (alu
->op
!= nir_op_fdot2
)
265 b
->cursor
= nir_before_instr(&alu
->instr
);
267 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
268 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
270 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
272 nir_ssa_def
*sum
= nir_fadd(b
,
273 nir_channel(b
, product
, 0),
274 nir_channel(b
, product
, 1));
276 /* Replace the fdot2 with this sum */
277 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
281 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
283 switch (instr
->intrinsic
) {
284 case nir_intrinsic_load_viewport_scale
:
285 return PAN_SYSVAL_VIEWPORT_SCALE
;
286 case nir_intrinsic_load_viewport_offset
:
287 return PAN_SYSVAL_VIEWPORT_OFFSET
;
294 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
297 return dst
->ssa
.index
;
299 assert(!dst
->reg
.indirect
);
300 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
304 static int sysval_for_instr(compiler_context
*ctx
, nir_instr
*instr
,
307 nir_intrinsic_instr
*intr
;
308 nir_dest
*dst
= NULL
;
312 switch (instr
->type
) {
313 case nir_instr_type_intrinsic
:
314 intr
= nir_instr_as_intrinsic(instr
);
315 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
318 case nir_instr_type_tex
:
319 tex
= nir_instr_as_tex(instr
);
320 if (tex
->op
!= nir_texop_txs
)
323 sysval
= PAN_SYSVAL(TEXTURE_SIZE
,
324 PAN_TXS_SYSVAL_ID(tex
->texture_index
,
325 nir_tex_instr_dest_size(tex
) -
326 (tex
->is_array
? 1 : 0),
335 *dest
= nir_dest_index(ctx
, dst
);
341 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
345 sysval
= sysval_for_instr(ctx
, instr
, NULL
);
349 /* We have a sysval load; check if it's already been assigned */
351 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
354 /* It hasn't -- so assign it now! */
356 unsigned id
= ctx
->sysval_count
++;
357 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
358 ctx
->sysvals
[id
] = sysval
;
362 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
364 ctx
->sysval_count
= 0;
366 nir_foreach_function(function
, shader
) {
367 if (!function
->impl
) continue;
369 nir_foreach_block(block
, function
->impl
) {
370 nir_foreach_instr_safe(instr
, block
) {
371 midgard_nir_assign_sysval_body(ctx
, instr
);
378 midgard_nir_lower_fdot2(nir_shader
*shader
)
380 bool progress
= false;
382 nir_foreach_function(function
, shader
) {
383 if (!function
->impl
) continue;
386 nir_builder
*b
= &_b
;
387 nir_builder_init(b
, function
->impl
);
389 nir_foreach_block(block
, function
->impl
) {
390 nir_foreach_instr_safe(instr
, block
) {
391 if (instr
->type
!= nir_instr_type_alu
) continue;
393 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
394 midgard_nir_lower_fdot2_body(b
, alu
);
400 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
408 optimise_nir(nir_shader
*nir
)
411 unsigned lower_flrp
=
412 (nir
->options
->lower_flrp16
? 16 : 0) |
413 (nir
->options
->lower_flrp32
? 32 : 0) |
414 (nir
->options
->lower_flrp64
? 64 : 0);
416 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
417 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
418 NIR_PASS(progress
, nir
, nir_lower_idiv
);
420 nir_lower_tex_options lower_tex_1st_pass_options
= {
425 nir_lower_tex_options lower_tex_2nd_pass_options
= {
426 .lower_txs_lod
= true,
429 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_1st_pass_options
);
430 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_2nd_pass_options
);
435 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
436 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
438 NIR_PASS(progress
, nir
, nir_copy_prop
);
439 NIR_PASS(progress
, nir
, nir_opt_dce
);
440 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
441 NIR_PASS(progress
, nir
, nir_opt_cse
);
442 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
443 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
444 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
446 if (lower_flrp
!= 0) {
447 bool lower_flrp_progress
= false;
448 NIR_PASS(lower_flrp_progress
,
452 false /* always_precise */,
453 nir
->options
->lower_ffma
);
454 if (lower_flrp_progress
) {
455 NIR_PASS(progress
, nir
,
456 nir_opt_constant_folding
);
460 /* Nothing should rematerialize any flrps, so we only
461 * need to do this lowering once.
466 NIR_PASS(progress
, nir
, nir_opt_undef
);
467 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
470 nir_var_function_temp
);
472 NIR_PASS(progress
, nir
, nir_opt_vectorize
);
475 /* Must be run at the end to prevent creation of fsin/fcos ops */
476 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
481 NIR_PASS(progress
, nir
, nir_opt_dce
);
482 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
483 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
484 NIR_PASS(progress
, nir
, nir_copy_prop
);
487 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
489 /* We implement booleans as 32-bit 0/~0 */
490 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
492 /* Now that booleans are lowered, we can run out late opts */
493 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
495 /* Lower mods for float ops only. Integer ops don't support modifiers
496 * (saturate doesn't make sense on integers, neg/abs require dedicated
499 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
500 NIR_PASS(progress
, nir
, nir_copy_prop
);
501 NIR_PASS(progress
, nir
, nir_opt_dce
);
503 /* Take us out of SSA */
504 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
505 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
507 /* We are a vector architecture; write combine where possible */
508 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
509 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
511 NIR_PASS(progress
, nir
, nir_opt_dce
);
514 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
515 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
516 * r0. See the comments in compiler_context */
519 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
521 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
522 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
525 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
528 unalias_ssa(compiler_context
*ctx
, int dest
)
530 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
531 /* TODO: Remove from leftover or no? */
534 /* Do not actually emit a load; instead, cache the constant for inlining */
537 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
539 nir_ssa_def def
= instr
->def
;
541 float *v
= rzalloc_array(NULL
, float, 4);
542 nir_const_load_to_arr(v
, instr
, f32
);
543 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
547 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
550 return src
->ssa
->index
;
552 assert(!src
->reg
.indirect
);
553 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
558 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
560 return nir_src_index(ctx
, &src
->src
);
564 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
566 unsigned comp
= src
->swizzle
[0];
568 for (unsigned c
= 1; c
< nr_components
; ++c
) {
569 if (src
->swizzle
[c
] != comp
)
576 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
577 * output of a conditional test) into that register */
580 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
582 int condition
= nir_src_index(ctx
, src
);
584 /* Source to swizzle the desired component into w */
586 const midgard_vector_alu_src alu_src
= {
587 .swizzle
= SWIZZLE(component
, component
, component
, component
),
590 /* There is no boolean move instruction. Instead, we simulate a move by
591 * ANDing the condition with itself to get it into r31.w */
593 midgard_instruction ins
= {
596 /* We need to set the conditional as close as possible */
597 .precede_break
= true,
598 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
603 .dest
= SSA_FIXED_REGISTER(31),
607 .op
= midgard_alu_op_iand
,
608 .outmod
= midgard_outmod_int_wrap
,
609 .reg_mode
= midgard_reg_mode_32
,
610 .dest_override
= midgard_dest_override_none
,
611 .mask
= (0x3 << 6), /* w */
612 .src1
= vector_alu_srco_unsigned(alu_src
),
613 .src2
= vector_alu_srco_unsigned(alu_src
)
617 emit_mir_instruction(ctx
, ins
);
620 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
624 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
626 int condition
= nir_src_index(ctx
, &src
->src
);
628 /* Source to swizzle the desired component into w */
630 const midgard_vector_alu_src alu_src
= {
631 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
634 /* There is no boolean move instruction. Instead, we simulate a move by
635 * ANDing the condition with itself to get it into r31.w */
637 midgard_instruction ins
= {
639 .precede_break
= true,
643 .dest
= SSA_FIXED_REGISTER(31),
646 .op
= midgard_alu_op_iand
,
647 .outmod
= midgard_outmod_int_wrap
,
648 .reg_mode
= midgard_reg_mode_32
,
649 .dest_override
= midgard_dest_override_none
,
650 .mask
= expand_writemask(mask_of(nr_comp
)),
651 .src1
= vector_alu_srco_unsigned(alu_src
),
652 .src2
= vector_alu_srco_unsigned(alu_src
)
656 emit_mir_instruction(ctx
, ins
);
661 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
662 * pinning to eliminate this move in all known cases */
665 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
667 int offset
= nir_src_index(ctx
, src
);
669 midgard_instruction ins
= {
672 .src0
= SSA_UNUSED_1
,
674 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
677 .op
= midgard_alu_op_imov
,
678 .outmod
= midgard_outmod_int_wrap
,
679 .reg_mode
= midgard_reg_mode_32
,
680 .dest_override
= midgard_dest_override_none
,
681 .mask
= (0x3 << 6), /* w */
682 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
683 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
687 emit_mir_instruction(ctx
, ins
);
690 #define ALU_CASE(nir, _op) \
692 op = midgard_alu_op_##_op; \
695 #define ALU_CASE_BCAST(nir, _op, count) \
697 op = midgard_alu_op_##_op; \
698 broadcast_swizzle = count; \
701 nir_is_fzero_constant(nir_src src
)
703 if (!nir_src_is_const(src
))
706 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
707 if (nir_src_comp_as_float(src
, c
) != 0.0)
714 /* Analyze the sizes of the inputs to determine which reg mode. Ops needed
715 * special treatment override this anyway. */
717 static midgard_reg_mode
718 reg_mode_for_nir(nir_alu_instr
*instr
)
720 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
722 switch (src_bitsize
) {
724 return midgard_reg_mode_8
;
726 return midgard_reg_mode_16
;
728 return midgard_reg_mode_32
;
730 return midgard_reg_mode_64
;
732 unreachable("Invalid bit size");
737 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
739 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
741 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
742 unsigned nr_components
= nir_dest_num_components(instr
->dest
.dest
);
743 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
745 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
746 * supported. A few do not and are commented for now. Also, there are a
747 * number of NIR ops which Midgard does not support and need to be
748 * lowered, also TODO. This switch block emits the opcode and calling
749 * convention of the Midgard instruction; actual packing is done in
754 /* Number of components valid to check for the instruction (the rest
755 * will be forced to the last), or 0 to use as-is. Relevant as
756 * ball-type instructions have a channel count in NIR but are all vec4
759 unsigned broadcast_swizzle
= 0;
761 /* What register mode should we operate in? */
762 midgard_reg_mode reg_mode
=
763 reg_mode_for_nir(instr
);
765 /* Do we need a destination override? Used for inline
768 midgard_dest_override dest_override
=
769 midgard_dest_override_none
;
771 /* Should we use a smaller respective source and sign-extend? */
773 bool half_1
= false, sext_1
= false;
774 bool half_2
= false, sext_2
= false;
777 ALU_CASE(fadd
, fadd
);
778 ALU_CASE(fmul
, fmul
);
779 ALU_CASE(fmin
, fmin
);
780 ALU_CASE(fmax
, fmax
);
781 ALU_CASE(imin
, imin
);
782 ALU_CASE(imax
, imax
);
783 ALU_CASE(umin
, umin
);
784 ALU_CASE(umax
, umax
);
785 ALU_CASE(ffloor
, ffloor
);
786 ALU_CASE(fround_even
, froundeven
);
787 ALU_CASE(ftrunc
, ftrunc
);
788 ALU_CASE(fceil
, fceil
);
789 ALU_CASE(fdot3
, fdot3
);
790 ALU_CASE(fdot4
, fdot4
);
791 ALU_CASE(iadd
, iadd
);
792 ALU_CASE(isub
, isub
);
793 ALU_CASE(imul
, imul
);
795 /* Zero shoved as second-arg */
796 ALU_CASE(iabs
, iabsdiff
);
800 ALU_CASE(feq32
, feq
);
801 ALU_CASE(fne32
, fne
);
802 ALU_CASE(flt32
, flt
);
803 ALU_CASE(ieq32
, ieq
);
804 ALU_CASE(ine32
, ine
);
805 ALU_CASE(ilt32
, ilt
);
806 ALU_CASE(ult32
, ult
);
808 /* We don't have a native b2f32 instruction. Instead, like many
809 * GPUs, we exploit booleans as 0/~0 for false/true, and
810 * correspondingly AND
811 * by 1.0 to do the type conversion. For the moment, prime us
814 * iand [whatever], #0
816 * At the end of emit_alu (as MIR), we'll fix-up the constant
819 ALU_CASE(b2f32
, iand
);
820 ALU_CASE(b2i32
, iand
);
822 /* Likewise, we don't have a dedicated f2b32 instruction, but
823 * we can do a "not equal to 0.0" test. */
825 ALU_CASE(f2b32
, fne
);
826 ALU_CASE(i2b32
, ine
);
828 ALU_CASE(frcp
, frcp
);
829 ALU_CASE(frsq
, frsqrt
);
830 ALU_CASE(fsqrt
, fsqrt
);
831 ALU_CASE(fexp2
, fexp2
);
832 ALU_CASE(flog2
, flog2
);
834 ALU_CASE(f2i32
, f2i_rtz
);
835 ALU_CASE(f2u32
, f2u_rtz
);
836 ALU_CASE(i2f32
, i2f_rtz
);
837 ALU_CASE(u2f32
, u2f_rtz
);
839 ALU_CASE(fsin
, fsin
);
840 ALU_CASE(fcos
, fcos
);
842 /* Second op implicit #0 */
843 ALU_CASE(inot
, inor
);
844 ALU_CASE(iand
, iand
);
846 ALU_CASE(ixor
, ixor
);
847 ALU_CASE(ishl
, ishl
);
848 ALU_CASE(ishr
, iasr
);
849 ALU_CASE(ushr
, ilsr
);
851 ALU_CASE_BCAST(b32all_fequal2
, fball_eq
, 2);
852 ALU_CASE_BCAST(b32all_fequal3
, fball_eq
, 3);
853 ALU_CASE(b32all_fequal4
, fball_eq
);
855 ALU_CASE_BCAST(b32any_fnequal2
, fbany_neq
, 2);
856 ALU_CASE_BCAST(b32any_fnequal3
, fbany_neq
, 3);
857 ALU_CASE(b32any_fnequal4
, fbany_neq
);
859 ALU_CASE_BCAST(b32all_iequal2
, iball_eq
, 2);
860 ALU_CASE_BCAST(b32all_iequal3
, iball_eq
, 3);
861 ALU_CASE(b32all_iequal4
, iball_eq
);
863 ALU_CASE_BCAST(b32any_inequal2
, ibany_neq
, 2);
864 ALU_CASE_BCAST(b32any_inequal3
, ibany_neq
, 3);
865 ALU_CASE(b32any_inequal4
, ibany_neq
);
867 /* Source mods will be shoved in later */
868 ALU_CASE(fabs
, fmov
);
869 ALU_CASE(fneg
, fmov
);
870 ALU_CASE(fsat
, fmov
);
872 /* For size conversion, we use a move. Ideally though we would squash
873 * these ops together; maybe that has to happen after in NIR as part of
874 * propagation...? An earlier algebraic pass ensured we step down by
875 * only / exactly one size. If stepping down, we use a dest override to
876 * reduce the size; if stepping up, we use a larger-sized move with a
877 * half source and a sign/zero-extension modifier */
882 /* If we end up upscale, we'll need a sign-extend on the
883 * operand (the second argument) */
889 op
= midgard_alu_op_imov
;
891 unsigned src_bitsize
= nir_src_bit_size(instr
->src
[0].src
);
892 unsigned dst_bitsize
= nir_dest_bit_size(instr
->dest
.dest
);
895 if (dst_bitsize
== (src_bitsize
* 2)) {
899 /* Use a greater register mode */
901 } else if (src_bitsize
== (dst_bitsize
* 2)) {
902 /* Converting down */
903 dest_override
= midgard_dest_override_lower
;
909 /* For greater-or-equal, we lower to less-or-equal and flip the
917 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
918 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
919 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
920 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
923 /* Swap via temporary */
924 nir_alu_src temp
= instr
->src
[1];
925 instr
->src
[1] = instr
->src
[0];
926 instr
->src
[0] = temp
;
931 case nir_op_b32csel
: {
932 /* Midgard features both fcsel and icsel, depending on
933 * the type of the arguments/output. However, as long
934 * as we're careful we can _always_ use icsel and
935 * _never_ need fcsel, since the latter does additional
936 * floating-point-specific processing whereas the
937 * former just moves bits on the wire. It's not obvious
938 * why these are separate opcodes, save for the ability
939 * to do things like sat/pos/abs/neg for free */
941 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
942 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
944 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
947 /* Emit the condition into r31 */
950 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
952 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
954 /* The condition is the first argument; move the other
955 * arguments up one to be a binary instruction for
958 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
963 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
968 /* Midgard can perform certain modifiers on output of an ALU op */
971 if (midgard_is_integer_out_op(op
)) {
972 outmod
= midgard_outmod_int_wrap
;
974 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
975 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
978 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
980 if (instr
->op
== nir_op_fmax
) {
981 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
982 op
= midgard_alu_op_fmov
;
984 outmod
= midgard_outmod_pos
;
985 instr
->src
[0] = instr
->src
[1];
986 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
987 op
= midgard_alu_op_fmov
;
989 outmod
= midgard_outmod_pos
;
993 /* Fetch unit, quirks, etc information */
994 unsigned opcode_props
= alu_opcode_props
[op
].props
;
995 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
997 /* src0 will always exist afaik, but src1 will not for 1-argument
998 * instructions. The latter can only be fetched if the instruction
999 * needs it, or else we may segfault. */
1001 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
1002 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
1004 /* Rather than use the instruction generation helpers, we do it
1005 * ourselves here to avoid the mess */
1007 midgard_instruction ins
= {
1010 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
1011 .src1
= quirk_flipped_r24
? src0
: src1
,
1016 nir_alu_src
*nirmods
[2] = { NULL
};
1018 if (nr_inputs
== 2) {
1019 nirmods
[0] = &instr
->src
[0];
1020 nirmods
[1] = &instr
->src
[1];
1021 } else if (nr_inputs
== 1) {
1022 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
1027 /* These were lowered to a move, so apply the corresponding mod */
1029 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
1030 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
1032 if (instr
->op
== nir_op_fneg
)
1033 s
->negate
= !s
->negate
;
1035 if (instr
->op
== nir_op_fabs
)
1039 bool is_int
= midgard_is_integer_op(op
);
1041 midgard_vector_alu alu
= {
1043 .reg_mode
= reg_mode
,
1044 .dest_override
= dest_override
,
1047 /* Writemask only valid for non-SSA NIR */
1048 .mask
= expand_writemask(mask_of(nr_components
)),
1050 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, sext_1
)),
1051 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
, broadcast_swizzle
, half_2
, sext_2
)),
1054 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
1057 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
1061 /* Late fixup for emulated instructions */
1063 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
1064 /* Presently, our second argument is an inline #0 constant.
1065 * Switch over to an embedded 1.0 constant (that can't fit
1066 * inline, since we're 32-bit, not 16-bit like the inline
1069 ins
.ssa_args
.inline_constant
= false;
1070 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1071 ins
.has_constants
= true;
1073 if (instr
->op
== nir_op_b2f32
) {
1074 ins
.constants
[0] = 1.0f
;
1076 /* Type pun it into place */
1078 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
1081 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1082 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
1083 /* Lots of instructions need a 0 plonked in */
1084 ins
.ssa_args
.inline_constant
= false;
1085 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1086 ins
.has_constants
= true;
1087 ins
.constants
[0] = 0.0f
;
1088 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
1089 } else if (instr
->op
== nir_op_inot
) {
1090 /* ~b = ~(b & b), so duplicate the source */
1091 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
1092 ins
.alu
.src2
= ins
.alu
.src1
;
1095 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
1096 /* To avoid duplicating the lookup tables (probably), true LUT
1097 * instructions can only operate as if they were scalars. Lower
1098 * them here by changing the component. */
1100 uint8_t original_swizzle
[4];
1101 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
1103 for (int i
= 0; i
< nr_components
; ++i
) {
1104 /* Mask the associated component, dropping the
1105 * instruction if needed */
1107 ins
.alu
.mask
= (0x3) << (2 * i
);
1108 ins
.alu
.mask
&= alu
.mask
;
1113 for (int j
= 0; j
< 4; ++j
)
1114 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1116 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
, broadcast_swizzle
, half_1
, false));
1117 emit_mir_instruction(ctx
, ins
);
1120 emit_mir_instruction(ctx
, ins
);
1126 /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly
1127 * optimized) versions of UBO #0 */
1131 compiler_context
*ctx
,
1134 nir_src
*indirect_offset
,
1137 /* TODO: half-floats */
1139 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
&& index
== 0) {
1140 /* Fast path: For the first 16 uniforms, direct accesses are
1141 * 0-cycle, since they're just a register fetch in the usual
1142 * case. So, we alias the registers while we're still in
1145 int reg_slot
= 23 - offset
;
1146 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1148 /* Otherwise, read from the 'special' UBO to access
1149 * higher-indexed uniforms, at a performance cost. More
1150 * generally, we're emitting a UBO read instruction. */
1152 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1154 /* TODO: Don't split */
1155 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1156 ins
.load_store
.address
= offset
>> 3;
1158 if (indirect_offset
) {
1159 emit_indirect_offset(ctx
, indirect_offset
);
1160 ins
.load_store
.unknown
= 0x8700 | index
; /* xxx: what is this? */
1162 ins
.load_store
.unknown
= 0x1E00 | index
; /* xxx: what is this? */
1165 /* TODO respect index */
1167 emit_mir_instruction(ctx
, ins
);
1173 compiler_context
*ctx
,
1174 unsigned dest
, unsigned offset
,
1175 unsigned nr_comp
, unsigned component
,
1176 nir_src
*indirect_offset
, nir_alu_type type
)
1178 /* XXX: Half-floats? */
1179 /* TODO: swizzle, mask */
1181 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1182 ins
.load_store
.mask
= mask_of(nr_comp
);
1183 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1185 midgard_varying_parameter p
= {
1187 .interpolation
= midgard_interp_default
,
1188 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1192 memcpy(&u
, &p
, sizeof(p
));
1193 ins
.load_store
.varying_parameters
= u
;
1195 if (indirect_offset
) {
1196 /* We need to add in the dynamic index, moved to r27.w */
1197 emit_indirect_offset(ctx
, indirect_offset
);
1198 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1200 /* Just a direct load */
1201 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1204 /* Use the type appropriate load */
1208 ins
.load_store
.op
= midgard_op_ld_vary_32u
;
1211 ins
.load_store
.op
= midgard_op_ld_vary_32i
;
1213 case nir_type_float
:
1214 ins
.load_store
.op
= midgard_op_ld_vary_32
;
1217 unreachable("Attempted to load unknown type");
1221 emit_mir_instruction(ctx
, ins
);
1225 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
)
1228 /* Figure out which uniform this is */
1229 int sysval
= sysval_for_instr(ctx
, instr
, &dest
);
1230 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1232 /* Sysvals are prefix uniforms */
1233 unsigned uniform
= ((uintptr_t) val
) - 1;
1235 /* Emit the read itself -- this is never indirect */
1236 emit_ubo_read(ctx
, dest
, uniform
, NULL
, 0);
1239 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1240 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1241 * generations have faster vectorized reads. This operation is for blend
1242 * shaders in particular; reading the tilebuffer from the fragment shader
1243 * remains an open problem. */
1246 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1248 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1249 ins
.load_store
.swizzle
= 0; /* xxxx */
1251 /* Read each component sequentially */
1253 for (unsigned c
= 0; c
< 4; ++c
) {
1254 ins
.load_store
.mask
= (1 << c
);
1255 ins
.load_store
.unknown
= c
;
1256 emit_mir_instruction(ctx
, ins
);
1259 /* vadd.u2f hr2, zext(hr2), #0 */
1261 midgard_vector_alu_src alu_src
= blank_alu_src
;
1262 alu_src
.mod
= midgard_int_zero_extend
;
1263 alu_src
.half
= true;
1265 midgard_instruction u2f
= {
1269 .src1
= SSA_UNUSED_0
,
1271 .inline_constant
= true
1274 .op
= midgard_alu_op_u2f_rtz
,
1275 .reg_mode
= midgard_reg_mode_16
,
1276 .dest_override
= midgard_dest_override_none
,
1278 .src1
= vector_alu_srco_unsigned(alu_src
),
1279 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1283 emit_mir_instruction(ctx
, u2f
);
1285 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1289 midgard_instruction fmul
= {
1291 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1295 .src1
= SSA_UNUSED_0
,
1296 .inline_constant
= true
1299 .op
= midgard_alu_op_fmul
,
1300 .reg_mode
= midgard_reg_mode_32
,
1301 .dest_override
= midgard_dest_override_none
,
1302 .outmod
= midgard_outmod_sat
,
1304 .src1
= vector_alu_srco_unsigned(alu_src
),
1305 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1309 emit_mir_instruction(ctx
, fmul
);
1313 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1315 unsigned offset
= 0, reg
;
1317 switch (instr
->intrinsic
) {
1318 case nir_intrinsic_discard_if
:
1319 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1323 case nir_intrinsic_discard
: {
1324 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1325 struct midgard_instruction discard
= v_branch(conditional
, false);
1326 discard
.branch
.target_type
= TARGET_DISCARD
;
1327 emit_mir_instruction(ctx
, discard
);
1329 ctx
->can_discard
= true;
1333 case nir_intrinsic_load_uniform
:
1334 case nir_intrinsic_load_ubo
:
1335 case nir_intrinsic_load_input
: {
1336 bool is_uniform
= instr
->intrinsic
== nir_intrinsic_load_uniform
;
1337 bool is_ubo
= instr
->intrinsic
== nir_intrinsic_load_ubo
;
1339 /* Get the base type of the intrinsic */
1340 /* TODO: Infer type? Does it matter? */
1342 is_ubo
? nir_type_uint
: nir_intrinsic_type(instr
);
1343 t
= nir_alu_type_get_base_type(t
);
1346 offset
= nir_intrinsic_base(instr
);
1349 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1351 nir_src
*src_offset
= nir_get_io_offset_src(instr
);
1353 bool direct
= nir_src_is_const(*src_offset
);
1356 offset
+= nir_src_as_uint(*src_offset
);
1358 /* We may need to apply a fractional offset */
1359 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1360 nir_intrinsic_component(instr
) : 0;
1361 reg
= nir_dest_index(ctx
, &instr
->dest
);
1363 if (is_uniform
&& !ctx
->is_blend
) {
1364 emit_ubo_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
, 0);
1365 } else if (is_ubo
) {
1366 nir_src index
= instr
->src
[0];
1368 /* We don't yet support indirect UBOs. For indirect
1369 * block numbers (if that's possible), we don't know
1370 * enough about the hardware yet. For indirect sources,
1371 * we know what we need but we need to add some NIR
1372 * support for lowering correctly with respect to
1375 assert(nir_src_is_const(index
));
1376 assert(nir_src_is_const(*src_offset
));
1378 /* TODO: Alignment */
1379 assert((offset
& 0xF) == 0);
1381 uint32_t uindex
= nir_src_as_uint(index
) + 1;
1382 emit_ubo_read(ctx
, reg
, offset
/ 16, NULL
, uindex
);
1383 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1384 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
, t
);
1385 } else if (ctx
->is_blend
) {
1386 /* For blend shaders, load the input color, which is
1387 * preloaded to r0 */
1389 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1390 emit_mir_instruction(ctx
, move
);
1391 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1392 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1393 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1394 ins
.load_store
.mask
= mask_of(nr_comp
);
1396 /* Use the type appropriate load */
1400 ins
.load_store
.op
= midgard_op_ld_attr_32u
;
1403 ins
.load_store
.op
= midgard_op_ld_attr_32i
;
1405 case nir_type_float
:
1406 ins
.load_store
.op
= midgard_op_ld_attr_32
;
1409 unreachable("Attempted to load unknown type");
1413 emit_mir_instruction(ctx
, ins
);
1415 DBG("Unknown load\n");
1422 /* Reads off the tilebuffer during blending, tasty */
1423 case nir_intrinsic_load_raw_output_pan
:
1424 reg
= nir_dest_index(ctx
, &instr
->dest
);
1425 assert(ctx
->is_blend
);
1426 emit_fb_read_blend_scalar(ctx
, reg
);
1429 case nir_intrinsic_load_blend_const_color_rgba
: {
1430 assert(ctx
->is_blend
);
1431 reg
= nir_dest_index(ctx
, &instr
->dest
);
1433 /* Blend constants are embedded directly in the shader and
1434 * patched in, so we use some magic routing */
1436 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1437 ins
.has_constants
= true;
1438 ins
.has_blend_constant
= true;
1439 emit_mir_instruction(ctx
, ins
);
1443 case nir_intrinsic_store_output
:
1444 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1446 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1448 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1450 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1451 /* gl_FragColor is not emitted with load/store
1452 * instructions. Instead, it gets plonked into
1453 * r0 at the end of the shader and we do the
1454 * framebuffer writeout dance. TODO: Defer
1457 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1458 emit_mir_instruction(ctx
, move
);
1460 /* Save the index we're writing to for later reference
1461 * in the epilogue */
1463 ctx
->fragment_output
= reg
;
1464 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1465 /* Varyings are written into one of two special
1466 * varying register, r26 or r27. The register itself is
1467 * selected as the register in the st_vary instruction,
1468 * minus the base of 26. E.g. write into r27 and then
1469 * call st_vary(1) */
1471 midgard_instruction ins
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1472 emit_mir_instruction(ctx
, ins
);
1474 /* We should have been vectorized, though we don't
1475 * currently check that st_vary is emitted only once
1476 * per slot (this is relevant, since there's not a mask
1477 * parameter available on the store [set to 0 by the
1478 * blob]). We do respect the component by adjusting the
1481 unsigned component
= nir_intrinsic_component(instr
);
1483 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1484 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1485 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1486 emit_mir_instruction(ctx
, st
);
1488 DBG("Unknown store\n");
1494 /* Special case of store_output for lowered blend shaders */
1495 case nir_intrinsic_store_raw_output_pan
:
1496 assert (ctx
->stage
== MESA_SHADER_FRAGMENT
);
1497 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1499 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1500 emit_mir_instruction(ctx
, move
);
1501 ctx
->fragment_output
= reg
;
1505 case nir_intrinsic_load_alpha_ref_float
:
1506 assert(instr
->dest
.is_ssa
);
1508 float ref_value
= ctx
->alpha_ref
;
1510 float *v
= ralloc_array(NULL
, float, 4);
1511 memcpy(v
, &ref_value
, sizeof(float));
1512 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1515 case nir_intrinsic_load_viewport_scale
:
1516 case nir_intrinsic_load_viewport_offset
:
1517 emit_sysval_read(ctx
, &instr
->instr
);
1521 printf ("Unhandled intrinsic\n");
1528 midgard_tex_format(enum glsl_sampler_dim dim
)
1531 case GLSL_SAMPLER_DIM_1D
:
1532 case GLSL_SAMPLER_DIM_BUF
:
1535 case GLSL_SAMPLER_DIM_2D
:
1536 case GLSL_SAMPLER_DIM_EXTERNAL
:
1539 case GLSL_SAMPLER_DIM_3D
:
1542 case GLSL_SAMPLER_DIM_CUBE
:
1543 return MALI_TEX_CUBE
;
1546 DBG("Unknown sampler dim type\n");
1552 /* Tries to attach an explicit LOD / bias as a constant. Returns whether this
1556 pan_attach_constant_bias(
1557 compiler_context
*ctx
,
1559 midgard_texture_word
*word
)
1561 /* To attach as constant, it has to *be* constant */
1563 if (!nir_src_is_const(lod
))
1566 float f
= nir_src_as_float(lod
);
1568 /* Break into fixed-point */
1570 float lod_frac
= f
- lod_int
;
1572 /* Carry over negative fractions */
1573 if (lod_frac
< 0.0) {
1579 word
->bias
= float_to_ubyte(lod_frac
);
1580 word
->bias_int
= lod_int
;
1585 static enum mali_sampler_type
1586 midgard_sampler_type(nir_alu_type t
)
1588 switch (nir_alu_type_get_base_type(t
)) {
1589 case nir_type_float
:
1590 return MALI_SAMPLER_FLOAT
;
1592 return MALI_SAMPLER_SIGNED
;
1594 return MALI_SAMPLER_UNSIGNED
;
1596 unreachable("Unknown sampler type");
1601 emit_texop_native(compiler_context
*ctx
, nir_tex_instr
*instr
,
1602 unsigned midgard_texop
)
1605 //assert (!instr->sampler);
1606 //assert (!instr->texture_array_size);
1608 /* Allocate registers via a round robin scheme to alternate between the two registers */
1609 int reg
= ctx
->texture_op_count
& 1;
1610 int in_reg
= reg
, out_reg
= reg
;
1612 /* Make room for the reg */
1614 if (ctx
->texture_index
[reg
] > -1)
1615 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1617 int texture_index
= instr
->texture_index
;
1618 int sampler_index
= texture_index
;
1620 /* No helper to build texture words -- we do it all here */
1621 midgard_instruction ins
= {
1622 .type
= TAG_TEXTURE_4
,
1624 .op
= midgard_texop
,
1625 .format
= midgard_tex_format(instr
->sampler_dim
),
1626 .texture_handle
= texture_index
,
1627 .sampler_handle
= sampler_index
,
1629 /* TODO: Regalloc it in */
1630 .swizzle
= SWIZZLE_XYZW
,
1637 .sampler_type
= midgard_sampler_type(instr
->dest_type
),
1641 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1642 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1643 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1644 int nr_comp
= nir_src_num_components(instr
->src
[i
].src
);
1645 midgard_vector_alu_src alu_src
= blank_alu_src
;
1647 switch (instr
->src
[i
].src_type
) {
1648 case nir_tex_src_coord
: {
1649 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1650 /* texelFetch is undefined on samplerCube */
1651 assert(midgard_texop
!= TEXTURE_OP_TEXEL_FETCH
);
1653 /* For cubemaps, we need to load coords into
1654 * special r27, and then use a special ld/st op
1655 * to select the face and copy the xy into the
1656 * texture register */
1658 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1660 midgard_instruction move
= v_mov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1661 emit_mir_instruction(ctx
, move
);
1663 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1664 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1665 st
.load_store
.mask
= 0x3; /* xy */
1666 st
.load_store
.swizzle
= alu_src
.swizzle
;
1667 emit_mir_instruction(ctx
, st
);
1669 ins
.texture
.in_reg_swizzle
= swizzle_of(2);
1671 ins
.texture
.in_reg_swizzle
= alu_src
.swizzle
= swizzle_of(nr_comp
);
1673 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1674 mov
.alu
.mask
= expand_writemask(mask_of(nr_comp
));
1675 emit_mir_instruction(ctx
, mov
);
1677 if (midgard_texop
== TEXTURE_OP_TEXEL_FETCH
) {
1678 /* Texel fetch opcodes care about the
1679 * values of z and w, so we actually
1680 * need to spill into a second register
1681 * for a texel fetch with register bias
1682 * (for non-2D). TODO: Implement that
1685 assert(instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
);
1687 midgard_instruction zero
= v_mov(index
, alu_src
, reg
);
1688 zero
.ssa_args
.inline_constant
= true;
1689 zero
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1690 zero
.has_constants
= true;
1691 zero
.alu
.mask
= ~mov
.alu
.mask
;
1692 emit_mir_instruction(ctx
, zero
);
1694 ins
.texture
.in_reg_swizzle
= SWIZZLE_XYZZ
;
1696 /* Non-texel fetch doesn't need that
1697 * nonsense. However we do use the Z
1698 * for array indexing */
1699 bool is_3d
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_3D
;
1700 ins
.texture
.in_reg_swizzle
= is_3d
? SWIZZLE_XYZZ
: SWIZZLE_XYXZ
;
1707 case nir_tex_src_bias
:
1708 case nir_tex_src_lod
: {
1709 /* Try as a constant if we can */
1711 bool is_txf
= midgard_texop
== TEXTURE_OP_TEXEL_FETCH
;
1712 if (!is_txf
&& pan_attach_constant_bias(ctx
, instr
->src
[i
].src
, &ins
.texture
))
1715 /* Otherwise we use a register. To keep RA simple, we
1716 * put the bias/LOD into the w component of the input
1717 * source, which is otherwise in xy */
1719 alu_src
.swizzle
= SWIZZLE_XXXX
;
1721 midgard_instruction mov
= v_mov(index
, alu_src
, reg
);
1722 mov
.alu
.mask
= expand_writemask(1 << COMPONENT_W
);
1723 emit_mir_instruction(ctx
, mov
);
1725 ins
.texture
.lod_register
= true;
1727 midgard_tex_register_select sel
= {
1737 memcpy(&packed
, &sel
, sizeof(packed
));
1738 ins
.texture
.bias
= packed
;
1744 unreachable("Unknown texture source type\n");
1748 /* Set registers to read and write from the same place */
1749 ins
.texture
.in_reg_select
= in_reg
;
1750 ins
.texture
.out_reg_select
= out_reg
;
1752 emit_mir_instruction(ctx
, ins
);
1754 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1756 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1757 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1758 ctx
->texture_index
[reg
] = o_index
;
1760 midgard_instruction ins2
= v_mov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1761 emit_mir_instruction(ctx
, ins2
);
1763 /* Used for .cont and .last hinting */
1764 ctx
->texture_op_count
++;
1768 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1770 /* Fixup op, since only textureLod is permitted in VS but NIR can give
1771 * generic tex in some cases (which confuses the hardware) */
1773 bool is_vertex
= ctx
->stage
== MESA_SHADER_VERTEX
;
1775 if (is_vertex
&& instr
->op
== nir_texop_tex
)
1776 instr
->op
= nir_texop_txl
;
1778 switch (instr
->op
) {
1781 emit_texop_native(ctx
, instr
, TEXTURE_OP_NORMAL
);
1784 emit_texop_native(ctx
, instr
, TEXTURE_OP_LOD
);
1787 emit_texop_native(ctx
, instr
, TEXTURE_OP_TEXEL_FETCH
);
1790 emit_sysval_read(ctx
, &instr
->instr
);
1793 unreachable("Unhanlded texture op");
1798 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1800 switch (instr
->type
) {
1801 case nir_jump_break
: {
1802 /* Emit a branch out of the loop */
1803 struct midgard_instruction br
= v_branch(false, false);
1804 br
.branch
.target_type
= TARGET_BREAK
;
1805 br
.branch
.target_break
= ctx
->current_loop_depth
;
1806 emit_mir_instruction(ctx
, br
);
1813 DBG("Unknown jump type %d\n", instr
->type
);
1819 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1821 switch (instr
->type
) {
1822 case nir_instr_type_load_const
:
1823 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1826 case nir_instr_type_intrinsic
:
1827 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1830 case nir_instr_type_alu
:
1831 emit_alu(ctx
, nir_instr_as_alu(instr
));
1834 case nir_instr_type_tex
:
1835 emit_tex(ctx
, nir_instr_as_tex(instr
));
1838 case nir_instr_type_jump
:
1839 emit_jump(ctx
, nir_instr_as_jump(instr
));
1842 case nir_instr_type_ssa_undef
:
1847 DBG("Unhandled instruction type\n");
1853 /* ALU instructions can inline or embed constants, which decreases register
1854 * pressure and saves space. */
1856 #define CONDITIONAL_ATTACH(src) { \
1857 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1860 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1861 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1866 inline_alu_constants(compiler_context
*ctx
)
1868 mir_foreach_instr(ctx
, alu
) {
1869 /* Other instructions cannot inline constants */
1870 if (alu
->type
!= TAG_ALU_4
) continue;
1872 /* If there is already a constant here, we can do nothing */
1873 if (alu
->has_constants
) continue;
1875 /* It makes no sense to inline constants on a branch */
1876 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1878 CONDITIONAL_ATTACH(src0
);
1880 if (!alu
->has_constants
) {
1881 CONDITIONAL_ATTACH(src1
)
1882 } else if (!alu
->inline_constant
) {
1883 /* Corner case: _two_ vec4 constants, for instance with a
1884 * csel. For this case, we can only use a constant
1885 * register for one, we'll have to emit a move for the
1886 * other. Note, if both arguments are constants, then
1887 * necessarily neither argument depends on the value of
1888 * any particular register. As the destination register
1889 * will be wiped, that means we can spill the constant
1890 * to the destination register.
1893 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1894 unsigned scratch
= alu
->ssa_args
.dest
;
1897 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1898 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1900 /* Force a break XXX Defer r31 writes */
1901 ins
.unit
= UNIT_VLUT
;
1903 /* Set the source */
1904 alu
->ssa_args
.src1
= scratch
;
1906 /* Inject us -before- the last instruction which set r31 */
1907 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1913 /* Midgard supports two types of constants, embedded constants (128-bit) and
1914 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1915 * constants can be demoted to inline constants, for space savings and
1916 * sometimes a performance boost */
1919 embedded_to_inline_constant(compiler_context
*ctx
)
1921 mir_foreach_instr(ctx
, ins
) {
1922 if (!ins
->has_constants
) continue;
1924 if (ins
->ssa_args
.inline_constant
) continue;
1926 /* Blend constants must not be inlined by definition */
1927 if (ins
->has_blend_constant
) continue;
1929 /* src1 cannot be an inline constant due to encoding
1930 * restrictions. So, if possible we try to flip the arguments
1933 int op
= ins
->alu
.op
;
1935 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1937 /* These ops require an operational change to flip
1938 * their arguments TODO */
1939 case midgard_alu_op_flt
:
1940 case midgard_alu_op_fle
:
1941 case midgard_alu_op_ilt
:
1942 case midgard_alu_op_ile
:
1943 case midgard_alu_op_fcsel
:
1944 case midgard_alu_op_icsel
:
1945 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1950 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1951 /* Flip the SSA numbers */
1952 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1953 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1955 /* And flip the modifiers */
1959 src_temp
= ins
->alu
.src2
;
1960 ins
->alu
.src2
= ins
->alu
.src1
;
1961 ins
->alu
.src1
= src_temp
;
1965 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1966 /* Extract the source information */
1968 midgard_vector_alu_src
*src
;
1969 int q
= ins
->alu
.src2
;
1970 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1973 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1974 int component
= src
->swizzle
& 3;
1976 /* Scale constant appropriately, if we can legally */
1977 uint16_t scaled_constant
= 0;
1979 if (midgard_is_integer_op(op
)) {
1980 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1981 scaled_constant
= (uint16_t) iconstants
[component
];
1983 /* Constant overflow after resize */
1984 if (scaled_constant
!= iconstants
[component
])
1987 float original
= (float) ins
->constants
[component
];
1988 scaled_constant
= _mesa_float_to_half(original
);
1990 /* Check for loss of precision. If this is
1991 * mediump, we don't care, but for a highp
1992 * shader, we need to pay attention. NIR
1993 * doesn't yet tell us which mode we're in!
1994 * Practically this prevents most constants
1995 * from being inlined, sadly. */
1997 float fp32
= _mesa_half_to_float(scaled_constant
);
1999 if (fp32
!= original
)
2003 /* We don't know how to handle these with a constant */
2005 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
2006 DBG("Bailing inline constant...\n");
2010 /* Make sure that the constant is not itself a
2011 * vector by checking if all accessed values
2012 * (by the swizzle) are the same. */
2014 uint32_t *cons
= (uint32_t *) ins
->constants
;
2015 uint32_t value
= cons
[component
];
2017 bool is_vector
= false;
2018 unsigned mask
= effective_writemask(&ins
->alu
);
2020 for (int c
= 1; c
< 4; ++c
) {
2021 /* We only care if this component is actually used */
2022 if (!(mask
& (1 << c
)))
2025 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
2027 if (test
!= value
) {
2036 /* Get rid of the embedded constant */
2037 ins
->has_constants
= false;
2038 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
2039 ins
->ssa_args
.inline_constant
= true;
2040 ins
->inline_constant
= scaled_constant
;
2045 /* Map normal SSA sources to other SSA sources / fixed registers (like
2049 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
2051 /* Sign is used quite deliberately for unused */
2055 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
2058 /* Remove entry in leftovers to avoid a redunant fmov */
2060 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
2063 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
2065 /* Assign the alias map */
2071 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
2072 * texture pipeline */
2075 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
2077 bool progress
= false;
2079 mir_foreach_instr_in_block_safe(block
, ins
) {
2080 if (ins
->type
!= TAG_ALU_4
) continue;
2081 if (ins
->compact_branch
) continue;
2083 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
2084 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
2086 mir_remove_instruction(ins
);
2093 /* Dead code elimination for branches at the end of a block - only one branch
2094 * per block is legal semantically */
2097 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
2099 bool branched
= false;
2101 mir_foreach_instr_in_block_safe(block
, ins
) {
2102 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2104 /* We ignore prepacked branches since the fragment epilogue is
2105 * just generally special */
2106 if (ins
->prepacked_branch
) continue;
2108 /* Discards are similarly special and may not correspond to the
2111 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
2114 /* We already branched, so this is dead */
2115 mir_remove_instruction(ins
);
2123 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
2126 if (!is_int
&& src
.mod
) return true;
2128 /* Other int mods don't matter in isolation */
2129 if (is_int
&& src
.mod
== midgard_int_shift
) return true;
2131 /* size-conversion */
2132 if (src
.half
) return true;
2135 for (unsigned c
= 0; c
< 4; ++c
) {
2136 if (!(mask
& (1 << c
))) continue;
2137 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
2144 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
2146 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
2147 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2149 midgard_vector_alu_src src2
=
2150 vector_alu_from_unsigned(ins
->alu
.src2
);
2152 return mir_nontrivial_mod(src2
, is_int
, mask
);
2156 mir_nontrivial_outmod(midgard_instruction
*ins
)
2158 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
2159 unsigned mod
= ins
->alu
.outmod
;
2161 /* Type conversion is a sort of outmod */
2162 if (ins
->alu
.dest_override
!= midgard_dest_override_none
)
2166 return mod
!= midgard_outmod_int_wrap
;
2168 return mod
!= midgard_outmod_none
;
2172 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
2174 bool progress
= false;
2176 mir_foreach_instr_in_block_safe(block
, ins
) {
2177 if (ins
->type
!= TAG_ALU_4
) continue;
2178 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2180 unsigned from
= ins
->ssa_args
.src1
;
2181 unsigned to
= ins
->ssa_args
.dest
;
2183 /* We only work on pure SSA */
2185 if (to
>= SSA_FIXED_MINIMUM
) continue;
2186 if (from
>= SSA_FIXED_MINIMUM
) continue;
2187 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
2188 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2190 /* Constant propagation is not handled here, either */
2191 if (ins
->ssa_args
.inline_constant
) continue;
2192 if (ins
->has_constants
) continue;
2194 if (mir_nontrivial_source2_mod(ins
)) continue;
2195 if (mir_nontrivial_outmod(ins
)) continue;
2197 /* We're clear -- rewrite */
2198 mir_rewrite_index_src(ctx
, to
, from
);
2199 mir_remove_instruction(ins
);
2206 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
2207 * the move can be propagated away entirely */
2210 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
2213 if (comp
== midgard_outmod_none
)
2216 if (*outmod
== midgard_outmod_none
) {
2221 /* TODO: Compose rules */
2226 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
2228 bool progress
= false;
2230 mir_foreach_instr_in_block_safe(block
, ins
) {
2231 if (ins
->type
!= TAG_ALU_4
) continue;
2232 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
2233 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
2235 /* TODO: Registers? */
2236 unsigned src
= ins
->ssa_args
.src1
;
2237 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
2238 assert(!mir_has_multiple_writes(ctx
, src
));
2240 /* There might be a source modifier, too */
2241 if (mir_nontrivial_source2_mod(ins
)) continue;
2243 /* Backpropagate the modifier */
2244 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2245 if (v
->type
!= TAG_ALU_4
) continue;
2246 if (v
->ssa_args
.dest
!= src
) continue;
2248 /* Can we even take a float outmod? */
2249 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
2251 midgard_outmod_float temp
= v
->alu
.outmod
;
2252 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
2254 /* Throw in the towel.. */
2255 if (!progress
) break;
2257 /* Otherwise, transfer the modifier */
2258 v
->alu
.outmod
= temp
;
2259 ins
->alu
.outmod
= midgard_outmod_none
;
2269 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
2271 bool progress
= false;
2273 mir_foreach_instr_in_block_safe(block
, ins
) {
2274 if (ins
->type
!= TAG_ALU_4
) continue;
2275 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
2277 unsigned from
= ins
->ssa_args
.src1
;
2278 unsigned to
= ins
->ssa_args
.dest
;
2280 /* Make sure it's simple enough for us to handle */
2282 if (from
>= SSA_FIXED_MINIMUM
) continue;
2283 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
2284 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
2285 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
2287 bool eliminated
= false;
2289 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
2290 /* The texture registers are not SSA so be careful.
2291 * Conservatively, just stop if we hit a texture op
2292 * (even if it may not write) to where we are */
2294 if (v
->type
!= TAG_ALU_4
)
2297 if (v
->ssa_args
.dest
== from
) {
2298 /* We don't want to track partial writes ... */
2299 if (v
->alu
.mask
== 0xF) {
2300 v
->ssa_args
.dest
= to
;
2309 mir_remove_instruction(ins
);
2311 progress
|= eliminated
;
2317 /* The following passes reorder MIR instructions to enable better scheduling */
2320 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2322 mir_foreach_instr_in_block_safe(block
, ins
) {
2323 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2325 /* We've found a load/store op. Check if next is also load/store. */
2326 midgard_instruction
*next_op
= mir_next_op(ins
);
2327 if (&next_op
->link
!= &block
->instructions
) {
2328 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2329 /* If so, we're done since we're a pair */
2330 ins
= mir_next_op(ins
);
2334 /* Maximum search distance to pair, to avoid register pressure disasters */
2335 int search_distance
= 8;
2337 /* Otherwise, we have an orphaned load/store -- search for another load */
2338 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2339 /* Terminate search if necessary */
2340 if (!(search_distance
--)) break;
2342 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2344 /* Stores cannot be reordered, since they have
2345 * dependencies. For the same reason, indirect
2346 * loads cannot be reordered as their index is
2347 * loaded in r27.w */
2349 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2351 /* It appears the 0x800 bit is set whenever a
2352 * load is direct, unset when it is indirect.
2353 * Skip indirect loads. */
2355 if (!(c
->load_store
.unknown
& 0x800)) continue;
2357 /* We found one! Move it up to pair and remove it from the old location */
2359 mir_insert_instruction_before(ins
, *c
);
2360 mir_remove_instruction(c
);
2368 /* If there are leftovers after the below pass, emit actual fmov
2369 * instructions for the slow-but-correct path */
2372 emit_leftover_move(compiler_context
*ctx
)
2374 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2375 int base
= ((uintptr_t) leftover
->key
) - 1;
2378 map_ssa_to_alias(ctx
, &mapped
);
2379 EMIT(mov
, mapped
, blank_alu_src
, base
);
2384 actualise_ssa_to_alias(compiler_context
*ctx
)
2386 mir_foreach_instr(ctx
, ins
) {
2387 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2388 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2391 emit_leftover_move(ctx
);
2395 emit_fragment_epilogue(compiler_context
*ctx
)
2397 /* Special case: writing out constants requires us to include the move
2398 * explicitly now, so shove it into r0 */
2400 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2402 if (constant_value
) {
2403 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2404 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2405 emit_mir_instruction(ctx
, ins
);
2408 /* Perform the actual fragment writeout. We have two writeout/branch
2409 * instructions, forming a loop until writeout is successful as per the
2410 * docs. TODO: gl_FragDepth */
2412 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2413 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2416 static midgard_block
*
2417 emit_block(compiler_context
*ctx
, nir_block
*block
)
2419 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2420 list_addtail(&this_block
->link
, &ctx
->blocks
);
2422 this_block
->is_scheduled
= false;
2425 ctx
->texture_index
[0] = -1;
2426 ctx
->texture_index
[1] = -1;
2428 /* Add us as a successor to the block we are following */
2429 if (ctx
->current_block
)
2430 midgard_block_add_successor(ctx
->current_block
, this_block
);
2432 /* Set up current block */
2433 list_inithead(&this_block
->instructions
);
2434 ctx
->current_block
= this_block
;
2436 nir_foreach_instr(instr
, block
) {
2437 emit_instr(ctx
, instr
);
2438 ++ctx
->instruction_count
;
2441 inline_alu_constants(ctx
);
2442 embedded_to_inline_constant(ctx
);
2444 /* Perform heavylifting for aliasing */
2445 actualise_ssa_to_alias(ctx
);
2447 midgard_pair_load_store(ctx
, this_block
);
2449 /* Append fragment shader epilogue (value writeout) */
2450 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2451 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2452 emit_fragment_epilogue(ctx
);
2456 if (block
== nir_start_block(ctx
->func
->impl
))
2457 ctx
->initial_block
= this_block
;
2459 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2460 ctx
->final_block
= this_block
;
2462 /* Allow the next control flow to access us retroactively, for
2464 ctx
->current_block
= this_block
;
2466 /* Document the fallthrough chain */
2467 ctx
->previous_source_block
= this_block
;
2472 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2475 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2477 /* Conditional branches expect the condition in r31.w; emit a move for
2478 * that in the _previous_ block (which is the current block). */
2479 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2481 /* Speculatively emit the branch, but we can't fill it in until later */
2482 EMIT(branch
, true, true);
2483 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2485 /* Emit the two subblocks */
2486 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2488 /* Emit a jump from the end of the then block to the end of the else */
2489 EMIT(branch
, false, false);
2490 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2492 /* Emit second block, and check if it's empty */
2494 int else_idx
= ctx
->block_count
;
2495 int count_in
= ctx
->instruction_count
;
2496 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2497 int after_else_idx
= ctx
->block_count
;
2499 /* Now that we have the subblocks emitted, fix up the branches */
2504 if (ctx
->instruction_count
== count_in
) {
2505 /* The else block is empty, so don't emit an exit jump */
2506 mir_remove_instruction(then_exit
);
2507 then_branch
->branch
.target_block
= after_else_idx
;
2509 then_branch
->branch
.target_block
= else_idx
;
2510 then_exit
->branch
.target_block
= after_else_idx
;
2515 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2517 /* Remember where we are */
2518 midgard_block
*start_block
= ctx
->current_block
;
2520 /* Allocate a loop number, growing the current inner loop depth */
2521 int loop_idx
= ++ctx
->current_loop_depth
;
2523 /* Get index from before the body so we can loop back later */
2524 int start_idx
= ctx
->block_count
;
2526 /* Emit the body itself */
2527 emit_cf_list(ctx
, &nloop
->body
);
2529 /* Branch back to loop back */
2530 struct midgard_instruction br_back
= v_branch(false, false);
2531 br_back
.branch
.target_block
= start_idx
;
2532 emit_mir_instruction(ctx
, br_back
);
2534 /* Mark down that branch in the graph. Note that we're really branching
2535 * to the block *after* we started in. TODO: Why doesn't the branch
2536 * itself have an off-by-one then...? */
2537 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2539 /* Find the index of the block about to follow us (note: we don't add
2540 * one; blocks are 0-indexed so we get a fencepost problem) */
2541 int break_block_idx
= ctx
->block_count
;
2543 /* Fix up the break statements we emitted to point to the right place,
2544 * now that we can allocate a block number for them */
2546 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2547 mir_foreach_instr_in_block(block
, ins
) {
2548 if (ins
->type
!= TAG_ALU_4
) continue;
2549 if (!ins
->compact_branch
) continue;
2550 if (ins
->prepacked_branch
) continue;
2552 /* We found a branch -- check the type to see if we need to do anything */
2553 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2555 /* It's a break! Check if it's our break */
2556 if (ins
->branch
.target_break
!= loop_idx
) continue;
2558 /* Okay, cool, we're breaking out of this loop.
2559 * Rewrite from a break to a goto */
2561 ins
->branch
.target_type
= TARGET_GOTO
;
2562 ins
->branch
.target_block
= break_block_idx
;
2566 /* Now that we've finished emitting the loop, free up the depth again
2567 * so we play nice with recursion amid nested loops */
2568 --ctx
->current_loop_depth
;
2571 static midgard_block
*
2572 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2574 midgard_block
*start_block
= NULL
;
2576 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2577 switch (node
->type
) {
2578 case nir_cf_node_block
: {
2579 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2582 start_block
= block
;
2587 case nir_cf_node_if
:
2588 emit_if(ctx
, nir_cf_node_as_if(node
));
2591 case nir_cf_node_loop
:
2592 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2595 case nir_cf_node_function
:
2604 /* Due to lookahead, we need to report the first tag executed in the command
2605 * stream and in branch targets. An initial block might be empty, so iterate
2606 * until we find one that 'works' */
2609 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2611 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2613 unsigned first_tag
= 0;
2616 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2618 if (initial_bundle
) {
2619 first_tag
= initial_bundle
->tag
;
2623 /* Initial block is empty, try the next block */
2624 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2625 } while(initial_block
!= NULL
);
2632 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2634 struct util_dynarray
*compiled
= &program
->compiled
;
2636 midgard_debug
= debug_get_option_midgard_debug();
2638 compiler_context ictx
= {
2640 .stage
= nir
->info
.stage
,
2642 .is_blend
= is_blend
,
2643 .blend_constant_offset
= -1,
2645 .alpha_ref
= program
->alpha_ref
2648 compiler_context
*ctx
= &ictx
;
2650 /* TODO: Decide this at runtime */
2651 ctx
->uniform_cutoff
= 8;
2653 /* Initialize at a global (not block) level hash tables */
2655 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2656 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
2657 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2658 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2659 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
2661 /* Record the varying mapping for the command stream's bookkeeping */
2663 struct exec_list
*varyings
=
2664 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2666 unsigned max_varying
= 0;
2667 nir_foreach_variable(var
, varyings
) {
2668 unsigned loc
= var
->data
.driver_location
;
2669 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2671 for (int c
= 0; c
< sz
; ++c
) {
2672 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2673 max_varying
= MAX2(max_varying
, loc
+ c
);
2677 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2678 * (so we don't accidentally duplicate the epilogue since mesa/st has
2679 * messed with our I/O quite a bit already) */
2681 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2683 if (ctx
->stage
== MESA_SHADER_VERTEX
)
2684 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2686 NIR_PASS_V(nir
, nir_lower_var_copies
);
2687 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2688 NIR_PASS_V(nir
, nir_split_var_copies
);
2689 NIR_PASS_V(nir
, nir_lower_var_copies
);
2690 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2691 NIR_PASS_V(nir
, nir_lower_var_copies
);
2692 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2694 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2696 /* Optimisation passes */
2700 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2701 nir_print_shader(nir
, stdout
);
2704 /* Assign sysvals and counts, now that we're sure
2705 * (post-optimisation) */
2707 midgard_nir_assign_sysvals(ctx
, nir
);
2709 program
->uniform_count
= nir
->num_uniforms
;
2710 program
->sysval_count
= ctx
->sysval_count
;
2711 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2713 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
2714 program
->varying_count
= max_varying
+ 1; /* Fencepost off-by-one */
2716 nir_foreach_function(func
, nir
) {
2720 list_inithead(&ctx
->blocks
);
2721 ctx
->block_count
= 0;
2724 emit_cf_list(ctx
, &func
->impl
->body
);
2725 emit_block(ctx
, func
->impl
->end_block
);
2727 break; /* TODO: Multi-function shaders */
2730 util_dynarray_init(compiled
, NULL
);
2732 /* MIR-level optimizations */
2734 bool progress
= false;
2739 mir_foreach_block(ctx
, block
) {
2740 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2741 progress
|= midgard_opt_copy_prop(ctx
, block
);
2742 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
2743 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2747 /* Nested control-flow can result in dead branches at the end of the
2748 * block. This messes with our analysis and is just dead code, so cull
2750 mir_foreach_block(ctx
, block
) {
2751 midgard_opt_cull_dead_branch(ctx
, block
);
2755 schedule_program(ctx
);
2757 /* Now that all the bundles are scheduled and we can calculate block
2758 * sizes, emit actual branch instructions rather than placeholders */
2760 int br_block_idx
= 0;
2762 mir_foreach_block(ctx
, block
) {
2763 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2764 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2765 midgard_instruction
*ins
= bundle
->instructions
[c
];
2767 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2769 if (ins
->prepacked_branch
) continue;
2771 /* Parse some basic branch info */
2772 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2773 bool is_conditional
= ins
->branch
.conditional
;
2774 bool is_inverted
= ins
->branch
.invert_conditional
;
2775 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2777 /* Determine the block we're jumping to */
2778 int target_number
= ins
->branch
.target_block
;
2780 /* Report the destination tag */
2781 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2783 /* Count up the number of quadwords we're
2784 * jumping over = number of quadwords until
2785 * (br_block_idx, target_number) */
2787 int quadword_offset
= 0;
2790 /* Jump to the end of the shader. We
2791 * need to include not only the
2792 * following blocks, but also the
2793 * contents of our current block (since
2794 * discard can come in the middle of
2797 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2799 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2800 quadword_offset
+= quadword_size(bun
->tag
);
2803 mir_foreach_block_from(ctx
, blk
, b
) {
2804 quadword_offset
+= b
->quadword_count
;
2807 } else if (target_number
> br_block_idx
) {
2810 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2811 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2814 quadword_offset
+= blk
->quadword_count
;
2817 /* Jump backwards */
2819 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2820 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2823 quadword_offset
-= blk
->quadword_count
;
2827 /* Unconditional extended branches (far jumps)
2828 * have issues, so we always use a conditional
2829 * branch, setting the condition to always for
2830 * unconditional. For compact unconditional
2831 * branches, cond isn't used so it doesn't
2832 * matter what we pick. */
2834 midgard_condition cond
=
2835 !is_conditional
? midgard_condition_always
:
2836 is_inverted
? midgard_condition_false
:
2837 midgard_condition_true
;
2839 midgard_jmp_writeout_op op
=
2840 is_discard
? midgard_jmp_writeout_op_discard
:
2841 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2842 midgard_jmp_writeout_op_branch_cond
;
2845 midgard_branch_extended branch
=
2846 midgard_create_branch_extended(
2851 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2852 } else if (is_conditional
|| is_discard
) {
2853 midgard_branch_cond branch
= {
2855 .dest_tag
= dest_tag
,
2856 .offset
= quadword_offset
,
2860 assert(branch
.offset
== quadword_offset
);
2862 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2864 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2866 midgard_branch_uncond branch
= {
2868 .dest_tag
= dest_tag
,
2869 .offset
= quadword_offset
,
2873 assert(branch
.offset
== quadword_offset
);
2875 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2883 /* Emit flat binary from the instruction arrays. Iterate each block in
2884 * sequence. Save instruction boundaries such that lookahead tags can
2885 * be assigned easily */
2887 /* Cache _all_ bundles in source order for lookahead across failed branches */
2889 int bundle_count
= 0;
2890 mir_foreach_block(ctx
, block
) {
2891 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2893 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2895 mir_foreach_block(ctx
, block
) {
2896 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2897 source_order_bundles
[bundle_idx
++] = bundle
;
2901 int current_bundle
= 0;
2903 /* Midgard prefetches instruction types, so during emission we
2904 * need to lookahead. Unless this is the last instruction, in
2905 * which we return 1. Or if this is the second to last and the
2906 * last is an ALU, then it's also 1... */
2908 mir_foreach_block(ctx
, block
) {
2909 mir_foreach_bundle_in_block(block
, bundle
) {
2912 if (current_bundle
+ 1 < bundle_count
) {
2913 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2915 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2922 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2926 /* TODO: Free deeper */
2927 //util_dynarray_fini(&block->instructions);
2930 free(source_order_bundles
);
2932 /* Report the very first tag executed */
2933 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2935 /* Deal with off-by-one related to the fencepost problem */
2936 program
->work_register_count
= ctx
->work_registers
+ 1;
2938 program
->can_discard
= ctx
->can_discard
;
2939 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2941 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2943 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2944 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);