2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #include <sys/types.h>
33 #include "main/mtypes.h"
34 #include "compiler/glsl/glsl_to_nir.h"
35 #include "compiler/nir_types.h"
36 #include "main/imports.h"
37 #include "compiler/nir/nir_builder.h"
38 #include "util/half_float.h"
39 #include "util/u_debug.h"
40 #include "util/u_dynarray.h"
41 #include "util/list.h"
42 #include "main/mtypes.h"
45 #include "midgard_nir.h"
46 #include "midgard_compile.h"
47 #include "midgard_ops.h"
51 #include "disassemble.h"
53 static const struct debug_named_value debug_options
[] = {
54 {"msgs", MIDGARD_DBG_MSGS
, "Print debug messages"},
55 {"shaders", MIDGARD_DBG_SHADERS
, "Dump shaders in NIR and MIR"},
59 DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug
, "MIDGARD_MESA_DEBUG", debug_options
, 0)
61 int midgard_debug
= 0;
63 #define DBG(fmt, ...) \
64 do { if (midgard_debug & MIDGARD_DBG_MSGS) \
65 fprintf(stderr, "%s:%d: "fmt, \
66 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
69 midgard_is_branch_unit(unsigned unit
)
71 return (unit
== ALU_ENAB_BRANCH
) || (unit
== ALU_ENAB_BR_COMPACT
);
75 midgard_block_add_successor(midgard_block
*block
, midgard_block
*successor
)
77 block
->successors
[block
->nr_successors
++] = successor
;
78 assert(block
->nr_successors
<= ARRAY_SIZE(block
->successors
));
81 /* Helpers to generate midgard_instruction's using macro magic, since every
82 * driver seems to do it that way */
84 #define EMIT(op, ...) emit_mir_instruction(ctx, v_##op(__VA_ARGS__));
85 #define SWIZZLE_XXXX SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X)
86 #define SWIZZLE_XYXX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_X)
87 #define SWIZZLE_XYZX SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_X)
88 #define SWIZZLE_XYZW SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W)
89 #define SWIZZLE_XYXZ SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_X, COMPONENT_Z)
90 #define SWIZZLE_WWWW SWIZZLE(COMPONENT_W, COMPONENT_W, COMPONENT_W, COMPONENT_W)
92 static inline unsigned
93 swizzle_of(unsigned comp
)
105 unreachable("Invalid component count");
109 static inline unsigned
110 mask_of(unsigned nr_comp
)
112 return (1 << nr_comp
) - 1;
115 #define M_LOAD_STORE(name, rname, uname) \
116 static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
117 midgard_instruction i = { \
118 .type = TAG_LOAD_STORE_4, \
125 .op = midgard_op_##name, \
127 .swizzle = SWIZZLE_XYZW, \
135 #define M_LOAD(name) M_LOAD_STORE(name, dest, src0)
136 #define M_STORE(name) M_LOAD_STORE(name, src0, dest)
138 /* Inputs a NIR ALU source, with modifiers attached if necessary, and outputs
139 * the corresponding Midgard source */
141 static midgard_vector_alu_src
142 vector_alu_modifiers(nir_alu_src
*src
, bool is_int
)
144 if (!src
) return blank_alu_src
;
146 midgard_vector_alu_src alu_src
= {
149 .half
= 0, /* TODO */
150 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
)
154 /* TODO: sign-extend/zero-extend */
155 alu_src
.mod
= midgard_int_normal
;
157 /* These should have been lowered away */
158 assert(!(src
->abs
|| src
->negate
));
160 alu_src
.mod
= (src
->abs
<< 0) | (src
->negate
<< 1);
166 /* load/store instructions have both 32-bit and 16-bit variants, depending on
167 * whether we are using vectors composed of highp or mediump. At the moment, we
168 * don't support half-floats -- this requires changes in other parts of the
169 * compiler -- therefore the 16-bit versions are commented out. */
171 //M_LOAD(ld_attr_16);
173 //M_LOAD(ld_vary_16);
175 //M_LOAD(ld_uniform_16);
176 M_LOAD(ld_uniform_32
);
177 M_LOAD(ld_color_buffer_8
);
178 //M_STORE(st_vary_16);
180 M_STORE(st_cubemap_coords
);
182 static midgard_instruction
183 v_alu_br_compact_cond(midgard_jmp_writeout_op op
, unsigned tag
, signed offset
, unsigned cond
)
185 midgard_branch_cond branch
= {
193 memcpy(&compact
, &branch
, sizeof(branch
));
195 midgard_instruction ins
= {
197 .unit
= ALU_ENAB_BR_COMPACT
,
198 .prepacked_branch
= true,
199 .compact_branch
= true,
200 .br_compact
= compact
203 if (op
== midgard_jmp_writeout_op_writeout
)
209 static midgard_instruction
210 v_branch(bool conditional
, bool invert
)
212 midgard_instruction ins
= {
214 .unit
= ALU_ENAB_BRANCH
,
215 .compact_branch
= true,
217 .conditional
= conditional
,
218 .invert_conditional
= invert
225 static midgard_branch_extended
226 midgard_create_branch_extended( midgard_condition cond
,
227 midgard_jmp_writeout_op op
,
229 signed quadword_offset
)
231 /* For unclear reasons, the condition code is repeated 8 times */
232 uint16_t duplicated_cond
=
242 midgard_branch_extended branch
= {
244 .dest_tag
= dest_tag
,
245 .offset
= quadword_offset
,
246 .cond
= duplicated_cond
253 attach_constants(compiler_context
*ctx
, midgard_instruction
*ins
, void *constants
, int name
)
255 ins
->has_constants
= true;
256 memcpy(&ins
->constants
, constants
, 16);
260 glsl_type_size(const struct glsl_type
*type
, bool bindless
)
262 return glsl_count_attribute_slots(type
, false);
265 /* Lower fdot2 to a vector multiplication followed by channel addition */
267 midgard_nir_lower_fdot2_body(nir_builder
*b
, nir_alu_instr
*alu
)
269 if (alu
->op
!= nir_op_fdot2
)
272 b
->cursor
= nir_before_instr(&alu
->instr
);
274 nir_ssa_def
*src0
= nir_ssa_for_alu_src(b
, alu
, 0);
275 nir_ssa_def
*src1
= nir_ssa_for_alu_src(b
, alu
, 1);
277 nir_ssa_def
*product
= nir_fmul(b
, src0
, src1
);
279 nir_ssa_def
*sum
= nir_fadd(b
,
280 nir_channel(b
, product
, 0),
281 nir_channel(b
, product
, 1));
283 /* Replace the fdot2 with this sum */
284 nir_ssa_def_rewrite_uses(&alu
->dest
.dest
.ssa
, nir_src_for_ssa(sum
));
288 midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr
*instr
)
290 switch (instr
->intrinsic
) {
291 case nir_intrinsic_load_viewport_scale
:
292 return PAN_SYSVAL_VIEWPORT_SCALE
;
293 case nir_intrinsic_load_viewport_offset
:
294 return PAN_SYSVAL_VIEWPORT_OFFSET
;
301 midgard_nir_assign_sysval_body(compiler_context
*ctx
, nir_instr
*instr
)
305 if (instr
->type
== nir_instr_type_intrinsic
) {
306 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
307 sysval
= midgard_nir_sysval_for_intrinsic(intr
);
313 /* We have a sysval load; check if it's already been assigned */
315 if (_mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
))
318 /* It hasn't -- so assign it now! */
320 unsigned id
= ctx
->sysval_count
++;
321 _mesa_hash_table_u64_insert(ctx
->sysval_to_id
, sysval
, (void *) ((uintptr_t) id
+ 1));
322 ctx
->sysvals
[id
] = sysval
;
326 midgard_nir_assign_sysvals(compiler_context
*ctx
, nir_shader
*shader
)
328 ctx
->sysval_count
= 0;
330 nir_foreach_function(function
, shader
) {
331 if (!function
->impl
) continue;
333 nir_foreach_block(block
, function
->impl
) {
334 nir_foreach_instr_safe(instr
, block
) {
335 midgard_nir_assign_sysval_body(ctx
, instr
);
342 midgard_nir_lower_fdot2(nir_shader
*shader
)
344 bool progress
= false;
346 nir_foreach_function(function
, shader
) {
347 if (!function
->impl
) continue;
350 nir_builder
*b
= &_b
;
351 nir_builder_init(b
, function
->impl
);
353 nir_foreach_block(block
, function
->impl
) {
354 nir_foreach_instr_safe(instr
, block
) {
355 if (instr
->type
!= nir_instr_type_alu
) continue;
357 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
358 midgard_nir_lower_fdot2_body(b
, alu
);
364 nir_metadata_preserve(function
->impl
, nir_metadata_block_index
| nir_metadata_dominance
);
372 optimise_nir(nir_shader
*nir
)
375 unsigned lower_flrp
=
376 (nir
->options
->lower_flrp16
? 16 : 0) |
377 (nir
->options
->lower_flrp32
? 32 : 0) |
378 (nir
->options
->lower_flrp64
? 64 : 0);
380 NIR_PASS(progress
, nir
, nir_lower_regs_to_ssa
);
381 NIR_PASS(progress
, nir
, midgard_nir_lower_fdot2
);
382 NIR_PASS(progress
, nir
, nir_lower_idiv
);
384 nir_lower_tex_options lower_tex_options
= {
389 NIR_PASS(progress
, nir
, nir_lower_tex
, &lower_tex_options
);
394 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
395 NIR_PASS(progress
, nir
, nir_lower_vars_to_ssa
);
397 NIR_PASS(progress
, nir
, nir_copy_prop
);
398 NIR_PASS(progress
, nir
, nir_opt_dce
);
399 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
400 NIR_PASS(progress
, nir
, nir_opt_cse
);
401 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 64, false, true);
402 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
403 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
405 if (lower_flrp
!= 0) {
406 bool lower_flrp_progress
= false;
407 NIR_PASS(lower_flrp_progress
,
411 false /* always_precise */,
412 nir
->options
->lower_ffma
);
413 if (lower_flrp_progress
) {
414 NIR_PASS(progress
, nir
,
415 nir_opt_constant_folding
);
419 /* Nothing should rematerialize any flrps, so we only
420 * need to do this lowering once.
425 NIR_PASS(progress
, nir
, nir_opt_undef
);
426 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
,
429 nir_var_function_temp
);
431 /* TODO: Enable vectorize when merged upstream */
432 // NIR_PASS(progress, nir, nir_opt_vectorize);
435 /* Must be run at the end to prevent creation of fsin/fcos ops */
436 NIR_PASS(progress
, nir
, midgard_nir_scale_trig
);
441 NIR_PASS(progress
, nir
, nir_opt_dce
);
442 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
443 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
444 NIR_PASS(progress
, nir
, nir_copy_prop
);
447 NIR_PASS(progress
, nir
, nir_opt_algebraic_late
);
449 /* We implement booleans as 32-bit 0/~0 */
450 NIR_PASS(progress
, nir
, nir_lower_bool_to_int32
);
452 /* Now that booleans are lowered, we can run out late opts */
453 NIR_PASS(progress
, nir
, midgard_nir_lower_algebraic_late
);
455 /* Lower mods for float ops only. Integer ops don't support modifiers
456 * (saturate doesn't make sense on integers, neg/abs require dedicated
459 NIR_PASS(progress
, nir
, nir_lower_to_source_mods
, nir_lower_float_source_mods
);
460 NIR_PASS(progress
, nir
, nir_copy_prop
);
461 NIR_PASS(progress
, nir
, nir_opt_dce
);
463 /* Take us out of SSA */
464 NIR_PASS(progress
, nir
, nir_lower_locals_to_regs
);
465 NIR_PASS(progress
, nir
, nir_convert_from_ssa
, true);
467 /* We are a vector architecture; write combine where possible */
468 NIR_PASS(progress
, nir
, nir_move_vec_src_uses_to_dest
);
469 NIR_PASS(progress
, nir
, nir_lower_vec_to_movs
);
471 NIR_PASS(progress
, nir
, nir_opt_dce
);
474 /* Front-half of aliasing the SSA slots, merely by inserting the flag in the
475 * appropriate hash table. Intentional off-by-one to avoid confusing NULL with
476 * r0. See the comments in compiler_context */
479 alias_ssa(compiler_context
*ctx
, int dest
, int src
)
481 _mesa_hash_table_u64_insert(ctx
->ssa_to_alias
, dest
+ 1, (void *) ((uintptr_t) src
+ 1));
482 _mesa_set_add(ctx
->leftover_ssa_to_alias
, (void *) (uintptr_t) (dest
+ 1));
485 /* ...or undo it, after which the original index will be used (dummy move should be emitted alongside this) */
488 unalias_ssa(compiler_context
*ctx
, int dest
)
490 _mesa_hash_table_u64_remove(ctx
->ssa_to_alias
, dest
+ 1);
491 /* TODO: Remove from leftover or no? */
494 /* Do not actually emit a load; instead, cache the constant for inlining */
497 emit_load_const(compiler_context
*ctx
, nir_load_const_instr
*instr
)
499 nir_ssa_def def
= instr
->def
;
501 float *v
= rzalloc_array(NULL
, float, 4);
502 nir_const_load_to_arr(v
, instr
, f32
);
503 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, def
.index
+ 1, v
);
507 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
510 return src
->ssa
->index
;
512 assert(!src
->reg
.indirect
);
513 return ctx
->func
->impl
->ssa_alloc
+ src
->reg
.reg
->index
;
518 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
521 return dst
->ssa
.index
;
523 assert(!dst
->reg
.indirect
);
524 return ctx
->func
->impl
->ssa_alloc
+ dst
->reg
.reg
->index
;
529 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
531 return nir_src_index(ctx
, &src
->src
);
535 nir_is_non_scalar_swizzle(nir_alu_src
*src
, unsigned nr_components
)
537 unsigned comp
= src
->swizzle
[0];
539 for (unsigned c
= 1; c
< nr_components
; ++c
) {
540 if (src
->swizzle
[c
] != comp
)
547 /* Midgard puts scalar conditionals in r31.w; move an arbitrary source (the
548 * output of a conditional test) into that register */
551 emit_condition(compiler_context
*ctx
, nir_src
*src
, bool for_branch
, unsigned component
)
553 int condition
= nir_src_index(ctx
, src
);
555 /* Source to swizzle the desired component into w */
557 const midgard_vector_alu_src alu_src
= {
558 .swizzle
= SWIZZLE(component
, component
, component
, component
),
561 /* There is no boolean move instruction. Instead, we simulate a move by
562 * ANDing the condition with itself to get it into r31.w */
564 midgard_instruction ins
= {
567 /* We need to set the conditional as close as possible */
568 .precede_break
= true,
569 .unit
= for_branch
? UNIT_SMUL
: UNIT_SADD
,
574 .dest
= SSA_FIXED_REGISTER(31),
578 .op
= midgard_alu_op_iand
,
579 .outmod
= midgard_outmod_int_wrap
,
580 .reg_mode
= midgard_reg_mode_32
,
581 .dest_override
= midgard_dest_override_none
,
582 .mask
= (0x3 << 6), /* w */
583 .src1
= vector_alu_srco_unsigned(alu_src
),
584 .src2
= vector_alu_srco_unsigned(alu_src
)
588 emit_mir_instruction(ctx
, ins
);
591 /* Or, for mixed conditions (with csel_v), here's a vector version using all of
595 emit_condition_mixed(compiler_context
*ctx
, nir_alu_src
*src
, unsigned nr_comp
)
597 int condition
= nir_src_index(ctx
, &src
->src
);
599 /* Source to swizzle the desired component into w */
601 const midgard_vector_alu_src alu_src
= {
602 .swizzle
= SWIZZLE_FROM_ARRAY(src
->swizzle
),
605 /* There is no boolean move instruction. Instead, we simulate a move by
606 * ANDing the condition with itself to get it into r31.w */
608 midgard_instruction ins
= {
610 .precede_break
= true,
614 .dest
= SSA_FIXED_REGISTER(31),
617 .op
= midgard_alu_op_iand
,
618 .outmod
= midgard_outmod_int_wrap
,
619 .reg_mode
= midgard_reg_mode_32
,
620 .dest_override
= midgard_dest_override_none
,
621 .mask
= expand_writemask(mask_of(nr_comp
)),
622 .src1
= vector_alu_srco_unsigned(alu_src
),
623 .src2
= vector_alu_srco_unsigned(alu_src
)
627 emit_mir_instruction(ctx
, ins
);
632 /* Likewise, indirect offsets are put in r27.w. TODO: Allow componentwise
633 * pinning to eliminate this move in all known cases */
636 emit_indirect_offset(compiler_context
*ctx
, nir_src
*src
)
638 int offset
= nir_src_index(ctx
, src
);
640 midgard_instruction ins
= {
643 .src0
= SSA_UNUSED_1
,
645 .dest
= SSA_FIXED_REGISTER(REGISTER_OFFSET
),
648 .op
= midgard_alu_op_imov
,
649 .outmod
= midgard_outmod_int_wrap
,
650 .reg_mode
= midgard_reg_mode_32
,
651 .dest_override
= midgard_dest_override_none
,
652 .mask
= (0x3 << 6), /* w */
653 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
654 .src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
)
658 emit_mir_instruction(ctx
, ins
);
661 #define ALU_CASE(nir, _op) \
663 op = midgard_alu_op_##_op; \
666 nir_is_fzero_constant(nir_src src
)
668 if (!nir_src_is_const(src
))
671 for (unsigned c
= 0; c
< nir_src_num_components(src
); ++c
) {
672 if (nir_src_comp_as_float(src
, c
) != 0.0)
680 emit_alu(compiler_context
*ctx
, nir_alu_instr
*instr
)
682 bool is_ssa
= instr
->dest
.dest
.is_ssa
;
684 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
.dest
);
685 unsigned nr_components
= is_ssa
? instr
->dest
.dest
.ssa
.num_components
: instr
->dest
.dest
.reg
.reg
->num_components
;
686 unsigned nr_inputs
= nir_op_infos
[instr
->op
].num_inputs
;
688 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
689 * supported. A few do not and are commented for now. Also, there are a
690 * number of NIR ops which Midgard does not support and need to be
691 * lowered, also TODO. This switch block emits the opcode and calling
692 * convention of the Midgard instruction; actual packing is done in
698 ALU_CASE(fadd
, fadd
);
699 ALU_CASE(fmul
, fmul
);
700 ALU_CASE(fmin
, fmin
);
701 ALU_CASE(fmax
, fmax
);
702 ALU_CASE(imin
, imin
);
703 ALU_CASE(imax
, imax
);
704 ALU_CASE(umin
, umin
);
705 ALU_CASE(umax
, umax
);
706 ALU_CASE(ffloor
, ffloor
);
707 ALU_CASE(fround_even
, froundeven
);
708 ALU_CASE(ftrunc
, ftrunc
);
709 ALU_CASE(fceil
, fceil
);
710 ALU_CASE(fdot3
, fdot3
);
711 ALU_CASE(fdot4
, fdot4
);
712 ALU_CASE(iadd
, iadd
);
713 ALU_CASE(isub
, isub
);
714 ALU_CASE(imul
, imul
);
716 /* Zero shoved as second-arg */
717 ALU_CASE(iabs
, iabsdiff
);
721 ALU_CASE(feq32
, feq
);
722 ALU_CASE(fne32
, fne
);
723 ALU_CASE(flt32
, flt
);
724 ALU_CASE(ieq32
, ieq
);
725 ALU_CASE(ine32
, ine
);
726 ALU_CASE(ilt32
, ilt
);
727 ALU_CASE(ult32
, ult
);
729 /* We don't have a native b2f32 instruction. Instead, like many
730 * GPUs, we exploit booleans as 0/~0 for false/true, and
731 * correspondingly AND
732 * by 1.0 to do the type conversion. For the moment, prime us
735 * iand [whatever], #0
737 * At the end of emit_alu (as MIR), we'll fix-up the constant
740 ALU_CASE(b2f32
, iand
);
741 ALU_CASE(b2i32
, iand
);
743 /* Likewise, we don't have a dedicated f2b32 instruction, but
744 * we can do a "not equal to 0.0" test. */
746 ALU_CASE(f2b32
, fne
);
747 ALU_CASE(i2b32
, ine
);
749 ALU_CASE(frcp
, frcp
);
750 ALU_CASE(frsq
, frsqrt
);
751 ALU_CASE(fsqrt
, fsqrt
);
752 ALU_CASE(fexp2
, fexp2
);
753 ALU_CASE(flog2
, flog2
);
755 ALU_CASE(f2i32
, f2i_rtz
);
756 ALU_CASE(f2u32
, f2u_rtz
);
757 ALU_CASE(i2f32
, i2f_rtz
);
758 ALU_CASE(u2f32
, u2f_rtz
);
760 ALU_CASE(fsin
, fsin
);
761 ALU_CASE(fcos
, fcos
);
763 /* Second op implicit #0 */
764 ALU_CASE(inot
, inor
);
765 ALU_CASE(iand
, iand
);
767 ALU_CASE(ixor
, ixor
);
768 ALU_CASE(ishl
, ishl
);
769 ALU_CASE(ishr
, iasr
);
770 ALU_CASE(ushr
, ilsr
);
772 ALU_CASE(b32all_fequal2
, fball_eq
);
773 ALU_CASE(b32all_fequal3
, fball_eq
);
774 ALU_CASE(b32all_fequal4
, fball_eq
);
776 ALU_CASE(b32any_fnequal2
, fbany_neq
);
777 ALU_CASE(b32any_fnequal3
, fbany_neq
);
778 ALU_CASE(b32any_fnequal4
, fbany_neq
);
780 ALU_CASE(b32all_iequal2
, iball_eq
);
781 ALU_CASE(b32all_iequal3
, iball_eq
);
782 ALU_CASE(b32all_iequal4
, iball_eq
);
784 ALU_CASE(b32any_inequal2
, ibany_neq
);
785 ALU_CASE(b32any_inequal3
, ibany_neq
);
786 ALU_CASE(b32any_inequal4
, ibany_neq
);
788 /* Source mods will be shoved in later */
789 ALU_CASE(fabs
, fmov
);
790 ALU_CASE(fneg
, fmov
);
791 ALU_CASE(fsat
, fmov
);
793 /* For greater-or-equal, we lower to less-or-equal and flip the
801 instr
->op
== nir_op_fge
? midgard_alu_op_fle
:
802 instr
->op
== nir_op_fge32
? midgard_alu_op_fle
:
803 instr
->op
== nir_op_ige32
? midgard_alu_op_ile
:
804 instr
->op
== nir_op_uge32
? midgard_alu_op_ule
:
807 /* Swap via temporary */
808 nir_alu_src temp
= instr
->src
[1];
809 instr
->src
[1] = instr
->src
[0];
810 instr
->src
[0] = temp
;
815 case nir_op_b32csel
: {
816 /* Midgard features both fcsel and icsel, depending on
817 * the type of the arguments/output. However, as long
818 * as we're careful we can _always_ use icsel and
819 * _never_ need fcsel, since the latter does additional
820 * floating-point-specific processing whereas the
821 * former just moves bits on the wire. It's not obvious
822 * why these are separate opcodes, save for the ability
823 * to do things like sat/pos/abs/neg for free */
825 bool mixed
= nir_is_non_scalar_swizzle(&instr
->src
[0], nr_components
);
826 op
= mixed
? midgard_alu_op_icsel_v
: midgard_alu_op_icsel
;
828 /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */
831 /* Emit the condition into r31 */
834 emit_condition_mixed(ctx
, &instr
->src
[0], nr_components
);
836 emit_condition(ctx
, &instr
->src
[0].src
, false, instr
->src
[0].swizzle
[0]);
838 /* The condition is the first argument; move the other
839 * arguments up one to be a binary instruction for
842 memmove(instr
->src
, instr
->src
+ 1, 2 * sizeof(nir_alu_src
));
847 DBG("Unhandled ALU op %s\n", nir_op_infos
[instr
->op
].name
);
852 /* Midgard can perform certain modifiers on output of an ALU op */
855 if (midgard_is_integer_out_op(op
)) {
856 outmod
= midgard_outmod_int_wrap
;
858 bool sat
= instr
->dest
.saturate
|| instr
->op
== nir_op_fsat
;
859 outmod
= sat
? midgard_outmod_sat
: midgard_outmod_none
;
862 /* fmax(a, 0.0) can turn into a .pos modifier as an optimization */
864 if (instr
->op
== nir_op_fmax
) {
865 if (nir_is_fzero_constant(instr
->src
[0].src
)) {
866 op
= midgard_alu_op_fmov
;
868 outmod
= midgard_outmod_pos
;
869 instr
->src
[0] = instr
->src
[1];
870 } else if (nir_is_fzero_constant(instr
->src
[1].src
)) {
871 op
= midgard_alu_op_fmov
;
873 outmod
= midgard_outmod_pos
;
877 /* Fetch unit, quirks, etc information */
878 unsigned opcode_props
= alu_opcode_props
[op
].props
;
879 bool quirk_flipped_r24
= opcode_props
& QUIRK_FLIPPED_R24
;
881 /* src0 will always exist afaik, but src1 will not for 1-argument
882 * instructions. The latter can only be fetched if the instruction
883 * needs it, or else we may segfault. */
885 unsigned src0
= nir_alu_src_index(ctx
, &instr
->src
[0]);
886 unsigned src1
= nr_inputs
== 2 ? nir_alu_src_index(ctx
, &instr
->src
[1]) : SSA_UNUSED_0
;
888 /* Rather than use the instruction generation helpers, we do it
889 * ourselves here to avoid the mess */
891 midgard_instruction ins
= {
894 .src0
= quirk_flipped_r24
? SSA_UNUSED_1
: src0
,
895 .src1
= quirk_flipped_r24
? src0
: src1
,
900 nir_alu_src
*nirmods
[2] = { NULL
};
902 if (nr_inputs
== 2) {
903 nirmods
[0] = &instr
->src
[0];
904 nirmods
[1] = &instr
->src
[1];
905 } else if (nr_inputs
== 1) {
906 nirmods
[quirk_flipped_r24
] = &instr
->src
[0];
911 /* These were lowered to a move, so apply the corresponding mod */
913 if (instr
->op
== nir_op_fneg
|| instr
->op
== nir_op_fabs
) {
914 nir_alu_src
*s
= nirmods
[quirk_flipped_r24
];
916 if (instr
->op
== nir_op_fneg
)
917 s
->negate
= !s
->negate
;
919 if (instr
->op
== nir_op_fabs
)
923 bool is_int
= midgard_is_integer_op(op
);
925 midgard_vector_alu alu
= {
927 .reg_mode
= midgard_reg_mode_32
,
928 .dest_override
= midgard_dest_override_none
,
931 /* Writemask only valid for non-SSA NIR */
932 .mask
= expand_writemask(mask_of(nr_components
)),
934 .src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
)),
935 .src2
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[1], is_int
)),
938 /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */
941 alu
.mask
&= expand_writemask(instr
->dest
.write_mask
);
945 /* Late fixup for emulated instructions */
947 if (instr
->op
== nir_op_b2f32
|| instr
->op
== nir_op_b2i32
) {
948 /* Presently, our second argument is an inline #0 constant.
949 * Switch over to an embedded 1.0 constant (that can't fit
950 * inline, since we're 32-bit, not 16-bit like the inline
953 ins
.ssa_args
.inline_constant
= false;
954 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
955 ins
.has_constants
= true;
957 if (instr
->op
== nir_op_b2f32
) {
958 ins
.constants
[0] = 1.0f
;
960 /* Type pun it into place */
962 memcpy(&ins
.constants
[0], &one
, sizeof(uint32_t));
965 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
966 } else if (nr_inputs
== 1 && !quirk_flipped_r24
) {
967 /* Lots of instructions need a 0 plonked in */
968 ins
.ssa_args
.inline_constant
= false;
969 ins
.ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
970 ins
.has_constants
= true;
971 ins
.constants
[0] = 0.0f
;
972 ins
.alu
.src2
= vector_alu_srco_unsigned(blank_alu_src_xxxx
);
973 } else if (instr
->op
== nir_op_inot
) {
974 /* ~b = ~(b & b), so duplicate the source */
975 ins
.ssa_args
.src1
= ins
.ssa_args
.src0
;
976 ins
.alu
.src2
= ins
.alu
.src1
;
979 if ((opcode_props
& UNITS_ALL
) == UNIT_VLUT
) {
980 /* To avoid duplicating the lookup tables (probably), true LUT
981 * instructions can only operate as if they were scalars. Lower
982 * them here by changing the component. */
984 uint8_t original_swizzle
[4];
985 memcpy(original_swizzle
, nirmods
[0]->swizzle
, sizeof(nirmods
[0]->swizzle
));
987 for (int i
= 0; i
< nr_components
; ++i
) {
988 /* Mask the associated component, dropping the
989 * instruction if needed */
991 ins
.alu
.mask
= (0x3) << (2 * i
);
992 ins
.alu
.mask
&= alu
.mask
;
997 for (int j
= 0; j
< 4; ++j
)
998 nirmods
[0]->swizzle
[j
] = original_swizzle
[i
]; /* Pull from the correct component */
1000 ins
.alu
.src1
= vector_alu_srco_unsigned(vector_alu_modifiers(nirmods
[0], is_int
));
1001 emit_mir_instruction(ctx
, ins
);
1004 emit_mir_instruction(ctx
, ins
);
1011 emit_uniform_read(compiler_context
*ctx
, unsigned dest
, unsigned offset
, nir_src
*indirect_offset
)
1013 /* TODO: half-floats */
1015 if (!indirect_offset
&& offset
< ctx
->uniform_cutoff
) {
1016 /* Fast path: For the first 16 uniforms, direct accesses are
1017 * 0-cycle, since they're just a register fetch in the usual
1018 * case. So, we alias the registers while we're still in
1021 int reg_slot
= 23 - offset
;
1022 alias_ssa(ctx
, dest
, SSA_FIXED_REGISTER(reg_slot
));
1024 /* Otherwise, read from the 'special' UBO to access
1025 * higher-indexed uniforms, at a performance cost. More
1026 * generally, we're emitting a UBO read instruction. */
1028 midgard_instruction ins
= m_ld_uniform_32(dest
, offset
);
1030 /* TODO: Don't split */
1031 ins
.load_store
.varying_parameters
= (offset
& 7) << 7;
1032 ins
.load_store
.address
= offset
>> 3;
1034 if (indirect_offset
) {
1035 emit_indirect_offset(ctx
, indirect_offset
);
1036 ins
.load_store
.unknown
= 0x8700; /* xxx: what is this? */
1038 ins
.load_store
.unknown
= 0x1E00; /* xxx: what is this? */
1041 emit_mir_instruction(ctx
, ins
);
1047 compiler_context
*ctx
,
1048 unsigned dest
, unsigned offset
,
1049 unsigned nr_comp
, unsigned component
,
1050 nir_src
*indirect_offset
)
1052 /* XXX: Half-floats? */
1053 /* TODO: swizzle, mask */
1055 midgard_instruction ins
= m_ld_vary_32(dest
, offset
);
1056 ins
.load_store
.mask
= mask_of(nr_comp
);
1057 ins
.load_store
.swizzle
= SWIZZLE_XYZW
>> (2 * component
);
1059 midgard_varying_parameter p
= {
1061 .interpolation
= midgard_interp_default
,
1062 .flat
= /*var->data.interpolation == INTERP_MODE_FLAT*/ 0
1066 memcpy(&u
, &p
, sizeof(p
));
1067 ins
.load_store
.varying_parameters
= u
;
1069 if (indirect_offset
) {
1070 /* We need to add in the dynamic index, moved to r27.w */
1071 emit_indirect_offset(ctx
, indirect_offset
);
1072 ins
.load_store
.unknown
= 0x79e; /* xxx: what is this? */
1074 /* Just a direct load */
1075 ins
.load_store
.unknown
= 0x1e9e; /* xxx: what is this? */
1078 emit_mir_instruction(ctx
, ins
);
1082 emit_sysval_read(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1084 /* First, pull out the destination */
1085 unsigned dest
= nir_dest_index(ctx
, &instr
->dest
);
1087 /* Now, figure out which uniform this is */
1088 int sysval
= midgard_nir_sysval_for_intrinsic(instr
);
1089 void *val
= _mesa_hash_table_u64_search(ctx
->sysval_to_id
, sysval
);
1091 /* Sysvals are prefix uniforms */
1092 unsigned uniform
= ((uintptr_t) val
) - 1;
1094 /* Emit the read itself -- this is never indirect */
1095 emit_uniform_read(ctx
, dest
, uniform
, NULL
);
1098 /* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register,
1099 * using scalar ops functional on earlier Midgard generations. Newer Midgard
1100 * generations have faster vectorized reads. This operation is for blend
1101 * shaders in particular; reading the tilebuffer from the fragment shader
1102 * remains an open problem. */
1105 emit_fb_read_blend_scalar(compiler_context
*ctx
, unsigned reg
)
1107 midgard_instruction ins
= m_ld_color_buffer_8(reg
, 0);
1108 ins
.load_store
.swizzle
= 0; /* xxxx */
1110 /* Read each component sequentially */
1112 for (unsigned c
= 0; c
< 4; ++c
) {
1113 ins
.load_store
.mask
= (1 << c
);
1114 ins
.load_store
.unknown
= c
;
1115 emit_mir_instruction(ctx
, ins
);
1118 /* vadd.u2f hr2, zext(hr2), #0 */
1120 midgard_vector_alu_src alu_src
= blank_alu_src
;
1121 alu_src
.mod
= midgard_int_zero_extend
;
1122 alu_src
.half
= true;
1124 midgard_instruction u2f
= {
1128 .src1
= SSA_UNUSED_0
,
1130 .inline_constant
= true
1133 .op
= midgard_alu_op_u2f_rtz
,
1134 .reg_mode
= midgard_reg_mode_16
,
1135 .dest_override
= midgard_dest_override_none
,
1137 .src1
= vector_alu_srco_unsigned(alu_src
),
1138 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1142 emit_mir_instruction(ctx
, u2f
);
1144 /* vmul.fmul.sat r1, hr2, #0.00392151 */
1148 midgard_instruction fmul
= {
1150 .inline_constant
= _mesa_float_to_half(1.0 / 255.0),
1154 .src1
= SSA_UNUSED_0
,
1155 .inline_constant
= true
1158 .op
= midgard_alu_op_fmul
,
1159 .reg_mode
= midgard_reg_mode_32
,
1160 .dest_override
= midgard_dest_override_none
,
1161 .outmod
= midgard_outmod_sat
,
1163 .src1
= vector_alu_srco_unsigned(alu_src
),
1164 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
1168 emit_mir_instruction(ctx
, fmul
);
1172 emit_intrinsic(compiler_context
*ctx
, nir_intrinsic_instr
*instr
)
1174 unsigned offset
, reg
;
1176 switch (instr
->intrinsic
) {
1177 case nir_intrinsic_discard_if
:
1178 emit_condition(ctx
, &instr
->src
[0], true, COMPONENT_X
);
1182 case nir_intrinsic_discard
: {
1183 bool conditional
= instr
->intrinsic
== nir_intrinsic_discard_if
;
1184 struct midgard_instruction discard
= v_branch(conditional
, false);
1185 discard
.branch
.target_type
= TARGET_DISCARD
;
1186 emit_mir_instruction(ctx
, discard
);
1188 ctx
->can_discard
= true;
1192 case nir_intrinsic_load_uniform
:
1193 case nir_intrinsic_load_input
:
1194 offset
= nir_intrinsic_base(instr
);
1196 unsigned nr_comp
= nir_intrinsic_dest_components(instr
);
1197 bool direct
= nir_src_is_const(instr
->src
[0]);
1200 offset
+= nir_src_as_uint(instr
->src
[0]);
1203 /* We may need to apply a fractional offset */
1204 int component
= instr
->intrinsic
== nir_intrinsic_load_input
?
1205 nir_intrinsic_component(instr
) : 0;
1206 reg
= nir_dest_index(ctx
, &instr
->dest
);
1208 if (instr
->intrinsic
== nir_intrinsic_load_uniform
&& !ctx
->is_blend
) {
1209 emit_uniform_read(ctx
, reg
, ctx
->sysval_count
+ offset
, !direct
? &instr
->src
[0] : NULL
);
1210 } else if (ctx
->stage
== MESA_SHADER_FRAGMENT
&& !ctx
->is_blend
) {
1211 emit_varying_read(ctx
, reg
, offset
, nr_comp
, component
, !direct
? &instr
->src
[0] : NULL
);
1212 } else if (ctx
->is_blend
) {
1213 /* For blend shaders, load the input color, which is
1214 * preloaded to r0 */
1216 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1217 emit_mir_instruction(ctx
, move
);
1218 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1219 midgard_instruction ins
= m_ld_attr_32(reg
, offset
);
1220 ins
.load_store
.unknown
= 0x1E1E; /* XXX: What is this? */
1221 ins
.load_store
.mask
= mask_of(nr_comp
);
1222 emit_mir_instruction(ctx
, ins
);
1224 DBG("Unknown load\n");
1230 case nir_intrinsic_load_output
:
1231 assert(nir_src_is_const(instr
->src
[0]));
1232 reg
= nir_dest_index(ctx
, &instr
->dest
);
1234 if (ctx
->is_blend
) {
1236 emit_fb_read_blend_scalar(ctx
, reg
);
1238 DBG("Unknown output load\n");
1244 case nir_intrinsic_load_blend_const_color_rgba
: {
1245 assert(ctx
->is_blend
);
1246 reg
= nir_dest_index(ctx
, &instr
->dest
);
1248 /* Blend constants are embedded directly in the shader and
1249 * patched in, so we use some magic routing */
1251 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, reg
);
1252 ins
.has_constants
= true;
1253 ins
.has_blend_constant
= true;
1254 emit_mir_instruction(ctx
, ins
);
1258 case nir_intrinsic_store_output
:
1259 assert(nir_src_is_const(instr
->src
[1]) && "no indirect outputs");
1261 offset
= nir_intrinsic_base(instr
) + nir_src_as_uint(instr
->src
[1]);
1263 reg
= nir_src_index(ctx
, &instr
->src
[0]);
1265 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1266 /* gl_FragColor is not emitted with load/store
1267 * instructions. Instead, it gets plonked into
1268 * r0 at the end of the shader and we do the
1269 * framebuffer writeout dance. TODO: Defer
1272 midgard_instruction move
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(0));
1273 emit_mir_instruction(ctx
, move
);
1275 /* Save the index we're writing to for later reference
1276 * in the epilogue */
1278 ctx
->fragment_output
= reg
;
1279 } else if (ctx
->stage
== MESA_SHADER_VERTEX
) {
1280 /* Varyings are written into one of two special
1281 * varying register, r26 or r27. The register itself is
1282 * selected as the register in the st_vary instruction,
1283 * minus the base of 26. E.g. write into r27 and then
1284 * call st_vary(1) */
1286 midgard_instruction ins
= v_mov(reg
, blank_alu_src
, SSA_FIXED_REGISTER(26));
1287 emit_mir_instruction(ctx
, ins
);
1289 /* We should have been vectorized, though we don't
1290 * currently check that st_vary is emitted only once
1291 * per slot (this is relevant, since there's not a mask
1292 * parameter available on the store [set to 0 by the
1293 * blob]). We do respect the component by adjusting the
1296 unsigned component
= nir_intrinsic_component(instr
);
1298 midgard_instruction st
= m_st_vary_32(SSA_FIXED_REGISTER(0), offset
);
1299 st
.load_store
.unknown
= 0x1E9E; /* XXX: What is this? */
1300 st
.load_store
.swizzle
= SWIZZLE_XYZW
<< (2*component
);
1301 emit_mir_instruction(ctx
, st
);
1303 DBG("Unknown store\n");
1309 case nir_intrinsic_load_alpha_ref_float
:
1310 assert(instr
->dest
.is_ssa
);
1312 float ref_value
= ctx
->alpha_ref
;
1314 float *v
= ralloc_array(NULL
, float, 4);
1315 memcpy(v
, &ref_value
, sizeof(float));
1316 _mesa_hash_table_u64_insert(ctx
->ssa_constants
, instr
->dest
.ssa
.index
+ 1, v
);
1319 case nir_intrinsic_load_viewport_scale
:
1320 case nir_intrinsic_load_viewport_offset
:
1321 emit_sysval_read(ctx
, instr
);
1325 printf ("Unhandled intrinsic\n");
1332 midgard_tex_format(enum glsl_sampler_dim dim
)
1335 case GLSL_SAMPLER_DIM_2D
:
1336 case GLSL_SAMPLER_DIM_EXTERNAL
:
1339 case GLSL_SAMPLER_DIM_3D
:
1342 case GLSL_SAMPLER_DIM_CUBE
:
1343 return TEXTURE_CUBE
;
1346 DBG("Unknown sampler dim type\n");
1353 midgard_tex_op(nir_texop op
)
1358 return TEXTURE_OP_NORMAL
;
1360 return TEXTURE_OP_LOD
;
1362 unreachable("Unhanlded texture op");
1367 emit_tex(compiler_context
*ctx
, nir_tex_instr
*instr
)
1370 //assert (!instr->sampler);
1371 //assert (!instr->texture_array_size);
1373 /* Allocate registers via a round robin scheme to alternate between the two registers */
1374 int reg
= ctx
->texture_op_count
& 1;
1375 int in_reg
= reg
, out_reg
= reg
;
1377 /* Make room for the reg */
1379 if (ctx
->texture_index
[reg
] > -1)
1380 unalias_ssa(ctx
, ctx
->texture_index
[reg
]);
1382 int texture_index
= instr
->texture_index
;
1383 int sampler_index
= texture_index
;
1385 unsigned position_swizzle
= 0;
1387 for (unsigned i
= 0; i
< instr
->num_srcs
; ++i
) {
1388 int reg
= SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ in_reg
);
1389 int index
= nir_src_index(ctx
, &instr
->src
[i
].src
);
1390 int nr_comp
= nir_src_num_components(instr
->src
[i
].src
);
1391 midgard_vector_alu_src alu_src
= blank_alu_src
;
1393 switch (instr
->src
[i
].src_type
) {
1394 case nir_tex_src_coord
: {
1395 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
1396 /* For cubemaps, we need to load coords into
1397 * special r27, and then use a special ld/st op
1398 * to select the face and copy the xy into the
1399 * texture register */
1401 alu_src
.swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_X
);
1403 midgard_instruction move
= v_mov(index
, alu_src
, SSA_FIXED_REGISTER(27));
1404 emit_mir_instruction(ctx
, move
);
1406 midgard_instruction st
= m_st_cubemap_coords(reg
, 0);
1407 st
.load_store
.unknown
= 0x24; /* XXX: What is this? */
1408 st
.load_store
.mask
= 0x3; /* xy */
1409 st
.load_store
.swizzle
= alu_src
.swizzle
;
1410 emit_mir_instruction(ctx
, st
);
1412 position_swizzle
= swizzle_of(2);
1414 position_swizzle
= alu_src
.swizzle
= swizzle_of(nr_comp
);
1416 midgard_instruction ins
= v_mov(index
, alu_src
, reg
);
1417 ins
.alu
.mask
= expand_writemask(mask_of(nr_comp
));
1418 emit_mir_instruction(ctx
, ins
);
1420 /* To the hardware, z is depth, w is array
1421 * layer. To NIR, z is array layer for a 2D
1424 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_2D
)
1425 position_swizzle
= SWIZZLE_XYXZ
;
1431 case nir_tex_src_bias
:
1432 case nir_tex_src_lod
: {
1433 /* To keep RA simple, we put the bias/LOD into the w
1434 * component of the input source, which is otherwise in xy */
1436 alu_src
.swizzle
= SWIZZLE_XXXX
;
1438 midgard_instruction ins
= v_mov(index
, alu_src
, reg
);
1439 ins
.alu
.mask
= expand_writemask(1 << COMPONENT_W
);
1440 emit_mir_instruction(ctx
, ins
);
1445 unreachable("Unknown texture source type\n");
1449 /* No helper to build texture words -- we do it all here */
1450 midgard_instruction ins
= {
1451 .type
= TAG_TEXTURE_4
,
1453 .op
= midgard_tex_op(instr
->op
),
1454 .format
= midgard_tex_format(instr
->sampler_dim
),
1455 .texture_handle
= texture_index
,
1456 .sampler_handle
= sampler_index
,
1458 /* TODO: Regalloc it in */
1459 .swizzle
= SWIZZLE_XYZW
,
1464 .in_reg_swizzle
= position_swizzle
,
1472 /* Set registers to read and write from the same place */
1473 ins
.texture
.in_reg_select
= in_reg
;
1474 ins
.texture
.out_reg_select
= out_reg
;
1476 /* Setup bias/LOD if necessary. Only register mode support right now.
1477 * TODO: Immediate mode for performance gains */
1479 if (instr
->op
== nir_texop_txb
|| instr
->op
== nir_texop_txl
) {
1480 ins
.texture
.lod_register
= true;
1482 midgard_tex_register_select sel
= {
1492 memcpy(&packed
, &sel
, sizeof(packed
));
1493 ins
.texture
.bias
= packed
;
1496 emit_mir_instruction(ctx
, ins
);
1498 /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */
1500 int o_reg
= REGISTER_TEXTURE_BASE
+ out_reg
, o_index
= nir_dest_index(ctx
, &instr
->dest
);
1501 alias_ssa(ctx
, o_index
, SSA_FIXED_REGISTER(o_reg
));
1502 ctx
->texture_index
[reg
] = o_index
;
1504 midgard_instruction ins2
= v_mov(SSA_FIXED_REGISTER(o_reg
), blank_alu_src
, o_index
);
1505 emit_mir_instruction(ctx
, ins2
);
1507 /* Used for .cont and .last hinting */
1508 ctx
->texture_op_count
++;
1512 emit_jump(compiler_context
*ctx
, nir_jump_instr
*instr
)
1514 switch (instr
->type
) {
1515 case nir_jump_break
: {
1516 /* Emit a branch out of the loop */
1517 struct midgard_instruction br
= v_branch(false, false);
1518 br
.branch
.target_type
= TARGET_BREAK
;
1519 br
.branch
.target_break
= ctx
->current_loop_depth
;
1520 emit_mir_instruction(ctx
, br
);
1527 DBG("Unknown jump type %d\n", instr
->type
);
1533 emit_instr(compiler_context
*ctx
, struct nir_instr
*instr
)
1535 switch (instr
->type
) {
1536 case nir_instr_type_load_const
:
1537 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
1540 case nir_instr_type_intrinsic
:
1541 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
1544 case nir_instr_type_alu
:
1545 emit_alu(ctx
, nir_instr_as_alu(instr
));
1548 case nir_instr_type_tex
:
1549 emit_tex(ctx
, nir_instr_as_tex(instr
));
1552 case nir_instr_type_jump
:
1553 emit_jump(ctx
, nir_instr_as_jump(instr
));
1556 case nir_instr_type_ssa_undef
:
1561 DBG("Unhandled instruction type\n");
1567 /* ALU instructions can inline or embed constants, which decreases register
1568 * pressure and saves space. */
1570 #define CONDITIONAL_ATTACH(src) { \
1571 void *entry = _mesa_hash_table_u64_search(ctx->ssa_constants, alu->ssa_args.src + 1); \
1574 attach_constants(ctx, alu, entry, alu->ssa_args.src + 1); \
1575 alu->ssa_args.src = SSA_FIXED_REGISTER(REGISTER_CONSTANT); \
1580 inline_alu_constants(compiler_context
*ctx
)
1582 mir_foreach_instr(ctx
, alu
) {
1583 /* Other instructions cannot inline constants */
1584 if (alu
->type
!= TAG_ALU_4
) continue;
1586 /* If there is already a constant here, we can do nothing */
1587 if (alu
->has_constants
) continue;
1589 /* It makes no sense to inline constants on a branch */
1590 if (alu
->compact_branch
|| alu
->prepacked_branch
) continue;
1592 CONDITIONAL_ATTACH(src0
);
1594 if (!alu
->has_constants
) {
1595 CONDITIONAL_ATTACH(src1
)
1596 } else if (!alu
->inline_constant
) {
1597 /* Corner case: _two_ vec4 constants, for instance with a
1598 * csel. For this case, we can only use a constant
1599 * register for one, we'll have to emit a move for the
1600 * other. Note, if both arguments are constants, then
1601 * necessarily neither argument depends on the value of
1602 * any particular register. As the destination register
1603 * will be wiped, that means we can spill the constant
1604 * to the destination register.
1607 void *entry
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, alu
->ssa_args
.src1
+ 1);
1608 unsigned scratch
= alu
->ssa_args
.dest
;
1611 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, scratch
);
1612 attach_constants(ctx
, &ins
, entry
, alu
->ssa_args
.src1
+ 1);
1614 /* Force a break XXX Defer r31 writes */
1615 ins
.unit
= UNIT_VLUT
;
1617 /* Set the source */
1618 alu
->ssa_args
.src1
= scratch
;
1620 /* Inject us -before- the last instruction which set r31 */
1621 mir_insert_instruction_before(mir_prev_op(alu
), ins
);
1627 /* Midgard supports two types of constants, embedded constants (128-bit) and
1628 * inline constants (16-bit). Sometimes, especially with scalar ops, embedded
1629 * constants can be demoted to inline constants, for space savings and
1630 * sometimes a performance boost */
1633 embedded_to_inline_constant(compiler_context
*ctx
)
1635 mir_foreach_instr(ctx
, ins
) {
1636 if (!ins
->has_constants
) continue;
1638 if (ins
->ssa_args
.inline_constant
) continue;
1640 /* Blend constants must not be inlined by definition */
1641 if (ins
->has_blend_constant
) continue;
1643 /* src1 cannot be an inline constant due to encoding
1644 * restrictions. So, if possible we try to flip the arguments
1647 int op
= ins
->alu
.op
;
1649 if (ins
->ssa_args
.src0
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1651 /* These ops require an operational change to flip
1652 * their arguments TODO */
1653 case midgard_alu_op_flt
:
1654 case midgard_alu_op_fle
:
1655 case midgard_alu_op_ilt
:
1656 case midgard_alu_op_ile
:
1657 case midgard_alu_op_fcsel
:
1658 case midgard_alu_op_icsel
:
1659 DBG("Missed non-commutative flip (%s)\n", alu_opcode_props
[op
].name
);
1664 if (alu_opcode_props
[op
].props
& OP_COMMUTES
) {
1665 /* Flip the SSA numbers */
1666 ins
->ssa_args
.src0
= ins
->ssa_args
.src1
;
1667 ins
->ssa_args
.src1
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
1669 /* And flip the modifiers */
1673 src_temp
= ins
->alu
.src2
;
1674 ins
->alu
.src2
= ins
->alu
.src1
;
1675 ins
->alu
.src1
= src_temp
;
1679 if (ins
->ssa_args
.src1
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
)) {
1680 /* Extract the source information */
1682 midgard_vector_alu_src
*src
;
1683 int q
= ins
->alu
.src2
;
1684 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
1687 /* Component is from the swizzle, e.g. r26.w -> w component. TODO: What if x is masked out? */
1688 int component
= src
->swizzle
& 3;
1690 /* Scale constant appropriately, if we can legally */
1691 uint16_t scaled_constant
= 0;
1693 if (midgard_is_integer_op(op
)) {
1694 unsigned int *iconstants
= (unsigned int *) ins
->constants
;
1695 scaled_constant
= (uint16_t) iconstants
[component
];
1697 /* Constant overflow after resize */
1698 if (scaled_constant
!= iconstants
[component
])
1701 float original
= (float) ins
->constants
[component
];
1702 scaled_constant
= _mesa_float_to_half(original
);
1704 /* Check for loss of precision. If this is
1705 * mediump, we don't care, but for a highp
1706 * shader, we need to pay attention. NIR
1707 * doesn't yet tell us which mode we're in!
1708 * Practically this prevents most constants
1709 * from being inlined, sadly. */
1711 float fp32
= _mesa_half_to_float(scaled_constant
);
1713 if (fp32
!= original
)
1717 /* We don't know how to handle these with a constant */
1719 if (src
->mod
|| src
->half
|| src
->rep_low
|| src
->rep_high
) {
1720 DBG("Bailing inline constant...\n");
1724 /* Make sure that the constant is not itself a
1725 * vector by checking if all accessed values
1726 * (by the swizzle) are the same. */
1728 uint32_t *cons
= (uint32_t *) ins
->constants
;
1729 uint32_t value
= cons
[component
];
1731 bool is_vector
= false;
1732 unsigned mask
= effective_writemask(&ins
->alu
);
1734 for (int c
= 1; c
< 4; ++c
) {
1735 /* We only care if this component is actually used */
1736 if (!(mask
& (1 << c
)))
1739 uint32_t test
= cons
[(src
->swizzle
>> (2 * c
)) & 3];
1741 if (test
!= value
) {
1750 /* Get rid of the embedded constant */
1751 ins
->has_constants
= false;
1752 ins
->ssa_args
.src1
= SSA_UNUSED_0
;
1753 ins
->ssa_args
.inline_constant
= true;
1754 ins
->inline_constant
= scaled_constant
;
1759 /* Map normal SSA sources to other SSA sources / fixed registers (like
1763 map_ssa_to_alias(compiler_context
*ctx
, int *ref
)
1765 /* Sign is used quite deliberately for unused */
1769 unsigned int alias
= (uintptr_t) _mesa_hash_table_u64_search(ctx
->ssa_to_alias
, *ref
+ 1);
1772 /* Remove entry in leftovers to avoid a redunant fmov */
1774 struct set_entry
*leftover
= _mesa_set_search(ctx
->leftover_ssa_to_alias
, ((void *) (uintptr_t) (*ref
+ 1)));
1777 _mesa_set_remove(ctx
->leftover_ssa_to_alias
, leftover
);
1779 /* Assign the alias map */
1785 /* Basic dead code elimination on the MIR itself, which cleans up e.g. the
1786 * texture pipeline */
1789 midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
)
1791 bool progress
= false;
1793 mir_foreach_instr_in_block_safe(block
, ins
) {
1794 if (ins
->type
!= TAG_ALU_4
) continue;
1795 if (ins
->compact_branch
) continue;
1797 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
1798 if (mir_is_live_after(ctx
, block
, ins
, ins
->ssa_args
.dest
)) continue;
1800 mir_remove_instruction(ins
);
1807 /* Dead code elimination for branches at the end of a block - only one branch
1808 * per block is legal semantically */
1811 midgard_opt_cull_dead_branch(compiler_context
*ctx
, midgard_block
*block
)
1813 bool branched
= false;
1815 mir_foreach_instr_in_block_safe(block
, ins
) {
1816 if (!midgard_is_branch_unit(ins
->unit
)) continue;
1818 /* We ignore prepacked branches since the fragment epilogue is
1819 * just generally special */
1820 if (ins
->prepacked_branch
) continue;
1822 /* Discards are similarly special and may not correspond to the
1825 if (ins
->branch
.target_type
== TARGET_DISCARD
) continue;
1828 /* We already branched, so this is dead */
1829 mir_remove_instruction(ins
);
1837 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
1840 if (!is_int
&& src
.mod
) return true;
1843 for (unsigned c
= 0; c
< 4; ++c
) {
1844 if (!(mask
& (1 << c
))) continue;
1845 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
1852 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
1854 unsigned mask
= squeeze_writemask(ins
->alu
.mask
);
1855 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
1857 midgard_vector_alu_src src2
=
1858 vector_alu_from_unsigned(ins
->alu
.src2
);
1860 return mir_nontrivial_mod(src2
, is_int
, mask
);
1864 mir_nontrivial_outmod(midgard_instruction
*ins
)
1866 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
1867 unsigned mod
= ins
->alu
.outmod
;
1870 return mod
!= midgard_outmod_int_wrap
;
1872 return mod
!= midgard_outmod_none
;
1876 midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
)
1878 bool progress
= false;
1880 mir_foreach_instr_in_block_safe(block
, ins
) {
1881 if (ins
->type
!= TAG_ALU_4
) continue;
1882 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
1884 unsigned from
= ins
->ssa_args
.src1
;
1885 unsigned to
= ins
->ssa_args
.dest
;
1887 /* We only work on pure SSA */
1889 if (to
>= SSA_FIXED_MINIMUM
) continue;
1890 if (from
>= SSA_FIXED_MINIMUM
) continue;
1891 if (to
>= ctx
->func
->impl
->ssa_alloc
) continue;
1892 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
1894 /* Constant propagation is not handled here, either */
1895 if (ins
->ssa_args
.inline_constant
) continue;
1896 if (ins
->has_constants
) continue;
1898 if (mir_nontrivial_source2_mod(ins
)) continue;
1899 if (mir_nontrivial_outmod(ins
)) continue;
1901 /* We're clear -- rewrite */
1902 mir_rewrite_index_src(ctx
, to
, from
);
1903 mir_remove_instruction(ins
);
1910 /* fmov.pos is an idiom for fpos. Propoagate the .pos up to the source, so then
1911 * the move can be propagated away entirely */
1914 mir_compose_float_outmod(midgard_outmod_float
*outmod
, midgard_outmod_float comp
)
1917 if (comp
== midgard_outmod_none
)
1920 if (*outmod
== midgard_outmod_none
) {
1925 /* TODO: Compose rules */
1930 midgard_opt_pos_propagate(compiler_context
*ctx
, midgard_block
*block
)
1932 bool progress
= false;
1934 mir_foreach_instr_in_block_safe(block
, ins
) {
1935 if (ins
->type
!= TAG_ALU_4
) continue;
1936 if (ins
->alu
.op
!= midgard_alu_op_fmov
) continue;
1937 if (ins
->alu
.outmod
!= midgard_outmod_pos
) continue;
1939 /* TODO: Registers? */
1940 unsigned src
= ins
->ssa_args
.src1
;
1941 if (src
>= ctx
->func
->impl
->ssa_alloc
) continue;
1942 assert(!mir_has_multiple_writes(ctx
, src
));
1944 /* There might be a source modifier, too */
1945 if (mir_nontrivial_source2_mod(ins
)) continue;
1947 /* Backpropagate the modifier */
1948 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
1949 if (v
->type
!= TAG_ALU_4
) continue;
1950 if (v
->ssa_args
.dest
!= src
) continue;
1952 /* Can we even take a float outmod? */
1953 if (midgard_is_integer_out_op(v
->alu
.op
)) continue;
1955 midgard_outmod_float temp
= v
->alu
.outmod
;
1956 progress
|= mir_compose_float_outmod(&temp
, ins
->alu
.outmod
);
1958 /* Throw in the towel.. */
1959 if (!progress
) break;
1961 /* Otherwise, transfer the modifier */
1962 v
->alu
.outmod
= temp
;
1963 ins
->alu
.outmod
= midgard_outmod_none
;
1973 midgard_opt_copy_prop_tex(compiler_context
*ctx
, midgard_block
*block
)
1975 bool progress
= false;
1977 mir_foreach_instr_in_block_safe(block
, ins
) {
1978 if (ins
->type
!= TAG_ALU_4
) continue;
1979 if (!OP_IS_MOVE(ins
->alu
.op
)) continue;
1981 unsigned from
= ins
->ssa_args
.src1
;
1982 unsigned to
= ins
->ssa_args
.dest
;
1984 /* Make sure it's simple enough for us to handle */
1986 if (from
>= SSA_FIXED_MINIMUM
) continue;
1987 if (from
>= ctx
->func
->impl
->ssa_alloc
) continue;
1988 if (to
< SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
)) continue;
1989 if (to
> SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE
+ 1)) continue;
1991 bool eliminated
= false;
1993 mir_foreach_instr_in_block_from_rev(block
, v
, mir_prev_op(ins
)) {
1994 /* The texture registers are not SSA so be careful.
1995 * Conservatively, just stop if we hit a texture op
1996 * (even if it may not write) to where we are */
1998 if (v
->type
!= TAG_ALU_4
)
2001 if (v
->ssa_args
.dest
== from
) {
2002 /* We don't want to track partial writes ... */
2003 if (v
->alu
.mask
== 0xF) {
2004 v
->ssa_args
.dest
= to
;
2013 mir_remove_instruction(ins
);
2015 progress
|= eliminated
;
2021 /* The following passes reorder MIR instructions to enable better scheduling */
2024 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
2026 mir_foreach_instr_in_block_safe(block
, ins
) {
2027 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
2029 /* We've found a load/store op. Check if next is also load/store. */
2030 midgard_instruction
*next_op
= mir_next_op(ins
);
2031 if (&next_op
->link
!= &block
->instructions
) {
2032 if (next_op
->type
== TAG_LOAD_STORE_4
) {
2033 /* If so, we're done since we're a pair */
2034 ins
= mir_next_op(ins
);
2038 /* Maximum search distance to pair, to avoid register pressure disasters */
2039 int search_distance
= 8;
2041 /* Otherwise, we have an orphaned load/store -- search for another load */
2042 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
2043 /* Terminate search if necessary */
2044 if (!(search_distance
--)) break;
2046 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
2048 /* Stores cannot be reordered, since they have
2049 * dependencies. For the same reason, indirect
2050 * loads cannot be reordered as their index is
2051 * loaded in r27.w */
2053 if (OP_IS_STORE(c
->load_store
.op
)) continue;
2055 /* It appears the 0x800 bit is set whenever a
2056 * load is direct, unset when it is indirect.
2057 * Skip indirect loads. */
2059 if (!(c
->load_store
.unknown
& 0x800)) continue;
2061 /* We found one! Move it up to pair and remove it from the old location */
2063 mir_insert_instruction_before(ins
, *c
);
2064 mir_remove_instruction(c
);
2072 /* If there are leftovers after the below pass, emit actual fmov
2073 * instructions for the slow-but-correct path */
2076 emit_leftover_move(compiler_context
*ctx
)
2078 set_foreach(ctx
->leftover_ssa_to_alias
, leftover
) {
2079 int base
= ((uintptr_t) leftover
->key
) - 1;
2082 map_ssa_to_alias(ctx
, &mapped
);
2083 EMIT(mov
, mapped
, blank_alu_src
, base
);
2088 actualise_ssa_to_alias(compiler_context
*ctx
)
2090 mir_foreach_instr(ctx
, ins
) {
2091 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src0
);
2092 map_ssa_to_alias(ctx
, &ins
->ssa_args
.src1
);
2095 emit_leftover_move(ctx
);
2099 emit_fragment_epilogue(compiler_context
*ctx
)
2101 /* Special case: writing out constants requires us to include the move
2102 * explicitly now, so shove it into r0 */
2104 void *constant_value
= _mesa_hash_table_u64_search(ctx
->ssa_constants
, ctx
->fragment_output
+ 1);
2106 if (constant_value
) {
2107 midgard_instruction ins
= v_mov(SSA_FIXED_REGISTER(REGISTER_CONSTANT
), blank_alu_src
, SSA_FIXED_REGISTER(0));
2108 attach_constants(ctx
, &ins
, constant_value
, ctx
->fragment_output
+ 1);
2109 emit_mir_instruction(ctx
, ins
);
2112 /* Perform the actual fragment writeout. We have two writeout/branch
2113 * instructions, forming a loop until writeout is successful as per the
2114 * docs. TODO: gl_FragDepth */
2116 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2117 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2120 /* For the blend epilogue, we need to convert the blended fragment vec4 (stored
2121 * in r0) to a RGBA8888 value by scaling and type converting. We then output it
2122 * with the int8 analogue to the fragment epilogue */
2125 emit_blend_epilogue(compiler_context
*ctx
)
2127 /* vmul.fmul.none.fulllow hr48, r0, #255 */
2129 midgard_instruction scale
= {
2132 .inline_constant
= _mesa_float_to_half(255.0),
2134 .src0
= SSA_FIXED_REGISTER(0),
2135 .src1
= SSA_UNUSED_0
,
2136 .dest
= SSA_FIXED_REGISTER(24),
2137 .inline_constant
= true
2140 .op
= midgard_alu_op_fmul
,
2141 .reg_mode
= midgard_reg_mode_32
,
2142 .dest_override
= midgard_dest_override_lower
,
2144 .src1
= vector_alu_srco_unsigned(blank_alu_src
),
2145 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2149 emit_mir_instruction(ctx
, scale
);
2151 /* vadd.f2u_rte.pos.low hr0, hr48, #0 */
2153 midgard_vector_alu_src alu_src
= blank_alu_src
;
2154 alu_src
.half
= true;
2156 midgard_instruction f2u_rte
= {
2159 .src0
= SSA_FIXED_REGISTER(24),
2160 .src1
= SSA_UNUSED_0
,
2161 .dest
= SSA_FIXED_REGISTER(0),
2162 .inline_constant
= true
2165 .op
= midgard_alu_op_f2u_rte
,
2166 .reg_mode
= midgard_reg_mode_16
,
2167 .dest_override
= midgard_dest_override_lower
,
2168 .outmod
= midgard_outmod_pos
,
2170 .src1
= vector_alu_srco_unsigned(alu_src
),
2171 .src2
= vector_alu_srco_unsigned(blank_alu_src
),
2175 emit_mir_instruction(ctx
, f2u_rte
);
2177 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, 0, midgard_condition_always
);
2178 EMIT(alu_br_compact_cond
, midgard_jmp_writeout_op_writeout
, TAG_ALU_4
, -1, midgard_condition_always
);
2181 static midgard_block
*
2182 emit_block(compiler_context
*ctx
, nir_block
*block
)
2184 midgard_block
*this_block
= calloc(sizeof(midgard_block
), 1);
2185 list_addtail(&this_block
->link
, &ctx
->blocks
);
2187 this_block
->is_scheduled
= false;
2190 ctx
->texture_index
[0] = -1;
2191 ctx
->texture_index
[1] = -1;
2193 /* Add us as a successor to the block we are following */
2194 if (ctx
->current_block
)
2195 midgard_block_add_successor(ctx
->current_block
, this_block
);
2197 /* Set up current block */
2198 list_inithead(&this_block
->instructions
);
2199 ctx
->current_block
= this_block
;
2201 nir_foreach_instr(instr
, block
) {
2202 emit_instr(ctx
, instr
);
2203 ++ctx
->instruction_count
;
2206 inline_alu_constants(ctx
);
2207 embedded_to_inline_constant(ctx
);
2209 /* Perform heavylifting for aliasing */
2210 actualise_ssa_to_alias(ctx
);
2212 midgard_pair_load_store(ctx
, this_block
);
2214 /* Append fragment shader epilogue (value writeout) */
2215 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2216 if (block
== nir_impl_last_block(ctx
->func
->impl
)) {
2218 emit_blend_epilogue(ctx
);
2220 emit_fragment_epilogue(ctx
);
2224 if (block
== nir_start_block(ctx
->func
->impl
))
2225 ctx
->initial_block
= this_block
;
2227 if (block
== nir_impl_last_block(ctx
->func
->impl
))
2228 ctx
->final_block
= this_block
;
2230 /* Allow the next control flow to access us retroactively, for
2232 ctx
->current_block
= this_block
;
2234 /* Document the fallthrough chain */
2235 ctx
->previous_source_block
= this_block
;
2240 static midgard_block
*emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
);
2243 emit_if(struct compiler_context
*ctx
, nir_if
*nif
)
2245 /* Conditional branches expect the condition in r31.w; emit a move for
2246 * that in the _previous_ block (which is the current block). */
2247 emit_condition(ctx
, &nif
->condition
, true, COMPONENT_X
);
2249 /* Speculatively emit the branch, but we can't fill it in until later */
2250 EMIT(branch
, true, true);
2251 midgard_instruction
*then_branch
= mir_last_in_block(ctx
->current_block
);
2253 /* Emit the two subblocks */
2254 midgard_block
*then_block
= emit_cf_list(ctx
, &nif
->then_list
);
2256 /* Emit a jump from the end of the then block to the end of the else */
2257 EMIT(branch
, false, false);
2258 midgard_instruction
*then_exit
= mir_last_in_block(ctx
->current_block
);
2260 /* Emit second block, and check if it's empty */
2262 int else_idx
= ctx
->block_count
;
2263 int count_in
= ctx
->instruction_count
;
2264 midgard_block
*else_block
= emit_cf_list(ctx
, &nif
->else_list
);
2265 int after_else_idx
= ctx
->block_count
;
2267 /* Now that we have the subblocks emitted, fix up the branches */
2272 if (ctx
->instruction_count
== count_in
) {
2273 /* The else block is empty, so don't emit an exit jump */
2274 mir_remove_instruction(then_exit
);
2275 then_branch
->branch
.target_block
= after_else_idx
;
2277 then_branch
->branch
.target_block
= else_idx
;
2278 then_exit
->branch
.target_block
= after_else_idx
;
2283 emit_loop(struct compiler_context
*ctx
, nir_loop
*nloop
)
2285 /* Remember where we are */
2286 midgard_block
*start_block
= ctx
->current_block
;
2288 /* Allocate a loop number, growing the current inner loop depth */
2289 int loop_idx
= ++ctx
->current_loop_depth
;
2291 /* Get index from before the body so we can loop back later */
2292 int start_idx
= ctx
->block_count
;
2294 /* Emit the body itself */
2295 emit_cf_list(ctx
, &nloop
->body
);
2297 /* Branch back to loop back */
2298 struct midgard_instruction br_back
= v_branch(false, false);
2299 br_back
.branch
.target_block
= start_idx
;
2300 emit_mir_instruction(ctx
, br_back
);
2302 /* Mark down that branch in the graph. Note that we're really branching
2303 * to the block *after* we started in. TODO: Why doesn't the branch
2304 * itself have an off-by-one then...? */
2305 midgard_block_add_successor(ctx
->current_block
, start_block
->successors
[0]);
2307 /* Find the index of the block about to follow us (note: we don't add
2308 * one; blocks are 0-indexed so we get a fencepost problem) */
2309 int break_block_idx
= ctx
->block_count
;
2311 /* Fix up the break statements we emitted to point to the right place,
2312 * now that we can allocate a block number for them */
2314 list_for_each_entry_from(struct midgard_block
, block
, start_block
, &ctx
->blocks
, link
) {
2315 mir_foreach_instr_in_block(block
, ins
) {
2316 if (ins
->type
!= TAG_ALU_4
) continue;
2317 if (!ins
->compact_branch
) continue;
2318 if (ins
->prepacked_branch
) continue;
2320 /* We found a branch -- check the type to see if we need to do anything */
2321 if (ins
->branch
.target_type
!= TARGET_BREAK
) continue;
2323 /* It's a break! Check if it's our break */
2324 if (ins
->branch
.target_break
!= loop_idx
) continue;
2326 /* Okay, cool, we're breaking out of this loop.
2327 * Rewrite from a break to a goto */
2329 ins
->branch
.target_type
= TARGET_GOTO
;
2330 ins
->branch
.target_block
= break_block_idx
;
2334 /* Now that we've finished emitting the loop, free up the depth again
2335 * so we play nice with recursion amid nested loops */
2336 --ctx
->current_loop_depth
;
2339 static midgard_block
*
2340 emit_cf_list(struct compiler_context
*ctx
, struct exec_list
*list
)
2342 midgard_block
*start_block
= NULL
;
2344 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2345 switch (node
->type
) {
2346 case nir_cf_node_block
: {
2347 midgard_block
*block
= emit_block(ctx
, nir_cf_node_as_block(node
));
2350 start_block
= block
;
2355 case nir_cf_node_if
:
2356 emit_if(ctx
, nir_cf_node_as_if(node
));
2359 case nir_cf_node_loop
:
2360 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2363 case nir_cf_node_function
:
2372 /* Due to lookahead, we need to report the first tag executed in the command
2373 * stream and in branch targets. An initial block might be empty, so iterate
2374 * until we find one that 'works' */
2377 midgard_get_first_tag_from_block(compiler_context
*ctx
, unsigned block_idx
)
2379 midgard_block
*initial_block
= mir_get_block(ctx
, block_idx
);
2381 unsigned first_tag
= 0;
2384 midgard_bundle
*initial_bundle
= util_dynarray_element(&initial_block
->bundles
, midgard_bundle
, 0);
2386 if (initial_bundle
) {
2387 first_tag
= initial_bundle
->tag
;
2391 /* Initial block is empty, try the next block */
2392 initial_block
= list_first_entry(&(initial_block
->link
), midgard_block
, link
);
2393 } while(initial_block
!= NULL
);
2400 midgard_compile_shader_nir(nir_shader
*nir
, midgard_program
*program
, bool is_blend
)
2402 struct util_dynarray
*compiled
= &program
->compiled
;
2404 midgard_debug
= debug_get_option_midgard_debug();
2406 compiler_context ictx
= {
2408 .stage
= nir
->info
.stage
,
2410 .is_blend
= is_blend
,
2411 .blend_constant_offset
= -1,
2413 .alpha_ref
= program
->alpha_ref
2416 compiler_context
*ctx
= &ictx
;
2418 /* TODO: Decide this at runtime */
2419 ctx
->uniform_cutoff
= 8;
2421 /* Initialize at a global (not block) level hash tables */
2423 ctx
->ssa_constants
= _mesa_hash_table_u64_create(NULL
);
2424 ctx
->ssa_to_alias
= _mesa_hash_table_u64_create(NULL
);
2425 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
2426 ctx
->sysval_to_id
= _mesa_hash_table_u64_create(NULL
);
2427 ctx
->leftover_ssa_to_alias
= _mesa_set_create(NULL
, _mesa_hash_pointer
, _mesa_key_pointer_equal
);
2429 /* Record the varying mapping for the command stream's bookkeeping */
2431 struct exec_list
*varyings
=
2432 ctx
->stage
== MESA_SHADER_VERTEX
? &nir
->outputs
: &nir
->inputs
;
2434 unsigned max_varying
= 0;
2435 nir_foreach_variable(var
, varyings
) {
2436 unsigned loc
= var
->data
.driver_location
;
2437 unsigned sz
= glsl_type_size(var
->type
, FALSE
);
2439 for (int c
= 0; c
< sz
; ++c
) {
2440 program
->varyings
[loc
+ c
] = var
->data
.location
+ c
;
2441 max_varying
= MAX2(max_varying
, loc
+ c
);
2445 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
2446 * (so we don't accidentally duplicate the epilogue since mesa/st has
2447 * messed with our I/O quite a bit already) */
2449 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2451 if (ctx
->stage
== MESA_SHADER_VERTEX
)
2452 NIR_PASS_V(nir
, nir_lower_viewport_transform
);
2454 NIR_PASS_V(nir
, nir_lower_var_copies
);
2455 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2456 NIR_PASS_V(nir
, nir_split_var_copies
);
2457 NIR_PASS_V(nir
, nir_lower_var_copies
);
2458 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
2459 NIR_PASS_V(nir
, nir_lower_var_copies
);
2460 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
2462 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, glsl_type_size
, 0);
2464 /* Optimisation passes */
2468 if (midgard_debug
& MIDGARD_DBG_SHADERS
) {
2469 nir_print_shader(nir
, stdout
);
2472 /* Assign sysvals and counts, now that we're sure
2473 * (post-optimisation) */
2475 midgard_nir_assign_sysvals(ctx
, nir
);
2477 program
->uniform_count
= nir
->num_uniforms
;
2478 program
->sysval_count
= ctx
->sysval_count
;
2479 memcpy(program
->sysvals
, ctx
->sysvals
, sizeof(ctx
->sysvals
[0]) * ctx
->sysval_count
);
2481 program
->attribute_count
= (ctx
->stage
== MESA_SHADER_VERTEX
) ? nir
->num_inputs
: 0;
2482 program
->varying_count
= max_varying
+ 1; /* Fencepost off-by-one */
2484 nir_foreach_function(func
, nir
) {
2488 list_inithead(&ctx
->blocks
);
2489 ctx
->block_count
= 0;
2492 emit_cf_list(ctx
, &func
->impl
->body
);
2493 emit_block(ctx
, func
->impl
->end_block
);
2495 break; /* TODO: Multi-function shaders */
2498 util_dynarray_init(compiled
, NULL
);
2500 /* MIR-level optimizations */
2502 bool progress
= false;
2507 mir_foreach_block(ctx
, block
) {
2508 progress
|= midgard_opt_pos_propagate(ctx
, block
);
2509 progress
|= midgard_opt_copy_prop(ctx
, block
);
2510 progress
|= midgard_opt_copy_prop_tex(ctx
, block
);
2511 progress
|= midgard_opt_dead_code_eliminate(ctx
, block
);
2515 /* Nested control-flow can result in dead branches at the end of the
2516 * block. This messes with our analysis and is just dead code, so cull
2518 mir_foreach_block(ctx
, block
) {
2519 midgard_opt_cull_dead_branch(ctx
, block
);
2523 schedule_program(ctx
);
2525 /* Now that all the bundles are scheduled and we can calculate block
2526 * sizes, emit actual branch instructions rather than placeholders */
2528 int br_block_idx
= 0;
2530 mir_foreach_block(ctx
, block
) {
2531 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2532 for (int c
= 0; c
< bundle
->instruction_count
; ++c
) {
2533 midgard_instruction
*ins
= bundle
->instructions
[c
];
2535 if (!midgard_is_branch_unit(ins
->unit
)) continue;
2537 if (ins
->prepacked_branch
) continue;
2539 /* Parse some basic branch info */
2540 bool is_compact
= ins
->unit
== ALU_ENAB_BR_COMPACT
;
2541 bool is_conditional
= ins
->branch
.conditional
;
2542 bool is_inverted
= ins
->branch
.invert_conditional
;
2543 bool is_discard
= ins
->branch
.target_type
== TARGET_DISCARD
;
2545 /* Determine the block we're jumping to */
2546 int target_number
= ins
->branch
.target_block
;
2548 /* Report the destination tag */
2549 int dest_tag
= is_discard
? 0 : midgard_get_first_tag_from_block(ctx
, target_number
);
2551 /* Count up the number of quadwords we're
2552 * jumping over = number of quadwords until
2553 * (br_block_idx, target_number) */
2555 int quadword_offset
= 0;
2558 /* Jump to the end of the shader. We
2559 * need to include not only the
2560 * following blocks, but also the
2561 * contents of our current block (since
2562 * discard can come in the middle of
2565 midgard_block
*blk
= mir_get_block(ctx
, br_block_idx
+ 1);
2567 for (midgard_bundle
*bun
= bundle
+ 1; bun
< (midgard_bundle
*)((char*) block
->bundles
.data
+ block
->bundles
.size
); ++bun
) {
2568 quadword_offset
+= quadword_size(bun
->tag
);
2571 mir_foreach_block_from(ctx
, blk
, b
) {
2572 quadword_offset
+= b
->quadword_count
;
2575 } else if (target_number
> br_block_idx
) {
2578 for (int idx
= br_block_idx
+ 1; idx
< target_number
; ++idx
) {
2579 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2582 quadword_offset
+= blk
->quadword_count
;
2585 /* Jump backwards */
2587 for (int idx
= br_block_idx
; idx
>= target_number
; --idx
) {
2588 midgard_block
*blk
= mir_get_block(ctx
, idx
);
2591 quadword_offset
-= blk
->quadword_count
;
2595 /* Unconditional extended branches (far jumps)
2596 * have issues, so we always use a conditional
2597 * branch, setting the condition to always for
2598 * unconditional. For compact unconditional
2599 * branches, cond isn't used so it doesn't
2600 * matter what we pick. */
2602 midgard_condition cond
=
2603 !is_conditional
? midgard_condition_always
:
2604 is_inverted
? midgard_condition_false
:
2605 midgard_condition_true
;
2607 midgard_jmp_writeout_op op
=
2608 is_discard
? midgard_jmp_writeout_op_discard
:
2609 (is_compact
&& !is_conditional
) ? midgard_jmp_writeout_op_branch_uncond
:
2610 midgard_jmp_writeout_op_branch_cond
;
2613 midgard_branch_extended branch
=
2614 midgard_create_branch_extended(
2619 memcpy(&ins
->branch_extended
, &branch
, sizeof(branch
));
2620 } else if (is_conditional
|| is_discard
) {
2621 midgard_branch_cond branch
= {
2623 .dest_tag
= dest_tag
,
2624 .offset
= quadword_offset
,
2628 assert(branch
.offset
== quadword_offset
);
2630 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2632 assert(op
== midgard_jmp_writeout_op_branch_uncond
);
2634 midgard_branch_uncond branch
= {
2636 .dest_tag
= dest_tag
,
2637 .offset
= quadword_offset
,
2641 assert(branch
.offset
== quadword_offset
);
2643 memcpy(&ins
->br_compact
, &branch
, sizeof(branch
));
2651 /* Emit flat binary from the instruction arrays. Iterate each block in
2652 * sequence. Save instruction boundaries such that lookahead tags can
2653 * be assigned easily */
2655 /* Cache _all_ bundles in source order for lookahead across failed branches */
2657 int bundle_count
= 0;
2658 mir_foreach_block(ctx
, block
) {
2659 bundle_count
+= block
->bundles
.size
/ sizeof(midgard_bundle
);
2661 midgard_bundle
**source_order_bundles
= malloc(sizeof(midgard_bundle
*) * bundle_count
);
2663 mir_foreach_block(ctx
, block
) {
2664 util_dynarray_foreach(&block
->bundles
, midgard_bundle
, bundle
) {
2665 source_order_bundles
[bundle_idx
++] = bundle
;
2669 int current_bundle
= 0;
2671 /* Midgard prefetches instruction types, so during emission we
2672 * need to lookahead. Unless this is the last instruction, in
2673 * which we return 1. Or if this is the second to last and the
2674 * last is an ALU, then it's also 1... */
2676 mir_foreach_block(ctx
, block
) {
2677 mir_foreach_bundle_in_block(block
, bundle
) {
2680 if (current_bundle
+ 1 < bundle_count
) {
2681 uint8_t next
= source_order_bundles
[current_bundle
+ 1]->tag
;
2683 if (!(current_bundle
+ 2 < bundle_count
) && IS_ALU(next
)) {
2690 emit_binary_bundle(ctx
, bundle
, compiled
, lookahead
);
2694 /* TODO: Free deeper */
2695 //util_dynarray_fini(&block->instructions);
2698 free(source_order_bundles
);
2700 /* Report the very first tag executed */
2701 program
->first_tag
= midgard_get_first_tag_from_block(ctx
, 0);
2703 /* Deal with off-by-one related to the fencepost problem */
2704 program
->work_register_count
= ctx
->work_registers
+ 1;
2706 program
->can_discard
= ctx
->can_discard
;
2707 program
->uniform_cutoff
= ctx
->uniform_cutoff
;
2709 program
->blend_patch_offset
= ctx
->blend_constant_offset
;
2711 if (midgard_debug
& MIDGARD_DBG_SHADERS
)
2712 disassemble_midgard(program
->compiled
.data
, program
->compiled
.size
);